From nobody Thu Sep 24 20:37:28 2026 Received: from out28-97.mail.aliyun.com (out28-97.mail.aliyun.com [115.124.28.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F07FB3546C6; Mon, 21 Sep 2026 05:56:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.97 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970189; cv=none; b=rSuwjHddenq9V2oRQaeH19STOXUCWhba40rmDVYJkx3QhmvzD50OzV+R/Zii/OU4mjjY8AuXl7bnxo/w7C92WfHbXCns43iHzMFmPz4bqM+tJD5U6QxCJBrOCJ9cHkGxtAokHXNy/joSvSVc2BGOmCIlomsn2Qpjvi3ZmDx3sGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970189; c=relaxed/simple; bh=cXkrNP3JB32lTor0Lxju0vrKYeAxIH2Rny1peyD21bI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j0r6ehGjateFYER5JfV3TmDBesdtmJC8lyB+4keLF6tatHu4IyRbAdWiE60+scpHNLjp89OFjW8aw28jfqSAPj0f19usgFW4d30LrBlIIuSCqCo6nAjBsobFGvVgqQZtYeRauIu9TQX1p8U8hdlFextzjDPQedSRpKTbk5u6GWM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.97 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436259|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.00968957-0.000549557-0.989761;FP=14369715923100386555|0|0|0|0|-1|-1|-1;HT=maildocker-contentspam033037017159;MF=wanglin@open-hieco.net;NM=1;PH=DS;RN=15;RT=15;SR=0;TI=SMTPD_---.jIkm1mR_1789970174; Received: from localhost.localdomain(mailfrom:wanglin@open-hieco.net fp:SMTPD_---.jIkm1mR_1789970174 cluster:ay29) by smtp.aliyun-inc.com; Mon, 21 Sep 2026 13:56:15 +0800 From: Lin Wang To: Borislav Petkov , Yazen Ghannam , Mario Limonciello Cc: Pu Wen , Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Tony Luck , Clemens Ladisch , Guenter Roeck , x86@kernel.org, linux-edac@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/8] x86/hygon: Add Family 0x18 DF node enumeration Date: Mon, 21 Sep 2026 13:55:56 +0800 Message-ID: <20260921055603.25112-2-wanglin@open-hieco.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260921055603.25112-1-wanglin@open-hieco.net> References: <20260921055603.25112-1-wanglin@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AMD node code locates function 3 for node N at PCI slot 0x18 + N. Hygon has no equivalent node-index-to-slot mapping: DF F3 devices are discovered by PCI ID and the PCI BDF is only an access point. Add a Hygon node cache that enumerates DF devices by PCI ID and obtains the socket ID and DFID for each node from DF configuration registers. Validate the enumerated socket set against the hardware-reported socket mask before making the cache available. Place Core and DDR Dies (CDDs) before I/O Dies (IODs) and order each group by socket and DFID to provide dense node indices. Export interfaces for node counts and identity, F3/F4 lookup, and PCI device-to-node lookup. Signed-off-by: Lin Wang --- MAINTAINERS | 3 + arch/x86/Kconfig | 4 + arch/x86/include/asm/hygon/node.h | 133 +++++++ arch/x86/kernel/Makefile | 1 + arch/x86/kernel/hygon_node.c | 609 ++++++++++++++++++++++++++++++ 5 files changed, 750 insertions(+) create mode 100644 arch/x86/include/asm/hygon/node.h create mode 100644 arch/x86/kernel/hygon_node.c diff --git a/MAINTAINERS b/MAINTAINERS index cc3cae2e378b..51b28cc0e5e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12135,9 +12135,12 @@ F: drivers/input/touchscreen/hycon-hy46xx.c =20 HYGON PROCESSOR SUPPORT M: Pu Wen +M: Lin Wang L: linux-kernel@vger.kernel.org S: Maintained +F: arch/x86/include/asm/hygon/ F: arch/x86/kernel/cpu/hygon.c +F: arch/x86/kernel/hygon_node.c =20 HYNIX HI556 SENSOR DRIVER M: Sakari Ailus diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 15fd9ec5ecac..6d72e62d87f7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -3078,6 +3078,10 @@ config AMD_NODE def_bool y depends on CPU_SUP_AMD && PCI =20 +config HYGON_NODE + def_bool y + depends on CPU_SUP_HYGON && PCI + endmenu =20 menu "Binary Emulations" diff --git a/arch/x86/include/asm/hygon/node.h b/arch/x86/include/asm/hygon= /node.h new file mode 100644 index 000000000000..b97eaee7c0d1 --- /dev/null +++ b/arch/x86/include/asm/hygon/node.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Hygon Family 0x18 Data Fabric node enumeration API + * + * This header declares Hygon Fam18h DF node enumeration and function + * access interfaces. + */ +#ifndef _ASM_X86_HYGON_NODE_H +#define _ASM_X86_HYGON_NODE_H + +#include +#include + +struct pci_dev; + +/* DF function indices supported by hygon_node_get_func(). */ +#define HYGON_DF_F3 3 +#define HYGON_DF_F4 4 + +/* + * Hygon Core and DDR Dies (CDDs) start at DFID 4. Each CDD contains + * CPU cores and UMCs. I/O Dies (IODs) occupy DFIDs 0-3. + */ +#define HYGON_CDD_DFID_BASE 4 + +/** + * enum hygon_node_type - DF node type, derived from DFID + * @HYGON_NODE_IOD: I/O die (DFID < HYGON_CDD_DFID_BASE); no UMC. + * @HYGON_NODE_CDD: Core and DDR Die (DFID >=3D HYGON_CDD_DFID_BASE); + * contains CPU cores and UMC controllers. + */ +enum hygon_node_type { + HYGON_NODE_IOD =3D 0, + HYGON_NODE_CDD =3D 1, +}; + +/** + * struct hygon_node_info - DF node information + * @socket_id: Physical socket ID, F1x200[30:28] + * @dfid: Data Fabric ID, model-dependent source + * @type: HYGON_NODE_CDD or HYGON_NODE_IOD + */ +struct hygon_node_info { + u8 socket_id; + u8 dfid; + enum hygon_node_type type; +}; + +#ifdef CONFIG_HYGON_NODE + +/** + * hygon_node_num() - Total number of DF nodes (CDD + IOD) + * + * This is the upper bound for every node index in this API. + * + * Return: total node count, or 0 if the cache is not ready. + */ +u16 hygon_node_num(void); + +/** + * hygon_cdd_num() - Number of Core and DDR Dies (CDD) + * + * A CDD (DFID >=3D 4) has CPU cores and UMC controllers; an IOD + * (DFID < 4) has neither. CDDs occupy nodes [0, hygon_cdd_num()). + * + * Return: CDD count, or 0 if the cache is not ready. + */ +u16 hygon_cdd_num(void); + +/** + * hygon_node_get_info() - Get information for a DF node + * @node: DF node index in [0, hygon_node_num()) + * @info: Output structure (socket_id, dfid, type) + * + * Return: 0 on success, -EINVAL if @node is out of range or @info is + * NULL, -ENODEV if the cache is not ready. + */ +int hygon_node_get_info(u16 node, struct hygon_node_info *info); + +/** + * hygon_node_get_func() - Get DF function PCI device for a node + * @node: DF node index in [0, hygon_node_num()) + * @func: HYGON_DF_F3 or HYGON_DF_F4 + * + * Return: referenced pci_dev on success. NULL if @node is out of + * range, @func is unsupported, or the cache is not ready. The + * caller must release the reference with pci_dev_put(). + */ +struct pci_dev *hygon_node_get_func(u16 node, u8 func); + +/** + * hygon_pci_dev_to_df_node() - Find DF node owning the given PCI device + * @pdev: PCI function on the same domain, bus and slot as a cached DF node + * + * Looks up the DF node whose misc (F3) device shares the same PCI + * domain, bus and slot as @pdev. + * + * Return: DF node index in [0, hygon_node_num()) on success, -EINVAL + * if @pdev is NULL, or -ENODEV if no matching node is found or the + * cache is not ready. + */ +int hygon_pci_dev_to_df_node(struct pci_dev *pdev); + +#else /* !CONFIG_HYGON_NODE */ + +static inline u16 hygon_node_num(void) +{ + return 0; +} + +static inline u16 hygon_cdd_num(void) +{ + return 0; +} + +static inline int hygon_node_get_info(u16 node, struct hygon_node_info *in= fo) +{ + return -ENODEV; +} + +static inline struct pci_dev *hygon_node_get_func(u16 node, u8 func) +{ + return NULL; +} + +static inline int hygon_pci_dev_to_df_node(struct pci_dev *pdev) +{ + return -ENODEV; +} + +#endif /* CONFIG_HYGON_NODE */ + +#endif /* _ASM_X86_HYGON_NODE_H */ diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 31f46fd00527..b8430e5e53fb 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -136,6 +136,7 @@ obj-$(CONFIG_HPET_TIMER) +=3D hpet.o =20 obj-$(CONFIG_AMD_NB) +=3D amd_nb.o obj-$(CONFIG_AMD_NODE) +=3D amd_node.o +obj-$(CONFIG_HYGON_NODE) +=3D hygon_node.o obj-$(CONFIG_DEBUG_NMI_SELFTEST) +=3D nmi_selftest.o =20 obj-$(CONFIG_KVM_GUEST) +=3D kvm.o kvmclock.o diff --git a/arch/x86/kernel/hygon_node.c b/arch/x86/kernel/hygon_node.c new file mode 100644 index 000000000000..e8346d86d8a6 --- /dev/null +++ b/arch/x86/kernel/hygon_node.c @@ -0,0 +1,609 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Hygon Family 0x18 Data Fabric node enumeration + * + * A DF instance exposes sibling PCI functions in one slot. Function 3 + * is the misc device used for enumeration, function 4 is the link + * device, and functions 1 and 5 provide the socket and DF identity. + * + * Enumerate F3 devices by PCI ID, validate their F4 siblings, read each + * node's socket ID and DFID, and validate the enumerated socket set + * against SocketPresent. Sort the nodes into a dense cache with Core + * and DDR Dies (CDDs) before I/O Dies (IODs), then by socket ID and + * DFID. + */ + +#define pr_fmt(fmt) "hygon_node: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * DF register offsets used for node identity discovery. + * + * F1x200 (SystemCfg) -- present on all supported models: + * [30:28] MySocketId - hardware socket ID + * [23:20] MyDieId - die ID (equals DFID on some models, see belo= w) + * + * F5x180 (FabricBlockInstanceInformation3_CS) -- used on Model 06h-08h: + * [19:16] DFID - Data Fabric ID for UMC/SMN addressing + * + * DFID source by model: + * Model 04h/05h: F1x200[23:20] (MyDieId =3D=3D DFID) + * Model 06h-08h: F5x180[19:16] (MyDieId !=3D DFID, different numbering) + */ +#define DF_F1_SYSTEM_CFG 0x200 +#define DF_F5_FABRIC_ID 0x180 + +#define DF_F1_SOCKET_ID GENMASK(30, 28) +#define DF_F1_DIE_ID GENMASK(23, 20) +#define DF_F1_SOCKET_PRESENT GENMASK(7, 0) +#define DF_F5_DFID GENMASK(19, 16) + +/* DF function numbers for sibling device access (internal use). */ +#define HYGON_DF_F1 1 +#define HYGON_DF_F5 5 + +/* PCI device IDs used only by Hygon DF node discovery. */ +#define PCI_DEVICE_ID_HYGON_18H_DF_F3 0x1463 +#define PCI_DEVICE_ID_HYGON_18H_DF_F4 0x1464 +#define PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1 0x1491 +#define PCI_DEVICE_ID_HYGON_18H_M04H_DF_F3 0x1493 +#define PCI_DEVICE_ID_HYGON_18H_M04H_DF_F4 0x1494 +#define PCI_DEVICE_ID_HYGON_18H_M05H_DF_F1 0x14b1 +#define PCI_DEVICE_ID_HYGON_18H_M05H_DF_F3 0x14b3 +#define PCI_DEVICE_ID_HYGON_18H_M05H_DF_F4 0x14b4 +#define PCI_DEVICE_ID_HYGON_18H_M06H_DF_F5 0x14b5 + +/* + * Cached identity for one DF instance. After sorting, CDDs occupy + * nodes[0..num_cdd-1]. + * + * The PCI BDF is the access point for a DF node, not its identity. + * The socket ID and DFID, read from DF registers, together identify + * the node in hardware. + */ +struct hygon_node { + struct pci_dev *misc; + struct pci_dev *link; + u8 socket_id; + u8 dfid; + bool is_cdd; +}; + +struct hygon_node_cache { + struct hygon_node *nodes; + u16 num_nodes; + u16 num_cdd; + u16 num_sockets; +}; + +struct hygon_df_id { + u8 socket_id; + u8 dfid; +}; + +/* DF sibling device IDs used to read node identity. */ +struct hygon_df_cfg { + u16 f1_id; + u16 f5_id; +}; + +/* DF misc (F3) device IDs for all supported Hygon Family 0x18 models. */ +static const struct pci_device_id hygon_nb_misc_ids[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_DF_F3) }, + { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M04H_DF_F3) }, + { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_DF_F3) }, + {} +}; + +/* DF link (F4) device IDs for supported models. */ +static const struct pci_device_id hygon_nb_link_ids[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_DF_F4) }, + { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M04H_DF_F4) }, + { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_DF_F4) }, + {} +}; + +static const struct hygon_df_cfg hygon_m04_df_cfg __initconst =3D { + .f1_id =3D PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1, +}; + +static const struct hygon_df_cfg hygon_m05_df_cfg __initconst =3D { + .f1_id =3D PCI_DEVICE_ID_HYGON_18H_M05H_DF_F1, +}; + +static const struct hygon_df_cfg hygon_m06_m08_df_cfg __initconst =3D { + .f1_id =3D PCI_DEVICE_ID_HYGON_18H_M05H_DF_F1, + .f5_id =3D PCI_DEVICE_ID_HYGON_18H_M06H_DF_F5, +}; + +static const struct x86_cpu_id hygon_df_cpuids[] __initconst =3D { + X86_MATCH_VENDOR_FAM_MODEL(HYGON, 0x18, 0x04, &hygon_m04_df_cfg), + X86_MATCH_VENDOR_FAM_MODEL(HYGON, 0x18, 0x05, &hygon_m05_df_cfg), + X86_MATCH_VENDOR_FAM_MODEL(HYGON, 0x18, 0x06, &hygon_m06_m08_df_cfg), + X86_MATCH_VENDOR_FAM_MODEL(HYGON, 0x18, 0x07, &hygon_m06_m08_df_cfg), + X86_MATCH_VENDOR_FAM_MODEL(HYGON, 0x18, 0x08, &hygon_m06_m08_df_cfg), + {} +}; + +static struct hygon_node_cache hygon_cache; + +/* + * Iterate Hygon PCI devices, returning the next one that matches @ids. + * Follows the pci_get_device() convention: @from is consumed (its + * reference is dropped) and the returned device has an elevated + * reference count. + */ +static struct pci_dev * __init next_hygon_dev(struct pci_dev *from, + const struct pci_device_id *ids) +{ + while ((from =3D pci_get_device(PCI_VENDOR_ID_HYGON, PCI_ANY_ID, from))) { + if (pci_match_id(ids, from)) + return from; + } + + return NULL; +} + +/* + * Find the DF link (function 4) sibling of a DF misc (function 3) + * device. Both functions share the same PCI bus and slot. + */ +static struct pci_dev * __init hygon_get_link(struct pci_dev *misc) +{ + struct pci_dev *link; + + link =3D pci_get_domain_bus_and_slot(pci_domain_nr(misc->bus), + misc->bus->number, + PCI_DEVFN(PCI_SLOT(misc->devfn), + HYGON_DF_F4)); + if (!link) + return NULL; + + if (!pci_match_id(hygon_nb_link_ids, link)) { + pci_dev_put(link); + return NULL; + } + + return link; +} + +static const struct hygon_df_cfg * __init hygon_get_df_cfg(void) +{ + const struct x86_cpu_id *id =3D x86_match_cpu(hygon_df_cpuids); + + return id ? (const void *)id->driver_data : NULL; +} + +/* + * Read a config register from a DF sibling function on the same PCI + * slot as @misc. Only functions 1 (F1, SystemCfg) and 5 (F5, + * FabricId) are supported. + */ +static int __init hygon_read_df_reg(struct pci_dev *misc, u8 func, + int offset, u32 *value) +{ + const struct hygon_df_cfg *cfg; + struct pci_dev *sibling; + u16 expected_device; + int err; + + cfg =3D hygon_get_df_cfg(); + if (!cfg) + return -ENODEV; + + if (func =3D=3D HYGON_DF_F1) { + expected_device =3D cfg->f1_id; + + /* + * Model 05h uses the M04H F1 device ID when F3 does not use + * the M05H device ID. + */ + if (boot_cpu_data.x86_model =3D=3D 0x5 && + misc->device !=3D PCI_DEVICE_ID_HYGON_18H_M05H_DF_F3) + expected_device =3D PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1; + } else if (func =3D=3D HYGON_DF_F5) { + expected_device =3D cfg->f5_id; + } else { + return -EINVAL; + } + + if (!expected_device) + return -ENODEV; + + sibling =3D pci_get_domain_bus_and_slot(pci_domain_nr(misc->bus), + misc->bus->number, + PCI_DEVFN(PCI_SLOT(misc->devfn), + func)); + if (!sibling) + return -ENODEV; + + if (sibling->vendor !=3D PCI_VENDOR_ID_HYGON || + sibling->device !=3D expected_device) { + pci_dev_put(sibling); + return -ENODEV; + } + + err =3D pci_read_config_dword(sibling, offset, value); + pci_dev_put(sibling); + + if (err) { + pr_warn("error reading %04x:%02x:%02x.%u offset 0x%x\n", + pci_domain_nr(misc->bus), misc->bus->number, + PCI_SLOT(misc->devfn), func, offset); + return pcibios_err_to_errno(err); + } + + /* Do not parse a PCI error response as DF identity. */ + if (PCI_POSSIBLE_ERROR(*value)) { + pr_warn("error response reading %04x:%02x:%02x.%u offset 0x%x\n", + pci_domain_nr(misc->bus), misc->bus->number, + PCI_SLOT(misc->devfn), func, offset); + return -ENODEV; + } + + return 0; +} + +/* + * Read the hardware identity for one DF misc device from its sibling + * functions. + * + * Supported models expose F1x200 (SystemCfg): socket_id from [30:28] and a + * die identifier (MyDieId) from [23:20]. + * On Model 06h-08h MyDieId differs from the DFID used by UMC and SMN + * addressing, so an additional F5x180 (FabricId) read obtains the DFID + * from [19:16]. + * + * The boot CPU model selects the DF register layout for all instances. + */ +static int __init hygon_read_df_id(struct pci_dev *misc, + struct hygon_df_id *id) +{ + const struct hygon_df_cfg *cfg =3D hygon_get_df_cfg(); + u32 reg; + int ret; + + if (!cfg) + return -ENODEV; + + ret =3D hygon_read_df_reg(misc, HYGON_DF_F1, DF_F1_SYSTEM_CFG, ®); + if (ret) + return ret; + + id->socket_id =3D FIELD_GET(DF_F1_SOCKET_ID, reg); + id->dfid =3D FIELD_GET(DF_F1_DIE_ID, reg); + + /* Read DFID from F5x180 on models that provide an F5 sibling. */ + if (cfg->f5_id) { + ret =3D hygon_read_df_reg(misc, HYGON_DF_F5, DF_F5_FABRIC_ID, + ®); + if (ret) + return ret; + id->dfid =3D FIELD_GET(DF_F5_DFID, reg); + } + + return 0; +} + +/* + * Read the system-wide SocketPresent mask from F1x200[7:0]. + * + * SocketPresent is system-wide rather than per-node. Read it once from + * the first DF misc device. A zero mask is invalid on supported models. + */ +static int __init hygon_read_socket_present(struct pci_dev *misc, + u8 *socket_present) +{ + u32 reg; + int ret; + + ret =3D hygon_read_df_reg(misc, HYGON_DF_F1, DF_F1_SYSTEM_CFG, ®); + if (ret) + return ret; + + *socket_present =3D FIELD_GET(DF_F1_SOCKET_PRESENT, reg); + if (!*socket_present) { + pr_warn("SocketPresent is zero\n"); + return -EINVAL; + } + + return 0; +} + +static void __init hygon_release_nodes(struct hygon_node *nodes, u16 count) +{ + u16 i; + + for (i =3D 0; i < count; i++) { + pci_dev_put(nodes[i].misc); + pci_dev_put(nodes[i].link); + } + + kfree(nodes); +} + +/* + * Walk all DF misc (F3) devices and read per-node identity (socket_id, + * dfid) from each, collecting them into a flat array. The system-wide + * SocketPresent mask is sampled once, and the enumerated socket set is + * validated against it; socket IDs must also be dense (0..N-1). + */ +static int __init hygon_collect_nodes(struct hygon_node_cache *cache) +{ + u8 observed_socket_mask =3D 0, socket_present_mask =3D 0; + struct pci_dev *misc =3D NULL, *link =3D NULL; + u16 capacity =3D 0, count =3D 0; + struct hygon_node *nodes; + int ret; + + while ((misc =3D next_hygon_dev(misc, hygon_nb_misc_ids))) + capacity++; + + if (!capacity) + return -ENODEV; + + nodes =3D kcalloc(capacity, sizeof(*nodes), GFP_KERNEL); + if (!nodes) + return -ENOMEM; + + while ((misc =3D next_hygon_dev(misc, hygon_nb_misc_ids))) { + struct hygon_df_id id; + + link =3D hygon_get_link(misc); + if (!link) { + ret =3D -ENODEV; + goto fail_put_devs; + } + + ret =3D hygon_read_df_id(misc, &id); + if (ret) + goto fail_put_devs; + + /* SocketPresent is system-wide, so sample it once. */ + if (!count) { + ret =3D hygon_read_socket_present(misc, + &socket_present_mask); + if (ret) + goto fail_put_devs; + } + + if (count >=3D capacity) { + ret =3D -ENODEV; + goto fail_put_devs; + } + + nodes[count].misc =3D pci_dev_get(misc); + nodes[count].link =3D link; + link =3D NULL; + nodes[count].socket_id =3D id.socket_id; + nodes[count].dfid =3D id.dfid; + nodes[count].is_cdd =3D (id.dfid >=3D HYGON_CDD_DFID_BASE); + count++; + + observed_socket_mask |=3D BIT(id.socket_id); + } + + if (count !=3D capacity) { + pr_warn("DF enumeration changed: expected %u nodes, got %u\n", + capacity, count); + ret =3D -ENODEV; + goto fail; + } + + /* + * Every populated socket must contribute at least one enumerated DF + * misc device. SocketPresent is guaranteed to be non-zero. + */ + if (observed_socket_mask !=3D socket_present_mask) { + pr_warn("SocketPresent mismatch: observed=3D0x%x present=3D0x%x\n", + observed_socket_mask, socket_present_mask); + ret =3D -EINVAL; + goto fail; + } + + cache->nodes =3D nodes; + cache->num_nodes =3D count; + cache->num_sockets =3D hweight8(socket_present_mask); + + if (socket_present_mask !=3D GENMASK(cache->num_sockets - 1, 0)) { + pr_warn("sparse socket IDs not supported (SocketPresent=3D0x%x)\n", + socket_present_mask); + ret =3D -EINVAL; + goto fail; + } + + return 0; + +fail_put_devs: + pci_dev_put(link); + pci_dev_put(misc); +fail: + hygon_release_nodes(nodes, count); + cache->nodes =3D NULL; + cache->num_nodes =3D 0; + cache->num_sockets =3D 0; + return ret; +} + +/* + * Sort CDD nodes before IOD nodes, then order by hardware + * (socket_id, dfid). + */ +static int __init hygon_node_cmp(const void *a, const void *b) +{ + const struct hygon_node *left =3D a, *right =3D b; + + if (left->is_cdd !=3D right->is_cdd) + return right->is_cdd - left->is_cdd; + + if (left->socket_id !=3D right->socket_id) + return (int)left->socket_id - right->socket_id; + + return (int)left->dfid - (int)right->dfid; +} + +static int __init hygon_sort_and_classify(struct hygon_node_cache *cache) +{ + u16 i; + + sort(cache->nodes, cache->num_nodes, sizeof(*cache->nodes), + hygon_node_cmp, NULL); + + cache->num_cdd =3D 0; + + for (i =3D 0; i < cache->num_nodes; i++) { + const struct hygon_node *node =3D &cache->nodes[i]; + + if (i) { + const struct hygon_node *prev =3D &cache->nodes[i - 1]; + + if (node->socket_id =3D=3D prev->socket_id && + node->dfid =3D=3D prev->dfid) { + pr_warn("duplicate DF node: socket=3D%u dfid=3D%u\n", + node->socket_id, node->dfid); + return -EINVAL; + } + } + + if (node->is_cdd) + cache->num_cdd++; + } + + if (!cache->num_cdd) + return -ENODEV; + + return 0; +} + +static int __init hygon_build_cache(void) +{ + struct hygon_node_cache cache =3D { }; + int err; + + err =3D hygon_collect_nodes(&cache); + if (err) + return err; + + err =3D hygon_sort_and_classify(&cache); + if (err) + goto fail; + + hygon_cache =3D cache; + + return 0; + +fail: + hygon_release_nodes(cache.nodes, cache.num_nodes); + return err; +} + +u16 hygon_node_num(void) +{ + return hygon_cache.num_nodes; +} +EXPORT_SYMBOL_GPL(hygon_node_num); + +u16 hygon_cdd_num(void) +{ + return hygon_cache.num_cdd; +} +EXPORT_SYMBOL_GPL(hygon_cdd_num); + +int hygon_node_get_info(u16 node, struct hygon_node_info *info) +{ + const struct hygon_node *n; + + if (!info) + return -EINVAL; + + if (!hygon_cache.nodes) + return -ENODEV; + + if (node >=3D hygon_cache.num_nodes) + return -EINVAL; + + n =3D &hygon_cache.nodes[node]; + info->socket_id =3D n->socket_id; + info->dfid =3D n->dfid; + info->type =3D n->is_cdd ? HYGON_NODE_CDD : HYGON_NODE_IOD; + return 0; +} +EXPORT_SYMBOL_GPL(hygon_node_get_info); + +struct pci_dev *hygon_node_get_func(u16 node, u8 func) +{ + if (!hygon_cache.nodes) + return NULL; + + if (node >=3D hygon_cache.num_nodes) + return NULL; + + switch (func) { + case HYGON_DF_F3: + return pci_dev_get(hygon_cache.nodes[node].misc); + case HYGON_DF_F4: + return pci_dev_get(hygon_cache.nodes[node].link); + default: + return NULL; + } +} +EXPORT_SYMBOL_GPL(hygon_node_get_func); + +int hygon_pci_dev_to_df_node(struct pci_dev *pdev) +{ + u16 i; + + if (!pdev) + return -EINVAL; + + if (!hygon_cache.nodes) + return -ENODEV; + + for (i =3D 0; i < hygon_cache.num_nodes; i++) { + struct pci_dev *misc =3D hygon_cache.nodes[i].misc; + + if (pci_domain_nr(misc->bus) =3D=3D pci_domain_nr(pdev->bus) && + misc->bus->number =3D=3D pdev->bus->number && + PCI_SLOT(misc->devfn) =3D=3D PCI_SLOT(pdev->devfn)) + return i; + } + + return -ENODEV; +} +EXPORT_SYMBOL_GPL(hygon_pci_dev_to_df_node); + +static int __init hygon_node_init(void) +{ + int ret; + + if (!hygon_get_df_cfg()) + return 0; + + ret =3D hygon_build_cache(); + if (ret) { + pr_warn("DF node cache build failed: %d\n", ret); + return ret; + } + + pr_info("%u DF nodes (%u CDDs, %u IODs) across %u sockets\n", + hygon_cache.num_nodes, hygon_cache.num_cdd, + hygon_cache.num_nodes - hygon_cache.num_cdd, + hygon_cache.num_sockets); + + return 0; +} +fs_initcall(hygon_node_init); --=20 2.43.0 From nobody Thu Sep 24 20:37:28 2026 Received: from out28-149.mail.aliyun.com (out28-149.mail.aliyun.com [115.124.28.149]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB91635F170; Mon, 21 Sep 2026 05:56:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.149 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970190; cv=none; b=GNRbYiupHshkGpiZJSvgvUxCf35l+IJ13qHXEmRrsv34Jro12MfldSVGKvnlaBGgNPpcFo8QG5IiqYG6sJIShMX0a1JgLLNUCJthXCqAh6Wr+NRCYLAoxvUlLq6v7Jb6KfmQEAt6VXTvCl6D2TPq5pQPQdKR3K06ru4JEfGknr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970190; c=relaxed/simple; bh=2nHF4r1kpHqm8vGYTwoo02+Kvtci5S4hxDU0kuNZkQg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PMR0fv/8r9myLsrfLzCbdT1gBKFG2fLQYrZe13SEqSMAh9sFQzP48LdbfbRuUZ0RpeAlEEREJfFhLzZuHemzuKjfCoXUVtTSkXDEZYDTodJeDzxtQofffT8Aam0wyHytoXmS/e+mvnwM1cGCMRJkX18eCw/ph0jbgftq9CWVLUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.149 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436529|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.00485698-0.000955166-0.994188;FP=13845733545864939739|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037031241;MF=wanglin@open-hieco.net;NM=1;PH=DS;RN=15;RT=15;SR=0;TI=SMTPD_---.jIkm1oI_1789970175; Received: from localhost.localdomain(mailfrom:wanglin@open-hieco.net fp:SMTPD_---.jIkm1oI_1789970175 cluster:ay29) by smtp.aliyun-inc.com; Mon, 21 Sep 2026 13:56:16 +0800 From: Lin Wang To: Borislav Petkov , Yazen Ghannam , Mario Limonciello Cc: Pu Wen , Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Tony Luck , Clemens Ladisch , Guenter Roeck , x86@kernel.org, linux-edac@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 2/8] x86/hygon: Map CPU NodeIds to DF nodes Date: Mon, 21 Sep 2026 13:55:57 +0800 Message-ID: <20260921055603.25112-3-wanglin@open-hieco.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260921055603.25112-1-wanglin@open-hieco.net> References: <20260921055603.25112-1-wanglin@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On bare-metal Hygon systems, CPUID 0x8000001E ECX[7:0] encodes a CPU's socket and local CDD ordinal. The value is sparse across sockets and cannot directly index the dense DF node cache. Resolve the encoded socket and local ordinal against CDD entries in the cache, which are ordered by socket and DFID. The NodeId reported by CPUID in a guest may not describe the physical DF topology, so return -ENODEV in guests or when it does not identify an enumerated CDD. Signed-off-by: Lin Wang --- arch/x86/include/asm/hygon/node.h | 22 +++++++++++++ arch/x86/kernel/hygon_node.c | 55 +++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/arch/x86/include/asm/hygon/node.h b/arch/x86/include/asm/hygon= /node.h index b97eaee7c0d1..23af0d44a432 100644 --- a/arch/x86/include/asm/hygon/node.h +++ b/arch/x86/include/asm/hygon/node.h @@ -77,6 +77,23 @@ u16 hygon_cdd_num(void); */ int hygon_node_get_info(u16 node, struct hygon_node_info *info); =20 +/** + * hygon_cpu_to_df_node() - Map CPU to dense DF CDD index + * @cpu: CPU index + * + * Hygon Fam18h exposes sparse physical node IDs via CPUID 0x8000001E + * ECX[7:0]. + * This function translates the per-CPU physical node ID into a dense + * DF CDD index in [0, hygon_cdd_num()). The NodeId reported by CPUID in + * a guest may not describe the physical DF topology, so the translation + * is unavailable in guests. + * + * Return: DF CDD index on success, -EINVAL if @cpu is out of range, + * -ENODEV if CPU-to-DF mapping is unavailable or the physical node ID + * does not map to a known DF node. + */ +int hygon_cpu_to_df_node(unsigned int cpu); + /** * hygon_node_get_func() - Get DF function PCI device for a node * @node: DF node index in [0, hygon_node_num()) @@ -118,6 +135,11 @@ static inline int hygon_node_get_info(u16 node, struct= hygon_node_info *info) return -ENODEV; } =20 +static inline int hygon_cpu_to_df_node(unsigned int cpu) +{ + return -ENODEV; +} + static inline struct pci_dev *hygon_node_get_func(u16 node, u8 func) { return NULL; diff --git a/arch/x86/kernel/hygon_node.c b/arch/x86/kernel/hygon_node.c index e8346d86d8a6..8c21190a19c2 100644 --- a/arch/x86/kernel/hygon_node.c +++ b/arch/x86/kernel/hygon_node.c @@ -26,6 +26,7 @@ #include #include #include +#include =20 #include #include @@ -489,6 +490,44 @@ static int __init hygon_sort_and_classify(struct hygon= _node_cache *cache) return 0; } =20 +#define HYGON_NODE_ID_SOCKET GENMASK(7, 4) +#define HYGON_NODE_ID_LOCAL GENMASK(3, 0) + +/* + * Translate a Hygon Fam18h phys_node_id (CPUID 8000001E ECX[7:0]) to a + * dense DF CDD index. On supported models, CPUID reports this + * encoding: + * + * phys_node_id =3D (socket_id << 4) | local_cdd_index_in_dfid_order + * + * The cache->nodes[] CDD region is sorted by (socket_id ASC, dfid ASC), + * so walk it and return the actual cache index of the CDD whose + * socket_id matches and whose socket-local ordinal is @local. + * + * Return -ENODEV if the cache is unavailable or no CDD matches. + */ +static int hygon_phys_nid_to_df_node(unsigned int phys_nid) +{ + unsigned int socket, local, ordinal =3D 0; + u16 i; + + socket =3D FIELD_GET(HYGON_NODE_ID_SOCKET, phys_nid); + local =3D FIELD_GET(HYGON_NODE_ID_LOCAL, phys_nid); + + if (!hygon_cache.nodes) + return -ENODEV; + + for (i =3D 0; i < hygon_cache.num_cdd; i++) { + if (hygon_cache.nodes[i].socket_id !=3D socket) + continue; + + if (ordinal++ =3D=3D local) + return i; + } + + return -ENODEV; +} + static int __init hygon_build_cache(void) { struct hygon_node_cache cache =3D { }; @@ -544,6 +583,22 @@ int hygon_node_get_info(u16 node, struct hygon_node_in= fo *info) } EXPORT_SYMBOL_GPL(hygon_node_get_info); =20 +int hygon_cpu_to_df_node(unsigned int cpu) +{ + if (cpu >=3D nr_cpu_ids) + return -EINVAL; + + /* + * The NodeId reported by CPUID in a guest may not describe the + * physical DF topology. + */ + if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) + return -ENODEV; + + return hygon_phys_nid_to_df_node(topology_amd_node_id(cpu)); +} +EXPORT_SYMBOL_GPL(hygon_cpu_to_df_node); + struct pci_dev *hygon_node_get_func(u16 node, u8 func) { if (!hygon_cache.nodes) --=20 2.43.0 From nobody Thu Sep 24 20:37:28 2026 Received: from out28-149.mail.aliyun.com (out28-149.mail.aliyun.com [115.124.28.149]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E8A33546FA; Mon, 21 Sep 2026 05:56:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.149 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970189; cv=none; b=T4PzI9ri29II3a+bMibbpnSyCpUgzd+cZAJ0jUr6O3g0uUaanCDE4R/ESouvg2qQLfXEm6Mt2yNcrV7IYXfxEOPUeChWsG4hDeEFpg9sabE4hmLIjenEpMt9ZiCGgVKZvcMtV/Qtw0GgQqTZ9Flvh0T70mYD75SBxq9F1nxM0Sc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970189; c=relaxed/simple; bh=DGdpSE+D8407wX1lx027Mqkdmg7kS/OSqXBc5HGoFRk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LVElwqqeZJdd9E+J1a7gSO+yez/7GE92uI/SnIbam2OR9QexvUBLM9MJ042L8HUXva3rt7EiUVjjm4kp/gu8UR0CyPWUHYqtqlkdnIp/fnUfh5Xkrx0Jrl4lWDA8eYQYHuBgXYUuuOtu9dndSvxpJv6vc8YHxyCxNcAHjvFYt3E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.149 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.2095796|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.00854596-0.0196614-0.971793;FP=3456624572916909203|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037022039;MF=wanglin@open-hieco.net;NM=1;PH=DS;RN=15;RT=15;SR=0;TI=SMTPD_---.jIkm1py_1789970177; Received: from localhost.localdomain(mailfrom:wanglin@open-hieco.net fp:SMTPD_---.jIkm1py_1789970177 cluster:ay29) by smtp.aliyun-inc.com; Mon, 21 Sep 2026 13:56:18 +0800 From: Lin Wang To: Borislav Petkov , Yazen Ghannam , Mario Limonciello Cc: Pu Wen , Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Tony Luck , Clemens Ladisch , Guenter Roeck , x86@kernel.org, linux-edac@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/8] EDAC/amd64: Stop matching Hygon CPUs Date: Mon, 21 Sep 2026 13:55:58 +0800 Message-ID: <20260921055603.25112-4-wanglin@open-hieco.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260921055603.25112-1-wanglin@open-hieco.net> References: <20260921055603.25112-1-wanglin@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Hygon match predates the conversion of the AMD northbridge cache from PCI-ID discovery to topology-derived node counts and fixed PCI slots. That conversion removed the Hygon F3 discovery path. Hygon DF devices do not follow the fixed-slot layout, so the cache is discarded before amd64_edac can probe a memory controller. Removing the Hygon match therefore does not disable a working EDAC configuration. The Family 0x18 case becomes unused and is removed with the match. MCE decoding in mce_amd.c is independent and remains unchanged. Hygon memory controller support will use the Hygon node interfaces in a separate series. Signed-off-by: Lin Wang --- drivers/edac/amd64_edac.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 475235c402e8..9e35098d3dd2 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3840,9 +3840,6 @@ static int per_family_init(struct amd64_pvt *pvt) } break; =20 - case 0x18: - break; - case 0x19: switch (pvt->model) { case 0x00 ... 0x0f: @@ -4120,7 +4117,6 @@ static const struct x86_cpu_id amd64_cpuids[] =3D { X86_MATCH_VENDOR_FAM(AMD, 0x15, NULL), X86_MATCH_VENDOR_FAM(AMD, 0x16, NULL), X86_MATCH_VENDOR_FAM(AMD, 0x17, NULL), - X86_MATCH_VENDOR_FAM(HYGON, 0x18, NULL), X86_MATCH_VENDOR_FAM(AMD, 0x19, NULL), X86_MATCH_VENDOR_FAM(AMD, 0x1A, NULL), { } --=20 2.43.0 From nobody Thu Sep 24 20:37:28 2026 Received: from out28-121.mail.aliyun.com (out28-121.mail.aliyun.com [115.124.28.121]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A792364024; Mon, 21 Sep 2026 05:56:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.121 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970193; cv=none; b=tofG4iUgyNHzMzZu8akqSuYV6f+tna6YSBFwV0+OHXttlD1BUXHGlfo7qT3siUpt+gAHjigM9WcHY04u8Ld/NwQsPyOldNto240CX7yMYLOPrMV70AlAaMrWaE9Hh2LzDY1fG4/jAOw+h8BwX4HjToCsFf18xbSoZcbMaFhinXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970193; c=relaxed/simple; bh=HR7oYhW91ZwnoYD8zmXknGJwkQKZmCDelZbGRX2zOck=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qesnCPCADRZwUmgYRE2gDh+OPpayReFdarBQKRd5/XzrXKFSTwbbd025lfWG2+1sLqjADl3XAPRHsx/tLD++lZEf4VfCmR8wPEidZRVEYR/REmIxP7aGfsLMwFR8S4GL0uJr06EzH6m7+E8NxkI3KnItAksfx8XjYfxu8hkbxao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.121 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.2045835|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.0220792-0.18182-0.796101;FP=3290717549377439377|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033040074035;MF=wanglin@open-hieco.net;NM=1;PH=DS;RN=15;RT=15;SR=0;TI=SMTPD_---.jIkm1rS_1789970178; Received: from localhost.localdomain(mailfrom:wanglin@open-hieco.net fp:SMTPD_---.jIkm1rS_1789970178 cluster:ay29) by smtp.aliyun-inc.com; Mon, 21 Sep 2026 13:56:19 +0800 From: Lin Wang To: Borislav Petkov , Yazen Ghannam , Mario Limonciello Cc: Pu Wen , Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Tony Luck , Clemens Ladisch , Guenter Roeck , x86@kernel.org, linux-edac@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/8] RAS/AMD/ATL: Match AMD CPUs only Date: Mon, 21 Sep 2026 13:55:59 +0800 Message-ID: <20260921055603.25112-5-wanglin@open-hieco.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260921055603.25112-1-wanglin@open-hieco.net> References: <20260921055603.25112-1-wanglin@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ATL matches Hygon through X86_FEATURE_SMCA and X86_FEATURE_ZEN, but relies on the AMD northbridge cache for its node count and F4 devices. The cache uses fixed PCI slots that do not represent the Hygon topology. The cache is therefore discarded before ATL can register its decoder, so excluding Hygon from these feature matches does not disable a working address translation path. Qualify both feature matches with the AMD vendor. Hygon address translation will use the Hygon node interfaces in a separate series. Signed-off-by: Lin Wang --- drivers/ras/amd/atl/core.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/ras/amd/atl/core.c b/drivers/ras/amd/atl/core.c index d77dacdd4f56..fe84fc52c657 100644 --- a/drivers/ras/amd/atl/core.c +++ b/drivers/ras/amd/atl/core.c @@ -176,18 +176,17 @@ static void check_for_legacy_df_access(void) } =20 /* - * This library provides functionality for AMD-based systems with a Data F= abric. + * This library provides functionality for AMD systems with a Data Fabric. * The set of systems with a Data Fabric is equivalent to the set of Zen-b= ased systems * and the set of systems with the Scalable MCA feature at this time. Howe= ver, these * are technically independent things. * * It's possible to match on the PCI IDs of the Data Fabric devices, but t= his will be - * an ever expanding list. Instead, match on the SMCA and Zen features to = cover all - * relevant systems. + * an ever expanding list. Instead, match AMD CPUs with the SMCA and Zen f= eatures. */ static const struct x86_cpu_id amd_atl_cpuids[] =3D { - X86_MATCH_FEATURE(X86_FEATURE_SMCA, NULL), - X86_MATCH_FEATURE(X86_FEATURE_ZEN, NULL), + X86_MATCH_VENDOR_FEATURE(AMD, X86_FEATURE_SMCA, NULL), + X86_MATCH_VENDOR_FEATURE(AMD, X86_FEATURE_ZEN, NULL), { } }; =20 --=20 2.43.0 From nobody Thu Sep 24 20:37:28 2026 Received: from out28-52.mail.aliyun.com (out28-52.mail.aliyun.com [115.124.28.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 069C7366075; Mon, 21 Sep 2026 05:56:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970194; cv=none; b=MBjXEZpPEySUM8oVhbqG0JBfsYZgvdCbYNpzx6uniGlNEgiCeF7MQWG8IIukEeKwnSp/qw0dPEmHZV6YViXkMO+IHuZMPkH6RmXPPnvU6POGwHdgY5ZuI2/2BpgqfE74es39IUi3DuHmuny//Y4lAs5dRTQ5INmM4PCma37EZiI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970194; c=relaxed/simple; bh=NGDaMpWiNltodxcimxCk88oo3QIUlS8Ijo6xmvmMCaI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dk3imHfn9nPR8JGGrExgO1EFRVHg1amljcEUdB7dzK+Wvb1+FusUhLLr2j0N0YgbC2tTrd5S9POnmBHRmh4Jk1S/hyC445Zy6CGHZ0jB2d4gb6O29tzplbStghxXZedFCIyR+hLFDXw1cpvzczQVhUOw9a7YxYEStQk5SIhyDBQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07442075|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.0281794-0.00185859-0.969962;FP=11946942792445002263|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037028158;MF=wanglin@open-hieco.net;NM=1;PH=DS;RN=15;RT=15;SR=0;TI=SMTPD_---.jIkm1sn_1789970179; Received: from localhost.localdomain(mailfrom:wanglin@open-hieco.net fp:SMTPD_---.jIkm1sn_1789970179 cluster:ay29) by smtp.aliyun-inc.com; Mon, 21 Sep 2026 13:56:20 +0800 From: Lin Wang To: Borislav Petkov , Yazen Ghannam , Mario Limonciello Cc: Pu Wen , Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Tony Luck , Clemens Ladisch , Guenter Roeck , x86@kernel.org, linux-edac@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 5/8] hwmon: (k10temp) Stop matching Hygon devices Date: Mon, 21 Sep 2026 13:56:00 +0800 Message-ID: <20260921055603.25112-6-wanglin@open-hieco.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260921055603.25112-1-wanglin@open-hieco.net> References: <20260921055603.25112-1-wanglin@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" k10temp matches the Hygon F3 device, but derives the node passed to amd_smn_read() from the F3 PCI slot using the AMD fixed-slot mapping (slot - 0x18). Hygon PCI slots do not encode DF node identity, and their SMN roots are grouped by socket. The derived node number therefore cannot identify a valid Hygon SMN target or provide usable temperature monitoring. Removing the match does not disable a working monitoring path. Remove the Hygon PCI match and Family 0x18 branch. Hygon temperature monitoring will use the Hygon node and SMN interfaces in a separate series. Signed-off-by: Lin Wang --- Documentation/hwmon/k10temp.rst | 8 +++----- drivers/hwmon/k10temp.c | 5 ++--- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/Documentation/hwmon/k10temp.rst b/Documentation/hwmon/k10temp.= rst index 91b99adc6c48..9680c4f3383c 100644 --- a/Documentation/hwmon/k10temp.rst +++ b/Documentation/hwmon/k10temp.rst @@ -28,8 +28,6 @@ Supported chips: =20 * AMD Family 17h processors: "Zen", "Zen 2" =20 -* AMD Family 18h processors: "Hygon Dhyana" - * AMD Family 19h processors: "Zen 3" =20 Prefix: 'k10temp' @@ -128,7 +126,7 @@ it. Models from 17h family report relative temperature, the driver aims to compensate and report the real temperature. =20 -On Family 17h and Family 18h CPUs, additional temperature sensors may repo= rt -Core Complex Die (CCD) temperatures. Up to 8 such temperatures are reported -as temp{3..10}_input, labeled Tccd{1..8}. Actual support depends on the CPU +On Family 17h CPUs, additional temperature sensors may report Core Complex +Die (CCD) temperatures. Up to 8 such temperatures are reported as +temp{3..10}_input, labeled Tccd{1..8}. Actual support depends on the CPU variant. diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index 3e7e63edc6a3..e0a7211a513c 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -64,7 +64,7 @@ MODULE_PARM_DESC(force, "force loading on processors with= erratum 319"); #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 =20 -/* Common for Zen CPU families (Family 17h and 18h and 19h and 1Ah) */ +/* Common for Zen CPU families (Family 17h, 19h and 1Ah) */ #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800 =20 #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \ @@ -475,7 +475,7 @@ static int k10temp_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) data->read_tempreg =3D read_tempreg_pci; } =20 - if (boot_cpu_data.x86 =3D=3D 0x17 || boot_cpu_data.x86 =3D=3D 0x18) { + if (boot_cpu_data.x86 =3D=3D 0x17) { switch (boot_cpu_data.x86_model) { case 0x1: /* Zen */ case 0x8: /* Zen+ */ @@ -583,7 +583,6 @@ static const struct pci_device_id k10temp_id_table[] = =3D { { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3) }, { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3) }, { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M90H_DF_F3) }, - { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, {} }; MODULE_DEVICE_TABLE(pci, k10temp_id_table); --=20 2.43.0 From nobody Thu Sep 24 20:37:28 2026 Received: from out198-18.us.a.mail.aliyun.com (out198-18.us.a.mail.aliyun.com [47.90.198.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8997B365A0F; Mon, 21 Sep 2026 05:56:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970205; cv=none; b=VDHDfOg3BY/4Z0gPZyM4We1H2RFAfW4CEQyamxDlLRsaxfjXgXwBwe6P3O4fZ9GB/MO6R7wZDOji6oFKxx/qtJf2RXaa4NxjX2aPI3yCFPzPTsVQkrLN/AlbS9I7nzer+E69JXr7LbWWxE2q+LGawdXt8wf9wCFpdXE68+fbvkU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970205; c=relaxed/simple; bh=Y19hvtuGGIPWGRHUaLnout1jeLW6wcOtdMLMoTiH57s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=O13YYrw08YHHWnTgdZfJntRKqIjeh2Hwyqt9nzShpwSdCeThZ8X8jLB4nM1QuxL+hg9kep+2BbG8sFUdVsZCK3oFe1H7vecFsVjHZHBXLy9XxQPQwjtVQHNJGDs/La6VJM0cS6LwR5hj6YWRfOKOjSrKCEULfk0u/SYxbaYxjXw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=47.90.198.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.105473|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.00706148-0.0109065-0.982032;FP=5300217843762596315|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037022039;MF=wanglin@open-hieco.net;NM=1;PH=DS;RN=15;RT=15;SR=0;TI=SMTPD_---.jIkm1uO_1789970180; Received: from localhost.localdomain(mailfrom:wanglin@open-hieco.net fp:SMTPD_---.jIkm1uO_1789970180 cluster:ay29) by smtp.aliyun-inc.com; Mon, 21 Sep 2026 13:56:21 +0800 From: Lin Wang To: Borislav Petkov , Yazen Ghannam , Mario Limonciello Cc: Pu Wen , Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Tony Luck , Clemens Ladisch , Guenter Roeck , x86@kernel.org, linux-edac@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 6/8] x86/amd_nb: Restrict the northbridge framework to AMD CPUs Date: Mon, 21 Sep 2026 13:56:01 +0800 Message-ID: <20260921055603.25112-7-wanglin@open-hieco.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260921055603.25112-1-wanglin@open-hieco.net> References: <20260921055603.25112-1-wanglin@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AMD northbridge cache previously discovered Hygon F3 devices by PCI ID. It now derives the node count from CPU topology and locates node functions at fixed PCI slots. Hygon DF devices do not follow that layout, so the Hygon branch no longer builds a usable cache. amd64_edac and ATL no longer use this cache on Hygon. Restrict northbridge initialization and the early northbridge check to AMD CPUs. Keep amd_get_mmconfig_range() available on Hygon because it reads the MMCONFIG MSR without using the northbridge cache. Signed-off-by: Lin Wang Reviewed-by: Yazen Ghannam --- arch/x86/kernel/amd_nb.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 5d364540673d..848ed2ca17c3 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -125,8 +125,7 @@ bool __init early_is_amd_nb(u32 device) const struct pci_device_id *id; u32 vendor =3D device & 0xffff; =20 - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD && - boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON) + if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD) return false; =20 if (cpu_feature_enabled(X86_FEATURE_ZEN)) @@ -315,8 +314,7 @@ static __init void fix_erratum_688(void) =20 static __init int init_amd_nbs(void) { - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD && - boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON) + if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD) return 0; =20 amd_cache_northbridges(); --=20 2.43.0 From nobody Thu Sep 24 20:37:28 2026 Received: from out28-4.mail.aliyun.com (out28-4.mail.aliyun.com [115.124.28.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 909BB367F36; Mon, 21 Sep 2026 05:56:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970196; cv=none; b=tqFeGOmlm/mAyBC7ZjmyF0XlxuTkq9VzuY/Y3TWuAu/7qJ12/4D5hIM1uufiIyJ+NRi9mW09acZQz1sYCNedzieKx/HPqTd8hF0EOGQYu/AxZNI6ELZSic/Ojcmb4sYyR1l4+Yrfqn07Y3xLQSzb0donAf1/4qpS3YhOaxIyAk8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970196; c=relaxed/simple; bh=bkvlccMVkNJNgMPa5KZtN0Rj9B2vVWUR+4ZVGEMptx0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MscxUk5c6j9SQksbQTDRo+hOBHTbr3xGw9V7LjHN8mAvu7uAzhQ2l9li3JPFTQ+pXv1u9ktZf02VuTmDA3ZJt9+NnADKHaLQFkYD7FL9O1ek4YoOx5OiLCP76GNR9uPbKVg7/vZVKPGxfPqQpXBx+LcmpVoeVHx3vHDm+fZIYz8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.08401445|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.00227817-0.00107444-0.996647;FP=6920001056461840522|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037071049;MF=wanglin@open-hieco.net;NM=1;PH=DS;RN=15;RT=15;SR=0;TI=SMTPD_---.jIkm1vY_1789970182; Received: from localhost.localdomain(mailfrom:wanglin@open-hieco.net fp:SMTPD_---.jIkm1vY_1789970182 cluster:ay29) by smtp.aliyun-inc.com; Mon, 21 Sep 2026 13:56:23 +0800 From: Lin Wang To: Borislav Petkov , Yazen Ghannam , Mario Limonciello Cc: Pu Wen , Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Tony Luck , Clemens Ladisch , Guenter Roeck , x86@kernel.org, linux-edac@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 7/8] x86/amd_node: Restrict SMN setup to AMD CPUs Date: Mon, 21 Sep 2026 13:56:02 +0800 Message-ID: <20260921055603.25112-8-wanglin@open-hieco.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260921055603.25112-1-wanglin@open-hieco.net> References: <20260921055603.25112-1-wanglin@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" amd_smn_init() divides host bridge roots among amd_num_nodes() entries in PCI enumeration order. Hygon DF nodes instead share one SMN ingress per socket, so the AMD root map cannot provide Hygon SMN access. amd64_edac, ATL and k10temp no longer depend on AMD northbridge or SMN state on Hygon. Restrict AMD SMN setup and root discovery to AMD CPUs, leaving the Hygon roots available for the Hygon node layer. Signed-off-by: Lin Wang --- arch/x86/kernel/amd_node.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/amd_node.c b/arch/x86/kernel/amd_node.c index b7926ba3610a..c36b410d04a4 100644 --- a/arch/x86/kernel/amd_node.c +++ b/arch/x86/kernel/amd_node.c @@ -229,8 +229,7 @@ static struct pci_dev *get_next_root(struct pci_dev *ro= ot) if (root->devfn) continue; =20 - if (root->vendor !=3D PCI_VENDOR_ID_AMD && - root->vendor !=3D PCI_VENDOR_ID_HYGON) + if (root->vendor !=3D PCI_VENDOR_ID_AMD) continue; =20 break; @@ -253,6 +252,9 @@ static int __init amd_smn_init(void) u16 count, num_roots, roots_per_node, node, num_nodes; struct pci_dev *root __free(pci_dev_put) =3D NULL; =20 + if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD) + return 0; + if (!cpu_feature_enabled(X86_FEATURE_ZEN)) return 0; =20 --=20 2.43.0 From nobody Thu Sep 24 20:37:28 2026 Received: from out28-74.mail.aliyun.com (out28-74.mail.aliyun.com [115.124.28.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 781D0369D66; Mon, 21 Sep 2026 05:56:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970197; cv=none; b=oPWgPFcCD4WRCx9/sh3gleMmmfjBnQhRfFh3XuF5eAQAxmi7GN+eluCNzU3w1yKVDUymx9o9NuqQV/fDABldQvNvsJ7DAPI4GIkmvkCulq/sNcXeN03kpcYODp+lyTX1M/SQHhBmqzZxhgyqWK9ScgT+FW1H25vbp3SddgyD+F8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789970197; c=relaxed/simple; bh=gAXN7vJN3KL194iCrO3inFV0GNoyn37f9MiEYQVUpB0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Li9mfRpS1u0VBkhYM4nzCcppZdgmg+nNUOngwVUZTyN1xfN4kjD4epxyPCJqOpyffCo+QKA9SkIOcr0v4QbbPcTGjByjGzUGobiVT/OroBpOLwq3Omr/CAJoeVAqK1FgmmHEjwQN3ptvhDWLj2KcqWlfu5rZZNnAFg6+8hSc914= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436259|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.00852627-4.91589e-05-0.991425;FP=18014799132210578666|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033023018039;MF=wanglin@open-hieco.net;NM=1;PH=DS;RN=15;RT=15;SR=0;TI=SMTPD_---.jIkm1x1_1789970183; Received: from localhost.localdomain(mailfrom:wanglin@open-hieco.net fp:SMTPD_---.jIkm1x1_1789970183 cluster:ay29) by smtp.aliyun-inc.com; Mon, 21 Sep 2026 13:56:24 +0800 From: Lin Wang To: Borislav Petkov , Yazen Ghannam , Mario Limonciello Cc: Pu Wen , Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Tony Luck , Clemens Ladisch , Guenter Roeck , x86@kernel.org, linux-edac@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 8/8] x86/hygon: Add Family 0x18 SMN access Date: Mon, 21 Sep 2026 13:56:03 +0800 Message-ID: <20260921055603.25112-9-wanglin@open-hieco.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260921055603.25112-1-wanglin@open-hieco.net> References: <20260921055603.25112-1-wanglin@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hygon Family 0x18 DF nodes in a socket share an SMN ingress. The root groups therefore need to be associated with sockets before they can be expanded to the dense DF node indices. Build the node-to-root map after DF enumeration. Retain a reference to and reserve PCI config space for every enumerated root, and serialize each index/data transaction. Make Hygon SMN access available only after setup succeeds; a failure leaves the DF node cache usable without SMN access. Signed-off-by: Lin Wang --- arch/x86/include/asm/hygon/node.h | 40 ++++- arch/x86/kernel/hygon_node.c | 248 +++++++++++++++++++++++++++++- 2 files changed, 285 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/hygon/node.h b/arch/x86/include/asm/hygon= /node.h index 23af0d44a432..a2048f552d02 100644 --- a/arch/x86/include/asm/hygon/node.h +++ b/arch/x86/include/asm/hygon/node.h @@ -2,8 +2,8 @@ /* * Hygon Family 0x18 Data Fabric node enumeration API * - * This header declares Hygon Fam18h DF node enumeration and function - * access interfaces. + * DF node identity, CPU-to-DF-node translation, DF function lookup and + * SMN access for Hygon Family 0x18. */ #ifndef _ASM_X86_HYGON_NODE_H #define _ASM_X86_HYGON_NODE_H @@ -118,6 +118,30 @@ struct pci_dev *hygon_node_get_func(u16 node, u8 func); */ int hygon_pci_dev_to_df_node(struct pci_dev *pdev); =20 +/** + * hygon_smn_read() - Read a 32-bit value from a Hygon SMN address + * @node: DF node index in [0, hygon_node_num()) + * @address: SMN address + * @value: Output value + * + * Return: 0 on success, -EINVAL if @value is NULL, -ENODEV if Hygon + * SMN is not initialized or @node is out of range, or a negative + * errno from the underlying PCI config access. + */ +int __must_check hygon_smn_read(u16 node, u32 address, u32 *value); + +/** + * hygon_smn_write() - Write a 32-bit value to a Hygon SMN address + * @node: DF node index in [0, hygon_node_num()) + * @address: SMN address + * @value: Value to write + * + * Return: 0 on success, -ENODEV if Hygon SMN is not initialized or + * @node is out of range, or a negative errno from the underlying + * PCI config access. + */ +int __must_check hygon_smn_write(u16 node, u32 address, u32 value); + #else /* !CONFIG_HYGON_NODE */ =20 static inline u16 hygon_node_num(void) @@ -150,6 +174,18 @@ static inline int hygon_pci_dev_to_df_node(struct pci_= dev *pdev) return -ENODEV; } =20 +static inline int __must_check hygon_smn_read(u16 node, u32 address, + u32 *value) +{ + return -ENODEV; +} + +static inline int __must_check hygon_smn_write(u16 node, u32 address, + u32 value) +{ + return -ENODEV; +} + #endif /* CONFIG_HYGON_NODE */ =20 #endif /* _ASM_X86_HYGON_NODE_H */ diff --git a/arch/x86/kernel/hygon_node.c b/arch/x86/kernel/hygon_node.c index 8c21190a19c2..6aeea04c30f2 100644 --- a/arch/x86/kernel/hygon_node.c +++ b/arch/x86/kernel/hygon_node.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hygon Family 0x18 Data Fabric node enumeration + * Hygon Family 0x18 Data Fabric node enumeration and SMN access * * A DF instance exposes sibling PCI functions in one slot. Function 3 * is the misc device used for enumeration, function 4 is the link @@ -17,10 +17,12 @@ =20 #include #include +#include #include #include #include #include +#include #include #include #include @@ -641,6 +643,246 @@ int hygon_pci_dev_to_df_node(struct pci_dev *pdev) } EXPORT_SYMBOL_GPL(hygon_pci_dev_to_df_node); =20 +/* + * SMN index/data register pair offsets in the host-bridge PCI config + * space. Reads and writes to a (node, address) pair are issued as a + * two-step transaction: write the SMN address to the index register, + * then read or write the value at the data register. + */ +#define HYGON_SMN_INDEX_OFFSET 0x60 +#define HYGON_SMN_DATA_OFFSET 0x64 + +/* + * Runtime SMN state. + * + * The hygon_smn_reserved_roots array owns the independent PCI references = and + * config-space reservations for the lifetime of the built-in node layer. = The + * hygon_smn_roots array contains per-node aliases and is published only a= fter + * setup succeeds. + */ +static struct pci_dev **hygon_smn_roots; +static struct pci_dev **hygon_smn_reserved_roots; +static u16 hygon_smn_num_nodes; +static DEFINE_MUTEX(hygon_smn_mutex); + +/* Internal cache accessors used by SMN setup. */ +static u8 __init hygon_node_socket(u16 node) +{ + if (!hygon_cache.nodes || node >=3D hygon_cache.num_nodes) + return U8_MAX; + return hygon_cache.nodes[node].socket_id; +} + +static u16 __init hygon_socket_num(void) +{ + return hygon_cache.num_sockets; +} + +/* + * Walk PCI host-bridge devices matching the Hygon vendor. The SMN + * index/data registers live in function 0 of each root complex. This + * follows pci_get_class() iterator semantics: @root is consumed and the + * returned device has an iterator reference. A retained device needs an + * independent reference before the iterator advances. + */ +static struct pci_dev * __init hygon_get_next_root(struct pci_dev *root) +{ + while ((root =3D pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, root))) { + if (root->devfn) + continue; + if (root->vendor !=3D PCI_VENDOR_ID_HYGON) + continue; + break; + } + return root; +} + +/* Release each config region before dropping its owning device reference.= */ +static void __init hygon_release_reserved_roots(struct pci_dev **roots, + u16 count) +{ + u16 i; + + for (i =3D 0; i < count; i++) { + pci_release_config_region(roots[i], 0, PCI_CFG_SPACE_SIZE); + pci_dev_put(roots[i]); + } +} + +/* + * Select one root from each contiguous per-socket enumeration group, + * then map every DF node to the root for its socket. The root socket ID + * cannot be read back, so the grouping follows PCI enumeration order. + * + * The hygon_smn_reserved_roots array owns the PCI references and config + * regions. The hygon_smn_roots array contains per-node aliases. Enable SMN + * access only after both arrays are complete. + */ +static int __init hygon_smn_setup(void) +{ + u16 num_roots, roots_per_socket, node, num_nodes, num_sockets, reserved; + struct pci_dev **reserved_roots, **roots; + struct pci_dev *root =3D NULL; + u8 socket_id; + int ret; + + num_roots =3D 0; + while ((root =3D hygon_get_next_root(root))) + num_roots++; + + pr_debug("Found %u Hygon SMN root devices\n", num_roots); + + if (!num_roots) + return -ENODEV; + + num_nodes =3D hygon_node_num(); + if (!num_nodes) + return -ENODEV; + + num_sockets =3D hygon_socket_num(); + if (!num_sockets) + return -ENODEV; + + if (num_roots % num_sockets) { + pr_err("Root count %u not divisible by socket count %u\n", + num_roots, num_sockets); + return -ENODEV; + } + + roots =3D kcalloc(num_nodes, sizeof(*roots), GFP_KERNEL); + if (!roots) + return -ENOMEM; + + reserved_roots =3D kcalloc(num_roots, sizeof(*reserved_roots), + GFP_KERNEL); + if (!reserved_roots) { + kfree(roots); + return -ENOMEM; + } + + /* Reserve every root before publishing the node-to-root mapping. */ + roots_per_socket =3D num_roots / num_sockets; + reserved =3D 0; + while ((root =3D hygon_get_next_root(root))) { + if (reserved >=3D num_roots) { + ret =3D -ENODEV; + goto err_release; + } + + pci_dbg(root, "Reserving PCI config space\n"); + + /* + * Mark the entire PCI config space kernel-exclusive because it + * contains the SMN index/data registers. + */ + if (!pci_request_config_region_exclusive(root, 0, + PCI_CFG_SPACE_SIZE, + NULL)) { + pci_err(root, "Failed to reserve config space\n"); + ret =3D -EEXIST; + goto err_release; + } + + reserved_roots[reserved++] =3D pci_dev_get(root); + } + + if (reserved !=3D num_roots) { + pr_err("Root enumeration changed: expected %u roots, got %u\n", + num_roots, reserved); + ret =3D -ENODEV; + goto err_release; + } + + for (node =3D 0; node < num_nodes; node++) { + socket_id =3D hygon_node_socket(node); + + if (socket_id >=3D num_sockets) { + ret =3D -ENODEV; + goto err_release; + } + + roots[node] =3D reserved_roots[socket_id * roots_per_socket]; + + pci_dbg(roots[node], + "is root for Hygon node %u (socket %u)\n", + node, socket_id); + } + + hygon_smn_reserved_roots =3D reserved_roots; + hygon_smn_num_nodes =3D num_nodes; + hygon_smn_roots =3D roots; + return 0; + +err_release: + pci_dev_put(root); + hygon_release_reserved_roots(reserved_roots, reserved); + kfree(reserved_roots); + kfree(roots); + return ret; +} + +/* + * Serialize the PCI index/data pair between in-kernel SMN users. + * The access sequence follows amd_smn_read() and amd_smn_write(). + * The Hygon node-to-root mapping comes from hygon_smn_setup(). + */ +static int __hygon_smn_rw(u16 node, u32 address, u32 *value, bool write) +{ + struct pci_dev *root; + int err; + + if (!hygon_smn_roots || node >=3D hygon_smn_num_nodes) + return -ENODEV; + + root =3D hygon_smn_roots[node]; + if (!root) + return -ENODEV; + + guard(mutex)(&hygon_smn_mutex); + + err =3D pci_write_config_dword(root, HYGON_SMN_INDEX_OFFSET, address); + if (err) { + pr_warn("SMN index write failed (addr 0x%x)\n", address); + return pcibios_err_to_errno(err); + } + + err =3D write ? pci_write_config_dword(root, HYGON_SMN_DATA_OFFSET, *valu= e) + : pci_read_config_dword(root, HYGON_SMN_DATA_OFFSET, value); + + return pcibios_err_to_errno(err); +} + +int hygon_smn_read(u16 node, u32 address, u32 *value) +{ + int err; + + if (!value) + return -EINVAL; + + err =3D __hygon_smn_rw(node, address, value, false); + + /* Clear the output so callers do not consume a stale value. */ + if (err) { + *value =3D 0; + return err; + } + + /* Treat the PCI all-ones value as a missing device. */ + if (PCI_POSSIBLE_ERROR(*value)) { + *value =3D 0; + return -ENODEV; + } + + return 0; +} +EXPORT_SYMBOL_GPL(hygon_smn_read); + +int hygon_smn_write(u16 node, u32 address, u32 value) +{ + return __hygon_smn_rw(node, address, &value, true); +} +EXPORT_SYMBOL_GPL(hygon_smn_write); + static int __init hygon_node_init(void) { int ret; @@ -659,6 +901,10 @@ static int __init hygon_node_init(void) hygon_cache.num_nodes - hygon_cache.num_cdd, hygon_cache.num_sockets); =20 + ret =3D hygon_smn_setup(); + if (ret) + pr_warn("SMN setup failed: %d\n", ret); + return 0; } fs_initcall(hygon_node_init); --=20 2.43.0