From nobody Fri Sep 25 21:04:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40361493D44; Mon, 21 Sep 2026 12:27:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789993648; cv=none; b=BOuLi0FXPuDYfyg217r18hAklHSXtYKhEo+7WJdYSDhkmg2/zc+3+MLxWxLnjvXJv/MZAcM/dFvuKiaO0PbQMv7LsO8zolNbx6q1Bkx3bN4v4MeXaUOzGcYc36UHWGbkJt7VuUn+lY4MgNkjnuO62TPoQEw0AC4DDMJG5JhCccA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789993648; c=relaxed/simple; bh=nlX8+ZEvmtGvscRdSJ9FwPw4/iLV4sfdeuARDFxL3SU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QuTQZPPo2UuP5cZ7IXJfub4xhZ3IWl+wJBfQl1F8ziieJ+OqEeswdFfQyidWYBvhjXWoNvJCVN6Zl40AXDuzei7e2y2xJrhvrgRScWI3uLqmryt4b3bL6L2mdD5s/GP+fSDajEkNWoelPmRzS9tEG+aR2KyFGoPplcrgDLidS1c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Z601kbIa; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Z601kbIa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BA3511F00893; Mon, 21 Sep 2026 12:27:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789993646; bh=dFvHrjq0ePXXh5iBLlUENtWHcaZyZBRhrnp1IAHS2tI=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Z601kbIa9VSfIfHNKTEpmBalJufxQA/bArlgRDVF37yrMBOBoyWhpgkWJ+Xut1PKi o6gEp2mkBaghr4j1DpATyzKBQp8qZURn6Tk7m/fmazSpf80LqYSkrFxphZ6oomow1I 5eWkwReNwMc84goCHDydh0J8BbTrCBIbjqpyREhZpOv5nZiN9qUOqlnqYSHpqd4Sr2 hnoXYXL+c4TqRz3nxQofwUHM5o9qn5+6FXmGnQiPUzFMlE8Kv+JqPCvuuYXZApTZ3a ifkNNg8icwnqKOL8v+vqV9bRlwaOFIckKtpCQPVzreuSnB7DiB4SyRneQ4+dlrs4UV 1DOwgBQDoZlOQ== From: "GUO Ren (XuanTie)" Date: Mon, 21 Sep 2026 12:27:01 +0000 Subject: [PATCH RFC v4 1/4] RISC-V: paravirt: Add pvqspinlock KVM backend Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-pvqspinlock-v4-1-409a22aed6ef@kernel.org> References: <20260921-pvqspinlock-v4-0-409a22aed6ef@kernel.org> In-Reply-To: <20260921-pvqspinlock-v4-0-409a22aed6ef@kernel.org> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Shuah Khan , Randy Dunlap , Fangyu Yu , CHEN Jiankang Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Leonardo Bras , "GUO Ren (XuanTie)" X-Mailer: b4 0.16.0 Add the KVM backend for the SBI PVLOCK (paravirt qspinlock kick_cpu) extension. kvm_sbi_ext_pvlock_kick_cpu() kicks the target vCPU out of the halted state via kvm_vcpu_kick(), and yields to it with kvm_vcpu_yield_to() when the target is already runnable. Reviewed-by: Leonardo Bras Signed-off-by: GUO Ren (XuanTie) --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 + arch/riscv/include/asm/sbi.h | 5 ++++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu_sbi.c | 4 +++ arch/riscv/kvm/vcpu_sbi_pvlock.c | 54 +++++++++++++++++++++++++++++++= ++++ 6 files changed, 66 insertions(+) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index f01a2860c751..cdc16e64ad19 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -114,6 +114,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext= _fwft; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_mpxy; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pvlock; =20 #ifdef CONFIG_RISCV_PMU_SBI extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu; diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 5725e0ca4dda..724ab834ad85 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -38,6 +38,7 @@ enum sbi_ext_id { SBI_EXT_FWFT =3D 0x46574654, SBI_EXT_MPXY =3D 0x4D505859, SBI_EXT_DBTR =3D 0x44425452, + SBI_EXT_PVLOCK =3D 0x50564C4B, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -534,6 +535,10 @@ union sbi_dbtr_shmem_entry { struct sbi_dbtr_id_msg id; }; =20 +enum sbi_ext_pvlock_fid { + SBI_EXT_PVLOCK_KICK_CPU =3D 0, +}; + /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 20d9959ca44f..110a0d62113f 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -228,6 +228,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_SUSP, KVM_RISCV_SBI_EXT_FWFT, KVM_RISCV_SBI_EXT_MPXY, + KVM_RISCV_SBI_EXT_PVLOCK, KVM_RISCV_SBI_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 296c2ba05089..404a4c5f8984 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -38,6 +38,7 @@ kvm-y +=3D vcpu_sbi_sta.o kvm-y +=3D vcpu_sbi_system.o kvm-$(CONFIG_RISCV_SBI_V01) +=3D vcpu_sbi_v01.o kvm-y +=3D vcpu_switch.o +kvm-y +=3D vcpu_sbi_pvlock.o kvm-y +=3D vcpu_timer.o kvm-y +=3D vcpu_vector.o kvm-y +=3D vm.o diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 1c4f874368fb..07f72e619fd5 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -94,6 +94,10 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ex= t[] =3D { .ext_idx =3D KVM_RISCV_SBI_EXT_VENDOR, .ext_ptr =3D &vcpu_sbi_ext_vendor, }, + { + .ext_idx =3D KVM_RISCV_SBI_EXT_PVLOCK, + .ext_ptr =3D &vcpu_sbi_ext_pvlock, + }, }; =20 static const struct kvm_riscv_sbi_extension_entry * diff --git a/arch/riscv/kvm/vcpu_sbi_pvlock.c b/arch/riscv/kvm/vcpu_sbi_pvl= ock.c new file mode 100644 index 000000000000..728e59f3f18f --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi_pvlock.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 GUO Ren (XuanTie) + */ + +#include +#include +#include +#include +#include + +static int kvm_sbi_ext_pvlock_kick_cpu(struct kvm_vcpu *vcpu) +{ + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + struct kvm *kvm =3D vcpu->kvm; + struct kvm_vcpu *target; + + target =3D kvm_get_vcpu_by_id(kvm, cp->a0); + if (!target) + return SBI_ERR_INVALID_PARAM; + + kvm_vcpu_kick(target); + + if (READ_ONCE(target->ready)) + kvm_vcpu_yield_to(target); + + return SBI_SUCCESS; +} + +static int kvm_sbi_ext_pvlock_handler(struct kvm_vcpu *vcpu, struct kvm_ru= n *run, + struct kvm_vcpu_sbi_return *retdata) +{ + int ret =3D 0; + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + unsigned long funcid =3D cp->a6; + + switch (funcid) { + case SBI_EXT_PVLOCK_KICK_CPU: + ret =3D kvm_sbi_ext_pvlock_kick_cpu(vcpu); + break; + default: + ret =3D SBI_ERR_NOT_SUPPORTED; + } + + retdata->err_val =3D ret; + + return 0; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pvlock =3D { + .extid_start =3D SBI_EXT_PVLOCK, + .extid_end =3D SBI_EXT_PVLOCK, + .handler =3D kvm_sbi_ext_pvlock_handler, +}; --=20 2.43.0 From nobody Fri Sep 25 21:04:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A66474973A3; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FizKey6A" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BCA321F000FF; Mon, 21 Sep 2026 12:27:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789993652; bh=ZL+jHBhm3Lazx2elITuFIbb5JJW3ttCHLqLMtnrVQrE=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=FizKey6Agi7E+O7B943oOu9OU8rX9A6+d+R5RAdFZstk/eu0fKvoM8/gcUDsap1QM v8HwFrI7KOQdTw7ftgDofA98CMyyMWD4kb/zvBUdBOFAG4la7VzUcYt+0YiZKfLf9F TJvD2cqFvmVk5DBDZSbg6LqVxKjYX6gOFaGa3SQv4Mf+W+CMruCT1Nto8PQIAHha7d eu/TXsUvKj7jSAMJwAFaMVEUuYe9jlpFyiskfVZgnj9SljcwikOLG8YisyIB437ldQ 1v59Rdmf5jezzqvjwlPUCjNb3bd5F1Y6/Ot3zoDZWvYc+qnNsehKJHs8umS3XPqE91 OkpvmJ8Tm2sLA== From: "GUO Ren (XuanTie)" Date: Mon, 21 Sep 2026 12:27:02 +0000 Subject: [PATCH RFC v4 2/4] RISC-V: paravirt: Add pvqspinlock frontend Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-pvqspinlock-v4-2-409a22aed6ef@kernel.org> References: <20260921-pvqspinlock-v4-0-409a22aed6ef@kernel.org> In-Reply-To: <20260921-pvqspinlock-v4-0-409a22aed6ef@kernel.org> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Shuah Khan , Randy Dunlap , Fangyu Yu , CHEN Jiankang Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Leonardo Bras , "GUO Ren (XuanTie)" X-Mailer: b4 0.16.0 Add a virtualization-friendly unfair qspinlock frontend that halts the virtual CPU instead of spinning. Use static_call to switch between: native_queued_spin_lock_slowpath() __pv_queued_spin_lock_slowpath() native_queued_spin_unlock() __pv_queued_spin_unlock() Add the pv_wait and pv_kick implementations. Reviewed-by: Leonardo Bras Signed-off-by: GUO Ren (XuanTie) --- arch/riscv/Kconfig | 12 ++++++ arch/riscv/include/asm/Kbuild | 1 - arch/riscv/include/asm/qspinlock.h | 33 ++++++++++++++ arch/riscv/include/asm/qspinlock_paravirt.h | 26 +++++++++++ arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/qspinlock_paravirt.c | 67 +++++++++++++++++++++++++= ++++ arch/riscv/kernel/setup.c | 5 +++ 7 files changed, 145 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d6c2dbf8455c..9af53ef5ee95 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -1165,6 +1165,18 @@ config PARAVIRT_TIME_ACCOUNTING =20 If in doubt, say N here. =20 +config PARAVIRT_SPINLOCKS + bool "Paravirtualization layer for spinlocks" + depends on QUEUED_SPINLOCKS + default y + help + Paravirtualized spinlocks allow a unfair qspinlock to replace the + test-set kvm-guest virt spinlock implementation with something + virtualization-friendly, for example, halt the virtual CPU rather + than spinning. + + If you are unsure how to answer this question, answer Y. + config RELOCATABLE bool "Build a relocatable kernel" select MODULE_SECTIONS if MODULES diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 7721b63642f4..3d8800d4fe48 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -13,7 +13,6 @@ generic-y +=3D spinlock_types.h generic-y +=3D ticket_spinlock.h generic-y +=3D qrwlock.h generic-y +=3D qrwlock_types.h -generic-y +=3D qspinlock.h generic-y +=3D ring_buffer.h generic-y +=3D user.h generic-y +=3D vmlinux.lds.h diff --git a/arch/riscv/include/asm/qspinlock.h b/arch/riscv/include/asm/qs= pinlock.h new file mode 100644 index 000000000000..330b714edc44 --- /dev/null +++ b/arch/riscv/include/asm/qspinlock.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 GUO Ren (XuanTie) + */ + +#ifndef _ASM_RISCV_QSPINLOCK_H +#define _ASM_RISCV_QSPINLOCK_H + +#ifdef CONFIG_PARAVIRT_SPINLOCKS +#include + +/* How long a lock should spin before we consider blocking */ +#define SPIN_THRESHOLD (1 << 15) + +void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val); +void __pv_init_lock_hash(void); +void __pv_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val); + +static inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 v= al) +{ + static_call(pv_queued_spin_lock_slowpath)(lock, val); +} + +#define queued_spin_unlock queued_spin_unlock +static inline void queued_spin_unlock(struct qspinlock *lock) +{ + static_call(pv_queued_spin_unlock)(lock); +} +#endif /* CONFIG_PARAVIRT_SPINLOCKS */ + +#include + +#endif /* _ASM_RISCV_QSPINLOCK_H */ diff --git a/arch/riscv/include/asm/qspinlock_paravirt.h b/arch/riscv/inclu= de/asm/qspinlock_paravirt.h new file mode 100644 index 000000000000..7261cd9b13b2 --- /dev/null +++ b/arch/riscv/include/asm/qspinlock_paravirt.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 GUO Ren (XuanTie) + */ + +#ifndef _ASM_RISCV_QSPINLOCK_PARAVIRT_H +#define _ASM_RISCV_QSPINLOCK_PARAVIRT_H + +void pv_wait(u8 *ptr, u8 val); +void pv_kick(int cpu); + +void dummy_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val); +void dummy_queued_spin_unlock(struct qspinlock *lock); + +DECLARE_STATIC_CALL(pv_queued_spin_lock_slowpath, dummy_queued_spin_lock_s= lowpath); +DECLARE_STATIC_CALL(pv_queued_spin_unlock, dummy_queued_spin_unlock); + +bool __init pv_qspinlock_init(void); + +void __pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked); + +bool pv_is_native_spin_unlock(void); + +void __pv_queued_spin_unlock(struct qspinlock *lock); + +#endif /* _ASM_RISCV_QSPINLOCK_PARAVIRT_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index ebe1c3588177..b9b0763dba32 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -130,3 +130,5 @@ obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) +=3D bugs.o obj-$(CONFIG_RISCV_USER_CFI) +=3D usercfi.o =20 obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos.o + +obj-$(CONFIG_PARAVIRT_SPINLOCKS) +=3D qspinlock_paravirt.o diff --git a/arch/riscv/kernel/qspinlock_paravirt.c b/arch/riscv/kernel/qsp= inlock_paravirt.c new file mode 100644 index 000000000000..c534447437fe --- /dev/null +++ b/arch/riscv/kernel/qspinlock_paravirt.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 GUO Ren (XuanTie) + */ + +#include +#include +#include + +void pv_kick(int cpu) +{ + sbi_ecall(SBI_EXT_PVLOCK, SBI_EXT_PVLOCK_KICK_CPU, + cpuid_to_hartid_map(cpu), 0, 0, 0, 0, 0); +} + +void pv_wait(u8 *ptr, u8 val) +{ + unsigned long flags; + + if (in_nmi()) + return; + + local_irq_save(flags); + if (READ_ONCE(*ptr) !=3D val) + goto out; + + wait_for_interrupt(); +out: + local_irq_restore(flags); +} + +static void native_queued_spin_unlock(struct qspinlock *lock) +{ + /* + * unlock() needs release semantics: + */ + smp_store_release(&lock->locked, 0); +} + +DEFINE_STATIC_CALL(pv_queued_spin_lock_slowpath, native_queued_spin_lock_s= lowpath); +EXPORT_STATIC_CALL(pv_queued_spin_lock_slowpath); + +DEFINE_STATIC_CALL(pv_queued_spin_unlock, native_queued_spin_unlock); +EXPORT_STATIC_CALL(pv_queued_spin_unlock); + +bool __init pv_qspinlock_init(void) +{ + if (num_possible_cpus() =3D=3D 1) + return false; + + if (!sbi_probe_extension(SBI_EXT_PVLOCK)) + return false; + + pr_info("PV qspinlocks enabled\n"); + __pv_init_lock_hash(); + + static_call_update(pv_queued_spin_lock_slowpath, __pv_queued_spin_lock_sl= owpath); + static_call_update(pv_queued_spin_unlock, __pv_queued_spin_unlock); + + return true; +} + +bool pv_is_native_spin_unlock(void) +{ + return static_call_query(pv_queued_spin_unlock) =3D=3D + native_queued_spin_unlock; +} diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index a32344bb220d..ccfa92b7c81a 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -281,6 +281,11 @@ static void __init riscv_spinlock_init(void) return; } =20 +#ifdef CONFIG_PARAVIRT_SPINLOCKS + if (pv_qspinlock_init()) + return; +#endif + if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA) && IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZACAS) && --=20 2.43.0 From nobody Fri Sep 25 21:04:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D397C484899; Mon, 21 Sep 2026 12:27:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 21 Sep 2026 12:27:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789993658; bh=npVan5VYT3AMl8n3RsICnE+OLDep7BXyveNoQgrKcOA=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=A1Cb4P8ThKMPt2giCW4nM7EaQmmLM33Ov/QZQmZa2tIcFUjS8Q7l9LaKF6xwPTAyb xFHga9ra0KEbMXmpWx+sVZqNKmutZBveKjqGjRhkIV+S84Lq0mgyEP5yW4NSG8SD4/ dDVWFR94zsYs8mHpKyZhXlOe+k0xNlYSLuDK5jugzVHc1fNr0RV3T9XY4ZY0Z/zzLF iA4zjbpCooMCQdKYj63+sKREzy75dn7cP8XMPKfQ2b0hNbrxuULvO0P91pV25XhEDs fT7ENzTXbDfCjyN3N5mDTPvh5OO3H0jVLh8eQxFFwbi7r6TS4fDAhmHiDtJdkzUbso 8PUTqwSZAhPCg== From: "GUO Ren (XuanTie)" Date: Mon, 21 Sep 2026 12:27:03 +0000 Subject: [PATCH RFC v4 3/4] RISC-V: paravirt: pvqspinlock: Add trace point for pv_kick/wait Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-pvqspinlock-v4-3-409a22aed6ef@kernel.org> References: <20260921-pvqspinlock-v4-0-409a22aed6ef@kernel.org> In-Reply-To: <20260921-pvqspinlock-v4-0-409a22aed6ef@kernel.org> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Shuah Khan , Randy Dunlap , Fangyu Yu , CHEN Jiankang Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Leonardo Bras , "GUO Ren (XuanTie)" X-Mailer: b4 0.16.0 Add tracepoints for pv_kick and pv_wait to observe the paravirt qspinlock behavior: # cd /sys/kernel/debug/tracing # echo 1 > events/paravirt/enable # cat trace TASK-PID CPU# ||||| TIMESTAMP FUNCTION | | | ||||| | | sh-100 [001] d..2. 28.312294: pv_wait: cpu 1 out of wfi -0 [000] d.h4. 28.322030: pv_kick: cpu 0 kick target cpu 1 Reviewed-by: Leonardo Bras Signed-off-by: GUO Ren (XuanTie) --- arch/riscv/kernel/qspinlock_paravirt.c | 7 +++ arch/riscv/kernel/trace_events_filter_paravirt.h | 58 ++++++++++++++++++++= ++++ 2 files changed, 65 insertions(+) diff --git a/arch/riscv/kernel/qspinlock_paravirt.c b/arch/riscv/kernel/qsp= inlock_paravirt.c index c534447437fe..04b13994e971 100644 --- a/arch/riscv/kernel/qspinlock_paravirt.c +++ b/arch/riscv/kernel/qspinlock_paravirt.c @@ -7,8 +7,13 @@ #include #include =20 +#define CREATE_TRACE_POINTS +#include "trace_events_filter_paravirt.h" + void pv_kick(int cpu) { + trace_pv_kick(smp_processor_id(), cpu); + sbi_ecall(SBI_EXT_PVLOCK, SBI_EXT_PVLOCK_KICK_CPU, cpuid_to_hartid_map(cpu), 0, 0, 0, 0, 0); } @@ -25,6 +30,8 @@ void pv_wait(u8 *ptr, u8 val) goto out; =20 wait_for_interrupt(); + + trace_pv_wait(smp_processor_id()); out: local_irq_restore(flags); } diff --git a/arch/riscv/kernel/trace_events_filter_paravirt.h b/arch/riscv/= kernel/trace_events_filter_paravirt.h new file mode 100644 index 000000000000..8d57efda2c17 --- /dev/null +++ b/arch/riscv/kernel/trace_events_filter_paravirt.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 GUO Ren (XuanTie) + */ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM paravirt + +#if !defined(_TRACE_PARAVIRT_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_PARAVIRT_H + +#include + +TRACE_EVENT(pv_kick, + TP_PROTO(int cpu, int target), + TP_ARGS(cpu, target), + + TP_STRUCT__entry( + __field(int, cpu) + __field(int, target) + ), + + TP_fast_assign( + __entry->cpu =3D cpu; + __entry->target =3D target; + ), + + TP_printk("cpu %d pv_kick target cpu %d", + __entry->cpu, + __entry->target + ) +); + +TRACE_EVENT(pv_wait, + TP_PROTO(int cpu), + TP_ARGS(cpu), + + TP_STRUCT__entry( + __field(int, cpu) + ), + + TP_fast_assign( + __entry->cpu =3D cpu; + ), + + TP_printk("cpu %d out of wfi", + __entry->cpu + ) +); + +#endif /* _TRACE_PARAVIRT_H || TRACE_HEADER_MULTI_READ */ + +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_PATH ../../../arch/riscv/kernel/ +#define TRACE_INCLUDE_FILE trace_events_filter_paravirt + +/* This part must be outside protection */ +#include --=20 2.43.0 From nobody Fri Sep 25 21:04:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47071484899; Mon, 21 Sep 2026 12:27:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Mon, 21 Sep 2026 12:27:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789993662; bh=QVGKnIWRxvPTWA2suCoWlo2Ot1kTECvUDXRzzxTCpoM=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=KdhQCyIlB9toTwTgP1fKUeF0D9GY67k/HlhBgQCthL9+Bpv51wUpCNkXxQVPmnGdN Hr9YRZp2g9/na6SQKQQSQwpNDakxuzC6PvKUzI/yjkt90TBSRiae5h1hXQrLn1Sua5 UYjsQ8MLe73HFumUIWh+RPqqaL6cGzwRtneNo5/6AF2qwJMN4SOuJA9yFikStz4eFP ELYlhNbO9H+Di7qfwuRgYA05o2tCm+GSxzWqcwvoYoRxcRj70c6Mt9JAFy3AioJ7Mf 0MykNXAR/pDFVH2l+LQNtWgUouIC/bW4MAVtmKxnupn3grr2nRE7IR9n/xidfBqFuw VbQ1rDWaHluVA== From: "GUO Ren (XuanTie)" Date: Mon, 21 Sep 2026 12:27:04 +0000 Subject: [PATCH RFC v4 4/4] RISC-V: paravirt: Support nopvspin to disable PARAVIRT_SPINLOCKS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-pvqspinlock-v4-4-409a22aed6ef@kernel.org> References: <20260921-pvqspinlock-v4-0-409a22aed6ef@kernel.org> In-Reply-To: <20260921-pvqspinlock-v4-0-409a22aed6ef@kernel.org> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Shuah Khan , Randy Dunlap , Fangyu Yu , CHEN Jiankang Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, "GUO Ren (XuanTie)" X-Mailer: b4 0.16.0 VM guests should fall back to a Test-and-Set spinlock when PARAVIRT_SPINLOCKS is disabled, because fair locks suffer from severe lock-holder preemption issues. The virt_spin_lock_key shortcuts queued_spin_lock_slowpath(), allowing virt_spin_lock() to hijack it. See commit 43b3f02899f7 ("locking/qspinlock/x86: Fix performance regression under unaccelerated VMs"). Add a static key controlling whether virt_spin_lock() is called, and add nopvspin support mirroring x86. Signed-off-by: GUO Ren (XuanTie) --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/riscv/include/asm/qspinlock.h | 24 +++++++++++++++++++++= +++ arch/riscv/kernel/qspinlock_paravirt.c | 8 ++++++++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 33cd30996e47..d32bb7db9f91 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4632,7 +4632,7 @@ Kernel parameters as generic guest with no PV drivers. Currently support XEN HVM, KVM, HYPER_V and VMWARE guest. =20 - nopvspin [X86,XEN,KVM,EARLY] + nopvspin [X86,RISCV,XEN,KVM,EARLY] Disables the qspinlock slow path using PV optimizations which allow the hypervisor to 'idle' the guest on lock contention. diff --git a/arch/riscv/include/asm/qspinlock.h b/arch/riscv/include/asm/qs= pinlock.h index 330b714edc44..9c7108baa40a 100644 --- a/arch/riscv/include/asm/qspinlock.h +++ b/arch/riscv/include/asm/qspinlock.h @@ -12,6 +12,8 @@ /* How long a lock should spin before we consider blocking */ #define SPIN_THRESHOLD (1 << 15) =20 +extern bool nopvspin; + void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val); void __pv_init_lock_hash(void); void __pv_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val); @@ -29,5 +31,27 @@ static inline void queued_spin_unlock(struct qspinlock *= lock) #endif /* CONFIG_PARAVIRT_SPINLOCKS */ =20 #include +#include + +/* + * KVM guests fall back to a Test-and-Set spinlock because fair locks suff= er + * from severe lock-holder-preemption issues. When virt_spin_lock_key is + * enabled, virt_spin_lock() shortcuts queued_spin_lock_slowpath() and hij= acks + * the lock acquisition. + */ +DECLARE_STATIC_KEY_FALSE(virt_spin_lock_key); + +#define virt_spin_lock rv_virt_spin_lock +static inline bool rv_virt_spin_lock(struct qspinlock *lock) +{ + if (!static_branch_likely(&virt_spin_lock_key)) + return false; + + do { + smp_cond_load_relaxed((s32 *)&lock->val, VAL =3D=3D 0); + } while (atomic_cmpxchg(&lock->val, 0, _Q_LOCKED_VAL) !=3D 0); + + return true; +} =20 #endif /* _ASM_RISCV_QSPINLOCK_H */ diff --git a/arch/riscv/kernel/qspinlock_paravirt.c b/arch/riscv/kernel/qsp= inlock_paravirt.c index 04b13994e971..28c6c78d7e84 100644 --- a/arch/riscv/kernel/qspinlock_paravirt.c +++ b/arch/riscv/kernel/qspinlock_paravirt.c @@ -50,6 +50,8 @@ EXPORT_STATIC_CALL(pv_queued_spin_lock_slowpath); DEFINE_STATIC_CALL(pv_queued_spin_unlock, native_queued_spin_unlock); EXPORT_STATIC_CALL(pv_queued_spin_unlock); =20 +DEFINE_STATIC_KEY_FALSE(virt_spin_lock_key); + bool __init pv_qspinlock_init(void) { if (num_possible_cpus() =3D=3D 1) @@ -58,6 +60,12 @@ bool __init pv_qspinlock_init(void) if (!sbi_probe_extension(SBI_EXT_PVLOCK)) return false; =20 + if (nopvspin) { + static_branch_enable(&virt_spin_lock_key); + pr_info("virt_spin_lock enabled by nopvspin\n"); + return true; + } + pr_info("PV qspinlocks enabled\n"); __pv_init_lock_hash(); =20 --=20 2.43.0