From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 809D24F68A2; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014752; cv=none; b=NuGo2sHt5fLPNS4DDvyAFBTGvQ2Ywjz624kkR13AqzMFTSg+lrjSVS44tAldNVc4ieG987GVLQb7yoq/uZSIxNfM22u77qGAZ/AwXVq02KTEGPmC51sfOVCvblycebuXixD5wEvRb6DdXytvPzCIEvzqbgMQIkNYdp8RPb9CWOU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014752; c=relaxed/simple; bh=z/SlYdPV3JRXBJJoCnExC5/YQjozcYeHEwt6sapibcc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R6K3/LTiTdF/rOtiI0uPCMno7SuNy5qd+xNzqaIOn6uXcUKXAfu+MvoHXfewGURvn7wF+MxYqAV54pogpPzeJ6KliYIfoJLvwvRmff21TU1iB0Xdhdazu2TgktgwzXS1DlW6aJd3nFK/5tWJRvOStwVDeq74rTuGVbChasKf0BQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=C8UP2HhT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="C8UP2HhT" Received: by smtp.kernel.org (Postfix) with ESMTPS id 13BC2C2BCF6; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014752; bh=z/SlYdPV3JRXBJJoCnExC5/YQjozcYeHEwt6sapibcc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=C8UP2HhTUIPPU5beEpky3RUNEuSzbhAhwAa8X4IELtB+uE5M8H6NsrjKql9OjGdsm ATzgQUQKLLc/nkBIIBnKqNF8R7WH/F2oHqKGTmRIGlaWGjvVkFtGBSjIEuBhs/pWnS cenhSOYpoCXaF2hiH8yRIaHlsgN8Vbse9wpKWdo6on0/J96TBaoczMDpuZvZqrsKQ0 MhoB3b318khLfbCNxqeksU6db1CkCmSIr0V8jvxSnqPaLh+VVFgg9q6+cCXo2eicFN Skcs+QDhV+16X87gOJrSVNr1HsbE179qNTRMQ18h8Y1CEFdro3+52Ny1EStsTE5Vif ug1fZhaujMmKA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBB72C982ED; Mon, 21 Sep 2026 18:19:11 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:18:52 +0300 Subject: [PATCH v3 01/19] dt-bindings: clock: qcom: Add MSM8952 global clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-1-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=10258; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=6yamRkkc/1prVGfyRPwK42y2ZFPSTA+V8diWvp5gE08=; b=9Wy1PQ//ghj2qdhC/NRmtQJMES4zkNB3t/Gwnodh2akLIraAO8rVLnRARGDpfhLL6g+1RscfI tzCmh4g1xajCpuB4i+JL+82eeChu011C4ryQpelSHSWQG4GccnnTr0m X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add a device tree binding to describe clocks, resets and power domains provided by the global clock controller on MSM8952 SoC. MSM8952 GCC driver is mainly based on MSM8939 GCC driver. Signed-off-by: Muzaffer Kadir --- .../bindings/clock/qcom,gcc-msm8952.yaml | 65 +++++++ include/dt-bindings/clock/qcom,gcc-msm8952.h | 215 +++++++++++++++++= ++++ 2 files changed, 280 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8952.yaml = b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8952.yaml new file mode 100644 index 000000000000..035f2f7451cd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8952.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8952.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8952 + +maintainers: + - Muzaffer Kadir + +description: | + Qualcomm global clock control module provides the clocks, resets and pow= er + domains on MSM8952. + + See also: + include/dt-bindings/clock/qcom,gcc-msm8952.h + +properties: + compatible: + enum: + - qcom,gcc-msm8952 + + clocks: + items: + - description: XO source + - description: Always-on XO source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + + power-domains: + items: + - description: CX power domain + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8952"; + reg =3D <0x01800000 0x80000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,gcc-msm8952.h b/include/dt-bind= ings/clock/qcom,gcc-msm8952.h new file mode 100644 index 000000000000..5b5c38a9f4dd --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8952.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Linaro Limited + * Copyright 2026 Muzaffer Kadir + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8952_H +#define _DT_BINDINGS_CLK_MSM_GCC_8952_H + +#define GPLL0 0 +#define GPLL0_VOTE 1 +#define GPLL3 2 +#define GPLL3_EARLY 3 +#define GPLL4 4 +#define GPLL4_VOTE 5 +#define GPLL6 6 +#define GPLL6_VOTE 7 +#define CAMSS_TOP_AHB_CLK_SRC 8 +#define APSS_AHB_CLK_SRC 9 +#define CSI0_CLK_SRC 10 +#define CSI1_CLK_SRC 11 +#define GFX3D_CLK_SRC 12 +#define VFE0_CLK_SRC 13 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 14 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 15 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 16 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 17 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 18 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 19 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 20 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 21 +#define BLSP1_UART1_APPS_CLK_SRC 22 +#define BLSP1_UART2_APPS_CLK_SRC 23 +#define CCI_CLK_SRC 24 +#define CAMSS_GP0_CLK_SRC 25 +#define CAMSS_GP1_CLK_SRC 26 +#define JPEG0_CLK_SRC 27 +#define MCLK0_CLK_SRC 28 +#define MCLK1_CLK_SRC 29 +#define CSI0PHYTIMER_CLK_SRC 30 +#define CSI1PHYTIMER_CLK_SRC 31 +#define CPP_CLK_SRC 32 +#define CRYPTO_CLK_SRC 33 +#define GP1_CLK_SRC 34 +#define GP2_CLK_SRC 35 +#define GP3_CLK_SRC 36 +#define BYTE0_CLK_SRC 37 +#define ESC0_CLK_SRC 38 +#define MDP_CLK_SRC 39 +#define PCLK0_CLK_SRC 40 +#define VSYNC_CLK_SRC 41 +#define PDM2_CLK_SRC 42 +#define SDCC1_APPS_CLK_SRC 43 +#define SDCC2_APPS_CLK_SRC 44 +#define USB_HS_SYSTEM_CLK_SRC 45 +#define VCODEC0_CLK_SRC 46 +#define GCC_BLSP1_AHB_CLK 47 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 48 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 49 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 50 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 51 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 52 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 53 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 54 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 55 +#define GCC_BLSP1_UART1_APPS_CLK 56 +#define GCC_BLSP1_UART2_APPS_CLK 57 +#define GCC_BOOT_ROM_AHB_CLK 58 +#define GCC_CAMSS_CCI_AHB_CLK 59 +#define GCC_CAMSS_CCI_CLK 60 +#define GCC_CAMSS_CSI0_AHB_CLK 61 +#define GCC_CAMSS_CSI0_CLK 62 +#define GCC_CAMSS_CSI0PHY_CLK 63 +#define GCC_CAMSS_CSI0PIX_CLK 64 +#define GCC_CAMSS_CSI0RDI_CLK 65 +#define GCC_CAMSS_CSI1_AHB_CLK 66 +#define GCC_CAMSS_CSI1_CLK 67 +#define GCC_CAMSS_CSI1PHY_CLK 68 +#define GCC_CAMSS_CSI1PIX_CLK 69 +#define GCC_CAMSS_CSI1RDI_CLK 70 +#define GCC_CAMSS_CSI_VFE0_CLK 71 +#define GCC_CAMSS_GP0_CLK 72 +#define GCC_CAMSS_GP1_CLK 73 +#define GCC_CAMSS_ISPIF_AHB_CLK 74 +#define GCC_CAMSS_JPEG0_CLK 75 +#define GCC_CAMSS_JPEG_AHB_CLK 76 +#define GCC_CAMSS_JPEG_AXI_CLK 77 +#define GCC_CAMSS_MCLK0_CLK 78 +#define GCC_CAMSS_MCLK1_CLK 79 +#define GCC_CAMSS_MICRO_AHB_CLK 80 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 81 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 82 +#define GCC_CAMSS_AHB_CLK 83 +#define GCC_CAMSS_TOP_AHB_CLK 84 +#define GCC_CAMSS_CPP_AHB_CLK 85 +#define GCC_CAMSS_CPP_CLK 86 +#define GCC_CAMSS_VFE0_CLK 87 +#define GCC_CAMSS_VFE0_AHB_CLK 88 +#define GCC_CAMSS_VFE0_AXI_CLK 89 +#define GCC_CRYPTO_AHB_CLK 90 +#define GCC_CRYPTO_AXI_CLK 91 +#define GCC_CRYPTO_CLK 92 +#define GCC_OXILI_GMEM_CLK 93 +#define GCC_GP1_CLK 94 +#define GCC_GP2_CLK 95 +#define GCC_GP3_CLK 96 +#define GCC_MDSS_AHB_CLK 97 +#define GCC_MDSS_AXI_CLK 98 +#define GCC_MDSS_BYTE0_CLK 99 +#define GCC_MDSS_ESC0_CLK 100 +#define GCC_MDSS_MDP_CLK 101 +#define GCC_MDSS_PCLK0_CLK 102 +#define GCC_MDSS_VSYNC_CLK 103 +#define GCC_MSS_CFG_AHB_CLK 104 +#define GCC_OXILI_AHB_CLK 105 +#define GCC_OXILI_GFX3D_CLK 106 +#define GCC_PDM2_CLK 107 +#define GCC_PDM_AHB_CLK 108 +#define GCC_PRNG_AHB_CLK 109 +#define GCC_SDCC1_AHB_CLK 110 +#define GCC_SDCC1_APPS_CLK 111 +#define GCC_SDCC2_AHB_CLK 112 +#define GCC_SDCC2_APPS_CLK 113 +#define GCC_GTCU_AHB_CLK 114 +#define GCC_JPEG_TBU_CLK 115 +#define GCC_MDP_TBU_CLK 116 +#define GCC_SMMU_CFG_CLK 117 +#define GCC_VENUS_TBU_CLK 118 +#define GCC_VFE_TBU_CLK 119 +#define GCC_USB2A_PHY_SLEEP_CLK 120 +#define GCC_USB_HS_AHB_CLK 121 +#define GCC_USB_HS_SYSTEM_CLK 122 +#define GCC_VENUS0_AHB_CLK 123 +#define GCC_VENUS0_AXI_CLK 124 +#define GCC_VENUS0_VCODEC0_CLK 125 +#define GCC_APSS_TCU_CLK 126 +#define GCC_GFX_TCU_CLK 127 +#define GCC_BIMC_GFX_CLK 128 +#define GCC_BIMC_GPU_CLK 129 +#define GCC_MSS_Q6_BIMC_AXI_CLK 130 +#define GCC_GFX_TBU_CLK 131 +#define GCC_CPP_TBU_CLK 132 +#define USB_FS_SYSTEM_CLK_SRC 133 +#define USB_FS_IC_CLK_SRC 134 +#define GCC_USB_FS_AHB_CLK 135 +#define GCC_USB_FS_IC_CLK 136 +#define GCC_USB_FS_SYSTEM_CLK 137 +#define GCC_VENUS0_CORE0_VCODEC0_CLK 138 +#define GCC_VENUS0_CORE1_VCODEC0_CLK 139 +#define GCC_OXILI_TIMER_CLK 140 +#define GCC_USB_HS_PHY_CFG_AHB_CLK 141 +#define CSI2_CLK_SRC 142 +#define GCC_CAMSS_CSI2_AHB_CLK 143 +#define GCC_CAMSS_CSI2_CLK 144 +#define GCC_CAMSS_CSI2PHY_CLK 145 +#define GCC_CAMSS_CSI2PIX_CLK 146 +#define GCC_CAMSS_CSI2RDI_CLK 147 +#define SDCC1_ICE_CORE_CLK_SRC 148 +#define GCC_SDCC1_ICE_CORE_CLK 149 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 150 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 151 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 152 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 153 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 154 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 155 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 156 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 157 +#define BLSP2_UART1_APPS_CLK_SRC 158 +#define BLSP2_UART2_APPS_CLK_SRC 159 +#define GCC_BLSP2_AHB_CLK 160 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 161 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 162 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 163 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 164 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 165 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 166 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 167 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 168 +#define GCC_BLSP2_UART1_APPS_CLK 169 +#define GCC_BLSP2_UART2_APPS_CLK 170 +#define VFE1_CLK_SRC 171 +#define GCC_CAMSS_VFE1_CLK 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Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=100064; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=PnkGbEgGJ+b0dbMHdgGjxIFeH5lb2pzLKFSnNos1qmQ=; b=Cvl85GA01+nstjRm5T9ZYIjK00lxQs5POkaRZMJbYM5PzJ85BMCgdnpDsWq3mEhJ098OYkHnP AsPXzvszK4jDVQD5C9+HlFYMdufficyWbAAfxrz7IY8WV1U1zjb5VJD X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir This driver provides clocks, resets and power domains needed for various components of the MSM8952. Some downstreams merge MSM8952 to MSM8917 and MSM8937. But upstreamed GCC driver for 8917 series has different pll structure and ported from different GCC driver. MSM8952 GCC driver is mainly based on MSM8939 GCC driver, with some parts added from existing other GCC drivers. Link: https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-w= ear-7.0.0_r0.3/drivers/clk/qcom/clock-gcc-8952.c Signed-off-by: Muzaffer Kadir Reviewed-by: Abel Vesa --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-msm8952.c | 3548 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 3559 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b3ffe1dced01..ec9655be86ba 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -778,6 +778,16 @@ config MSM_GCC_8939 Say Y if you want to use devices such as UART, SPI i2c, USB, SD/eMMC, display, graphics, camera etc. =20 +config MSM_GCC_8952 + tristate "MSM8952 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + default ARCH_QCOM + help + Support for the global clock controller on MSM8952 devices. + Say Y if you want to use devices such as UART, SPI i2c, USB, + SD/eMMC, display, graphics, camera etc. + config MSM_GCC_8960 tristate "APQ8064/MSM8960 Global Clock Controller" depends on ARM || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index a6c676f68b79..3c3f27dcc68d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_MSM_GCC_8909) +=3D gcc-msm8909.o obj-$(CONFIG_MSM_GCC_8916) +=3D gcc-msm8916.o obj-$(CONFIG_MSM_GCC_8917) +=3D gcc-msm8917.o obj-$(CONFIG_MSM_GCC_8939) +=3D gcc-msm8939.o +obj-$(CONFIG_MSM_GCC_8952) +=3D gcc-msm8952.o obj-$(CONFIG_MSM_GCC_8953) +=3D gcc-msm8953.o obj-$(CONFIG_MSM_GCC_8960) +=3D gcc-msm8960.o obj-$(CONFIG_MSM_GCC_8974) +=3D gcc-msm8974.o diff --git a/drivers/clk/qcom/gcc-msm8952.c b/drivers/clk/qcom/gcc-msm8952.c new file mode 100644 index 000000000000..de2811307a86 --- /dev/null +++ b/drivers/clk/qcom/gcc-msm8952.c @@ -0,0 +1,3548 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2026 Muzaffer Kadir + * + * Based on gcc-msm8939.c: + * Copyright 2020 Linaro Limited + * adapted with data from clock-gcc-8952.c in Qualcomm's msm-3.10 release + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * with parts taken from gcc-msm8976.c: + * Copyright (c) 2016-2021, AngeloGioacchino Del Regno + * + * Copyright (c) 2021, Konrad Dybcio + * Marijn Suijten + * with some resets copied from gcc-msm8953: + * Copyright (c) 2021, The Linux Foundation. All rights reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-alpha-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "reset.h" +#include "gdsc.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_DSI0PLL, + DT_DSI0PLL_BYTE, +}; + +enum { + P_XO, + P_XO_A, + P_GPLL0, + P_GPLL0_OUT_MAIN, + P_GPLL0_AUX, + P_GPLL3, + P_GPLL4, + P_GPLL6, + P_GPLL6_AUX, + P_GPLL6_OUT_MAIN, + P_DSI0_PHYPLL_BYTE, + P_DSI0_PHYPLL_DSI, +}; + +static const struct clk_parent_data gcc_xo_parent_data[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static struct clk_pll gpll0 =3D { + .l_reg =3D 0x21004, + .m_reg =3D 0x21008, + .n_reg =3D 0x2100c, + .config_reg =3D 0x21014, + .mode_reg =3D 0x21000, + .status_reg =3D 0x2101c, + .status_bit =3D 17, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll0", + .parent_data =3D gcc_xo_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_parent_data), + .ops =3D &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll0_vote =3D { + .enable_reg =3D 0x45000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll0_vote", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_pll_vote_ops, + }, +}; + +static const struct pll_vco gpll3_p_vco[] =3D { + { 700000000, 1400000000, 0 }, +}; + +static const struct alpha_pll_config gpll3_early_config =3D { + .l =3D 63, + .config_ctl_val =3D 0x4001055b, + .main_output_mask =3D BIT(0), + .test_ctl_val =3D 0x0, + .test_ctl_mask =3D GENMASK(31, 0), + .test_ctl_hi_val =3D 0x40000600, + .test_ctl_hi_mask =3D GENMASK(31, 0), + .alpha_en_mask =3D BIT(24), + .post_div_val =3D BIT(8), + .post_div_mask =3D GENMASK(11, 8), +}; + +static struct clk_alpha_pll gpll3_early =3D { + .offset =3D 0x22000, + .config =3D &gpll3_early_config, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .vco_table =3D gpll3_p_vco, + .num_vco =3D ARRAY_SIZE(gpll3_p_vco), + .flags =3D SUPPORTS_DYNAMIC_UPDATE, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll3_early", + .parent_data =3D gcc_xo_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_parent_data), + .ops =3D &clk_alpha_pll_ops, + }, +}; + +static struct clk_alpha_pll_postdiv gpll3 =3D { + .offset =3D 0x22000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll3", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll3_early.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_pll gpll4 =3D { + .l_reg =3D 0x24004, + .m_reg =3D 0x24008, + .n_reg =3D 0x2400c, + .config_reg =3D 0x24018, + .mode_reg =3D 0x24000, + .status_reg =3D 0x24000, + .status_bit =3D 30, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll4", + .parent_data =3D gcc_xo_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_parent_data), + .ops =3D &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll4_vote =3D { + .enable_reg =3D 0x45000, + .enable_mask =3D BIT(5), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll4_vote", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll4.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_pll_vote_ops, + }, +}; + +static struct clk_pll gpll6 =3D { + .l_reg =3D 0x37004, + .m_reg =3D 0x37008, + .n_reg =3D 0x3700c, + .config_reg =3D 0x37014, + .mode_reg =3D 0x37000, + .status_reg =3D 0x3701c, + .status_bit =3D 17, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll6", + .parent_data =3D gcc_xo_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_parent_data), + .ops =3D &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll6_vote =3D { + .enable_reg =3D 0x45000, + .enable_mask =3D BIT(7), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll6_vote", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll6.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_pll_vote_ops, + }, +}; + +static const struct parent_map gcc_xo_gpll0_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 1 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_parent_data[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_out_main_map[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_out_main_parent_data[] = =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct parent_map gcc_xo_a_gpll0_map[] =3D { + { P_XO_A, 0 }, + { P_GPLL0, 1 }, +}; + +static const struct clk_parent_data gcc_xo_a_gpll0_parent_data[] =3D { + { .index =3D DT_BI_TCXO_AO }, + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll3_gpll6a_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL3, 2 }, + { P_GPLL6_AUX, 3 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll3_gpll6a_parent_data[= ] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0_vote.hw }, + { .hw =3D &gpll3.clkr.hw }, + { .hw =3D &gpll6_vote.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll4_parent_data[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0_vote.hw }, + { .hw =3D &gpll4_vote.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll6_map[] =3D { + { P_XO, 0 }, + { P_GPLL6, 2 }, + { P_GPLL0, 1 }, +}; + +static const struct parent_map gcc_xo_gpll6_out_main_map[] =3D { + { P_XO, 0 }, + { P_GPLL6_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll6_parent_data[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll6_vote.hw }, + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct parent_map gcc_xo_gpll0a_map[] =3D { + { P_XO, 0 }, + { P_GPLL0_AUX, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct clk_parent_data gcc_gpll0_parent_data[] =3D { + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct parent_map gcc_gpll0_map[] =3D { + { P_GPLL0, 1 }, +}; + +static const struct parent_map gcc_xo_map[] =3D { + { P_XO, 0, }, +}; + +static const struct parent_map gcc_xo_dsibyte_map[] =3D { + { P_XO, 0 }, + { P_DSI0_PHYPLL_BYTE, 1 }, +}; + +static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0PLL_BYTE }, +}; + +static const struct parent_map gcc_xo_dsiphy_map[] =3D { + { P_XO, 0 }, + { P_DSI0_PHYPLL_DSI, 1 }, +}; + +static const struct clk_parent_data gcc_xo_dsiphy_parent_data[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0PLL }, +}; + +static const struct parent_map gcc_xo_gpll0_dsiphy_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_DSI0_PHYPLL_DSI, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_dsiphy_parent_data[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0_vote.hw }, + { .index =3D DT_DSI0PLL }, +}; + +static const struct clk_parent_data gcc_xo_gpll6_out_main_parent_data[] = =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll6_vote.hw }, +}; + +static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] =3D { + F(40000000, P_GPLL0, 10, 1, 2), + F(61540000, P_GPLL0, 13, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + { } +}; + +static struct clk_rcg2 camss_top_ahb_clk_src =3D { + .cmd_rcgr =3D 0x5a000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_top_ahb_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "camss_top_ahb_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_apss_ahb_clk[] =3D { + F(19200000, P_XO_A, 1, 0, 0), + { } +}; + +static struct clk_rcg2 apss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x46000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_a_gpll0_map, + .freq_tbl =3D ftbl_apss_ahb_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "apss_ahb_clk_src", + .parent_data =3D gcc_xo_a_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_a_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + /* + * This clock allows the CPUs to communicate with + * the rest of the SoC. Without it, the brain will + * operate without the rest of the body. + */ + .flags =3D CLK_IS_CRITICAL, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csi0_1_2_clk[] =3D { + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 csi0_clk_src =3D { + .cmd_rcgr =3D 0x4e020, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_csi0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "csi0_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi1_clk_src =3D { + .cmd_rcgr =3D 0x4f020, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_csi0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "csi1_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi2_clk_src =3D { + .cmd_rcgr =3D 0x3c020, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_csi0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "csi2_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(228570000, P_GPLL0, 3.5, 0, 0), + F(240000000, P_GPLL6_AUX, 4.5, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(400000000, P_GPLL0, 2, 0, 0), + F(465000000, P_GPLL3, 1, 0, 0), + F(500000000, P_GPLL3, 1, 0, 0), + F(550000000, P_GPLL3, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gfx3d_clk_src =3D { + .cmd_rcgr =3D 0x59000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll3_gpll6a_map, + .freq_tbl =3D ftbl_gcc_oxili_gfx3d_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gfx3d_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll3_gpll6a_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll3_gpll6a_parent_data), + .ops =3D &clk_rcg2_ops, + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] =3D { + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(133330000, P_GPLL0, 6, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(177780000, P_GPLL0, 4.5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(308570000, P_GPLL6, 3.5, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + F(360000000, P_GPLL6, 3, 0, 0), + { } +}; + +static struct clk_rcg2 vfe0_clk_src =3D { + .cmd_rcgr =3D 0x58000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_vfe0_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "vfe0_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 vfe1_clk_src =3D { + .cmd_rcgr =3D 0x58054, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_vfe0_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "vfe1_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x0200c, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup1_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] =3D { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(16000000, P_GPLL0, 10, 1, 5), + F(19200000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0, 16, 1, 2), + F(50000000, P_GPLL0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x02024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup1_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x03000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup2_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x03014, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup2_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x04000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup3_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x04024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup3_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x05000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup4_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x05024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup4_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] =3D { + F(3686400, P_GPLL0, 1, 72, 15625), + F(7372800, P_GPLL0, 1, 144, 15625), + F(14745600, P_GPLL0, 1, 288, 15625), + F(16000000, P_GPLL0, 10, 1, 5), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 1, 3, 100), + F(25000000, P_GPLL0, 16, 1, 2), + F(32000000, P_GPLL0, 1, 1, 25), + F(40000000, P_GPLL0, 1, 1, 20), + F(46400000, P_GPLL0, 1, 29, 500), + F(48000000, P_GPLL0, 1, 3, 50), + F(51200000, P_GPLL0, 1, 8, 125), + F(56000000, P_GPLL0, 1, 7, 100), + F(58982400, P_GPLL0, 1, 1152, 15625), + F(60000000, P_GPLL0, 1, 3, 40), + { } +}; + +static struct clk_rcg2 blsp1_uart1_apps_clk_src =3D { + .cmd_rcgr =3D 0x02044, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_uart1_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart2_apps_clk_src =3D { + .cmd_rcgr =3D 0x03034, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_uart2_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x0c00c, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup1_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x0c024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup1_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x0d000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup2_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x0d014, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup2_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x0f000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup3_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x0f024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup3_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x18000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup4_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x18024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup4_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_uart1_apps_clk_src =3D { + .cmd_rcgr =3D 0x0c044, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_uart1_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_uart2_apps_clk_src =3D { + .cmd_rcgr =3D 0x0d034, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_uart2_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_cci_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + F(37500000, P_GPLL0_AUX, 1, 3, 64), + { } +}; + +static struct clk_rcg2 cci_clk_src =3D { + .cmd_rcgr =3D 0x51000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0a_map, + .freq_tbl =3D ftbl_gcc_camss_cci_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "cci_clk_src", + .parent_data =3D gcc_xo_gpll0a_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0a_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_camss_gp0_1_clk_src[] =3D { + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 camss_gp0_clk_src =3D { + .cmd_rcgr =3D 0x54000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_gpll0_map, + .freq_tbl =3D ftbl_camss_gp0_1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "camss_gp0_clk_src", + .parent_data =3D gcc_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 camss_gp1_clk_src =3D { + .cmd_rcgr =3D 0x55000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_gpll0_map, + .freq_tbl =3D ftbl_camss_gp0_1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "camss_gp1_clk_src", + .parent_data =3D gcc_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] =3D { + F(133330000, P_GPLL0, 6, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 jpeg0_clk_src =3D { + .cmd_rcgr =3D 0x57000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_jpeg0_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "jpeg0_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_mclk0_1_2_clk[] =3D { + F(6150000, P_GPLL0, 1, 1, 130), + F(8000000, P_GPLL0, 1, 1, 100), + F(24000000, P_GPLL6, 1, 1, 45), + F(66670000, P_GPLL0, 12, 0, 0), + { } +}; + +static struct clk_rcg2 mclk0_clk_src =3D { + .cmd_rcgr =3D 0x52000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_mclk0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "mclk0_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 mclk1_clk_src =3D { + .cmd_rcgr =3D 0x53000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_mclk0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "mclk1_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 mclk2_clk_src =3D { + .cmd_rcgr =3D 0x5c000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_mclk0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "mclk2_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] =3D { + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 csi0phytimer_clk_src =3D { + .cmd_rcgr =3D 0x4e000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_csi0_1phytimer_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "csi0phytimer_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi1phytimer_clk_src =3D { + .cmd_rcgr =3D 0x4f000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_csi0_1phytimer_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "csi1phytimer_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] =3D { + F(133330000, P_GPLL0, 6, 0, 0), + F(180000000, P_GPLL6, 6, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(308570000, P_GPLL6, 3.5, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cpp_clk_src =3D { + .cmd_rcgr =3D 0x58018, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_cpp_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "cpp_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_crypto_clk[] =3D { + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + { } +}; + +static struct clk_rcg2 crypto_clk_src =3D { + .cmd_rcgr =3D 0x16004, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_crypto_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "crypto_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +/* + * This is a frequency table for "General Purpose" clocks. + * These clocks can be muxed to the SoC pins and may be used by + * external devices. They're often used as PWM source. + * + * Please note that MND divider must be enabled for duty-cycle + * control to be possible. (M !=3D N) Also since D register is configured + * with a value multiplied by 2, and duty cycle is calculated as + * (2 * D) % 2^W + * DutyCycle =3D ---------------- + * 2 * (N % 2^W) + * (where W =3D .mnd_width) + * N must be half or less than maximum value for the register. + * Otherwise duty-cycle control would be limited. + * (e.g. for 8-bit NMD N should be less than 128) + */ +static const struct freq_tbl ftbl_gcc_gp1_3_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gp1_clk_src =3D { + .cmd_rcgr =3D 0x08004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_map, + .freq_tbl =3D ftbl_gcc_gp1_3_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gp1_clk_src", + .parent_data =3D gcc_xo_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gp2_clk_src =3D { + .cmd_rcgr =3D 0x09004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_map, + .freq_tbl =3D ftbl_gcc_gp1_3_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gp2_clk_src", + .parent_data =3D gcc_xo_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gp3_clk_src =3D { + .cmd_rcgr =3D 0x0a004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_map, + .freq_tbl =3D ftbl_gcc_gp1_3_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gp3_clk_src", + .parent_data =3D gcc_xo_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 byte0_clk_src =3D { + .cmd_rcgr =3D 0x4d044, + .hid_width =3D 5, + .parent_map =3D gcc_xo_dsibyte_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "byte0_clk_src", + .parent_data =3D gcc_xo_dsibyte_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_dsibyte_parent_data), + .ops =3D &clk_byte2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 esc0_clk_src =3D { + .cmd_rcgr =3D 0x4d05c, + .hid_width =3D 5, + .parent_map =3D gcc_xo_map, + .freq_tbl =3D ftbl_gcc_mdss_esc_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "esc0_clk_src", + .parent_data =3D gcc_xo_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] =3D { + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(145450000, P_GPLL0, 5.5, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(177780000, P_GPLL0, 4.5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 mdp_clk_src =3D { + .cmd_rcgr =3D 0x4d014, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_dsiphy_map, + .freq_tbl =3D ftbl_gcc_mdss_mdp_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "mdp_clk_src", + .parent_data =3D gcc_xo_gpll0_dsiphy_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_dsiphy_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 pclk0_clk_src =3D { + .cmd_rcgr =3D 0x4d000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_dsiphy_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "pclk0_clk_src", + .parent_data =3D gcc_xo_dsiphy_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_dsiphy_parent_data), + .ops =3D &clk_pixel_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 vsync_clk_src =3D { + .cmd_rcgr =3D 0x4d02c, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0a_map, + .freq_tbl =3D ftbl_gcc_mdss_vsync_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "vsync_clk_src", + .parent_data =3D gcc_xo_gpll0a_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0a_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk[] =3D { + F(64000000, P_GPLL0, 12.5, 0, 0), + { } +}; + +static struct clk_rcg2 pdm2_clk_src =3D { + .cmd_rcgr =3D 0x44010, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_pdm2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "pdm2_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] =3D { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_GPLL0, 10, 1, 4), + F(25000000, P_GPLL0, 16, 1, 2), + F(50000000, P_GPLL0, 16, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(177770000, P_GPLL0, 4.5, 0, 0), + F(192000000, P_GPLL4, 6, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(384000000, P_GPLL4, 3, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x42004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll4_map, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "sdcc1_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll4_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll4_parent_data), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] =3D { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_GPLL0, 10, 1, 4), + F(25000000, P_GPLL0, 16, 1, 2), + F(50000000, P_GPLL0, 16, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(177770000, P_GPLL0, 4.5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc2_apps_clk_src =3D { + .cmd_rcgr =3D 0x43004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_sdcc2_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "sdcc2_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk[] =3D { + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x5d000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_out_main_map, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "sdcc1_ice_core_clk_src", + .parent_data =3D gcc_xo_gpll0_out_main_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_out_main_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0x5d014, + .clkr =3D { + .enable_reg =3D 0x5d014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] =3D { + F(57140000, P_GPLL0, 14, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(133330000, P_GPLL0, 6, 0, 0), + F(177780000, P_GPLL0, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 usb_hs_system_clk_src =3D { + .cmd_rcgr =3D 0x41010, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_usb_hs_system_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "usb_hs_system_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] =3D { + F(64000000, P_GPLL0_AUX, 12.5, 0, 0), + { } +}; + +static struct clk_rcg2 usb_fs_system_clk_src =3D { + .cmd_rcgr =3D 0x3f010, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0a_map, + .freq_tbl =3D ftbl_gcc_usb_fs_system_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "usb_fs_system_clk_src", + .parent_data =3D gcc_xo_gpll0a_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0a_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] =3D { + F(60000000, P_GPLL6_OUT_MAIN, 9, 1, 2), + { } +}; + +static struct clk_rcg2 usb_fs_ic_clk_src =3D { + .cmd_rcgr =3D 0x3f034, + .hid_width =3D 5, + .mnd_width =3D 8, + .parent_map =3D gcc_xo_gpll6_out_main_map, + .freq_tbl =3D ftbl_gcc_usb_fs_ic_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "usb_fs_ic_clk_src", + .parent_data =3D gcc_xo_gpll6_out_main_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll6_out_main_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] =3D { + F(133330000, P_GPLL0, 6, 0, 0), + F(180000000, P_GPLL6, 6, 0, 0), + F(228570000, P_GPLL0, 3.5, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(308570000, P_GPLL6, 3.5, 0, 0), + { } +}; + +static struct clk_rcg2 vcodec0_clk_src =3D { + .cmd_rcgr =3D 0x4C000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_venus0_vcodec0_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "vcodec0_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_blsp1_ahb_clk =3D { + .halt_reg =3D 0x01008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(10), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk =3D { + .halt_reg =3D 0x02008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x02008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup1_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk =3D { + .halt_reg =3D 0x02004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x02004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup1_spi_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup1_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk =3D { + .halt_reg =3D 0x03010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x03010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup2_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk =3D { + .halt_reg =3D 0x0300c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0300c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup2_spi_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup2_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk =3D { + .halt_reg =3D 0x04020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x04020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup3_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk =3D { + .halt_reg =3D 0x0401c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0401c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup3_spi_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup3_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk =3D { + .halt_reg =3D 0x05020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x05020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup4_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk =3D { + .halt_reg =3D 0x0501c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0501c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup4_spi_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup4_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart1_apps_clk =3D { + .halt_reg =3D 0x0203c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0203c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_uart1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_uart1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart2_apps_clk =3D { + .halt_reg =3D 0x0302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_uart2_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_uart2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_ahb_clk =3D { + .halt_reg =3D 0x0b008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(20), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk =3D { + .halt_reg =3D 0x0c008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0c008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup1_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup1_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup1_spi_apps_clk =3D { + .halt_reg =3D 0x0c004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0c004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup1_spi_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup1_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_uart1_apps_clk =3D { + .halt_reg =3D 0x0c03c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0c03c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_uart1_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_uart1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk =3D { + .halt_reg =3D 0x0d010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0d010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup2_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup2_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup2_spi_apps_clk =3D { + .halt_reg =3D 0x0d00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0d00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup2_spi_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup2_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_uart2_apps_clk =3D { + .halt_reg =3D 0x0d02c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0d02c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_uart2_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_uart2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk =3D { + .halt_reg =3D 0x0f020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0f020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup3_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup3_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup3_spi_apps_clk =3D { + .halt_reg =3D 0x0f01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0f01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup3_spi_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup3_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk =3D { + .halt_reg =3D 0x18020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x18020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup4_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup4_spi_apps_clk =3D { + .halt_reg =3D 0x1801c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1801c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup4_spi_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup4_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x1300c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(7), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cci_ahb_clk =3D { + .halt_reg =3D 0x5101c, + .clkr =3D { + .enable_reg =3D 0x5101c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_cci_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cci_clk =3D { + .halt_reg =3D 0x51018, + .clkr =3D { + .enable_reg =3D 0x51018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_cci_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &cci_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0_ahb_clk =3D { + .halt_reg =3D 0x4e040, + .clkr =3D { + .enable_reg =3D 0x4e040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0_clk =3D { + .halt_reg =3D 0x4e03c, + .clkr =3D { + .enable_reg =3D 0x4e03c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0phy_clk =3D { + .halt_reg =3D 0x4e048, + .clkr =3D { + .enable_reg =3D 0x4e048, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0phy_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0pix_clk =3D { + .halt_reg =3D 0x4e058, + .clkr =3D { + .enable_reg =3D 0x4e058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0pix_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0rdi_clk =3D { + .halt_reg =3D 0x4e050, + .clkr =3D { + .enable_reg =3D 0x4e050, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0rdi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1_ahb_clk =3D { + .halt_reg =3D 0x4f040, + .clkr =3D { + .enable_reg =3D 0x4f040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1_clk =3D { + .halt_reg =3D 0x4f03c, + .clkr =3D { + .enable_reg =3D 0x4f03c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1phy_clk =3D { + .halt_reg =3D 0x4f048, + .clkr =3D { + .enable_reg =3D 0x4f048, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1phy_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1pix_clk =3D { + .halt_reg =3D 0x4f058, + .clkr =3D { + .enable_reg =3D 0x4f058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1pix_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1rdi_clk =3D { + .halt_reg =3D 0x4f050, + .clkr =3D { + .enable_reg =3D 0x4f050, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1rdi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2_ahb_clk =3D { + .halt_reg =3D 0x3c040, + .clkr =3D { + .enable_reg =3D 0x3c040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi2_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2_clk =3D { + .halt_reg =3D 0x3c03c, + .clkr =3D { + .enable_reg =3D 0x3c03c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2phy_clk =3D { + .halt_reg =3D 0x3c048, + .clkr =3D { + .enable_reg =3D 0x3c048, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi2phy_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2pix_clk =3D { + .halt_reg =3D 0x3c058, + .clkr =3D { + .enable_reg =3D 0x3c058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi2pix_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2rdi_clk =3D { + .halt_reg =3D 0x3c050, + .clkr =3D { + .enable_reg =3D 0x3c050, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi2rdi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk2_clk =3D { + .halt_reg =3D 0x5c018, + .clkr =3D { + .enable_reg =3D 0x5c018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_mclk2_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &mclk2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi_vfe0_clk =3D { + .halt_reg =3D 0x58050, + .clkr =3D { + .enable_reg =3D 0x58050, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi_vfe0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vfe0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_gp0_clk =3D { + .halt_reg =3D 0x54018, + .clkr =3D { + .enable_reg =3D 0x54018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_gp0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_gp0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_gp1_clk =3D { + .halt_reg =3D 0x55018, + .clkr =3D { + .enable_reg =3D 0x55018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_ispif_ahb_clk =3D { + .halt_reg =3D 0x50004, + .clkr =3D { + .enable_reg =3D 0x50004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_ispif_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg0_clk =3D { + .halt_reg =3D 0x57020, + .clkr =3D { + .enable_reg =3D 0x57020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_jpeg0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &jpeg0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg_ahb_clk =3D { + .halt_reg =3D 0x57024, + .clkr =3D { + .enable_reg =3D 0x57024, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_jpeg_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg_axi_clk =3D { + .halt_reg =3D 0x57028, + .clkr =3D { + .enable_reg =3D 0x57028, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_jpeg_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk0_clk =3D { + .halt_reg =3D 0x52018, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_mclk0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &mclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk1_clk =3D { + .halt_reg =3D 0x53018, + .clkr =3D { + .enable_reg =3D 0x53018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_mclk1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &mclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_micro_ahb_clk =3D { + .halt_reg =3D 0x5600c, + .clkr =3D { + .enable_reg =3D 0x5600c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_micro_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0phytimer_clk =3D { + .halt_reg =3D 0x4e01c, + .clkr =3D { + .enable_reg =3D 0x4e01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi0phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1phytimer_clk =3D { + .halt_reg =3D 0x4f01c, + .clkr =3D { + .enable_reg =3D 0x4f01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi1phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_ahb_clk =3D { + .halt_reg =3D 0x56004, + .clkr =3D { + .enable_reg =3D 0x56004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_top_ahb_clk =3D { + .halt_reg =3D 0x5a014, + .clkr =3D { + .enable_reg =3D 0x5a014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_top_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe0_ahb_clk =3D { + .halt_reg =3D 0x58044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x58044, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data) { + .name =3D "gcc_camss_vfe0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + .flags =3D CLK_SET_RATE_PARENT, + } + } +}; + +static struct clk_branch gcc_camss_vfe0_axi_clk =3D { + .halt_reg =3D 0x58048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x58048, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data) { + .name =3D "gcc_camss_vfe0_axi_clk", + .ops =3D &clk_branch2_ops, + } + } +}; + +static struct clk_branch gcc_camss_cpp_ahb_clk =3D { + .halt_reg =3D 0x58040, + .clkr =3D { + .enable_reg =3D 0x58040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_cpp_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_clk =3D { + .halt_reg =3D 0x5803c, + .clkr =3D { + .enable_reg =3D 0x5803c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_cpp_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &cpp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe0_clk =3D { + .halt_reg =3D 0x58038, + .clkr =3D { + .enable_reg =3D 0x58038, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_vfe0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vfe0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_axi_clk =3D { + .halt_reg =3D 0x58064, + .clkr =3D { + .enable_reg =3D 0x58064, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_cpp_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_ahb_clk =3D { + .halt_reg =3D 0x16024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_crypto_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_axi_clk =3D { + .halt_reg =3D 0x16020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(1), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_crypto_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_clk =3D { + .halt_reg =3D 0x1601c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(2), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &crypto_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_oxili_gmem_clk =3D { + .halt_reg =3D 0x59024, + .clkr =3D { + .enable_reg =3D 0x59024, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_oxili_gmem_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x08000, + .clkr =3D { + .enable_reg =3D 0x08000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x09000, + .clkr =3D { + .enable_reg =3D 0x09000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x0a000, + .clkr =3D { + .enable_reg =3D 0x0a000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_ahb_clk =3D { + .halt_reg =3D 0x4d07c, + .clkr =3D { + .enable_reg =3D 0x4d07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_axi_clk =3D { + .halt_reg =3D 0x4d080, + .clkr =3D { + .enable_reg =3D 0x4d080, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_byte0_clk =3D { + .halt_reg =3D 0x4d094, + .clkr =3D { + .enable_reg =3D 0x4d094, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_esc0_clk =3D { + .halt_reg =3D 0x4d098, + .clkr =3D { + .enable_reg =3D 0x4d098, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_mdp_clk =3D { + .halt_reg =3D 0x4D088, + .clkr =3D { + .enable_reg =3D 0x4D088, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x4d084, + .clkr =3D { + .enable_reg =3D 0x4d084, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_vsync_clk =3D { + .halt_reg =3D 0x4d090, + .clkr =3D { + .enable_reg =3D 0x4d090, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_cfg_ahb_clk =3D { + .halt_reg =3D 0x49000, + .clkr =3D { + .enable_reg =3D 0x49000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mss_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_q6_bimc_axi_clk =3D { + .halt_reg =3D 0x49004, + .clkr =3D { + .enable_reg =3D 0x49004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mss_q6_bimc_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_oxili_ahb_clk =3D { + .halt_reg =3D 0x59028, + .clkr =3D { + .enable_reg =3D 0x59028, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_oxili_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_oxili_gfx3d_clk =3D { + .halt_reg =3D 0x59020, + .clkr =3D { + .enable_reg =3D 0x59020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_oxili_gfx3d_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x4400c, + .clkr =3D { + .enable_reg =3D 0x4400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x44004, + .clkr =3D { + .enable_reg =3D 0x44004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk =3D { + .halt_reg =3D 0x13004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(8), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_prng_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x4201c, + .clkr =3D { + .enable_reg =3D 0x4201c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x42018, + .clkr =3D { + .enable_reg =3D 0x42018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk =3D { + .halt_reg =3D 0x4301c, + .clkr =3D { + .enable_reg =3D 0x4301c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk =3D { + .halt_reg =3D 0x43018, + .clkr =3D { + .enable_reg =3D 0x43018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_apss_tcu_clk =3D { + .halt_reg =3D 0x12018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(1), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_apss_tcu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gfx_tcu_clk =3D { + .halt_reg =3D 0x12020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(2), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gfx_tcu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gfx_tbu_clk =3D { + .halt_reg =3D 0x12010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(3), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gfx_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdp_tbu_clk =3D { + .halt_reg =3D 0x1201c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(4), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdp_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus_tbu_clk =3D { + .halt_reg =3D 0x12014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(5), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi_vfe1_clk =3D { + .halt_reg =3D 0x58074, + .clkr =3D { + .enable_reg =3D 0x58074, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi_vfe1_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &vfe1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_clk =3D { + .halt_reg =3D 0x5805c, + .clkr =3D { + .enable_reg =3D 0x5805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_vfe1_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &vfe1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_ahb_clk =3D { + .halt_reg =3D 0x58060, + .clkr =3D { + .enable_reg =3D 0x58060, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_vfe1_ahb_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_axi_clk =3D { + .halt_reg =3D 0x58068, + .clkr =3D { + .enable_reg =3D 0x58068, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_vfe1_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vfe_tbu_clk =3D { + .halt_reg =3D 0x1203c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(9), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_vfe_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_jpeg_tbu_clk =3D { + .halt_reg =3D 0x12034, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(10), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_jpeg_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_smmu_cfg_clk =3D { + .halt_reg =3D 0x12038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(12), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_smmu_cfg_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gtcu_ahb_clk =3D { + .halt_reg =3D 0x12044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(13), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gtcu_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpp_tbu_clk =3D { + .halt_reg =3D 0x12040, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(14), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpp_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vfe1_tbu_clk =3D { + .halt_reg =3D 0x12090, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(17), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_vfe1_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ipa_tbu_clk =3D { + .halt_reg =3D 0x120a0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(16), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ipa_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gfx_clk =3D { + .halt_reg =3D 0x59034, + .clkr =3D { + .enable_reg =3D 0x59034, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_bimc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gpu_clk =3D { + .halt_reg =3D 0x59030, + .clkr =3D { + .enable_reg =3D 0x59030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_bimc_gpu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2a_phy_sleep_clk =3D { + .halt_reg =3D 0x4102c, + .clkr =3D { + .enable_reg =3D 0x4102c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb2a_phy_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_fs_ahb_clk =3D { + .halt_reg =3D 0x3f008, + .clkr =3D { + .enable_reg =3D 0x3f008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_fs_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk =3D { + .halt_reg =3D 0x41030, + .clkr =3D { + .enable_reg =3D 0x41030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_hs_phy_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_fs_ic_clk =3D { + .halt_reg =3D 0x3f030, + .clkr =3D { + .enable_reg =3D 0x3f030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_fs_ic_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &usb_fs_ic_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_fs_system_clk =3D { + .halt_reg =3D 0x3f004, + .clkr =3D { + .enable_reg =3D 0x3f004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_fs_system_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &usb_fs_system_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_hs_ahb_clk =3D { + .halt_reg =3D 0x41008, + .clkr =3D { + .enable_reg =3D 0x41008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_hs_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_hs_system_clk =3D { + .halt_reg =3D 0x41004, + .clkr =3D { + .enable_reg =3D 0x41004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_hs_system_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &usb_hs_system_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus0_ahb_clk =3D { + .halt_reg =3D 0x4c020, + .clkr =3D { + .enable_reg =3D 0x4c020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus0_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus0_axi_clk =3D { + .halt_reg =3D 0x4c024, + .clkr =3D { + .enable_reg =3D 0x4c024, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus0_vcodec0_clk =3D { + .halt_reg =3D 0x4c01c, + .clkr =3D { + .enable_reg =3D 0x4c01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus0_vcodec0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vcodec0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus0_core0_vcodec0_clk =3D { + .halt_reg =3D 0x4c02c, + .clkr =3D { + .enable_reg =3D 0x4c02c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus0_core0_vcodec0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vcodec0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus0_core1_vcodec0_clk =3D { + .halt_reg =3D 0x4c034, + .clkr =3D { + .enable_reg =3D 0x4c034, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus0_core1_vcodec0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vcodec0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_oxili_timer_clk =3D { + .halt_reg =3D 0x59040, + .clkr =3D { + .enable_reg =3D 0x59040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_oxili_timer_clk", + .parent_data =3D gcc_xo_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_parent_data), + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc venus_gdsc =3D { + .gdscr =3D 0x4c018, + .cxcs =3D (unsigned int []){ 0x4c024, 0x4c01c }, + .cxc_count =3D 2, + .pd =3D { + .name =3D "venus_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc mdss_gdsc =3D { + .gdscr =3D 0x4d078, + .cxcs =3D (unsigned int []){ 0x4d080, 0x4d088 }, + .cxc_count =3D 2, + .pd =3D { + .name =3D "mdss_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc jpeg_gdsc =3D { + .gdscr =3D 0x5701c, + .cxcs =3D (unsigned int []){ 0x57020, 0x57028 }, + .cxc_count =3D 2, + .pd =3D { + .name =3D "jpeg_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc vfe0_gdsc =3D { + .gdscr =3D 0x58034, + .cxcs =3D (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 }, + .cxc_count =3D 4, + .pd =3D { + .name =3D "vfe0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc vfe1_gdsc =3D { + .gdscr =3D 0x5806c, + .cxcs =3D (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 }, + .cxc_count =3D 4, + .pd =3D { + .name =3D "vfe1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc cpp_gdsc =3D { + .gdscr =3D 0x58078, + .cxcs =3D (unsigned int []){ 0x5803c, 0x58064 }, + .cxc_count =3D 2, + .pd =3D { + .name =3D "cpp_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc oxili_gx_gdsc =3D { + .gdscr =3D 0x5901c, + .cxcs =3D (unsigned int []){ 0x59000, 0x59024 }, + .cxc_count =3D 2, + .pd =3D { + .name =3D "oxili_gx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc venus_core0_gdsc =3D { + .gdscr =3D 0x4c028, + .cxcs =3D (unsigned int []){ 0x4c02c }, + .cxc_count =3D 1, + .pd =3D { + .name =3D "venus_core0_gdsc", + }, + .flags =3D HW_CTRL_TRIGGER, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc venus_core1_gdsc =3D { + .gdscr =3D 0x4c030, + .cxcs =3D (unsigned int []){ 0x4c034 }, + .cxc_count =3D 1, + .pd =3D { + .name =3D "venus_core1_gdsc", + }, + .flags =3D HW_CTRL_TRIGGER, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct clk_regmap *gcc_msm8952_clocks[] =3D { + [GPLL0] =3D &gpll0.clkr, + [GPLL0_VOTE] =3D &gpll0_vote, + [CAMSS_TOP_AHB_CLK_SRC] =3D &camss_top_ahb_clk_src.clkr, + [APSS_AHB_CLK_SRC] =3D &apss_ahb_clk_src.clkr, + [CSI0_CLK_SRC] =3D &csi0_clk_src.clkr, + [CSI1_CLK_SRC] =3D &csi1_clk_src.clkr, + [CSI2_CLK_SRC] =3D &csi2_clk_src.clkr, + [GFX3D_CLK_SRC] =3D &gfx3d_clk_src.clkr, + [VFE0_CLK_SRC] =3D &vfe0_clk_src.clkr, + [BLSP1_QUP1_I2C_APPS_CLK_SRC] =3D &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] =3D &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] =3D &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] =3D &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] =3D &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] =3D &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] =3D &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] =3D &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] =3D &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] =3D &blsp1_uart2_apps_clk_src.clkr, + [CCI_CLK_SRC] =3D &cci_clk_src.clkr, + [CAMSS_GP0_CLK_SRC] =3D &camss_gp0_clk_src.clkr, + [CAMSS_GP1_CLK_SRC] =3D &camss_gp1_clk_src.clkr, + [JPEG0_CLK_SRC] =3D &jpeg0_clk_src.clkr, + [MCLK0_CLK_SRC] =3D &mclk0_clk_src.clkr, + [MCLK1_CLK_SRC] =3D &mclk1_clk_src.clkr, + [CSI0PHYTIMER_CLK_SRC] =3D &csi0phytimer_clk_src.clkr, + [CSI1PHYTIMER_CLK_SRC] =3D &csi1phytimer_clk_src.clkr, + [CPP_CLK_SRC] =3D &cpp_clk_src.clkr, + [CRYPTO_CLK_SRC] =3D &crypto_clk_src.clkr, + [GP1_CLK_SRC] =3D &gp1_clk_src.clkr, + [GP2_CLK_SRC] =3D &gp2_clk_src.clkr, + [GP3_CLK_SRC] =3D &gp3_clk_src.clkr, + [BYTE0_CLK_SRC] =3D &byte0_clk_src.clkr, + [ESC0_CLK_SRC] =3D &esc0_clk_src.clkr, + [MDP_CLK_SRC] =3D &mdp_clk_src.clkr, + [PCLK0_CLK_SRC] =3D &pclk0_clk_src.clkr, + [VSYNC_CLK_SRC] =3D &vsync_clk_src.clkr, + [PDM2_CLK_SRC] =3D &pdm2_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] =3D &sdcc1_apps_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] =3D &sdcc2_apps_clk_src.clkr, + [SDCC1_ICE_CORE_CLK_SRC] =3D &sdcc1_ice_core_clk_src.clkr, + [USB_HS_SYSTEM_CLK_SRC] =3D &usb_hs_system_clk_src.clkr, + [VCODEC0_CLK_SRC] =3D &vcodec0_clk_src.clkr, + [GCC_BLSP1_AHB_CLK] =3D &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] =3D &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] =3D &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] =3D &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] =3D &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] =3D &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] =3D &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] =3D &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] =3D &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] =3D &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] =3D &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMSS_CCI_AHB_CLK] =3D &gcc_camss_cci_ahb_clk.clkr, + [GCC_CAMSS_CCI_CLK] =3D &gcc_camss_cci_clk.clkr, + [GCC_CAMSS_CSI0_AHB_CLK] =3D &gcc_camss_csi0_ahb_clk.clkr, + [GCC_CAMSS_CSI0_CLK] =3D &gcc_camss_csi0_clk.clkr, + [GCC_CAMSS_CSI0PHY_CLK] =3D &gcc_camss_csi0phy_clk.clkr, + [GCC_CAMSS_CSI0PIX_CLK] =3D &gcc_camss_csi0pix_clk.clkr, + [GCC_CAMSS_CSI0RDI_CLK] =3D &gcc_camss_csi0rdi_clk.clkr, + [GCC_CAMSS_CSI1_AHB_CLK] =3D &gcc_camss_csi1_ahb_clk.clkr, + [GCC_CAMSS_CSI1_CLK] =3D &gcc_camss_csi1_clk.clkr, + [GCC_CAMSS_CSI1PHY_CLK] =3D &gcc_camss_csi1phy_clk.clkr, + [GCC_CAMSS_CSI1PIX_CLK] =3D &gcc_camss_csi1pix_clk.clkr, + [GCC_CAMSS_CSI1RDI_CLK] =3D &gcc_camss_csi1rdi_clk.clkr, + [GCC_CAMSS_CSI2_AHB_CLK] =3D &gcc_camss_csi2_ahb_clk.clkr, + [GCC_CAMSS_CSI2_CLK] =3D &gcc_camss_csi2_clk.clkr, + [GCC_CAMSS_CSI2PHY_CLK] =3D &gcc_camss_csi2phy_clk.clkr, + [GCC_CAMSS_CSI2PIX_CLK] =3D &gcc_camss_csi2pix_clk.clkr, + [GCC_CAMSS_CSI2RDI_CLK] =3D &gcc_camss_csi2rdi_clk.clkr, + [GCC_CAMSS_CSI_VFE0_CLK] =3D &gcc_camss_csi_vfe0_clk.clkr, + [GCC_CAMSS_GP0_CLK] =3D &gcc_camss_gp0_clk.clkr, + [GCC_CAMSS_GP1_CLK] =3D &gcc_camss_gp1_clk.clkr, + [GCC_CAMSS_ISPIF_AHB_CLK] =3D &gcc_camss_ispif_ahb_clk.clkr, + [GCC_CAMSS_JPEG0_CLK] =3D &gcc_camss_jpeg0_clk.clkr, + [GCC_CAMSS_JPEG_AHB_CLK] =3D &gcc_camss_jpeg_ahb_clk.clkr, + [GCC_CAMSS_JPEG_AXI_CLK] =3D &gcc_camss_jpeg_axi_clk.clkr, + [GCC_CAMSS_MCLK0_CLK] =3D &gcc_camss_mclk0_clk.clkr, + [GCC_CAMSS_MCLK1_CLK] =3D &gcc_camss_mclk1_clk.clkr, + [GCC_CAMSS_MICRO_AHB_CLK] =3D &gcc_camss_micro_ahb_clk.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK] =3D &gcc_camss_csi0phytimer_clk.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK] =3D &gcc_camss_csi1phytimer_clk.clkr, + [GCC_CAMSS_AHB_CLK] =3D &gcc_camss_ahb_clk.clkr, + [GCC_CAMSS_TOP_AHB_CLK] =3D &gcc_camss_top_ahb_clk.clkr, + [GCC_CAMSS_VFE0_AHB_CLK] =3D &gcc_camss_vfe0_ahb_clk.clkr, + [GCC_CAMSS_VFE0_AXI_CLK] =3D &gcc_camss_vfe0_axi_clk.clkr, + [GCC_CAMSS_CPP_AHB_CLK] =3D &gcc_camss_cpp_ahb_clk.clkr, + [GCC_CAMSS_CPP_CLK] =3D &gcc_camss_cpp_clk.clkr, + [GCC_CAMSS_VFE0_CLK] =3D &gcc_camss_vfe0_clk.clkr, + [GCC_CRYPTO_AHB_CLK] =3D &gcc_crypto_ahb_clk.clkr, + [GCC_CRYPTO_AXI_CLK] =3D &gcc_crypto_axi_clk.clkr, + [GCC_CRYPTO_CLK] =3D &gcc_crypto_clk.clkr, + [GCC_OXILI_GMEM_CLK] =3D &gcc_oxili_gmem_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_MDSS_AHB_CLK] =3D &gcc_mdss_ahb_clk.clkr, + [GCC_MDSS_AXI_CLK] =3D &gcc_mdss_axi_clk.clkr, + [GCC_MDSS_BYTE0_CLK] =3D &gcc_mdss_byte0_clk.clkr, + [GCC_MDSS_ESC0_CLK] =3D &gcc_mdss_esc0_clk.clkr, + [GCC_MDSS_MDP_CLK] =3D &gcc_mdss_mdp_clk.clkr, + [GCC_MDSS_PCLK0_CLK] =3D &gcc_mdss_pclk0_clk.clkr, + [GCC_MDSS_VSYNC_CLK] =3D &gcc_mdss_vsync_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] =3D &gcc_mss_cfg_ahb_clk.clkr, + [GCC_OXILI_AHB_CLK] =3D &gcc_oxili_ahb_clk.clkr, + [GCC_OXILI_GFX3D_CLK] =3D &gcc_oxili_gfx3d_clk.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PRNG_AHB_CLK] =3D &gcc_prng_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, + [GCC_GTCU_AHB_CLK] =3D &gcc_gtcu_ahb_clk.clkr, + [GCC_JPEG_TBU_CLK] =3D &gcc_jpeg_tbu_clk.clkr, + [GCC_MDP_TBU_CLK] =3D &gcc_mdp_tbu_clk.clkr, + [GCC_SMMU_CFG_CLK] =3D &gcc_smmu_cfg_clk.clkr, + [GCC_VENUS_TBU_CLK] =3D &gcc_venus_tbu_clk.clkr, + [GCC_VFE_TBU_CLK] =3D &gcc_vfe_tbu_clk.clkr, + [GCC_USB2A_PHY_SLEEP_CLK] =3D &gcc_usb2a_phy_sleep_clk.clkr, + [GCC_USB_HS_AHB_CLK] =3D &gcc_usb_hs_ahb_clk.clkr, + [GCC_USB_HS_SYSTEM_CLK] =3D &gcc_usb_hs_system_clk.clkr, + [GCC_VENUS0_AHB_CLK] =3D &gcc_venus0_ahb_clk.clkr, + [GCC_VENUS0_AXI_CLK] =3D &gcc_venus0_axi_clk.clkr, + [GCC_VENUS0_VCODEC0_CLK] =3D &gcc_venus0_vcodec0_clk.clkr, + [GCC_APSS_TCU_CLK] =3D &gcc_apss_tcu_clk.clkr, + [GCC_GFX_TCU_CLK] =3D &gcc_gfx_tcu_clk.clkr, + [GCC_BIMC_GFX_CLK] =3D &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_GPU_CLK] =3D &gcc_bimc_gpu_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] =3D &gcc_mss_q6_bimc_axi_clk.clkr, + [GPLL3] =3D &gpll3.clkr, + [GPLL3_EARLY] =3D &gpll3_early.clkr, + [GPLL4] =3D &gpll4.clkr, + [GPLL4_VOTE] =3D &gpll4_vote, + [GPLL6] =3D &gpll6.clkr, + [GPLL6_VOTE] =3D &gpll6_vote, + [GCC_GFX_TBU_CLK] =3D &gcc_gfx_tbu_clk.clkr, + [GCC_CPP_TBU_CLK] =3D &gcc_cpp_tbu_clk.clkr, + [USB_FS_SYSTEM_CLK_SRC] =3D &usb_fs_system_clk_src.clkr, + [USB_FS_IC_CLK_SRC] =3D &usb_fs_ic_clk_src.clkr, + [GCC_USB_FS_AHB_CLK] =3D &gcc_usb_fs_ahb_clk.clkr, + [GCC_USB_HS_PHY_CFG_AHB_CLK] =3D &gcc_usb_hs_phy_cfg_ahb_clk.clkr, + [GCC_USB_FS_IC_CLK] =3D &gcc_usb_fs_ic_clk.clkr, + [GCC_USB_FS_SYSTEM_CLK] =3D &gcc_usb_fs_system_clk.clkr, + [GCC_VENUS0_CORE0_VCODEC0_CLK] =3D &gcc_venus0_core0_vcodec0_clk.clkr, + [GCC_VENUS0_CORE1_VCODEC0_CLK] =3D &gcc_venus0_core1_vcodec0_clk.clkr, + [GCC_OXILI_TIMER_CLK] =3D &gcc_oxili_timer_clk.clkr, + [BLSP2_QUP1_I2C_APPS_CLK_SRC] =3D &blsp2_qup1_i2c_apps_clk_src.clkr, + [BLSP2_QUP1_SPI_APPS_CLK_SRC] =3D &blsp2_qup1_spi_apps_clk_src.clkr, + [BLSP2_QUP2_I2C_APPS_CLK_SRC] =3D &blsp2_qup2_i2c_apps_clk_src.clkr, + [BLSP2_QUP2_SPI_APPS_CLK_SRC] =3D &blsp2_qup2_spi_apps_clk_src.clkr, + [BLSP2_QUP3_I2C_APPS_CLK_SRC] =3D &blsp2_qup3_i2c_apps_clk_src.clkr, + [BLSP2_QUP3_SPI_APPS_CLK_SRC] =3D &blsp2_qup3_spi_apps_clk_src.clkr, + [BLSP2_QUP4_I2C_APPS_CLK_SRC] =3D &blsp2_qup4_i2c_apps_clk_src.clkr, + [BLSP2_QUP4_SPI_APPS_CLK_SRC] =3D &blsp2_qup4_spi_apps_clk_src.clkr, + [BLSP2_UART1_APPS_CLK_SRC] =3D &blsp2_uart1_apps_clk_src.clkr, + [BLSP2_UART2_APPS_CLK_SRC] =3D &blsp2_uart2_apps_clk_src.clkr, + [GCC_BLSP2_AHB_CLK] =3D &gcc_blsp2_ahb_clk.clkr, + [GCC_BLSP2_QUP1_I2C_APPS_CLK] =3D &gcc_blsp2_qup1_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP1_SPI_APPS_CLK] =3D &gcc_blsp2_qup1_spi_apps_clk.clkr, + [GCC_BLSP2_QUP2_I2C_APPS_CLK] =3D &gcc_blsp2_qup2_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP2_SPI_APPS_CLK] =3D &gcc_blsp2_qup2_spi_apps_clk.clkr, + [GCC_BLSP2_QUP3_I2C_APPS_CLK] =3D &gcc_blsp2_qup3_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP3_SPI_APPS_CLK] =3D &gcc_blsp2_qup3_spi_apps_clk.clkr, + [GCC_BLSP2_QUP4_I2C_APPS_CLK] =3D &gcc_blsp2_qup4_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP4_SPI_APPS_CLK] =3D &gcc_blsp2_qup4_spi_apps_clk.clkr, + [GCC_BLSP2_UART1_APPS_CLK] =3D &gcc_blsp2_uart1_apps_clk.clkr, + [GCC_BLSP2_UART2_APPS_CLK] =3D &gcc_blsp2_uart2_apps_clk.clkr, + [VFE1_CLK_SRC] =3D &vfe1_clk_src.clkr, + [GCC_CAMSS_VFE1_CLK] =3D &gcc_camss_vfe1_clk.clkr, + [GCC_CAMSS_VFE1_AHB_CLK] =3D &gcc_camss_vfe1_ahb_clk.clkr, + [GCC_CAMSS_VFE1_AXI_CLK] =3D &gcc_camss_vfe1_axi_clk.clkr, + [GCC_CAMSS_CSI_VFE1_CLK] =3D &gcc_camss_csi_vfe1_clk.clkr, + [MCLK2_CLK_SRC] =3D &mclk2_clk_src.clkr, + [GCC_CAMSS_MCLK2_CLK] =3D &gcc_camss_mclk2_clk.clkr, + [GCC_VFE1_TBU_CLK] =3D &gcc_vfe1_tbu_clk.clkr, + [GCC_IPA_TBU_CLK] =3D &gcc_ipa_tbu_clk.clkr, + [GCC_CAMSS_CPP_AXI_CLK] =3D &gcc_camss_cpp_axi_clk.clkr, +}; + +static struct gdsc *gcc_msm8952_gdscs[] =3D { + [CPP_GDSC] =3D &cpp_gdsc, + [VENUS_GDSC] =3D &venus_gdsc, + [MDSS_GDSC] =3D &mdss_gdsc, + [JPEG_GDSC] =3D &jpeg_gdsc, + [VFE0_GDSC] =3D &vfe0_gdsc, + [VFE1_GDSC] =3D &vfe1_gdsc, + [OXILI_GX_GDSC] =3D &oxili_gx_gdsc, + [VENUS_CORE0_GDSC] =3D &venus_core0_gdsc, + [VENUS_CORE1_GDSC] =3D &venus_core1_gdsc, +}; + +static const struct qcom_reset_map gcc_msm8952_resets[] =3D { + [GCC_CRYPTO_BCR] =3D { 0x16000 }, + [GCC_USB_FS_BCR] =3D { 0x3f000 }, + [GCC_USB_HS_BCR] =3D { 0x41000 }, + [GCC_QUSB2_PHY_BCR] =3D { 0x4103c }, + [GCC_USB2_HS_PHY_ONLY_BCR] =3D { 0x41034 }, + [GCC_SDCC1_BCR] =3D { 0x42000 }, + [GCC_SDCC2_BCR] =3D { 0x43000 }, + [GCC_MDSS_BCR] =3D { 0x4d074 }, + [GCC_CAMSS_MICRO_BCR] =3D { 0x56008 }, + [GCC_MSS_BCR] =3D { 0x71000 }, +}; + +static const struct regmap_config gcc_msm8952_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x80000, + .fast_io =3D true, +}; + +static struct clk_alpha_pll *gcc_msm8952_alpha_plls[] =3D { + &gpll3_early, +}; + +static void clk_msm8952_regs_configure(struct device *dev, struct regmap *= regmap) +{ + /* Set Sleep and Wakeup cycles to 0 for GMEM clock */ + regmap_update_bits(regmap, gcc_oxili_gmem_clk.clkr.enable_reg, 0xff0, 0); + + /* Disable GMEM HW Dynamic, Without this write, GMEM can't get enabled */ + regmap_write(regmap, 0x7E004, 0x1); +} + +static const struct qcom_cc_driver_data gcc_msm8952_driver_data =3D { + .alpha_plls =3D gcc_msm8952_alpha_plls, + .num_alpha_plls =3D ARRAY_SIZE(gcc_msm8952_alpha_plls), + .clk_regs_configure =3D clk_msm8952_regs_configure, +}; + +static const struct qcom_cc_desc gcc_msm8952_desc =3D { + .config =3D &gcc_msm8952_regmap_config, + .clks =3D gcc_msm8952_clocks, + .num_clks =3D ARRAY_SIZE(gcc_msm8952_clocks), + .resets =3D gcc_msm8952_resets, + .num_resets =3D ARRAY_SIZE(gcc_msm8952_resets), + .gdscs =3D gcc_msm8952_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_msm8952_gdscs), + .use_rpm =3D true, + .driver_data =3D &gcc_msm8952_driver_data +}; + +static const struct of_device_id gcc_msm8952_match_table[] =3D { + { .compatible =3D "qcom,gcc-msm8952" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_msm8952_match_table); + +static int gcc_msm8952_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_msm8952_desc); +} + +static struct platform_driver gcc_msm8952_driver =3D { + .probe =3D gcc_msm8952_probe, + .driver =3D { + .name =3D "gcc-msm8952", + .of_match_table =3D gcc_msm8952_match_table, + }, +}; + +static int __init gcc_msm8952_init(void) +{ + return platform_driver_register(&gcc_msm8952_driver); +} +core_initcall(gcc_msm8952_init); + +static void __exit gcc_msm8952_exit(void) +{ + platform_driver_unregister(&gcc_msm8952_driver); +} +module_exit(gcc_msm8952_exit); + +MODULE_DESCRIPTION("Qualcomm GCC MSM8952 Driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Thu Sep 24 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7EmnZzfDK9poc2cXTOFgZErmy7j3H2YMDuUSj49idnFbGtyMZK/uU5pqoJ+/K953Ku Xynm3tzbRywGlPkd0LGIczEKPO/Zbi38T1yiufWXPTzoaBWhedRhDPTbm3FJB9AXHW 9EpSbpqtzuSrA4psMAlR241dNyPRwSjKbPVwaYSAJBdv5wuyX9HEhTJgeMG44ZsITM KwnwtMEq38GcA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 306F1C982E6; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:18:54 +0300 Subject: [PATCH v3 03/19] dt-bindings: nvmem: Add compatible for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-3-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=867; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=6JMvRgvxX2he4PG9Fo4mqxxQVXCwNkBZtmdxWuS+a1o=; b=ClIpLVxGYkGbsoPxZHFPXeK9OUKgRr+4EVaqNeySxB5n+7FGiJClSL03OKADreAzCOtMSR+Mx MfESgokzHOrAanG6sGN9o7D6COlrTWelirMITGQY1dWy+XhjtgzONz4 X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the QFPROM block found on MSM8952. Acked-by: Krzysztof Kozlowski Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Doc= umentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 566304ed4c78..646f2e8dcf4d 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -37,6 +37,7 @@ properties: - qcom,msm8916-qfprom - qcom,msm8917-qfprom - qcom,msm8937-qfprom + - qcom,msm8952-qfprom - qcom,msm8960-qfprom - qcom,msm8974-qfprom - qcom,msm8976-qfprom --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D24594F93C0; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014752; cv=none; b=Sf7OEaqHcXb47sfowMwA08pf/6NGahBDuUzpSiO47CLKLcnuCShwrlbUmqDZVnirWhFfd0ETMrlSWcdadKbTgsWPwZBb9uOuvCgnC4/7fFYqVN1TpJJj+36BhVdFW2iKHXj+bZBWhdwIE0Ul93kj3fhpwhaHvVyQHaFc1BnxJq4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014752; c=relaxed/simple; bh=9xqG+3+WmHmv5lQsSS1zepKcYxP21tK9ofhGCGMOOlo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PW6MMQDug5ZKyBs7H5DiFlVWKy8dLWjmMKfagvt4lth1X7owygIsOHu0X5HHHChWhVlrnodpfiu/9CPdpzUNztmDVnhBul1bljfGaz2CIvHBIVRhBoA3cUu3lAm0naYeUTyCVgVaMdbpMzqTvtqEu53YM4B2H/S85HHjn5WKKos= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OdTB7U0l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OdTB7U0l" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6003CC4AF49; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014752; bh=9xqG+3+WmHmv5lQsSS1zepKcYxP21tK9ofhGCGMOOlo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OdTB7U0lQewkI0pmDus7NxwFq7acEdAtJOeuxeyM0/xBhoRM9EDrVvkkiUHnf8IR0 Bp6M9orJHcVsb+FVwl2tTRDBRz8v0nqwAOCucHqCg41yYmbxHHmg5wldoSiUwykmi7 v+8y1RTKo5hvzbvLL30nQ+P+0o0SDjM56z0e3PIdms81rlWKhnuSCvo0hvJKirFWKM I7r03vGZcadTNVO3Qqq6SYHpiT6maS4Wk4D+/jW8LJHk3qdEElgzOMtptXfJsYdsbi mw10vVLaxpT8M/oJpcJw2tmbJW1VBIXdbzVMky42Hodf2gbGZJbJVH3g+EXVXH1BK3 YEW8Z05RbbWvg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4893EC982FB; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:18:55 +0300 Subject: [PATCH v3 04/19] dt-bindings: power: rpmpd: Add MSM8952 power domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-4-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=754; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=z3YwdcIAvY7eEvL/O1RSkMfScbVn/9IEcdYfTg2p+uc=; b=aD03aRLvv0uALeFCpOrG6qdXaG2xh7yMpxRCPexSUDqs3EZH4fNwHzu0upCWSCn+CDei2JEZQ t8/B0ovbu3JDDWOT6lneOyAFHnN9qW6xXWRfovibPb8icD9fO1iRHCx X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the compatible for the rpmpd found on MSM8952. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Docu= mentation/devicetree/bindings/power/qcom,rpmpd.yaml index a70bfacbc5d1..8ee1c25a7c9d 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -76,6 +76,7 @@ properties: - items: - enum: - qcom,msm8937-rpmpd + - qcom,msm8952-rpmpd - const: qcom,msm8917-rpmpd - items: - enum: --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 171754FB9B7; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; cv=none; b=dscr02/wd05nEx8IBdizYZ36YZ0T7lEqn74UOKzXg/Sh5ReHN6KjK37jE1HgBJ3DUqhGMHb2DBp5/TawDhVjSXRkSfvuaVXL8LEzBYBfOMmYIsChJkG+rcimUVLo02HMtnFlICZmBf+OIT8QIEqQ4nM5SWbaqecpKeTeFRGIyqw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; c=relaxed/simple; bh=ctHaSGcvyw3H8wQm3ii/7WZwBxWZ9vwphTZ5+6+nWy4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pfTKSrJEaDVnpBhsojD4oKWHy6rUzKBX7TnYhp56/eMKf9X36i1vkqxIRwNFeYcKpDmHkZ1C/NTTgkgSKZrT1/7DDvpZ8q9RJQlGOWcd/2VWnKALzaprmT9dVEwaNhQ6Cta5r5QvPQWioSw+nyRkl0bs7BqG7ISNYjvoCWrQk64= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KzdMzOkN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KzdMzOkN" Received: by smtp.kernel.org (Postfix) with ESMTPS id 80C21C4AF65; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014752; bh=ctHaSGcvyw3H8wQm3ii/7WZwBxWZ9vwphTZ5+6+nWy4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=KzdMzOkNOyXx50B/mZAp4Sr3zCItKvax/K+/7to3JTSZmuEkg1Fo6IXp/QiZJKhLE XlfgK9Fx7h8GzEkjNVF5OzQqudxluLBsMXvjSLn+TjAUMgNcJwXhR0wCWb5c3UD0t3 zmQluwH/ZBvdatwRj30JuTC7k1/JI3j2yEBULT08SuwWm23olKKXxHCNqH+h8F6PtJ /KFiKIboebz8ab6lnzRlvfqJN7KkfD0qVeE1ECPHB3EKJlEtcer86q+5SOXnOO3+OR PjS79Zr/bqC8g6O8LB9V3V0I8k9tX/YXyQ73mkP8a3mg1GoDES2DbVC/CaGIRCMzn4 CIDWTjE8Chbjg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 604E0C982FA; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:18:56 +0300 Subject: [PATCH v3 05/19] dt-bindings: mmc: sdhci-msm: Add MSM8952 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-5-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=861; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=uQuDsY7sKCtxhxupdBeZKbofdc/eOc+AEju250sV/h8=; b=5bo6Glg8xIDB0IqcOMpsjfx6TEdUNtAcAjWM6/Eh4Z25sWgteEFdun/P28zIXLJvbvsvxvCxQ F2N2run4UfSBrJoz80bZGUEy3gF9319Y08wgeBv0AX3+8jRewNt1abb X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the compatible string for the SDHCI controller on the MSM8952 platform. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Do= cumentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml index 69bd44e65ad7..9d4409c958fa 100644 --- a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml @@ -26,6 +26,7 @@ properties: - qcom,ipq4019-sdhci - qcom,ipq8074-sdhci - qcom,msm8226-sdhci + - qcom,msm8952-sdhci - qcom,msm8953-sdhci - qcom,msm8974-sdhci - qcom,msm8976-sdhci --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2B964F93C3; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014752; cv=none; b=tVC4SHE0c0u/Iib7pNb0htz3X0/uRGrWsqNX7ODBSKS3Jx6kE2VkACHAj0aArp3odyRE4Mp7Xfmpq3kmjVI9u1F0tYJ5tqshHSAghEC2TtcfvxJFhDSOTjNIfCDou3YhJG4Kr1yOO9fBf7DVBkvhL8BpxdwHaTyRC9wedgQBviM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014752; c=relaxed/simple; bh=wQbePRamCK6qP0HQmCfbQPjwS++8UxIWO8FopCf4Qv0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gL8USrjgdHH8vTnmoHJWGaGcw2vjAxyDc390cPy4oC+9GjPFyQCIhAKLmy91D9tPjc8X4+Rbn1RAj3No0JVTrNI2QUXn+puipbpMcrBUVHV6ijHgVaIB7TDKXe1/KobIGf00/fM9JZi0a0++hRO/F3K/EWvSj+iGzX5HqAW3Dr0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rztN/2Bu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rztN/2Bu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 902CFC2BD00; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014752; bh=wQbePRamCK6qP0HQmCfbQPjwS++8UxIWO8FopCf4Qv0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rztN/2BuhCFXQNHvQ8VJiFJVXpL1xw9rkc6SYX+/sCWTew/jjjewsWLbGAsVdT8Nm YnKK3F0O31muyHT52bd2J4dXq6lNyvxw+UCTUn28Z8a9kT6tBtctvfGLmSjV86e/st 5f2O8ej3iz3bI30z4r3VNBudscPFP9hzCagsF43CvqRliOe7JJGvMPwbYWhYTI6DVs 8RQslTDr1VZ7s2wLjdoITb8zS0e0lIzeQRxn9YrAQC5Z6P2/orMjAxiytzMpLKiJ/t duojVuJQscCTPrNPh8CSRTsXe51eF7snm5IMlPc1c1UPK+T8Jx7Q/0VCM0Kc2jh8Gf 1HKqH1mZsmpag== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7893CC982EE; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:18:57 +0300 Subject: [PATCH v3 06/19] dt-bindings: vendor-prefixes: Add General Mobile Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-6-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=921; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=PnYLUgGz3s0uCTErVdwKOvW0TSbIMZuWd4fgenpThBM=; b=oooIact20WyWw3vnWthGA4tgys+GchSsDImgXI2OZloY1CLI2yJ4FYpu2H1TfCf8iN/euYXgn MsqmOcr0/lhCkGVVwozpZirzO43nZZxcWp74nOGVPNFSnLIw3lavYc6 X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add vendor prefix for General Mobile. Link: https://www.generalmobile.com Acked-by: Krzysztof Kozlowski Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 4a5cf436eb14..8197b4155b6d 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -662,6 +662,8 @@ patternProperties: description: Gemei Digital Technology Co., Ltd. "^gemtek,.*": description: Gemtek Technology Co., Ltd. + "^generalmobile,.*": + description: General Mobile Fzc. "^genesys,.*": description: Genesys Logic, Inc. "^genexis,.*": --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBC564F93DB; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; cv=none; b=kQgI3X+30OLEUY86PLe2tvHZcWKeB/99n54pXL8EaI5JHiCY9v1x2BwGh52TtEQtLJzZYt2S2e59MxmM0nnqzx9P0iRIwbKJYVN67MX6nDMKa2nC4BvKHFMOx72Ocs/9UiXlCFrIQ5JLGYdTxoV/DRx9/PbQlPqaIj+ZL4msK6k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; c=relaxed/simple; bh=nP9JBFmDkgEbQVHNr73hEzI+IZ+hXAhU1/AGLWE1Ck0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ba1uS2XijdFA/hoiLMICfAh4l3TGiuiM/oQJ4Zp/JfvaqYWrCL5j58KhgKdgsOxIBjfqEn18P0HlDqvZgCOrkxqKgD4LCqBQODiLD27+zD8YXYASTVo6p/LtpsDLR68wjisV5y7PxfJmPtOw87Amv4UIo9JizeACtvBV7EQpe60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zw8aUJcY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zw8aUJcY" Received: by smtp.kernel.org (Postfix) with ESMTPS id B1519C2BCFB; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014752; bh=nP9JBFmDkgEbQVHNr73hEzI+IZ+hXAhU1/AGLWE1Ck0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Zw8aUJcYwtJ5e4I7FOUBhB3crzZg5ZzxAAlUWQ0D+tT0PlVp0JVGkR1BPfQJQ50YT Q7VOm3OQY24Q/+UnDetDEPDw3U3JnUhxuD9uh+Aqmj42Z+ZkgC6X9o0au2zjjXYrZp tAAZz8xAT+ohcJib+SSvLYtu8NiZ2zeaf8WEEVbasM1JuAnUB7Z6kKrlEBDCJySb8/ BPFY+H9y+ZT22toNLaxD3b0iSMCj6RFDqEzJbvKW9lkSOFQ3nbAqpMvrkqxAaPsh2a yGGK/cG++vJp5D5yG/UJpTrdcrAEIYjxeIbHx4vHams+6b+d4gfUBpOQSp7W8yyh6G txrJU+k4HyXVg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FAB9C982E6; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:18:58 +0300 Subject: [PATCH v3 07/19] dt-bindings: arm: qcom: Document MSM8952 SoC binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-7-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=1122; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=AJzo82+GowJ1DrA4G+irwKKpUINfQlsq4w+qyJQ1wNs=; b=CR+O8eOXF6KRKvbHo5vhCWclRk+uo9iFwNap7htKZyOF6mJ9MdxFR+BdM9fiJlf/E+sL4tesd uH4IEOs9GAsDAz0BpjUxeDI+4BhjbiyepRsp3bA6NhUkOiTgxrsnScW X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the MSM8952 and add General Mobile shamrock to it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index cf9d940f7371..e3b3c9b056d5 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -297,6 +297,11 @@ properties: - wingtech,wt82918hdhw39 - const: qcom,msm8939 =20 + - items: + - enum: + - generalmobile,shamrock + - const: qcom,msm8952 + - items: - enum: - flipkart,rimob @@ -1342,6 +1347,7 @@ allOf: - qcom,msm8917 - qcom,msm8937 - qcom,msm8939 + - qcom,msm8952 - qcom,msm8953 - qcom,msm8956 - qcom,msm8992 --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E4694FD26A; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; cv=none; b=EQcbwruYUEPKizVrvOIktfexly8Fp0/0zzGTA1aFayREuyu+PTC2R8wybcBnXf/6gQWGiRaME07NSuMnNNU4dF07+9Zp4FyQP4AIL81HSNgFT49tiy7pbeE88KaQSoP/oYwTBaomjEl36lidBzvYSVZjeGmJS6wW2EZ7l4D9xS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; c=relaxed/simple; bh=hMjOLXi4WnOlJoO4+au9mXBLP0X78laGn5iNJX8n4Zo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Uz264CTZrvZebrv7xWjbLDNxjePruHWjvUV719iv9JNxCKM4xX+vjiRHMz7wtxCwoWzQVev086p2hs8GJYoLXZanQV5da3FfxiFlNegRt6CcJTSechCccDJMLFjz3iKiEPz6IvZdZmNFqmgLCB/TSv+7Yx4IHUlLbBSwSUvE+B8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gCJhmdzB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gCJhmdzB" Received: by smtp.kernel.org (Postfix) with ESMTPS id EBBEAC4AF4D; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014753; bh=hMjOLXi4WnOlJoO4+au9mXBLP0X78laGn5iNJX8n4Zo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gCJhmdzBI4uafFPyvz/NA5jy3K4661cIKRLEWqXYA66qeSgJqV9exOmWUA0VKDd4l +nS8f3I20mvJabkMJZBRfF+nSWZq7QTeGaeN2Js0sXnvyO1h6Zjv2jalUzuDfr7iJW 8nU9SsI9fjMBK7Bi/nGUrfJTTJRwjkw6YnycAMRWez1naS1e6vg4WrgNx5JYzZ/8Tl 4hZv7+4h31dCR31KsN/vO6U0cVJyUZYyL8iPbiZE9Ke+xmt7C5orR0fWQjm5oUBWxD x1RI1gNLVtu8xzlVPNVHVLLdxvoL/fHUShCNi8sYKdKc4E80o8x1A3rW17OLV0nVvJ HeAaHHqUr1xKA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAB94C982ED; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:18:59 +0300 Subject: [PATCH v3 08/19] dt-bindings: iommu: qcom,iommu: Add MSM8952 IOMMU to SMMUv2 compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-8-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=899; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=0sCdnuV2zL4qFCD91/lsOBAdGEuX14F5OA12mUrh81M=; b=3wp/HtNlPzHfkvZaPzAf7wFmwQ5obdI7/17EfTPBGkMnmfiGf52VEGUMHqnrOE7CV5nhJqmeY Rd0C96WIDoSDfuPn3kcGfviiTLQElgFV64SsStjh2VK0GOAXGdTrSHl X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add MSM8952 compatible string with "qcom,msm-iommu-v2" as fallback for the MSM8952 IOMMU which is compatible with Qualcomm's secure fw "SMMU v2" implementation. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Docu= mentation/devicetree/bindings/iommu/qcom,iommu.yaml index 93a489025317..9952b9da9a6a 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml @@ -27,6 +27,7 @@ properties: - const: qcom,msm-iommu-v1 - items: - enum: + - qcom,msm8952-iommu - qcom,msm8953-iommu - qcom,msm8976-iommu - const: qcom,msm-iommu-v2 --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0E234FDA5A; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; cv=none; b=LD+kjIgfnregVyARxH/Jq3FXF2aDIAFH8Ixdw+QO75DDwzBS62nMuL+H0nd3BafPVk8aOkzyojvL9Kj0CJNuzU8l+oTxQZNH8vsWKkIfe7+T5Nwg2N6niDdbpi+e9MggQUxomybSdeW5+JJd5dBlHHWTb4BAwNv43gvBFYPP+Jw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; c=relaxed/simple; bh=ZxMzSJkRAAT8q4hnIB5+u1Z/6/ziiMQZPOtoIyl9iHo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D8YfSlLiaZvsaVlLp2PE9XaI86jIWnVViw7jEDQRUv+6m2d1aB0JUwYdqfvkL1XniJ28UwCkMZiEgJzlP4P9eX0PTExc6dJ1lIrzZskmoxzBhR2OM9hzAYa1/LJoOGYElGVeJvdXlK0EEfeoaWags7uIzknIX9Z6S93/n6raYKg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CK5Z2tAR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CK5Z2tAR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 157E0C4AF16; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014753; bh=ZxMzSJkRAAT8q4hnIB5+u1Z/6/ziiMQZPOtoIyl9iHo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CK5Z2tARvwPeZ1/xdU27WAjdzGWUjKA2V9vHyEvOAlwjAfgxCfogqYf84ze6ORhUq zqT3vQiukmFQZe/wqcZZWGXCmpx6ix5x8/kxqC10P5JZ0Lu+Add7zJCuaVp7Ev82wK H7BLXiiYUl0qVil45pKZ6GPFMoFI1im8lDvXMzx3asek7frPxxTODKdGF5124651ZK kBZZQt5fLyCpRzPCIEUtu/q0Rr9xpTXQpW/2tcsLR+/rVPhBdv6GgW59HJZ0E7YvBI ax14VHgMDVPumBJr5I3W3m+qmrsqpBi4vMuDZZymwwmc4f9k2CRFsB6zTndcaiKF35 fgCXfMoHizq5A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7488C982F7; Mon, 21 Sep 2026 18:19:12 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:19:00 +0300 Subject: [PATCH v3 09/19] dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-9-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=762; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=qeaBGCeLrtM04JD/SV5a/sI/wkX12kN/dQisJFr7ioM=; b=VdWCvBDNkApiw/UJrYCv60u25BFGJnfM7N+8tHo6WHIlKJsu+KeneYi4b3ug7N+xGJL5fL2Zf sDIB+SEtRgKCRH2qWrnV+1bZgvHggPig50SQpdxfnrID6t+2KX7hFX1 X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the qcom,tcsr-msm8952 compatible. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documen= tation/devicetree/bindings/mfd/qcom,tcsr.yaml index c3889f974ed3..a021e4dea486 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -60,6 +60,7 @@ properties: - qcom,tcsr-msm8916 - qcom,tcsr-msm8917 - qcom,tcsr-msm8937 + - qcom,tcsr-msm8952 - qcom,tcsr-msm8953 - qcom,tcsr-msm8960 - qcom,tcsr-msm8974 --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9152B4FD7BA; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; cv=none; b=YVULsyghEgCiCGaTrNXsubSwX3Ti7p7s5kK7WaIvIBXASHkcut/mED7eQXHH5WFrh3TfusHN3R5gddd67k5qGHFUSgJuGE8tEV0PZcDLfd1sBb7277ib23mkR21kChREQP3nmqlqrbyhQP4R76mAZzBCi4AvEXsnVengq7DHE78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; c=relaxed/simple; bh=kL7kpIG3qA+4AejsWI3BHXBQrYH/6KaVhM51d9C5+XE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mdzd+FMrV63a/Vg1TtoUcknpXAl543Fr7zdRnqwciH1czCTX+tXiA9Diza+/oH/rG0xB2zyfeW3wxiY/M0ubxPkPyijiFiJ7f3lG6s6/Ff4kAeA5F0CYjgAapWzcQ8kqENP+DejbVPu7HoEXdFM1hsBaxWDey5MrEZNWx+evYwk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E7pSdQwt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E7pSdQwt" Received: by smtp.kernel.org (Postfix) with ESMTPS id 28E8EC4AF1A; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014753; bh=kL7kpIG3qA+4AejsWI3BHXBQrYH/6KaVhM51d9C5+XE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=E7pSdQwtBN+vf5f/hhYLeG8xpE0N4+NCALq9uBD5VlncGsQMvh3af8JZr2rtF7Dyx ikd6eSWg6IwdgaL2UKXnlJU52qcsXZbVK9kC7MfnlueZNHsxRJ/Uj6FiR2VWYzEV7S TC12pgH/xVVQPar4Rud3Z6v+TaBRIPuyeWVrQoMNeWSWreW3e6vlzQyW+kou+mLcnV oReDWBMkrqGEHqbrU0AD8Xys1AgGgdO+nZkXnnKCfbt8Kl028ak2Bjbh219yzwPowQ EaWeRkcTKgfTf4NoxVQGL52nXQJZdhVdk148bzkteBWVmn83KZXFEGOhjRO6eYX+Ci +uqUNWgCL3Afg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EA48C982FA; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:19:01 +0300 Subject: [PATCH v3 10/19] dt-bindings: display/msm: qcom, mdp5: Add MSM8952 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-10-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=837; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=j1cyFUrA8K2mGnvaltP8lasGm8e1/N+retm6o6lMinU=; b=Oz1dz2ZWoRrkM/lfhYIwn4VuXlXdCrNE1OFmUAgmF8wpQEAerYbZSuqZHVhP2np2YFdFeO6HD 5osVLs6URJpDrK6+Y/vEPtnRtTZBqHeXZbh+19I+KrwRcYqfF1+xj01 X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add the compatible for the MDP5 found on MSM8952. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml b= /Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml index 2735c78b0b67..2f0a32a3f586 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml @@ -26,6 +26,7 @@ properties: - qcom,msm8916-mdp5 - qcom,msm8917-mdp5 - qcom,msm8937-mdp5 + - qcom,msm8952-mdp5 - qcom,msm8953-mdp5 - qcom,msm8974-mdp5 - qcom,msm8976-mdp5 --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9832D4FDA4F; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; cv=none; b=LFAjsAMiz8L/yHhtihCID0tecIuWWL+kIY3WX0vntlwNfsY3s6MOWxq9zF/rIm7BzyjEpnQhulbi4US7kpEiG1VtZ2GOZOobZyMtIYbYPngYCueoyFSDqLBXrCzOkVUyl48bLLyIG7tl2mKuDAxg1bHizhkZ8bZw1nvvr8jfc6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014753; c=relaxed/simple; bh=X7DSqOwmAcxIiCt2+nXcHu33pKG6YdQi8ZCCjwBSaI4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tEUr3iDlkNz5INZMamN6Kxl+wRxtCFwDhMTUzZKSLxpwgUlzRGncJUasK0tltORJrSXcaCh1zoowy+5a4HbtF4vAwNUhW9Pi7LYllU0KQ+JcChB/3Mc+0Kq29eAlf5gMvKXbsXCR/qVU+QdETxZ61AfJ/nolCddjdSGrpNMXrKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=umHpaTur; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="umHpaTur" Received: by smtp.kernel.org (Postfix) with ESMTPS id 51E4EC4AF0F; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014753; bh=X7DSqOwmAcxIiCt2+nXcHu33pKG6YdQi8ZCCjwBSaI4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=umHpaTurTr9vk3pM8b035xwH/vbJkvVWqsZnRGFwz5xW6leqUBj0k8+3w8QdlAQZn DC6zkZZvQchCseNTY7L6+3Ta3NuHcHzOfcHgSCAaXrV4ozuAn+JXT0WCrmdwgSoACd jMHVpMRSmr/E41XP10AWhglrbClfLQo224q3Hsg7vrCJZ+ZGOutK3HFhLaN9aBifj+ sCLEhGXAamAosOhf85LEatdjUimvq8fPF97eILjzYErQc+XUfUrJO70bwK3fKcHqA+ fJ09dM2lN7PmhmdX1I90g5TA/636L2aMbX6NKWIksQ4VRqPxZw6ayPTnhs5nPqYuGt hD23DJeU+TlDg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A3F9C982E6; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:19:02 +0300 Subject: [PATCH v3 11/19] dt-bindings: firmware: qcom,scm: Document MSM8952 SCM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-11-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=1326; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=OEY+8HQ+THyf1oFhHKgv6oxkhWtr6anAPLLMMsQ2ZwA=; b=8h2g1OsNVLQZ5G58JlmRNcIUzDJtJFplX7XTNAQKmEmnFCkJLkP35NBDD13XTbe68Xy3K/Sxe b7LmDiQhaBlDlh2nqG8YNRFGaVYsF9sg3PIH2TStKZvnx21T3Ei3Zhk X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the scm compatible for msm8952 SoC. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index ecee5aef65a7..40a267c54b00 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -45,6 +45,7 @@ properties: - qcom,scm-msm8660 - qcom,scm-msm8916 - qcom,scm-msm8937 + - qcom,scm-msm8952 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -153,6 +154,7 @@ allOf: - qcom,scm-msm8660 - qcom,scm-msm8916 - qcom,scm-msm8937 + - qcom,scm-msm8952 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -199,6 +201,7 @@ allOf: - qcom,scm-msm8226 - qcom,scm-msm8916 - qcom,scm-msm8937 + - qcom,scm-msm8952 - qcom,scm-msm8953 - qcom,scm-msm8974 - qcom,scm-msm8976 --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEF3B4FC32C; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; cv=none; b=YV1m+vT8OFxrcCa1cV+flYnBBiIrw0xm9wEt40XkNyOjvnrTfTmnc4v321GIiN6dnhwphsgeJYtInvV6yeN0UmbaxKIXUYLeCIJvBbTEmIQJ7pq6dplLnJZfy2t2ZMQBtPctsCF3z3UP5qPEYAFN47BT6Nq09P4GpB61QJpO5Z4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; c=relaxed/simple; bh=uQxBZuhyzSRvVDvx4PG5/I0odnbN9g2l43BKI3W/H7I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZE2i7/MDH55JquCx1hP7ZXTeNZRewdeL3VCGSd02HvasCRpvgCbpcBssSQxpnOksjbGfdNseVuedvCfbctFTHLBQJRd4UHp4FKglkqWJ1Hpd/7F/IDakYaAKq6vdPt3AWD4btVJ5igZgWY9f7BRtOD8F0KB/8GEAgE1v0KzLJts= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QmWp52f7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QmWp52f7" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5F9D8C4AF0E; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014753; bh=uQxBZuhyzSRvVDvx4PG5/I0odnbN9g2l43BKI3W/H7I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=QmWp52f79J9r9i7HjwALgvUJBvBJzUUTNhnafqlpSTNK653PQHaoeV24sI725vUHB sQB8TIpxT1UXb5bvzYAr1WeKvxakBaYCg/qApgC+/y+doXqeoxsrrqMypHKoiBuQIS f1ANayemXiBWyGLXVyeE6Ro4Wce6BrE/ctExV+3n3Rw9PuuF2ibUJNTUW9/jNCEbvT zTBZDsyUVX4YQbM8WvDrrzdQxpL+3/XtFR1sywL7i0bY4D1JEfh/IJwWlQ9plc1olw ZxZbuKCKss2WWmLLS0XjsibKFLgnYUhW4KJ33ZCmWLR1PFXh/7rJ43HZC5/1K4Zkus cvN9pRkCFfDiA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 439E6C982FB; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:19:03 +0300 Subject: [PATCH v3 12/19] dt-bindings: clock: qcom,rpmcc: Add MSM8952 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-12-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=845; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=CHNYHQsphKuLRM8ear9uJQ14PqO0HMwJNgURPd6NrV8=; b=PEp+BwfKYQUrAQIcgVk3NGd8VQhuG4/ZuLc1L3bk6bGK9kDA9TN5L9SKfaW7UpZgsCanXP/IY HMP3UZ9sfQ1CdAX+ULyy+UkLjKCluSLqsyYjJbKuIc4elbdkOKHyUrt X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the rpmcc found on MSM8952. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Docu= mentation/devicetree/bindings/clock/qcom,rpmcc.yaml index 17332aa55886..aa532f208f5a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml @@ -56,6 +56,11 @@ properties: - qcom,rpmcc-shikra - const: qcom,rpmcc-qcm2290 - const: qcom,rpmcc + - items: + - enum: + - qcom,rpmcc-msm8952 + - const: qcom,rpmcc-msm8976 + - const: qcom,rpmcc =20 '#clock-cells': const: 1 --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BEBF4FE2EF; Mon, 21 Sep 2026 18:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; cv=none; b=grzazpidxi0KpG0jjUS4tmql/QY3kOrx6NdXT+dPoq3Q1Nr9fxBoNGwruaqhdKReCx1Z3OAiLALO3yCNdt3OiYPOiCvulwXJbKLEjjUZQYks1270i2xGsU1n3nZq5RysmEyoxUmJsqFxwQ4f3b6XM3X2plxkflnubC4LdxZIV/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; c=relaxed/simple; bh=68xt0rCfMk3htQ+CNQtRlu7SHWfHYk23uy9xMNYUavE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hW1enxJuJIo6gheuG6WYzdmNvQRcB5orhq1nxus7jJYccwrqCIu3dYkmzP95UPyOJA7vnE2b+Ij0IbioXXSm+j4+HwszYK/HmQ5esTESnr86171Bd5EbimWcfjenC1sU96DLsXyvKY4txqEipVZ0JXZBUgfYW9oYvGmajptTr4g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZN9YXJj0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZN9YXJj0" Received: by smtp.kernel.org (Postfix) with ESMTPS id 840BDC4DDED; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014753; bh=68xt0rCfMk3htQ+CNQtRlu7SHWfHYk23uy9xMNYUavE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZN9YXJj0fGFK6AUFhbXnWFffp0y4s82+p4PsgoN4dL7FEpM58cnItW0FjJWCFTb5p WCxkqlLsg7XjXD87ZgHI3yITT2lDrWl6AQc8BCFQVuM5JJ5gIGTROPmrm1esLcmUcr 3O8vjFObtUv8k9DsRf7np2VF8VAeUzPGkwBdDR6fT3yU8x35s3GmuF5+EIgp8Wozdj Ekjuj9Rsuh+JXIn8Mg0GgbW215FORK+cVQ1fAmclGhCuMwq09d7xcexNayeX21VKL9 I3Ag1XEhaiJAx/Us+MVoXbh89TMGK7LpxYX3alLDlHPoOtdD6CiCXGmJ69gIfEB1A9 T9KLc0rg+3x4g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EB22C982ED; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:19:04 +0300 Subject: [PATCH v3 13/19] drm: msm: mdp5: Add MDP5 configuration for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-13-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=2908; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=iJr3V7WxoPjZJBrBl5G8abT5fWMjrLqAWAzBrQzyHX8=; b=dAS28igLGe744nahp/4sICanJ2FQZrszQF6q52UAZfRPDa5au5ffnkdHIc4IJsPXsPKDAGLnm qeBmlBArIMbCk7AUsZKnMWIPMuW0C4oTIIcSAnLZdfmvVx0i9IoO+tv X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add the mdp5_cfg_hw entry for MDP5 version v1.12 found on MSM8952. Signed-off-by: Muzaffer Kadir --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 81 ++++++++++++++++++++++++++++= ++++ 1 file changed, 81 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm= /disp/mdp5/mdp5_cfg.c index 7c91fc1915f3..d34c94d6f7e2 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -744,6 +744,86 @@ static const struct mdp5_cfg_hw msm8x76_config =3D { .max_clk =3D 360000000, }; =20 +static const struct mdp5_cfg_hw msm8952_config =3D { + .name =3D "msm8952", + .mdp =3D { + .count =3D 1, + .base =3D { 0x0 }, + .caps =3D MDP_CAP_SMP | + 0, + }, + .smp =3D { + .mmb_count =3D 8, + .mmb_size =3D 8192, + .clients =3D { + [SSPP_VIG0] =3D 1, [SSPP_DMA0] =3D 4, + [SSPP_RGB0] =3D 7, [SSPP_RGB1] =3D 8, + }, + }, + .ctl =3D { + .count =3D 3, + .base =3D { 0x01000, 0x01200, 0x01400 }, + .flush_hw_mask =3D 0xffffffff, + }, + .pipe_vig =3D { + .count =3D 1, + .base =3D { 0x04000 }, + .caps =3D MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | + MDP_PIPE_CAP_DECIMATION, + }, + .pipe_rgb =3D { + .count =3D 2, + .base =3D { 0x14000, 0x16000 }, + .caps =3D MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_DECIMATION, + }, + .pipe_dma =3D { + .count =3D 1, + .base =3D { 0x24000 }, + .caps =3D MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, + }, + .pipe_cursor =3D { + .count =3D 1, + .base =3D { 0x440DC }, + .caps =3D MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SW_PIX_EXT | + MDP_PIPE_CAP_CURSOR | + 0, + }, + .lm =3D { + .count =3D 2, + .base =3D { 0x44000, 0x47000 }, + .instances =3D { + { .id =3D 0, .pp =3D 0, .dspp =3D 0, + .caps =3D MDP_LM_CAP_DISPLAY, }, + { .id =3D 3, .pp =3D -1, .dspp =3D -1, + .caps =3D MDP_LM_CAP_WB }, + }, + .nb_stages =3D 8, + .max_width =3D 2048, + .max_height =3D 0xFFFF, + }, + .dspp =3D { + .count =3D 1, + .base =3D { 0x54000 }, + + }, + .pp =3D { + .count =3D 3, + .base =3D { 0x70000, 0x70800, 0x72000 }, + }, + .intf =3D { + .base =3D { 0x00000, 0x6a800 }, + .connect =3D { + [0] =3D INTF_DISABLED, + [1] =3D INTF_DSI, + }, + }, + .max_clk =3D 320000000, +}; + static const struct mdp5_cfg_hw msm8x53_config =3D { .name =3D "msm8x53", .mdp =3D { @@ -1017,6 +1097,7 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[= ] =3D { { .revision =3D 9, .config =3D { .hw =3D &msm8x94_config } }, { .revision =3D 7, .config =3D { .hw =3D &msm8x96_config } }, { .revision =3D 11, .config =3D { .hw =3D &msm8x76_config } }, + { .revision =3D 12, .config =3D { .hw =3D &msm8952_config } }, { .revision =3D 14, .config =3D { .hw =3D &msm8937_config } }, { .revision =3D 15, .config =3D { .hw =3D &msm8917_config } }, { .revision =3D 16, .config =3D { .hw =3D &msm8x53_config } }, --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FD144FE2F7; Mon, 21 Sep 2026 18:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-14-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. 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Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=1046; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=wTQZRJDoSbh+aK8zsamDgiJT0DGZohLPPtS+hjHbra4=; b=n1lp4+U7Yh5t8+vd3zap8e9dK5jdFN+aOP91W7fWczSgbfTQZcB8SSEsvOooA9L6WjpYpjTrJ e1CYQqKxYLbDniOP6fLzy8l3+5cYhz9WFVxZrr4fIlG3XFfXXNdv7XX X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir MSM8952 uses Adreno 405 and predates ubwc just like MSM8939. Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Muzaffer Kadir --- drivers/soc/qcom/ubwc_config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 36c90f72943f..53c1df3ca641 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -130,6 +130,7 @@ static const struct of_device_id qcom_ubwc_configs[] __= maybe_unused =3D { { .compatible =3D "qcom,msm8937", .data =3D &ubwc_1_0_hbb14 }, { .compatible =3D "qcom,msm8929", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8939", .data =3D &no_ubwc_data }, + { .compatible =3D "qcom,msm8952", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8953", .data =3D &ubwc_1_0_hbb14 }, { .compatible =3D "qcom,msm8956", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8974", .data =3D &no_ubwc_data }, --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41A7550129E; Mon, 21 Sep 2026 18:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; cv=none; b=VohkLz27LZUP3p5rkkdj6JRIbl6xtQgXuPP29HU9b1goukPTK6q28bhTKPhKedRJGzzU4z/eneaH/CPlq5FGxRtglHbp95iZRMm0l6ZpKQ42DfwVSQvNZ6HcuapiMWGdmdMZ2vukrI7akTHxaAL5nSsAnDl83xZVG4wO45rtJXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; c=relaxed/simple; bh=I4CTX75TF5hVx5UxMd8q7ZxWApioKhsfuYRkgccb7/o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cOINJz/e7jnHQ1JZPg5W7Vbtz9XH29pOzxwNDlamEpw7FJvENdd1eGBl+ZF0Ho6/J+JeVMbPS5nSG8YDIBPQMJRdLXw6VBSgYpsRw1NFP51RiMJ1SdPJ7tXfw3XqYDKYIah+S0KeGhicUBKWfCfxkgmV7XYFGGoqPEPPAlA+2rM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g6291az3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g6291az3" Received: by smtp.kernel.org (Postfix) with ESMTPS id C02C8C4DDF9; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014753; bh=I4CTX75TF5hVx5UxMd8q7ZxWApioKhsfuYRkgccb7/o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=g6291az37M+jbAewWt/dviDpjU20rFJE1NCdhM+e/JxssfuBBdj8xYzZtI3+2imF8 i25dmSYgoxBlWA5ZKWFhgwfcyfjytxDT28yozGVTgAUz3+AeWU3X6k4zjY0PYxqc5r isAESYIyuMHiDqnwaPpopakmfeOPWYPmRf3vdEH11pZYIOo4WI8JQSsmw3bKbO32OR iYI20QMNrGRcfu/Ij8lwaZwvr1lsAE6mxmwzIH4P9DzSPamKKrYyAvLGGJtuATrAWe jZefRIckQjXmZKaZZRtU9h9d2pPsJIGjUU2Fy1uNCkI8YWLJg0tnLcjb+OPBs5mjM8 esbTm5C6MEecg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B95BC982E6; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:19:06 +0300 Subject: [PATCH v3 15/19] dt-bindings: thermal: tsens: Add MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-15-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=797; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=qpZ4iKLD/3vBtZO46iDlquc+pQ/AKxoxvg54YFCLw48=; b=MEVmTnx+ohnip6Ej+T+h5SETZc0Rm5E1ytN31Hb6t8R9MslD1QDaUhScJSXh0jPz+SK/LEF5i wnB7Eh90IYmDph9N+7OTBpG0HsLn7yMqMPzMRq9CcBklXosB6EY/Pge X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add compatible string for tsens block found in MSM8952. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Do= cumentation/devicetree/bindings/thermal/qcom-tsens.yaml index 5a8f7673e730..c78074fbcecf 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -46,6 +46,7 @@ properties: items: - enum: - qcom,msm8937-tsens + - qcom,msm8952-tsens - qcom,msm8956-tsens - qcom,msm8976-tsens - qcom,qcs404-tsens --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 598FD5013C3; Mon, 21 Sep 2026 18:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; cv=none; b=ABF3gnF8N7U2h221zawKAey00Judcfx7eza4HvRDYtpZ+FxElHOztv1B7CVzlygge+YwUqK8tCBma3oCP4WpU+JEB4BO+CGshyxzVwbVclkEAU2VTGurh7j4+N4wyCmLBOfklVyCqT7c/5iU1F3CqF2fWqxGRZ+3sNBg95rMLv4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; c=relaxed/simple; bh=e8AQbyRP7RLyAcm9yJ1C4l2EkIpH9lqpf5eaVeei7Dg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p691ERO7/jbKLJPdlt1IDNmuivFpTxNbizdtunE/krxdM2ScaNe8mM+dFP05xoJHqf0P15ZnKrjHFNDpFyMJYVcm64KqY3idzM25Ev0rFJ776rbYRVR/9tPQ5dFUMnAg7XZzYcMYJnbFTzRqsJnkt3wNgDueSGoc9ApngVgNS6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ml7SsoOA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ml7SsoOA" Received: by smtp.kernel.org (Postfix) with ESMTPS id CB77CC4AF1C; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014754; bh=e8AQbyRP7RLyAcm9yJ1C4l2EkIpH9lqpf5eaVeei7Dg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ml7SsoOAkZs5w3MfKppbtXnYfPcb3+Y4Jp5nNgANuT2i7qUincBs/aFBQPC2lG/xN ZwXiX0KyeGaS6Um/tM15qrVTpafAhSU9Q3ZLaWVfYUHUrQILyvEzQYQNwCVh7K9ko1 xN46mtfWXOX4Zfy6OUDQsD9L/9p3qBWOC+qwPM5Jo0gKh2PTzlLb5sT0+V5Yd8aeo0 ef8lQTh86Rk3OhfCM6+8gizgCProwBI4JT/1N5f60hd5QUWJffVkVIzcAh3KD9OANc rbwMkyRdSb+H9cGawJqIayr6Ah0ma7A0aQXS+GCICGFhFB1vGL4C4NKaosCmiF1B7p azYV5w7SczrgA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B30AEC982F7; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:19:07 +0300 Subject: [PATCH v3 16/19] thermal: qcom: tsens: Add support for MSM8952 tsens Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-16-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=3737; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=vXpWx7d9wR4FUlrmSi9iyg3W662IEtM1fT94x3Vg7pY=; b=78/Pu94tu2l7kpYjz44z3MaPWHG5SSGXtcpdajtedv2cwzshsRC1ZgvRYzpKsZrP0j13Yqie6 92aoKqLvUytD7TPwM/myGsZrJItU6un7mRPmesJYkVSFVMntWAPd/oD X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add MSM8952 support for tsens. Downstream does a lot of advanced things with calculations. But seems like using tsens-v1 directly works too. Link: https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-w= ear-7.0.0_r0.3/drivers/thermal/msm-tsens.c#1621 Signed-off-by: Muzaffer Kadir --- drivers/thermal/qcom/tsens-v1.c | 44 +++++++++++++++++++++++++++++++++++++= ++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v= 1.c index faa5d00788ca..f4201748ea29 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -145,6 +145,37 @@ static const struct reg_field tsens_v1_regfields[MAX_R= EGFIELDS] =3D { [TRDY] =3D REG_FIELD(TM_TRDY_OFF, 0, 0), }; =20 +static int __init init_8952(struct tsens_priv *priv) +{ + for (int i =3D 0; i < priv->num_sensors; ++i) + priv->sensor[i].slope =3D 3200; + + priv->sensor[0].p1_calib_offset =3D 2; + priv->sensor[0].p2_calib_offset =3D -1; + priv->sensor[1].p1_calib_offset =3D -4; + priv->sensor[1].p2_calib_offset =3D -4; + priv->sensor[2].p1_calib_offset =3D 4; + priv->sensor[2].p2_calib_offset =3D 5; + priv->sensor[3].p1_calib_offset =3D 1; + priv->sensor[3].p2_calib_offset =3D 1; + priv->sensor[4].p1_calib_offset =3D 2; + priv->sensor[4].p2_calib_offset =3D 3; + priv->sensor[5].p1_calib_offset =3D -1; + priv->sensor[5].p2_calib_offset =3D -1; + priv->sensor[6].p1_calib_offset =3D 0; + priv->sensor[6].p2_calib_offset =3D -1; + priv->sensor[7].p1_calib_offset =3D 3; + priv->sensor[7].p2_calib_offset =3D 4; + priv->sensor[8].p1_calib_offset =3D 2; + priv->sensor[8].p2_calib_offset =3D 4; + priv->sensor[9].p1_calib_offset =3D 0; + priv->sensor[9].p2_calib_offset =3D 0; + priv->sensor[10].p1_calib_offset =3D -3; + priv->sensor[10].p2_calib_offset =3D -2; + + return init_common(priv); +} + static int __init init_8956(struct tsens_priv *priv) { priv->sensor[0].slope =3D 3313; priv->sensor[1].slope =3D 3275; @@ -223,6 +254,19 @@ struct tsens_plat_data data_8937 =3D { .fields =3D tsens_v1_regfields, }; =20 +static const struct tsens_ops ops_8952 =3D { + .init =3D init_8952, + .calibrate =3D tsens_calibrate_common, + .get_temp =3D get_temp_tsens_valid, +}; + +struct tsens_plat_data data_8952 =3D { + .num_sensors =3D 11, + .ops =3D &ops_8952, + .feat =3D &tsens_v1_feat, + .fields =3D tsens_v1_regfields, +}; + static const struct tsens_ops ops_8956 =3D { .init =3D init_8956, .calibrate =3D tsens_calibrate_common, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b5ec70201e2f..4d7013fc79d6 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -1191,6 +1191,9 @@ static const struct of_device_id tsens_table[] =3D { }, { .compatible =3D "qcom,msm8939-tsens", .data =3D &data_8939, + }, { + .compatible =3D "qcom,msm8952-tsens", + .data =3D &data_8952, }, { .compatible =3D "qcom,msm8956-tsens", .data =3D &data_8956, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index e8376accdff3..a35b15312961 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -669,7 +669,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, = data_8974, data_9607; =20 /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_89= 56; +extern struct tsens_plat_data data_tsens_v1, data_8937, data_8952, data_89= 76, data_8956; =20 /* TSENS v1 with no RPM targets */ extern const struct tsens_plat_data data_ipq5018; --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 930D850254B; Mon, 21 Sep 2026 18:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; cv=none; b=uj7Rft+8uJ3bgN7bommHAm7KDriCr0fRLJyRUxsBbgSRrHQCUO3f0okF+FILktG6jQYwnqU/T5X7Mdi/9VuVNp3Z3VPK2dJaGInqrJAns3bZXxkajGr6Ljzp7VUA7Py6/37rqYVOmrDwdGykDSagXi2ge3A0l4RDMSYb86TeQQ4= ARC-Message-Signature: i=1; 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b=KMR0+D89TYge8iBNrD5QaXflmWk9DtOkczH0FkdqtwLyubLacGY4orb/wE1wAhy28 RxYFz2kpERuNQvINY1m3e4cUDlAWaSrkv+FJMAyLREIOLaCT2bgPaZ9akBTcDLImio fDmy2cnE7WgRH0nAQWqG863zG6ezSmYIVdcw0gbe4jfcjzdH0lI3bfnfFswCS+yn1C f1syJd0VL8kEgwp8kmeUHb7U24F21EdNzgiH75Ql73AdpA1GiFsUBP2UQudhedTOkA tqrafyHflvqjihrAQCIz1P9zOGj3L1hTFfSiiBkV+3slDrsJWpImjXIZXqMGTc8bJe KzblSxAlv70gA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1E97C982EE; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:19:08 +0300 Subject: [PATCH v3 17/19] arm64: dts: qcom: Add initial support for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-17-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. 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Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=65149; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=I3aZIezP9k09Vh30NzJkyQLwJJSeEq3LzWpbGCzFbo8=; b=3lOYqBkWOJ4jAFaW60MOiAs8M2M3VNQpxo68d4JowGX2Mzr493qsPTGBskKTgpIh5e48Lvk5p VXLc2Lbai45D03oilbuGdxGOuuqdZ9Iv2bmZ6rqDC9JNaRm6AeaOnNh X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add initial support for MSM8952 SoC. AI help is used for calculating qfprom nodes. Downstream reference for port is [1] which is very lightly modified version of [2]. Downstream reference used to calculate qfprom: [3] Currently supported features in this port: - Internal Storage support - MDSS - Basic Adsp remote proc support - Blsp 1 and 2 with all i2c and spi - Tsens support - USB - RPM with mpm and master-stats [1] https://github.com/Asderdd/android_kernel_generalmobile_shamrock/blob/c= m-14.1/arch/arm/boot/dts/qcom/msm8952.dtsi [2] https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-wea= r-7.0.0_r0.3/arch/arm/boot/dts/qcom/msm8952.dtsi [3] https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-wea= r-7.0.0_r0.3/drivers/thermal/msm-tsens.c#1621 Assisted-by: LLM Signed-off-by: Muzaffer Kadir --- arch/arm64/boot/dts/qcom/msm8952.dtsi | 2696 +++++++++++++++++++++++++++++= ++++ 1 file changed, 2696 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8952.dtsi b/arch/arm64/boot/dts/qc= om/msm8952.dtsi new file mode 100644 index 000000000000..fa343271a024 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8952.dtsi @@ -0,0 +1,2696 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2026 Muzaffer Kadir + * + * Based on msm8937.dtsi: + * Copyright (c) 2023, Dang Huynh + * adapted with data from msm8952.dtsi and msm8952-*.dtsi files in Qualcom= m's msm-3.10 release + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc0>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x40000>; + cache-unified; + }; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc1>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc3>; + }; + + cpu4: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x100>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + clocks =3D <&apcs1>; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc4>; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-unified; + }; + }; + + cpu5: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x101>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + clocks =3D <&apcs1>; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc5>; + }; + + cpu6: cpu@102 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x102>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + clocks =3D <&apcs1>; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc6>; + }; + + cpu7: cpu@103 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x103>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + clocks =3D <&apcs1>; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + qcom,acc =3D <&acc7>; + }; + + cpu-map { + /* Little Cores */ + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + /* Big Cores */ + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-msm8952", "qcom,scm"; + clocks =3D <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names =3D "core", + "bus", + "iface"; + #reset-cells =3D <1>; + + qcom,dload-mode =3D <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0x80000000 0 0>; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + qseecom_mem: reserved@85b00000 { + reg =3D <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg =3D <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + mpss_mem: mpss@86c00000 { + reg =3D <0x0 0x86c00000 0x0 0x5600000>; + no-map; + }; + + adsp_mem: adsp@8c200000 { + reg =3D <0x0 0x8c200000 0x0 0x1700000>; + no-map; + }; + + rmtfs_mem: rmtfs { + compatible =3D "qcom,rmtfs-mem"; + + size =3D <0x0 0x200000>; + alloc-ranges =3D <0x0 0xa0000000 0x0 0x2000000>; + no-map; + + qcom,client-id =3D <1>; + }; + + ramoops_mem: ramoops@dffc0000 { + compatible =3D "ramoops"; + reg =3D <0x0 0xdffc0000 0x0 0x40000>; + + record-size =3D <0x10000>; + console-size =3D <0x10000>; + pmsg-size =3D <0x20000>; + + status =3D "disabled"; + }; + + mba_mem: mba { + size =3D <0x0 0x100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + + venus_mem: venus { + size =3D <0x0 0x500000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + }; + + cpu_opp_table_c0: opp-table-c0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz =3D /bits/ 64 <403200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + }; + + cpu_opp_table_c1: opp-table-c1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + }; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000>; + }; + + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + }; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + rpm: remoteproc { + compatible =3D "qcom,msm8952-rpm-proc", "qcom,rpm-proc"; + + master-stats { + compatible =3D "qcom,rpm-master-stats"; + qcom,rpm-msg-ram =3D <&apss_master_stats>, + <&mpss_master_stats>, + <&pronto_master_stats>, + <&tz_master_stats>, + <&lpass_master_stats>; + qcom,master-names =3D "APSS", + "MPSS", + "PRONTO", + "TZ", + "LPASS"; + }; + + smd-edge { + interrupts =3D ; + qcom,ipc =3D <&apcs1 8 0>; + qcom,smd-edge =3D <15>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-msm8952", "qcom,smd-rpm"; + qcom,smd-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-msm8952", + "qcom,rpmcc-msm8976", + "qcom,rpmcc"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmpd: power-controller { + compatible =3D "qcom,msm8952-rpmpd", + "qcom,msm8917-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level =3D ; + }; + }; + }; + }; + }; + + mpm: interrupt-controller { + compatible =3D "qcom,mpm"; + + interrupts =3D ; + + mboxes =3D <&apcs1 1>; + interrupt-controller; + #interrupt-cells =3D <2>; + #power-domain-cells =3D <0>; + interrupt-parent =3D <&intc>; + qcom,rpm-msg-ram =3D <&apss_mpm>; + qcom,mpm-pin-count =3D <64>; + qcom,mpm-pin-map =3D <2 184>, /* TSENS UPLOW */ + <49 140>, /* USB ASYNC */ + <53 72>, /* MDSS */ + <58 134>, /* USB */ + <62 190>; /* SPMI */ + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + + interrupts =3D ; + + mboxes =3D <&apcs1 10>; + qcom,smem =3D <443>, <429>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + interrupt-controller; + #interrupt-cells =3D <2>; + + qcom,entry-name =3D "slave-kernel"; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + + interrupts =3D ; + + mboxes =3D <&apcs1 14>; + qcom,smem =3D <435>, <428>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + interrupt-controller; + #interrupt-cells =3D <2>; + qcom,entry-name =3D "slave-kernel"; + }; + }; + + smp2p-wcnss { + compatible =3D "qcom,smp2p"; + + interrupts =3D ; + + mboxes =3D <&apcs1 18>; + qcom,smem =3D <451>, <431>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smp2p_in: slave-kernel { + interrupt-controller; + #interrupt-cells =3D <2>; + + qcom,entry-name =3D "slave-kernel"; + }; + }; + + smsm { + compatible =3D "qcom,smsm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + mboxes =3D <0>, <&apcs1 13>, <&apcs1 9>, <&apcs1 19>; + + apps_smsm: apps@0 { + reg =3D <0>; + + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smsm: hexagon@1 { + reg =3D <1>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wcnss_smsm: wcnss@6 { + reg =3D <6>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0xffffffff>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + rng@22000 { + compatible =3D "qcom,prng"; + reg =3D <0x00022000 0x140>; + clocks =3D <&gcc GCC_PRNG_AHB_CLK>; + clock-names =3D "core"; + }; + + qfprom: qfprom@5c000 { + compatible =3D "qcom,msm8952-qfprom", "qcom,qfprom"; + reg =3D <0x0005c000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tsens_base0: base0@a0 { + reg =3D <0xa0 0x1>; + bits =3D <0 8>; + }; + + tsens_s5_p1: s5-p1@a1 { + reg =3D <0xa1 0x1>; + bits =3D <0 6>; + }; + + tsens_s5_p2: s5-p2@a1 { + reg =3D <0xa1 0x2>; + bits =3D <6 6>; + }; + + tsens_s6_p1: s6-p1@a2 { + reg =3D <0xa2 0x2>; + bits =3D <4 6>; + }; + + tsens_s6_p2: s6-p2@a3 { + reg =3D <0xa3 0x1>; + bits =3D <2 6>; + }; + + tsens_s7_p1: s7-p1@a4 { + reg =3D <0xa4 0x1>; + bits =3D <0 6>; + }; + + tsens_s7_p2: s7-p2@a4 { + reg =3D <0xa4 0x2>; + bits =3D <6 6>; + }; + + tsens_s8_p1: s8-p1@a5 { + reg =3D <0xa5 0x2>; + bits =3D <4 6>; + }; + + tsens_s8_p2: s8-p2@a6 { + reg =3D <0xa6 0x1>; + bits =3D <2 6>; + }; + + tsens_base1: base1@a7 { + reg =3D <0xa7 0x1>; + bits =3D <0 8>; + }; + + tsens_mode: mode@d0 { + reg =3D <0xd0 0x1>; + bits =3D <0 3>; + }; + + tsens_s0_p1: s0-p1@d0 { + reg =3D <0xd0 0x2>; + bits =3D <3 6>; + }; + + tsens_s0_p2: s0-p2@d1 { + reg =3D <0xd1 0x1>; + bits =3D <1 6>; + }; + + tsens_s1_p1: s1-p1@d1 { + reg =3D <0xd1 0x2>; + bits =3D <7 6>; + }; + + tsens_s1_p2: s1-p2@d2 { + reg =3D <0xd2 0x2>; + bits =3D <5 6>; + }; + + tsens_s2_p1: s2-p1@d3 { + reg =3D <0xd3 0x2>; + bits =3D <3 6>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg =3D <0xd4 0x1>; + bits =3D <1 6>; + }; + + tsens_s3_p1: s3-p1@d4 { + reg =3D <0xd4 0x2>; + bits =3D <7 6>; + }; + + tsens_s3_p2: s3-p2@d5 { + reg =3D <0xd5 0x2>; + bits =3D <5 6>; + }; + + tsens_s4_p1: s4-p1@d6 { + reg =3D <0xd6 0x2>; + bits =3D <3 6>; + }; + + tsens_s4_p2: s4-p2@d7 { + reg =3D <0xd7 0x1>; + bits =3D <1 6>; + }; + + tsens_s9_p1: s9-p1@f0 { + reg =3D <0xf0 0x1>; + bits =3D <0 6>; + }; + + tsens_s9_p2: s9-p2@f0 { + reg =3D <0xf0 0x2>; + bits =3D <6 6>; + }; + + tsens_s10_p1: s10-p1@f1 { + reg =3D <0xf1 0x2>; + bits =3D <4 6>; + }; + + tsens_s10_p2: s10-p2@f2 { + reg =3D <0xf2 0x1>; + bits =3D <2 6>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible =3D "qcom,rpm-msg-ram", "mmio-sram"; + reg =3D <0x00060000 0x8000>; + + ranges =3D <0 0x00060000 0x8000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + apss_master_stats: sram@150 { + reg =3D <0x150 0x14>; + }; + + apss_mpm: sram@1d0 { + reg =3D <0x1d0 0x64>; + }; + + mpss_master_stats: sram@1150 { + reg =3D <0x1150 0x14>; + }; + + pronto_master_stats: sram@2550 { + reg =3D <0x2550 0x14>; + }; + + tz_master_stats: sram@3550 { + reg =3D <0x3550 0x14>; + }; + + lpass_master_stats: sram@4550 { + reg =3D <0x4550 0x14>; + }; + }; + + usb_hs_phy: phy@6c000 { + compatible =3D "qcom,usb-hs-28nm-femtophy"; + reg =3D <0x0006c000 0x200>; + #phy-cells =3D <0>; + clocks =3D <&xo_board>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names =3D "ref", + "ahb", + "sleep"; + resets =3D <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names =3D "phy", "por"; + + status =3D "disabled"; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,msm8952-tsens", "qcom,tsens-v1"; + reg =3D <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells =3D <&tsens_mode>, + <&tsens_base0>, <&tsens_base1>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names =3D "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; + interrupts-extended =3D <&mpm 2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "uplow"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <11>; + }; + + restart@4ab000 { + compatible =3D "qcom,pshold"; + reg =3D <0x004ab000 0x4>; + }; + + crypto_dma: dma-controller@704000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x00704000 0x20000>; + interrupts =3D ; + #dma-cells =3D <1>; + num-channels =3D <16>; + qcom,ee =3D <1>; + qcom,num-ees =3D <4>; + qcom,controlled-remotely; + }; + + crypto: crypto@73a000 { + compatible =3D "qcom,crypto-v5.4"; + reg =3D <0x0073a000 0x6000>; + clocks =3D <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names =3D "iface", + "bus", + "core"; + dmas =3D <&crypto_dma 2>, <&crypto_dma 3>; + dma-names =3D "rx", "tx"; + }; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8952-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 134>; + wakeup-parent =3D <&mpm>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + blsp1_uart1_console_default: blsp1-uart1-console-default-state { + rx-pins { + pins =3D "gpio1"; + function =3D "blsp_uart1"; + drive-strength =3D <16>; + bias-pull-up; + bootph-all; + }; + + tx-pins { + pins =3D "gpio0"; + function =3D "blsp_uart1"; + drive-strength =3D <16>; + bias-disable; + bootph-all; + }; + }; + + blsp1_uart1_console_sleep: blsp1-uart1-console-sleep-state { + pins =3D "gpio0", "gpio1"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "blsp_uart1"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c1_default: blsp1-i2c1-default-state { + pins =3D "gpio2", "gpio3"; + function =3D "blsp_i2c1"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { + pins =3D "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_spi1_default: blsp1-spi1-default-state { + cs-pins { + pins =3D "gpio2"; + function =3D "blsp_spi1"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio0", "gpio1", "gpio3"; + function =3D "blsp_spi1"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp1_spi1_sleep: blsp1-spi1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "blsp_uart2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "blsp_i2c2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins =3D "gpio6", "gpio7"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_spi2_default: blsp1-spi2-default-state { + cs-pins { + pins =3D "gpio6"; + function =3D "blsp_spi2"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio4", "gpio5", "gpio7"; + function =3D "blsp_spi2"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp1_spi2_sleep: blsp1-spi2-sleep-state { + pins =3D "gpio4", "gpio5", "gpio6", "gpio7"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins =3D "gpio10", "gpio11"; + function =3D "blsp_i2c3"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { + pins =3D "gpio10", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + cs-pins { + pins =3D "gpio10"; + function =3D "blsp_spi3"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "blsp_spi3"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp1_spi3_sleep: blsp1-spi3-sleep-state { + pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins =3D "gpio14", "gpio15"; + function =3D "blsp_i2c4"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { + pins =3D "gpio14", "gpio15"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_spi4_default: blsp1-spi4-default-state { + cs-pins { + pins =3D "gpio14"; + function =3D "blsp_spi4"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio12", "gpio13", "gpio15"; + function =3D "blsp_spi4"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp1_spi4_sleep: blsp1-spi4-sleep-state { + pins =3D "gpio12", "gpio13", "gpio14", "gpio15"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp2_i2c1_default: blsp2-i2c1-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "blsp_i2c5"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { + pins =3D "gpio18", "gpio19"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_spi1_default: blsp2-spi1-default-state { + cs-pins { + pins =3D "gpio18"; + function =3D "blsp_spi5"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio16", "gpio17", "gpio19"; + function =3D "blsp_spi5"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp2_spi1_sleep: blsp2-spi1-sleep-state { + pins =3D "gpio16", "gpio17", "gpio18", "gpio19"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp2_i2c2_default: blsp2-i2c2-default-state { + pins =3D "gpio22", "gpio23"; + function =3D "blsp_i2c6"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { + pins =3D "gpio22", "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_spi2_default: blsp2-spi2-default-state { + cs-pins { + pins =3D "gpio22"; + function =3D "blsp_spi6"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "blsp_spi6"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp2_spi2_sleep: blsp2-spi2-sleep-state { + pins =3D "gpio20", "gpio21", "gpio22", "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp2_i2c3_default: blsp2-i2c3-default-state { + pins =3D "gpio94", "gpio95"; + function =3D "blsp_i2c7"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { + pins =3D "gpio94", "gpio95"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_spi3_default: blsp2-spi3-default-state { + cs-pins { + pins =3D "gpio94"; + function =3D "blsp_spi7"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio92", "gpio93", "gpio95"; + function =3D "blsp_spi7"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp2_spi3_sleep: blsp2-spi3-sleep-state { + pins =3D "gpio92", "gpio93", "gpio94", "gpio95"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp2_i2c4_default: blsp2-i2c4-default-state { + pins =3D "gpio98", "gpio99"; + function =3D "blsp_i2c8"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { + pins =3D "gpio98", "gpio99"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_spi4_default: blsp2-spi4-default-state { + cs-pins { + pins =3D "gpio98"; + function =3D "blsp_spi8"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spi-pins { + pins =3D "gpio96", "gpio97", "gpio99"; + function =3D "blsp_spi8"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp2_spi4_sleep: blsp2-spi4-sleep-state { + pins =3D "gpio96", "gpio97", "gpio98", "gpio99"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + sdc2_cmd_default: cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <16>; + bias-pull-up; + }; + + sdc2_data_default: data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8952"; + reg =3D <0x01800000 0x80000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01905000 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1937000 { + compatible =3D "qcom,tcsr-msm8952", "syscon"; + reg =3D <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible =3D "qcom,mdss"; + reg =3D <0x01a00000 0x1000>, + <0x01ac8000 0x3000>; + reg-names =3D "mdss_phys", + "vbif_phys"; + + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "vsync"; + + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <1>; + + resets =3D <&gcc GCC_MDSS_BCR>; + + status =3D "disabled"; + + mdss_mdp: display-controller@1a01000 { + compatible =3D "qcom,msm8952-mdp5", "qcom,mdp5"; + reg =3D <0x01a01000 0x89000>; + reg-names =3D "mdp_phys"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&gcc MDSS_GDSC>; + + iommus =3D <&apps_iommu 0x17>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_mdp_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-266670000 { + opp-hz =3D /bits/ 64 <266670000>; + required-opps =3D <&rpmpd_opp_svs_plus>; + }; + + opp-320000000 { + opp-hz =3D /bits/ 64 <320000000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@1a98000 { + compatible =3D "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x01a98000 0x25c>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + assigned-clocks =3D <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys =3D <&mdss_dsi0_phy>; + + operating-points-v2 =3D <&dsi0_opp_table>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&mdss_mdp_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-120000000 { + opp-hz =3D /bits/ 64 <120000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a98300 { + compatible =3D "qcom,dsi-phy-28nm-lp"; + reg =3D <0x01a98300 0xd4>, + <0x01a98500 0x280>, + <0x01a98780 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + }; + + gpu: gpu@1c00000 { + compatible =3D "qcom,adreno-405.0", "qcom,adreno"; + reg =3D <0x01c00000 0x10000>; + reg-names =3D "kgsl_3d0_reg_memory"; + interrupts =3D ; + interrupt-names =3D "kgsl_3d0_irq"; + clocks =3D <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>, + <&gcc GCC_OXILI_TIMER_CLK>; + clock-names =3D "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d", + "rbbmtimer"; + power-domains =3D <&gcc OXILI_GX_GDSC>; + operating-points-v2 =3D <&opp_table>; + iommus =3D <&gpu_iommu 0>, <&gpu_iommu 1>; + #cooling-cells =3D <2>; + + status =3D "disabled"; + + opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmpd_opp_min_svs>; + }; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + required-opps =3D <&rpmpd_opp_svs_plus>; + }; + + opp-465000000 { + opp-hz =3D /bits/ 64 <465000000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmpd_opp_nom_plus>; + }; + + opp-550000000 { + opp-hz =3D /bits/ 64 <550000000>; + required-opps =3D <&rpmpd_opp_turbo>; + }; + }; + }; + + apps_iommu: iommu@1e20000 { + compatible =3D "qcom,msm8952-iommu", "qcom,msm-iommu-v2"; + ranges =3D <0 0x01e20000 0x20000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names =3D "iface", "bus"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + + qcom,iommu-secure-id =3D <17>; + + /* CPP */ + iommu-ctx@13000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x13000 0x1000>; + interrupts =3D ; + }; + + /* JPEG ENC0 */ + iommu-ctx@14000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x14000 0x1000>; + interrupts =3D ; + }; + + /* VFE */ + iommu-ctx@15000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x15000 0x1000>; + interrupts =3D ; + }; + + /* VENUS NS */ + iommu-ctx@16000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x16000 0x1000>; + interrupts =3D ; + }; + + /* MDP0 */ + iommu-ctx@17000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x17000 0x1000>; + interrupts =3D ; + }; + + /* PRONTO */ + iommu-ctx@18000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x18000 0x1000>; + interrupts =3D ; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible =3D "qcom,msm8952-iommu", "qcom,msm-iommu-v2"; + ranges =3D <0 0x01f08000 0x10000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names =3D "iface", "bus"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + + qcom,iommu-secure-id =3D <18>; + + /* gfx3d user */ + iommu-ctx@0 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x0 0x1000>; + interrupts =3D ; + qcom,ctx-asid =3D <0>; + }; + + /* gfx3d secure */ + iommu-ctx@1000 { + compatible =3D "qcom,msm-iommu-v2-sec"; + reg =3D <0x1000 0x1000>; + interrupts =3D ; + qcom,ctx-asid =3D <2>; + }; + + /* gfx3d priv */ + iommu-ctx@3000 { + compatible =3D "qcom,msm-iommu-v2-sec"; + reg =3D <0x3000 0x1000>; + interrupts =3D ; + qcom,ctx-asid =3D <1>; + }; + }; + + spmi_bus: spmi@200f000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&mpm 62 IRQ_TYPE_LEVEL_HIGH>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x04044000 0x19000>; + interrupts =3D ; + #dma-cells =3D <1>; + + num-channels =3D <6>; + qcom,ee =3D <0>; + qcom,num-ees =3D <1>; + qcom,powered-remotely; + + status =3D "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible =3D "qcom,msm8952-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07824900 0x500>, <0x07824000 0x800>, <0x7824e00 0x200>; + reg-names =3D "hc", "core", "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "core", "xo"; + + resets =3D <&gcc GCC_SDCC1_BCR>; + + pinctrl-0 =3D <&sdc1_default>; + pinctrl-1 =3D <&sdc1_sleep>; + pinctrl-names =3D "default", "sleep"; + + power-domains =3D <&rpmpd RPMPD_VDDCX>; + + mmc-hs400-1_8v; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + bus-width =3D <8>; + non-removable; + + status =3D "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible =3D "qcom,msm8952-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "core", "xo"; + + resets =3D <&gcc GCC_SDCC2_BCR>; + + pinctrl-0 =3D <&sdc2_default>; + pinctrl-1 =3D <&sdc2_sleep>; + pinctrl-names =3D "default", "sleep"; + + power-domains =3D <&rpmpd RPMPD_VDDCX>; + + bus-width =3D <4>; + + status =3D "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07884000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + num-channels =3D <12>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + qcom,controlled-remotely; + }; + + blsp1_uart1: serial@78af000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078af000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_uart1_console_default>; + pinctrl-1 =3D <&blsp1_uart1_console_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078b0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_uart2_default>; + pinctrl-1 =3D <&blsp1_uart2_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "disabled"; + }; + + blsp1_i2c1: i2c@78b5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_i2c1_default>; + pinctrl-1 =3D <&blsp1_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp1_spi1: spi@78b5000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b5000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_spi1_default>; + pinctrl-1 =3D <&blsp1_spi1_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b6000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_i2c2_default>; + pinctrl-1 =3D <&blsp1_i2c2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp1_spi2: spi@78b6000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_spi2_default>; + pinctrl-1 =3D <&blsp1_spi2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp1_i2c3: i2c@78b7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_i2c3_default>; + pinctrl-1 =3D <&blsp1_i2c3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp1_spi3: spi@78b7000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_spi3_default>; + pinctrl-1 =3D <&blsp1_spi3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b8000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_i2c4_default>; + pinctrl-1 =3D <&blsp1_i2c4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp1_spi4: spi@78b8000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b8000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_spi4_default>; + pinctrl-1 =3D <&blsp1_spi4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_dma: dma-controller@78c4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x078c4000 0x17000>; + interrupts =3D ; + #dma-cells =3D <1>; + num-channels =3D <4>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + qcom,controlled-remotely; + }; + + usb: usb@78db000 { + compatible =3D "qcom,ci-hdrc"; + reg =3D <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts-extended =3D <&mpm 58 IRQ_TYPE_LEVEL_HIGH>, + <&mpm 49 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names =3D "iface", + "core"; + assigned-clocks =3D <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates =3D <80000000>; + resets =3D <&gcc GCC_USB_HS_BCR>; + reset-names =3D "core"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config =3D <0>; + dr_mode =3D "otg"; + phy_type =3D "ulpi"; + phys =3D <&usb_hs_phy>; + phy-names =3D "usb-phy"; + #reset-cells =3D <1>; + + status =3D "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07ac4000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + qcom,controlled-remotely; + }; + + blsp2_i2c1: i2c@7af5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_i2c1_default>; + pinctrl-1 =3D <&blsp2_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp2_spi1: spi@7af5000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_spi1_default>; + pinctrl-1 =3D <&blsp2_spi1_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp2_i2c2: i2c@7af6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_i2c2_default>; + pinctrl-1 =3D <&blsp2_i2c2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp2_spi2: spi@7af6000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_spi2_default>; + pinctrl-1 =3D <&blsp2_spi2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp2_i2c3: i2c@7af7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_i2c3_default>; + pinctrl-1 =3D <&blsp2_i2c3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp2_spi3: spi@7af7000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_spi3_default>; + pinctrl-1 =3D <&blsp2_spi3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp2_i2c4: i2c@7af8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af8000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_i2c4_default>; + pinctrl-1 =3D <&blsp2_i2c4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp2_spi4: spi@7af8000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af8000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_spi4_default>; + pinctrl-1 =3D <&blsp2_spi4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + imem: sram@8600000 { + compatible =3D "qcom,msm8976-imem", + "syscon", "simple-mfd"; + reg =3D <0x08600000 0x1000>; + + ranges =3D <0 0x08600000 0x1000>; + #size-cells =3D <1>; + #address-cells =3D <1>; + + pil-reloc@94c { + compatible =3D "qcom,pil-reloc-info"; + reg =3D <0x94c 0xc8>; + }; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + reg =3D <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + apcs1: mailbox@b011000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b011000 0x1000>; + #mbox-cells =3D <1>; + clocks =3D <&a53pll_c1>, + <&gcc GPLL0_VOTE>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", + "aux", + "ref"; + #clock-cells =3D <0>; + }; + + a53pll_c1: clock@b016000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b016000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + operating-points-v2 =3D <&pll_opp_table_c1>; + + pll_opp_table_c1: opp-table { + compatible =3D "operating-points-v2"; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + }; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000>; + }; + + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + }; + }; + }; + + watchdog@b017000 { + compatible =3D "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg =3D <0x0b017000 0x1000>; + interrupts =3D , + ; + clocks =3D <&sleep_clk>; + }; + + acc4: clock-controller@b088000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b088000 0x1000>; + }; + + acc5: clock-controller@b098000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b098000 0x1000>; + }; + + acc6: clock-controller@b0a8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b0a8000 0x1000>; + }; + + acc7: clock-controller@b0b8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b0b8000 0x1000>; + }; + + apcs0: mailbox@b111000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b111000 0x1000>; + #mbox-cells =3D <1>; + clocks =3D <&a53pll_c0>, + <&gcc GPLL0_VOTE>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", + "aux", + "ref"; + #clock-cells =3D <0>; + }; + + a53pll_c0: clock@b116000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b116000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + operating-points-v2 =3D <&pll_opp_table_c0>; + + pll_opp_table_c0: opp-table { + compatible =3D "operating-points-v2"; + + opp-403200000 { + opp-hz =3D /bits/ 64 <403200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + }; + }; + + timer@b120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0b120000 0x1000>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clock-frequency =3D <19200000>; + + frame@b121000 { + reg =3D <0x0b121000 0x1000>, <0x0b122000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@b123000 { + reg =3D <0x0b123000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@b124000 { + reg =3D <0x0b124000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@b125000 { + reg =3D <0x0b125000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@b126000 { + reg =3D <0x0b126000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@b127000 { + reg =3D <0x0b127000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@b128000 { + reg =3D <0x0b128000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + + acc0: clock-controller@b188000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b188000 0x1000>; + }; + + acc1: clock-controller@b198000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b198000 0x1000>; + }; + + acc2: clock-controller@b1a8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b1a8000 0x1000>; + }; + + acc3: clock-controller@b1b8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b1b8000 0x1000>; + }; + + a53pll_cci: clock@b1d0000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b1d0000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + }; + + apcs2: mailbox@b1d1000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b1d1000 0x1000>; + clocks =3D <&a53pll_cci>, + <&gcc GPLL0_VOTE>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", + "aux", + "ref"; + #clock-cells =3D <0>; + #mbox-cells =3D <1>; + }; + + adsp: remoteproc@c200000 { + compatible =3D "qcom,msm8996-adsp-pil"; + reg =3D <0x0c200000 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks =3D <&rpmcc RPM_SMD_BB_CLK1>; + clock-names =3D "xo"; + + power-domains =3D <&rpmpd RPMPD_VDDCX>; + power-domain-names =3D "cx"; + + memory-region =3D <&adsp_mem>; + + qcom,smem-states =3D <&adsp_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + smd-edge { + interrupts =3D ; + + mboxes =3D <&apcs1 8>; + + qcom,smd-edge =3D <1>; + qcom,remote-pid =3D <2>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 1>; + + trips { + modem_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + qdsp-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 2>; + + trips { + qdsp_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + l2-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 4>; + + trips { + l2_alert0: trip-point0 { + temperature =3D <50000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + l2_alert1: trip-point1 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + l2_crit: l2-crit { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 5>; + + cooling-maps { + map0 { + trip =3D <&cpu4_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu4_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu4_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 6>; + + cooling-maps { + map0 { + trip =3D <&cpu5_alert1>; + cooling-device =3D <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu5_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu5_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 7>; + + cooling-maps { + map0 { + trip =3D <&cpu6_alert1>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu6_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu6_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 8>; + + cooling-maps { + map0 { + trip =3D <&cpu7_alert1>; + cooling-device =3D <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu7_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu7_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu0-3-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 9>; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu0_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 10>; + + trips { + gpu_crit: gpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <19200000>; + }; +}; --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83B50502541; Mon, 21 Sep 2026 18:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; cv=none; b=RisrMDFUeSxmR1r6iqbBl86xQNftSiAZcWz0lzPR0BrVJk/M6siHtIAj/ervqYDksRKedotpplVwN7fUWQVs8QdptimV0mCT94AdTxjuoX2FYMFMAT0tSnBE6BvXl1zmuYCrIqZrAJtqwkaoWl5EGP0NvmF0o7C7wxS4bW591gk= ARC-Message-Signature: i=1; a=rsa-sha256; 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b=FjzzYvIdv4mz7WtH84SsnUC0ZTLkzYBWqROlEHiYWK9OPyaY9/CKyk4GbrbWKdadT GqEjWfEJ+5jwxYRF3FKoptb/S0Kaq6WjumuEPJBcojho3FnvmKadV3niN0+SOdYvd6 KbZ0GRkilqiFyAGRuCoP5vFV8VppyTDoiC6Nq09ASP6qCgxmZGbTo7uRgN4XI7+frH qZ0L0Ip+rDH4cpujXG9K8+F5fTRfBqu74z4LdmKMlbV7xRyzdk77lmZgrD/LhOtL6A 53AoHd6Pk6Wq4JC50iAuqQ08zkGfUGo/tUOQ3jQ/NsS1LIvrvZ/qj8EOsrGJ5kSNm1 XX4pMwogm/IIw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAA83C982ED; Mon, 21 Sep 2026 18:19:13 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:19:09 +0300 Subject: [PATCH v3 18/19] dt-bindings: input: touchscreen: goodix: Add binding for GT970 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-18-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=1586; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=7Oq7rS5EzM26Gux3h9WgKT4CbZy8lSOyKUpp4zcOUuY=; b=5GNutjokBiTs7aasmJJm6UC3BS8bSmyr/ejrMAdp/A7QMobG7W8nu3jKLq8jr3hqtf3F9Azi4 X+TrEwDyGrDDqR42DoAb7uezNKegEQOwSc3QOhC1Ex/mwFnXZxA9EOR X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir GT970 works with GT911 driver, document it to be used with GT911 compatible. Signed-off-by: Muzaffer Kadir --- .../bindings/input/touchscreen/goodix.yaml | 35 ++++++++++++------= ---- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.yam= l b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml index a26a54d63a1c..4be2c137abd7 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml @@ -14,21 +14,26 @@ allOf: =20 properties: compatible: - enum: - - goodix,gt1151 - - goodix,gt1158 - - goodix,gt5663 - - goodix,gt5688 - - goodix,gt911 - - goodix,gt9110 - - goodix,gt912 - - goodix,gt9147 - - goodix,gt917s - - goodix,gt927 - - goodix,gt9271 - - goodix,gt928 - - goodix,gt9286 - - goodix,gt967 + oneOf: + - enum: + - goodix,gt1151 + - goodix,gt1158 + - goodix,gt5663 + - goodix,gt5688 + - goodix,gt911 + - goodix,gt9110 + - goodix,gt912 + - goodix,gt9147 + - goodix,gt917s + - goodix,gt927 + - goodix,gt9271 + - goodix,gt928 + - goodix,gt9286 + - goodix,gt967 + - items: + - enum: + - goodix,gt970 + - const: goodix,gt911 =20 reg: enum: [ 0x5d, 0x14 ] --=20 2.55.0 From nobody Thu Sep 24 18:42:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A03A050255A; Mon, 21 Sep 2026 18:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; cv=none; b=aDUVisQf9elaSID/oCvZvlWZxfwVEfiG1v3+ePXTFTFVoBwlreUHO7LTHwcNC7eq8R3oZ7YRNxpMO7M1L0QK6ZHhueeTepHs+ACCu/bOmvdPQzLv+OYNEKQr2OJz5vqfTAO5zJI0haYjb26xaziTJAhGpSrQTaE2yv0lQppPGmw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790014754; c=relaxed/simple; bh=5cXE6uCU2V3eae7E0njrVJ4gN89dQf7mLXcJnNlcbR0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pKFS1wAzTUycph5AejUEdPoHFjYu9wAUQ3b/CaelDXN4HVWt/nRaAa9G3DvM9XAVMBc1Qv5HbtngbWvQOSTaLVQA6CKXZ0+Re0XICizFgrckzbObAgGm5BP3a3hMbzbWGiwjJElJwzWRPzuyxlg2JRHbxIO21RzK7TrbzypcPMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MJsiOM7Q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MJsiOM7Q" Received: by smtp.kernel.org (Postfix) with ESMTPS id 238BCC4DDEF; Mon, 21 Sep 2026 18:19:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790014754; bh=5cXE6uCU2V3eae7E0njrVJ4gN89dQf7mLXcJnNlcbR0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MJsiOM7QISXDgvkjS7oDOQ7I2QLIA4muXGeoDpBd0sNUEHgX2QATAfHVYphYQGAO0 W/whggP4/Sb5xHI7OgDaLLajuHdDilAu4iXRmPyDRaWw8KIsDrayhBlRbHbXnLPCxR gDNBACrdirrjOQv/umrEkeucGlJcJdsxIQXOT1KGwQ9UcvG2U5EqeJRrBzEwtoue9Z fZiE4KdN+x6n2BWCaHffIVpb+EISGXTaef23Vo8IsA95sDrneWQO6rMjXQMcPUuAcT vcnE12dn1XP366wVakfeG5NXbmNCDoYiSJEotiNZcw8gcwMRBKvGdJp1m7VR0H1AFP KqayBPmi+XJlg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C7E1C982FA; Mon, 21 Sep 2026 18:19:14 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Mon, 21 Sep 2026 21:19:10 +0300 Subject: [PATCH v3 19/19] arm64: dts: qcom: generalmobile-shamrock: new device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-msm8952-initial-support-v3-19-b96fd3fe298b@mainlining.org> References: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> In-Reply-To: <20260921-msm8952-initial-support-v3-0-b96fd3fe298b@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790014748; l=11254; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=gxJWGZasJH0N7y1/tnmz0xZTEb+9bQ5AsajURmCeODc=; b=Zx+XEpGm7jWsY+IPPp4wws/rjBYZ7hJ7JOFM+6yQtbnyAlYHjs+YZkI69BqeYdmro9vNjEQEk WGAfwDKNOOuDWwhHfYVbt7uweKuN9KOtgqDn+bf50fx7esgew9dBPeg X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add General Mobile Shamrock (GM 5 Plus). Shamrock is designed similar to L9300. Downstream reference is [1]. [1] https://github.com/Asderdd/android_kernel_generalmobile_shamrock/blob/c= m-14.1/arch/arm/boot/dts/qcom/msm8952-l9300.dtsi Signed-off-by: Muzaffer Kadir --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/msm8952-generalmobile-shamrock.dts | 435 +++++++++++++++++= ++++ 2 files changed, 436 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 5c19f945c785..7713dd4cdc06 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-samsung-a7.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-wingtech-wt82918.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-wingtech-wt82918hd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D msm8952-generalmobile-shamrock.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-flipkart-rimob.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-xiaomi-daisy.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8952-generalmobile-shamrock.dts b/= arch/arm64/boot/dts/qcom/msm8952-generalmobile-shamrock.dts new file mode 100644 index 000000000000..259c75fa4a48 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8952-generalmobile-shamrock.dts @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8952.dtsi" +#include "pm8950.dtsi" +#include "pmi8950.dtsi" +#include +#include + +/ { + model =3D "General Mobile GM 5 Plus"; + compatible =3D "generalmobile,shamrock", "qcom,msm8952"; + chassis-type =3D "handset"; + qcom,msm-id =3D ; + qcom,board-id =3D ; + + aliases { + mmc0 =3D &sdhc_1; /* SDC1 eMMC slot */ + mmc1 =3D &sdhc_2; /* SDC2 SD card slot */ + serial0 =3D &blsp1_uart2; + }; + + battery: battery { + compatible =3D "simple-battery"; + + charge-term-current-microamp =3D <100000>; + charge-full-design-microamp-hours =3D <3100000>; + constant-charge-current-max-microamp =3D <3000000>; + constant-charge-voltage-max-microvolt =3D <4400000>; + voltage-min-design-microvolt =3D <3400000>; + voltage-max-design-microvolt =3D <4400000>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + + framebuffer { + compatible =3D "simple-framebuffer"; + memory-region =3D <&cont_splash_mem>; + + width =3D <1080>; + height =3D <1920>; + stride =3D <(1080 * 3)>; + format =3D "r8g8b8"; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + /* Front Flash */ + flash-led-controller { + compatible =3D "sgmicro,sgm3140"; + + enable-gpios =3D <&tlmm 33 GPIO_ACTIVE_HIGH>; + flash-gpios =3D <&tlmm 128 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&front_flash_default>; + pinctrl-names =3D "default"; + + front_flash_led: led { + function =3D LED_FUNCTION_FLASH; + color =3D ; + flash-max-microamp =3D <1000000>; + led-max-microamp =3D <625000>; + flash-max-timeout-us =3D <1280000>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&gpio_hall_sensor_default>, <&gpio_keys_default>; + pinctrl-names =3D "default"; + + button-volume-up { + label =3D "Volume Up"; + gpios =3D <&tlmm 85 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + wakeup-source; + linux,code =3D ; + }; + + event-hall-sensor { + label =3D "Hall Effect Sensor"; + gpios =3D <&tlmm 46 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,input-type =3D ; + linux,code =3D ; + linux,can-disable; + }; + }; + + multi-led { + compatible =3D "leds-group-multicolor"; + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + leds =3D <&red_status>, <&green_status>, <&blue_status>; + }; + + reserved-memory { + cont_splash_mem: cont-splash@83200000 { + reg =3D <0x0 0x83200000 0x0 (1080 * 1920 * 3)>; + no-map; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph-pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&adsp { + status =3D "okay"; +}; + +&blsp1_i2c2 { + status =3D "okay"; + /* SMB1351 @1d charger */ + /* wsa881x-i2c @e @44 @f @45 audio amplifier */ +}; + +&blsp1_i2c3 { + status =3D "okay"; + + /* himax,852x@48 Touchscreen */ + + touchscreen@5d { + compatible =3D "goodix,gt970", "goodix,gt911"; + reg =3D <0x5d>; + interrupts-extended =3D <&tlmm 65 IRQ_TYPE_EDGE_FALLING>; + irq-gpios =3D <&tlmm 65 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&tlmm 64 GPIO_ACTIVE_HIGH>; + AVDD28-supply =3D <&pm8950_l10>; + VDDIO-supply =3D <&pm8950_l6>; + + pinctrl-0 =3D <&touchscreen_default>; + pinctrl-names =3D "default"; + + touchscreen-size-x =3D <1080>; + touchscreen-size-y =3D <1920>; + }; +}; + +&blsp2_i2c1 { + status =3D "okay"; + + /* FUSB301 @25 USB-C Controller */ + + tpa6130a2: audio-controller@60 { + compatible =3D "ti,tpa6130a2"; + reg =3D <0x60>; + pinctrl-0 =3D <&tpa6130a2_default>; + pinctrl-names =3D "default"; + power-gpio =3D <&tlmm 61 GPIO_ACTIVE_HIGH>; + Vdd-supply =3D <&pm8950_l22>; + }; + + tusb320: usb@67 { + compatible =3D "ti,tusb320"; + reg =3D <0x67>; + interrupts-extended =3D <&tlmm 45 IRQ_TYPE_EDGE_FALLING>; + }; + + led-controller@68 { + compatible =3D "si-en,sn3193"; + reg =3D <0x68>; + + shutdown-gpios =3D <&tlmm 68 GPIO_ACTIVE_HIGH>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + red_status: led@1 { + reg =3D <1>; + label =3D "red:status"; + led-max-microamp =3D <17500>; + }; + + green_status: led@2 { + reg =3D <2>; + label =3D "green:status"; + led-max-microamp =3D <17500>; + }; + + blue_status: led@3 { + reg =3D <3>; + label =3D "blue:status"; + led-max-microamp =3D <17500>; + }; + }; +}; + +&pm8950_spmi_regulators { + /* PM8950 S5 + S6 =3D VDD_APC supply */ + pm8950_s5: s5 { + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1350000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&pm8950_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pmi8950_wled { + qcom,enabled-strings =3D <0 1>; + qcom,current-limit-microamp =3D <30000>; + qcom,ovp-millivolt =3D <29500>; + qcom,external-pfet; + + status =3D "okay"; +}; + +&ramoops_mem { + status =3D "okay"; +}; + +&rpm_requests { + pm8950_rpm_regulators: regulators { + compatible =3D "qcom,rpm-pm8950-regulators"; + vdd_s1-supply =3D <&vph_pwr>; + vdd_s2-supply =3D <&vph_pwr>; + vdd_s3-supply =3D <&vph_pwr>; + vdd_s4-supply =3D <&vph_pwr>; + vdd_s6-supply =3D <&vph_pwr>; + vdd_l1_l19-supply =3D <&pm8950_s3>; + vdd_l2_l23-supply =3D <&pm8950_s3>; + vdd_l3-supply =3D <&pm8950_s3>; + vdd_l5_l6_l7_l16-supply =3D <&pm8950_s4>; + vdd_l8_l11_l12_l17_l22-supply =3D <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply =3D <&vph_pwr>; + + pm8950_s1: s1 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1225000>; + }; + + pm8950_s3: s3 { + regulator-min-microvolt =3D <1300000>; + regulator-max-microvolt =3D <1300000>; + }; + + pm8950_s4: s4 { + regulator-min-microvolt =3D <2050000>; + regulator-max-microvolt =3D <2050000>; + }; + + pm8950_l2: l2 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + /* pm8950_l3 is managed by rpmpd (RPMPD_VDDMX) */ + + pm8950_l5: l5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l6: l6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l7: l7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l8: l8 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8950_l9: l9 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l10: l10 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8950_l11: l11 { + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <2950000>; + regulator-allow-set-load; + regulator-system-load =3D <200000>; + }; + + pm8950_l12: l12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8950_l13: l13 { + regulator-min-microvolt =3D <3075000>; + regulator-max-microvolt =3D <3075000>; + }; + + pm8950_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l17: l17 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2850000>; + }; + + pm8950_l19: l19 { + regulator-min-microvolt =3D <1225000>; + regulator-max-microvolt =3D <1350000>; + }; + + pm8950_l22: l22 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8950_l23: l23 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply =3D <&pm8950_l8>; + vqmmc-supply =3D <&pm8950_l5>; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; + vmmc-supply =3D <&pm8950_l11>; + vqmmc-supply =3D <&pm8950_l12>; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32768>; +}; + +&tlmm { + gpio-reserved-ranges =3D <20 4>; /* Unknown, TZ Protected */ + + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins =3D "gpio46"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + tpa6130a2_default: tpa6130a2-default-state { + pins =3D "gpio61"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; + + touchscreen_default: touchscreen-default-state { + ts-reset-pins { + pins =3D "gpio64"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + ts-irq-pins { + pins =3D "gpio65"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + gpio_keys_default: gpio-keys-default-state { + pins =3D "gpio85"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + front_flash_default: front-flash-default-state { + enable-pins { + pins =3D "gpio33"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + flash-pins { + pins =3D "gpio128"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; +}; + +&xo_board { + clock-frequency =3D <19200000>; +}; --=20 2.55.0