From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 249FC349CF0; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; cv=none; b=NQwPXE79lGD1126bT4MsLGGbVHqSAqtQJU7KfNZXfn83ngqiqiwCvtaTbUX345qLPGE2Quj2xdY0Itye6MI4A5EfSRaU5sae7epFWi8YlAD9Wyn8nGVL5o8ptLAOuc0rMnqi+L33sktW6OeIRYblDdLIBQhe12yAPRJ7FosV/6A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; c=relaxed/simple; bh=/EqyzhFKjVT1Spu2ADyKiMSyXx4yZn96DdPYCnXHJf8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IHJmFg05sDzFdym98+mH/szQOgc7IBupzfheyCLUKwEGUl+dAAGmzDSufIxxGYwfHjaXDUxRUq3UQ2WdBREG52fyWZ9Ak7RcYn1CjHnc2+wyG7WZIo0VVjkF/jF6aBMs/g2MPbaEGr2P+927zd3LY4fA5uRmlZlW++hod1oR6DM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cDcQGHZa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cDcQGHZa" Received: by smtp.kernel.org (Postfix) with ESMTPS id B22FFC2BCFA; Mon, 21 Sep 2026 04:23:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964611; bh=/EqyzhFKjVT1Spu2ADyKiMSyXx4yZn96DdPYCnXHJf8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cDcQGHZaWO/kbpRvK/YPi0kUc2Z1tA0GpJTlLbRuZmXYhGIC7dKrO2fgVLNww/Spd r52VnBvTAe2nPGPhaEie9Zs7Ob84hjV/RQqUzR9YM/kM4IWJjX83iJHqgcX/EMCiJi e7Lt+XFuGoF77mK/isUsg2JeXqPE+T5sgNRMsc/nc9iLD2e789Sw/Be22VGgtilkHC rProapQbCQQZnJ+Me+z2i/3CQSZT+gReeE4BluLmLr9FjJ6ijub9gfmMpDWzGsi4mB 4JJEecx8iTpSdgnVaZr0LpBl8zGDc43h1RuYOIZ0lP1gH/DiNR0LcGbQsi+6h+n/W4 xiZhL2Z25P6XA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A63BC982F1; Mon, 21 Sep 2026 04:23:31 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:20 +0800 Subject: [PATCH v8 01/18] dt-bindings: arm: add Ambarella CV75 platforms Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-1-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=1876; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=a3UsADFSuMY/QlkptOgZJzk4a6/aFRhf9dYNkAufvC4=; b=tdS3O/vAb/JGuglKe/bQoaZsCa/BpNt1njxdIRQtN1ZyVZPrSBqoBqKDX8Ilr9mKyyxo7a1iB P6qsn4+mfU3Dda0EhQELXRXv0glfv6jTiNX58GhlJtXFkf/t/SdVjbp X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add the Ambarella vendor prefix and CV75 EVK board compatible for the initial SoC bring-up. Reviewed-by: Linus Walleij Reviewed-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- .../devicetree/bindings/arm/ambarella.yaml | 24 ++++++++++++++++++= ++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 ++ 2 files changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ambarella.yaml b/Documen= tation/devicetree/bindings/arm/ambarella.yaml new file mode 100644 index 000000000000..72946e94fa76 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ambarella.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ambarella.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella SoC platforms + +maintainers: + - Long Zhao + +properties: + $nodename: + const: "/" + + compatible: + oneOf: + - description: Ambarella CV75 boards + items: + - enum: + - ambarella,cv75-evk + - const: ambarella,cv75 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 85a27937832e..f48aa6dabbe9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -112,6 +112,8 @@ patternProperties: description: Amarula Solutions "^amazon,.*": description: Amazon.com, Inc. + "^ambarella,.*": + description: Ambarella, Inc. "^amcc,.*": description: Applied Micro Circuits Corporation (APM, formally AMCC) "^amd,.*": --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24BDC34CFC2; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; cv=none; b=qjSGywb/CNt6fypjJIbkNZVvcce3zDdDgbwUX84srJDSnOVxXY/K7Ichu+W8eT2RD+Olk2qUlrOAdDR+ZQ5BP0sVlJr208/Ch88Z7dW0PFgTWk4SVIA59YcWNXhx7vM9RbLtfAaNIIIrKY/Pf7uup1cDZfVypmPJFE0icwltezE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; c=relaxed/simple; bh=n2PC5Ygmm3kKQRsnARaZvzzaiZN9N9d+mwOfSpacRzw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ahU6iDRax0SRWGlScf0fUyxfskhZifTdfo+EyFSCghLGPMTYRo3w7uTx7Y/Be9lNLwAumZeFvh7jemf+gFaw7Wnb+22Kzk7SEQ20oG+051JNRaiek5lBJWJgWWSXKwesrzDno0wuMj49DLR3QR4EG9p9nLa8DcIsiola0eWskQ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qlX4nmUs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qlX4nmUs" Received: by smtp.kernel.org (Postfix) with ESMTPS id D107EC2BD01; Mon, 21 Sep 2026 04:23:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964611; bh=n2PC5Ygmm3kKQRsnARaZvzzaiZN9N9d+mwOfSpacRzw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qlX4nmUsNet0rZajFt+qle/x2v+IDWwzAOGmwx+R+eY95PnoXF6uBEqBoZLA0w6xL t5G++ihPJH/zFG919Kml6khI+69UY/QaRgepDfKDHbRgjaOkyEfUL32TtEaTlJvPBV d1ochGAodBJZBh5sipGdI5MF9M5Ww/CBjv5fQ5ieFUwF+faXa4j0YENHq/WZi3eDDt 9KT7kqba1RXW5J/9HW89/co0HT/sVLCXAzb4eKqPT8tYgB1sc1kMDbL/K1J9G6qaUw gDk2yqqwDoC5aHfbFzCdcpXtVhjkxpUVGlQHnCXxDZEVx54GQnIz4zlGI1d0qmKo+b e9auK8mv4gFTw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7583C982F3; Mon, 21 Sep 2026 04:23:31 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:21 +0800 Subject: [PATCH v8 02/18] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-2-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=934; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=sWEDtsH7Lmq1R/x+RLJKvlPiYjtNzkc/ykiOxa9OBkU=; b=wljdeKkGrqNWfzTvFFVGbZAT8zmIebsIhjl5o8Gig48qo97VDNSel1vmcxttmUsF5GL6UVc2V ROhchdi/E/2AeNjF9VSr9sQKj3GjCJwsdWTXFeNd/kteyYJT2DJOIgq X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Allow ambarella,cv75-sec-scratchpad as a syscon for the shared secure scratchpad registers on CV75. Acked-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index fe882d3f828b..9ebf702c06f1 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -32,6 +32,7 @@ properties: - allwinner,sun50i-a64-system-controller - altr,l3regs - altr,sdr-ctl + - ambarella,cv75-sec-scratchpad - amd,pensando-elba-syscon - amlogic,meson-mx-assist - amlogic,meson-mx-bootrom --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24C6234D915; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; cv=none; b=N3XI7/5FR0v86A6Dtj2rUOJWxilZU1HTMTH63AhRYq+X3alREXktAjwfXuiNNd4TcVfcz3EVErHTn4eJLzVtRXMTErJ75GCFZaArwN2TmDntkUDmP3JHTYp1qlxkstUMBp5NYwKFoUVvXmeGWZ0FYciq7T4ETzacmZlv2bvjjvI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; c=relaxed/simple; bh=TA4UvtPaI6N/mD+iZIrCt55LdDwZ1OZdGI9FuRlVZFs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IftG1XdHIT5Hww2LSO/p7ffcxmmJ4QILUJjRBmaba8zbSsoqs8OAi5z4n7esIHLP/jB/BrMSKhBfa1vcljfK8+RXLdTsqIifwHh1XpDozU8aoG7f8Gc4znPtJT7Mi3HSoGXgV7NUEHsr+gafTND9J3Ay6ssze9hSD8AQEijECpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YXDG+4iC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YXDG+4iC" Received: by smtp.kernel.org (Postfix) with ESMTPS id D88D2C32781; Mon, 21 Sep 2026 04:23:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964611; bh=TA4UvtPaI6N/mD+iZIrCt55LdDwZ1OZdGI9FuRlVZFs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YXDG+4iCz0g4AjkXp0zPgxr89+LWM92Rjw8jPEYbzh4DVwYYfv31QuRGoMh0btsDj yauHG9nRf7i5tdpJFBxZ2RzAfXDYhL8PKAixtA/TiVP2WFBcnh5OoY8U3SfUkMZ7nc HVfz24vSCkC/NdaDdvqIr85upVN0UDb6BtkFsZwjvinKyEYRXB2CYMGhuhOmvKtOdl pVqO8QP0ZSh4qFfGc9zWxlW5QTbancS/7aQ9ge7q7iguj9J+3vf6a6hmhNo/6CkpMt MgcOZrMbIFwADALzPWymO2iwHzg2lkStnPIaev4d8TUARAUwtZRdTITaGNXsg+gR4l 0l2x1uf9RVfSg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C32D2C982DA; Mon, 21 Sep 2026 04:23:31 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:22 +0800 Subject: [PATCH v8 03/18] dt-bindings: clock: add Ambarella CV75 RCT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-3-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=2969; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=gEKr05f9YAOrNVHJfKB47io9QNiMkJyDyO/ZJBUGYg0=; b=YsBZstBCVTHRbdAfyDqmGjbG5IXalvAGyKsmzWy3IbGhkf/gJs65rUlzBeP6AMaTJ+o4Z8ykb Usen9LsxnOODJs2c+jgouGEmqMqGtZbAdXuF2KyMpDVpvV+4WpNAKqg X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Document the CV75 RCT clock controller and the clock ID header used by DT consumers. Document #reset-cells for the RCT reset-provider role. Soft-reset line IDs and the reset provider driver are deferred; this series has no resets=3D consumers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- .../bindings/clock/ambarella,cv75-rct.yaml | 64 ++++++++++++++++++= ++++ include/dt-bindings/clock/ambarella,cv75-rct.h | 14 +++++ 2 files changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yam= l b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml new file mode 100644 index 000000000000..be89bd75f9e2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ambarella,cv75-rct.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella CV75 RCT Clock Controller + +maintainers: + - Long Zhao + +description: | + The RCT (Reset and Clock Tree) block on the Ambarella CV75 SoC provides + PLLs, clock muxes, dividers and soft-reset controls for on-chip + peripherals. + + The same register region is also exposed as a syscon for other SoC + blocks (e.g. pin drive-strength), hence the "syscon" compatible. + + Clock indices are defined in include/dt-bindings/clock/ambarella,cv75-rc= t.h. + +properties: + + compatible: + items: + - const: ambarella,cv75-rct + - const: syscon + + reg: + maxItems: 1 + + clocks: + description: Reference crystal oscillator (typically 24 MHz) + maxItems: 1 + + clock-names: + const: osc + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ed080000 { + compatible =3D "ambarella,cv75-rct", "syscon"; + reg =3D <0xed080000 0x1000>; + clocks =3D <&osc>; + clock-names =3D "osc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/ambarella,cv75-rct.h b/include/dt-bi= ndings/clock/ambarella,cv75-rct.h new file mode 100644 index 000000000000..b3e965b4ff2e --- /dev/null +++ b/include/dt-bindings/clock/ambarella,cv75-rct.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2026 Ambarella, Inc. + */ + +#ifndef _DT_BINDINGS_CLOCK_AMBARELLA_CV75_RCT_H +#define _DT_BINDINGS_CLOCK_AMBARELLA_CV75_RCT_H + +#define CV75_GCLK_UART0 0 +#define CV75_GCLK_CORE 1 +#define CV75_GCLK_AHB 2 +#define CV75_GCLK_APB 3 + +#endif --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4236634DB72; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; cv=none; b=W7qsUkhS0ZKOcotupkDem6Q9SW2KcnAhls/z0kgKGVnoz+kQ5JxbXUeAn2ZK6y4m9338WKoCjTOOMtAHMO7+fXGSLjv0hmS3f7N5c6TREAkNPz9yuyEvQfn8rbgot0g0v0vR7fDr7E+PxPq2zUIYmoFX4dzTk0Ci2g+TQYxdQTo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; c=relaxed/simple; bh=tvheqHsmI7hix28b7pr10B/Z5B5TUMz+iHESIt74yC0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RK5rj3myuXWIP2VhYERNMuUf5mGZJf6yDvNdfg/0wov3/EdRzp4DWprhJYJE4FRfzWmhjIKwRQMbwvecVdFhe84mRpixpvWO1X9lF2wLiTcjfUSbR2Gv01trzTWBwFXcihWQoNR4dQjfA9RIr/z/5EpBrfK4qXIHD6/sp++nT6w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jx6i9HGP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jx6i9HGP" Received: by smtp.kernel.org (Postfix) with ESMTPS id F3EA8C2BCFC; Mon, 21 Sep 2026 04:23:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964612; bh=tvheqHsmI7hix28b7pr10B/Z5B5TUMz+iHESIt74yC0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=jx6i9HGPrujPnp/P4JgwwS1Cb/wOFfosAqtycTxdtIR1QVQ2QIYUPXyFwt5KYcZcT jgH79QJCUGqEb1QkOvI7CjZiKtJMpbYsuCYnWHZxGRSAOUAtnhkdtW0WFoZoPcg3/v qF5CqK0nsjsmJpqf1drxgzWpkX4dfPm9Zxm/zMFXuHcAFKwJdDV9pTGi5b5ujTztlS fk8OdMpr8Ljr5TM20gZSrVF3EFn8XjFMwg8LkplSTrK4RhVtj6qPp8CydXVsyQXuqY IPeXHPVbXRisHzZPc1YNhRkk6g7m6zHI2mGsUpNmXt/teCYzl4y4fKg6C/KrOnJzPd 9QmijuI73eoMA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC70CC982F4; Mon, 21 Sep 2026 04:23:31 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:23 +0800 Subject: [PATCH v8 04/18] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-4-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=6407; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=dt26uw9gyEL6VIYot6EABDm601cc1K43aUBkL9kWh+Y=; b=z274Bdj/pNfKh22iOWQXfeqE/TQIp38GeRfg9DIhObS7Fr7nJRV3w1wjSGoRd10Z3TgOqyyCb NTKVAH3tZbhADMcLZAF9I1yjbSsWtHxO7C6mL1zfLRH3lPF8qxESuPW X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Document the CV75 pin controller binding using generic function and groups properties for pinmux configuration. Reviewed-by: Linus Walleij Reviewed-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- .../bindings/pinctrl/ambarella,cv75-pinctrl.yaml | 237 +++++++++++++++++= ++++ 1 file changed, 237 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinct= rl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.= yaml new file mode 100644 index 000000000000..ee464a0f80d9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml @@ -0,0 +1,237 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ambarella,cv75-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella CV75 Pin Controller + +maintainers: + - Long Zhao + +description: + The Ambarella CV75 pin controller configures pin multiplexing, bias and + drive strength for the main GPIO banks. Pin groups and their mux settings + are defined by the pin controller driver and selected by function and gr= oup + names. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: ambarella,cv75-pinctrl + + reg: + maxItems: 1 + description: IOMUX registers + + ambarella,drive-strength-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: RCT syscon containing the drive-strength registers. + + ambarella,pull-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: Secure scratchpad syscon containing the pull registers. + +patternProperties: + "^[a-z0-9-]+-pins$": + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + additionalProperties: false + + properties: + function: + enum: + - can0 + - can1 + - dmic0 + - enet0 + - hsync0 + - hsync1 + - i2c0 + - i2c1 + - i2c2 + - i2c3 + - i2cs + - i2s0 + - i2s1 + - ir + - pwm0 + - pwm1 + - pwm2 + - pwm3 + - pwm4 + - pwm5 + - pwm6 + - pwm7 + - pwm8 + - pwm9 + - pwm10 + - pwm11 + - sdmmc0 + - sdmmc1 + - snand + - spi0 + - spi1 + - spi2 + - spi3 + - spi_slave + - spinor + - uart0 + - uart1 + - uart2 + - uart3 + - uart4 + - vin_master_sync + - vsync0 + - vsync1 + - vsync2 + - vsync3 + - wdt + + groups: + items: + enum: + - can0 + - can1 + - dmic0 + - enet_2nd_ref_clk_a + - enet_2nd_ref_clk_b + - enet_ext_osc_clk + - enet0_ptp_pps_o + - hsync0 + - hsync1 + - i2c0_a + - i2c0_b + - i2c1_a + - i2c1_b + - i2c2 + - i2c3_a + - i2c3_b + - i2c3_c + - i2cs_a + - i2cs_b + - i2cs_c + - i2cs_d + - i2s0 + - i2s1 + - ir + - pwm0 + - pwm1 + - pwm2 + - pwm3 + - pwm4_a + - pwm4_b + - pwm5_a + - pwm5_b + - pwm6_a + - pwm6_b + - pwm7_a + - pwm7_b + - pwm8_a + - pwm8_b + - pwm9_a + - pwm9_b + - pwm10_a + - pwm10_b + - pwm11_a + - pwm11_b + - rgmii0 + - rmii0 + - sdmmc0_1bit + - sdmmc0_4bit + - sdmmc0_cd + - sdmmc0_hs_sel + - sdmmc0_reset + - sdmmc0_wp + - sdmmc1_1bit + - sdmmc1_4bit + - sdmmc1_cd + - sdmmc1_hs_sel + - sdmmc1_reset + - sdmmc1_wp + - snand + - spi0 + - spi1 + - spi2 + - spi3_a + - spi3_b + - spi3_c + - spi_slave_a + - spi_slave_b + - spi_slave_c + - spi_slave_d + - spi_slave_e + - spinor + - uart0 + - uart1 + - uart1_flow + - uart2_a + - uart2_b + - uart2_c + - uart2_flow_a + - uart2_flow_b + - uart3_a + - uart3_b + - uart3_flow_a + - uart3_flow_b + - uart4_a + - uart4_b + - uart4_flow_a + - uart4_flow_b + - vin_master_sync_a + - vin_master_sync_b + - vin_master_sync_c + - vin_master_sync_d + - vin_master_sync_e + - vsync0 + - vsync1 + - vsync2 + - vsync3 + - wdt_a + - wdt_b + - wdt_c + - wdt_d + - wdt_e + - wdt_f + minItems: 1 + maxItems: 6 + uniqueItems: true + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + + drive-strength: + enum: [3, 4, 5, 6, 7, 8, 9, 12] + + required: + - function + - groups + +required: + - compatible + - reg + - ambarella,drive-strength-syscon + - ambarella,pull-syscon + +unevaluatedProperties: false + +examples: + - | + pinctrl: pinctrl@e4010000 { + compatible =3D "ambarella,cv75-pinctrl"; + reg =3D <0xe4010000 0x1000>; + ambarella,drive-strength-syscon =3D <&rct>; + ambarella,pull-syscon =3D <&scratchpad>; + + uart0-pins { + function =3D "uart0"; + groups =3D "uart0"; + bias-disable; + drive-strength =3D <8>; + }; + }; --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 616F9353A98; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; cv=none; b=Um8KoK/Z74nbw+vjMEVhrqNdLSOkcp0YbWJfVinI+XwWKz4iE/djpbcKri/NXXVwPT2Kc4mLNxyXjhvfWljPtfxkRTvaotzq1gjFSO/3LL2Hce7PTRr/obYxjuqGjuHXs4JocyBs57ByuaFSOaTB1wBOaKMxA3H3doIPWeMNXLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; c=relaxed/simple; bh=iSN13jQzT5q3aGEtcq9pGlkB8alxyY2QXP+GvUaeNFQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IThmD7qvixcKRbKZs30jHwg/kjlOkwPf/g51Q9pe4ASEYzfn0DC+1VV3jJCGiTkmuvS9HKCJC76zuo+4CtMjnEtJG/v8VUis/3coZA6iY5oO8gfY3JMTwhv4Dk/zBXhUKP/Z1wjK0ra570JyuigfvdNSrqc3JFRENxqT+goKGB4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N7V3g70G; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N7V3g70G" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2E471C32782; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964612; bh=iSN13jQzT5q3aGEtcq9pGlkB8alxyY2QXP+GvUaeNFQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=N7V3g70G+bTOGPzDuOo6jB8D8KkRSRG1Dvt49X+paLpNP8zI1knerv/xcqiziifSf yPx2bHWWdAlzI2usVtJTyOwIhTF2nsv8wCLQ3yFSIJeEh5fB3VHb7VkuonlTxfZ9sm 8UGCm3TpU1rtu2bjrvn8D3CyA55UCpKv66nc8xZ/aElujIMmwgW6eo1IqxUQyPyovh scYgNAMqQXMSvC7hzXM2d/l/eioN+cXRI8SvR6EWNfMACYyeU0CX6mNjLGbnaZVYZR +nTaBpYk+0b+OsYZWJPoGVtR6zMemL2730wiL8ZT0rU/p5n1sunE6zN3kh5Xan8xV6 x/zTXby8/WD4g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18C5EC982F2; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:24 +0800 Subject: [PATCH v8 05/18] dt-bindings: gpio: pl061: add Ambarella CV75 variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-5-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=2025; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=GVEIXtfx8rpLQa9TzFd09VjRop28rVpySsmXjUcyqZs=; b=Fo85IDH9CPKUggCRVyQ2gJURzjURGeK9VwzCX0zQQavK4eGy8LQzGOd51k3V62j04DGfXFOYr uA2NQBL+8O5CEp+xRahSZ2xOdeR3F1E7oyUkJgBszjw14265YYekQ84 X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao The CV75 GPIO banks sit on the AMBA PrimeCell bus but are not register-compatible with the ARM PL061. Each bank is 32-bit and 32 lines, with extra mask/enable registers, so arm,pl061 must not be used as a fallback compatible. The AMBA core matches the PL061 driver by PrimeCell ID, not by the DT compatible string. These blocks do not implement the standard PL061 ID (0x00041061) in the ID registers, so arm,primecell-periphid is required and is fixed to 0x000e8061; the driver uses that ID to select the Ambarella layout. gpio-ranges is required because each bank is a slice of the SoC pinctrl pin space. Signed-off-by: Long Zhao --- .../devicetree/bindings/gpio/pl061-gpio.yaml | 25 ++++++++++++++++++= +--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml b/Docum= entation/devicetree/bindings/gpio/pl061-gpio.yaml index 4d970e55104b..c22dd8a1d2c1 100644 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml @@ -15,7 +15,9 @@ select: properties: compatible: contains: - const: arm,pl061 + enum: + - arm,pl061 + - ambarella,cv75-gpio required: - compatible =20 @@ -25,7 +27,9 @@ properties: =20 compatible: items: - - const: arm,pl061 + - enum: + - ambarella,cv75-gpio + - arm,pl061 - const: arm,primecell =20 reg: @@ -64,6 +68,21 @@ required: - "#gpio-cells" - gpio-controller =20 -additionalProperties: false +allOf: + - $ref: /schemas/arm/primecell.yaml# + - if: + properties: + compatible: + contains: + const: ambarella,cv75-gpio + then: + properties: + arm,primecell-periphid: + const: 0x000e8061 + required: + - arm,primecell-periphid + - gpio-ranges + +unevaluatedProperties: false =20 ... --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AA41358D37; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; cv=none; b=pTByUgzjIefvzyidG0mfnqWZqTuhq/kGOdBXFhQIhFvzaei2VAd5/UVKdpaVrlsiE5PEPglw39CIDaQP7h+bWRFk8AWX1CUh2MH0Az2pg0GeOe7RxnR/rIo5ku4ldR864jFny7OkIhEiDWapKNaBEW5gGu4mFB1bxn8A9ipU0Yw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; c=relaxed/simple; bh=vqJg9MCrHhTQ3dSYeAuOSHwl+5KNi8MVa3c/QFLqYsE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XvDvp0eTPkGNKhR1vkOUKMZqtCzyex4NX0JKcl06BZGp83ihQSN5p2B8xx8TnXzHC4LckiTRdub+IZdXa8A5JW7Y0kWM5KxtNZdugxN6tM1n4q5awNsRRRP/GJPGtzel3pzZysuxYL2XRipzhPduSBksjUx0H7j+BOMAHkic6O0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AEnVPr+p; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AEnVPr+p" Received: by smtp.kernel.org (Postfix) with ESMTPS id 48300C2BCB3; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964612; bh=vqJg9MCrHhTQ3dSYeAuOSHwl+5KNi8MVa3c/QFLqYsE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AEnVPr+pRJ3tdpUjiYAC9Y7RpjsUmjo06MfJptFDBTqP0Ha48e4QJDM80uitDGof2 lDKQM8AvbjQmWqQbhg/zppTP+raqhmGJ45DzbCNw3+q3kgFmMKLkuO9Ne3sHEFk5is 2mRXNKbn55/K7yJ02GjSEo7NrLpRxUNOnIOnPSe7MjPMicbDRuyy+W4cse2w91KOnI /8FvIeG4Ek+4Uiqa7Cl0KxzNVImbCqsDY93OoFGx8RjbVSntjZyOieLW4UrdWNEtDZ +Dpv1VcJBKa4RX2alHCIBl8dlTuzeCv79jIQ0tcTJfa+AP8JSS2M1PcFAuyqqe8kp/ f0cMOQgz4oa9A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 324C8C982F1; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:25 +0800 Subject: [PATCH v8 06/18] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-6-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=1072; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=aI42/QWFrT0q/wEmjSA5wdZvhIPXU9faQz3G+ySJ344=; b=8KQp6zk0TUfhdEk2VE/BCaiOf+RzQeeu8ZyrQ1XCsEjYoqCSww3zBoiyHWZ/H2VFTOFDotiq0 G6g7AsHZEONDt68uTJFXn0HVCjrcg9Wv+H7gbtBaTW2/1BSQi6RdQyQ X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add the Ambarella CV75 compatible string to the Synopsys DW APB UART binding. The block is Ambarella IP with a DW-like register map, so it is described as a DW APB UART variant. Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 49f51b002879..cec5c679f1a9 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - ambarella,cv75-uart - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DC1E35AC20; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; cv=none; b=H8ih10Gm3X4U1Z28tqlXDMmRooHMuUaUvclguqtSLZRJn7/ItOZ4nd3zaL1mVNBSDTxbm8o8Tapo4mVPMWNVIdDR0roi0Rag/g0dv+QtibpwdoyXFdszc+CZaZHDPHU6SHu5mmwWT6F/OBBqWt0Mh2Q1+MkXwotUw5cfGvfWYHA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; c=relaxed/simple; bh=bqgS5XpvrstWVWKP9LuvnDwflt0rXBSfiLBunIlP0Gs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z7sAPzQppaqRtgRr1pKZK6WdEttMR0d4s64B/WpfnpTKLHsCswD9nGuqkZ22K4UM4MOaaqlzPAvrQCh3kac3782K+8M/gcxO7ih+UKKTaRBQYsM6n+DCReHO+7ZgAvO61yh9Xomj6kr45lZ5JFNhR414T69KFbf/eEUhEHKfq4g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lqSzWcdk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lqSzWcdk" Received: by smtp.kernel.org (Postfix) with ESMTPS id 639ADC2BCF7; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964612; bh=bqgS5XpvrstWVWKP9LuvnDwflt0rXBSfiLBunIlP0Gs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lqSzWcdkustJ9ELjmazlRi5ZNFyZHJbqa9DWTaRKIJUAliB7itWEQNd7FzTTalCSW 5+YaGFNdWUdOVFsLbOhXYFERZSswUWBQohHv5I2AVDU5nhDSAk3GstE4acWbkvh5r5 JphyNyNp8AOQokK1FaFJQcid7h24/zpoNUIEyiuzwq648HljRr0Dyzl52BKB4a0iFS k/glwGCj+qLxGZFdb4ez/TSkCiBQdhUExBg9UmXG7ouSL1LHJhisosjvbC8kKXZaA3 cKibCma/WirBQJZNS9Ec41nL4VUe7jUMQ8obai6OKzxEMYqDCIeRcqWcMJHTHM8rHO w/DRQ22Evuzpg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FA47C982DA; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:26 +0800 Subject: [PATCH v8 07/18] clk: ambarella: add CV75 RCT clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-7-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=12327; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=QChNsrVZVY8Pzfog5BXibva/KN+iXooU+fbG0vVELS4=; b=MRHSmKyxuASqaJdk9ZyTtdamRqALbw2BRVKiFaMaPoO4zmPDpcBDrCGA4fP9Jp2Vex2m9l/DB k6/+9T5kKPBD0Mz2H8IYYI/lqiOfnXsw7kOH/3PhbKaNMPVWfi15pnZ X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add a table-driven CCF driver for the CV75 root clock tree. Register the core PLL, AHB/APB fixed factors and UART0 composite clock, with osc supplied via clk_parent_data. Signed-off-by: Long Zhao --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/ambarella/Kconfig | 9 + drivers/clk/ambarella/Makefile | 3 + drivers/clk/ambarella/clk-cv75.c | 365 +++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 379 insertions(+) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1717ce75a907..fbbf4963716c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -506,6 +506,7 @@ config COMMON_CLK_RPMI the RISC-V platform management interface (RPMI) specification. =20 source "drivers/clk/actions/Kconfig" +source "drivers/clk/ambarella/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/aspeed/Kconfig" source "drivers/clk/bcm/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index cc108a75a900..30d823ee606f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_COMMON_CLK_XGENE) +=3D clk-xgene.o =20 # please keep this section sorted lexicographically by directory path name obj-y +=3D actions/ +obj-y +=3D ambarella/ obj-y +=3D analogbits/ obj-y +=3D aspeed/ obj-$(CONFIG_COMMON_CLK_AT91) +=3D at91/ diff --git a/drivers/clk/ambarella/Kconfig b/drivers/clk/ambarella/Kconfig new file mode 100644 index 000000000000..720eebdc5c9c --- /dev/null +++ b/drivers/clk/ambarella/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config CLK_AMBARELLA_CV75 + bool "Ambarella CV75 RCT clock controller" + depends on ARCH_AMBARELLA || COMPILE_TEST + default ARCH_AMBARELLA + help + Say Y to enable the Ambarella CV75 RCT clock controller for + early bring-up clocks (core PLL, AHB, APB, UART0). diff --git a/drivers/clk/ambarella/Makefile b/drivers/clk/ambarella/Makefile new file mode 100644 index 000000000000..29555e452441 --- /dev/null +++ b/drivers/clk/ambarella/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_CLK_AMBARELLA_CV75) +=3D clk-cv75.o diff --git a/drivers/clk/ambarella/clk-cv75.c b/drivers/clk/ambarella/clk-c= v75.c new file mode 100644 index 000000000000..4071dfd75659 --- /dev/null +++ b/drivers/clk/ambarella/clk-cv75.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Ambarella CV75 RCT clock controller + * + * Copyright (C) 2026 Ambarella, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define CV75_NUM_CLKS (CV75_GCLK_APB + 1) + +#define PLL_CTRL_BYPASS BIT(2) +#define PLL_CTRL_FRAC_MODE BIT(3) +#define PLL_CTRL_FORCE_RESET BIT(4) +#define PLL_CTRL_POWER_DOWN BIT(5) +#define PLL_CTRL_HALT_VCO BIT(6) +#define PLL_CTRL_SDIV GENMASK(15, 12) +#define PLL_CTRL_SOUT GENMASK(19, 16) +#define PLL_CTRL_INTP GENMASK(30, 24) + +#define PLL_CTRL2_VCODIV_DIV2 BIT(8) +#define PLL_CTRL2_FSDIV_DIV2 BIT(9) +#define PLL_CTRL2_FSOUT_DIV2 BIT(11) +#define PLL_CTRL2_BYPASS_HSDIV BIT(12) + +struct cv75_pll_hw { + struct clk_hw hw; + u32 ctrl; + u32 frac; + u32 ctrl2; +}; + +struct cv75_clk { + void __iomem *base; + spinlock_t lock; + struct cv75_pll_hw core; + struct cv75_pll_hw enet; + struct cv75_pll_hw sd; +}; + +struct cv75_pll { + const char *name; + struct cv75_pll_hw *hw; + unsigned long flags; + u32 ctrl; + u32 frac; + u32 ctrl2; + int id; +}; + +struct cv75_fixed_factor { + const char *name; + u32 id; + struct u16_fract ratio; +}; + +struct cv75_composite { + const char *name; + const struct clk_parent_data *parents; + unsigned long flags; + u32 id; + u16 mux_reg; + u16 div_reg; + u8 num_parents; + u8 mux_shift; + u8 mux_width; + u8 div_shift; + u8 div_width; +}; + +struct cv75_composite_hw { + struct clk_mux mux; + struct clk_divider div; + struct clk_gate gate; +}; + +static struct cv75_clk cv75_ccu; + +#define CV75_PLL(_id, _name, _ctrl, _frac, _ctrl2, _flags, _hw) { \ + .name =3D _name, \ + .hw =3D _hw, \ + .flags =3D _flags, \ + .ctrl =3D _ctrl, \ + .frac =3D _frac, \ + .ctrl2 =3D _ctrl2, \ + .id =3D _id, \ +} + +static const struct cv75_pll cv75_plls[] =3D { + CV75_PLL(CV75_GCLK_CORE, "core", 0x000, 0x004, 0x100, + CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL, &cv75_ccu.core), + CV75_PLL(-1, "pll_enet", 0x520, 0x524, 0x528, + CLK_GET_RATE_NOCACHE, &cv75_ccu.enet), + CV75_PLL(-1, "pll_sd", 0x4ac, 0x4b0, 0x4b4, + CLK_GET_RATE_NOCACHE, &cv75_ccu.sd), +}; + +static const struct cv75_fixed_factor cv75_fixed_factors[] =3D { + { .id =3D CV75_GCLK_AHB, .name =3D "ahb", .ratio =3D { 1, 2 } }, + { .id =3D CV75_GCLK_APB, .name =3D "apb", .ratio =3D { 1, 4 } }, +}; + +static const struct clk_parent_data cv75_uart_parents[] =3D { + { .fw_name =3D "osc" }, + { .hw =3D &cv75_ccu.core.hw }, + { .hw =3D &cv75_ccu.enet.hw }, + { .hw =3D &cv75_ccu.sd.hw }, +}; + +#define CV75_COMPOSITE(_id, _name, _parents, _mreg, _mshift, _mwidth, \ + _dreg, _dshift, _dwidth, _flags) \ +{ \ + .id =3D _id, \ + .name =3D _name, \ + .parents =3D _parents, \ + .num_parents =3D ARRAY_SIZE(_parents), \ + .mux_reg =3D _mreg, \ + .mux_shift =3D _mshift, \ + .mux_width =3D _mwidth, \ + .div_reg =3D _dreg, \ + .div_shift =3D _dshift, \ + .div_width =3D _dwidth, \ + .flags =3D _flags, \ +} + +static const struct cv75_composite cv75_composites[] =3D { + CV75_COMPOSITE(CV75_GCLK_UART0, "uart0", cv75_uart_parents, + 0x1c8, 0, 2, 0x038, 0, 24, + CLK_SET_RATE_NO_REPARENT), +}; + +#define to_cv75_pll(_hw) container_of(_hw, struct cv75_pll_hw, hw) + +static unsigned long cv75_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cv75_pll_hw *pll =3D to_cv75_pll(hw); + u32 ctrl, ctrl2, frac_val; + u32 intp, sdiv, sout; + u32 vcodiv, fsdiv, fsout; + u64 vco, frac =3D 0; + + ctrl =3D readl_relaxed(cv75_ccu.base + pll->ctrl); + if (ctrl & (PLL_CTRL_POWER_DOWN | PLL_CTRL_HALT_VCO | PLL_CTRL_FORCE_RESE= T)) + return 0; + + if (ctrl & PLL_CTRL_BYPASS) + return parent_rate; + + ctrl2 =3D readl_relaxed(cv75_ccu.base + pll->ctrl2); + intp =3D FIELD_GET(PLL_CTRL_INTP, ctrl) + 1; + sdiv =3D FIELD_GET(PLL_CTRL_SDIV, ctrl) + 1; + sout =3D FIELD_GET(PLL_CTRL_SOUT, ctrl) + 1; + vcodiv =3D (ctrl2 & PLL_CTRL2_VCODIV_DIV2) ? 2 : 1; + fsdiv =3D (ctrl2 & PLL_CTRL2_FSDIV_DIV2) ? 2 : 1; + fsout =3D (ctrl2 & PLL_CTRL2_FSOUT_DIV2) ? 2 : 1; + + vco =3D (u64)parent_rate * vcodiv * fsdiv * intp * sdiv; + if (ctrl & PLL_CTRL_FRAC_MODE) { + frac_val =3D readl_relaxed(cv75_ccu.base + pll->frac); + frac =3D mul_u64_u32_shr((u64)parent_rate * vcodiv * fsdiv * sdiv, + frac_val, 32); + vco +=3D frac; + } + + if (!(ctrl2 & PLL_CTRL2_BYPASS_HSDIV)) + vco =3D div_u64(vco, (u64)vcodiv * fsout * sout); + + return vco; +} + +static const struct clk_ops cv75_pll_ops =3D { + .recalc_rate =3D cv75_pll_recalc_rate, +}; + +static int cv75_register_plls(struct device *dev, + struct clk_hw_onecell_data *data) +{ + struct clk_parent_data parent_data =3D { .fw_name =3D "osc" }; + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(cv75_plls); i++) { + const struct cv75_pll *desc =3D &cv75_plls[i]; + struct cv75_pll_hw *pll =3D desc->hw; + struct clk_init_data init =3D {}; + int ret; + + pll->ctrl =3D desc->ctrl; + pll->frac =3D desc->frac; + pll->ctrl2 =3D desc->ctrl2; + + init.name =3D desc->name; + init.ops =3D &cv75_pll_ops; + init.parent_data =3D &parent_data; + init.num_parents =3D 1; + init.flags =3D desc->flags; + pll->hw.init =3D &init; + + ret =3D devm_clk_hw_register(dev, &pll->hw); + if (ret) + return ret; + + if (desc->id >=3D 0) + data->hws[desc->id] =3D &pll->hw; + } + + return 0; +} + +static int cv75_register_fixed_factors(struct device *dev, + struct clk_hw_onecell_data *data) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(cv75_fixed_factors); i++) { + const struct cv75_fixed_factor *f =3D &cv75_fixed_factors[i]; + struct clk_hw *hw; + + hw =3D devm_clk_hw_register_fixed_factor_parent_hw(dev, f->name, + &cv75_ccu.core.hw, 0, + f->ratio.numerator, + f->ratio.denominator); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + data->hws[f->id] =3D hw; + } + + return 0; +} + +static struct clk_hw *cv75_register_composite(struct device *dev, + const struct cv75_composite *c) +{ + const struct clk_ops *mux_ops =3D NULL, *div_ops =3D NULL, *gate_ops =3D = NULL; + struct clk_hw *mux_hw =3D NULL, *div_hw =3D NULL, *gate_hw =3D NULL; + struct cv75_composite_hw *comp; + + comp =3D devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL); + if (!comp) + return ERR_PTR(-ENOMEM); + + if (c->mux_width) { + comp->mux.reg =3D cv75_ccu.base + c->mux_reg; + comp->mux.shift =3D c->mux_shift; + comp->mux.mask =3D GENMASK(c->mux_width - 1, 0); + comp->mux.lock =3D &cv75_ccu.lock; + mux_hw =3D &comp->mux.hw; + mux_ops =3D &clk_mux_ops; + } + + if (c->div_width) { + comp->div.reg =3D cv75_ccu.base + c->div_reg; + comp->div.shift =3D c->div_shift; + comp->div.width =3D c->div_width; + comp->div.flags =3D CLK_DIVIDER_ONE_BASED; + comp->div.lock =3D &cv75_ccu.lock; + div_hw =3D &comp->div.hw; + div_ops =3D &clk_divider_ops; + + comp->gate.reg =3D cv75_ccu.base + c->div_reg; + comp->gate.bit_idx =3D c->div_shift + c->div_width; + comp->gate.flags =3D CLK_GATE_SET_TO_DISABLE; + comp->gate.lock =3D &cv75_ccu.lock; + gate_hw =3D &comp->gate.hw; + gate_ops =3D &clk_gate_ops; + } + + return devm_clk_hw_register_composite_pdata(dev, c->name, c->parents, + c->num_parents, + mux_hw, mux_ops, + div_hw, div_ops, + gate_hw, gate_ops, c->flags); +} + +static int cv75_register_composites(struct device *dev, + struct clk_hw_onecell_data *data) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(cv75_composites); i++) { + const struct cv75_composite *c =3D &cv75_composites[i]; + struct clk_hw *hw; + + hw =3D cv75_register_composite(dev, c); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + data->hws[c->id] =3D hw; + } + + return 0; +} + +static int cv75_rct_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *data; + struct device *dev =3D &pdev->dev; + int ret; + + spin_lock_init(&cv75_ccu.lock); + + cv75_ccu.base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cv75_ccu.base)) + return PTR_ERR(cv75_ccu.base); + + data =3D devm_kzalloc(dev, struct_size(data, hws, CV75_NUM_CLKS), GFP_KER= NEL); + if (!data) + return -ENOMEM; + data->num =3D CV75_NUM_CLKS; + + ret =3D cv75_register_plls(dev, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register plls\n"); + + ret =3D cv75_register_fixed_factors(dev, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register fixed factors\n"); + + ret =3D cv75_register_composites(dev, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register composites\n"); + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); + if (ret) + return dev_err_probe(dev, ret, "failed to add clock provider\n"); + + return 0; +} + +static const struct of_device_id cv75_rct_match[] =3D { + { .compatible =3D "ambarella,cv75-rct" }, + { } +}; +MODULE_DEVICE_TABLE(of, cv75_rct_match); + +static struct platform_driver cv75_rct_driver =3D { + .probe =3D cv75_rct_probe, + .driver =3D { + .name =3D "ambarella-cv75-rct", + .of_match_table =3D cv75_rct_match, + }, +}; +module_platform_driver(cv75_rct_driver); + +MODULE_AUTHOR("Cao Rongrong "); +MODULE_DESCRIPTION("Ambarella CV75 RCT clock controller"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A52ED35E1AC; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; cv=none; b=fxdQaAvsivKjnaZh6KN550FKfWpbA7itRnK6tLh1g2eUsOPZNPekhIDlCdMmpXoTeBMPPvr+1iBKaQcC2aA09OF6xuOyjk6tM4K43NpWDR64J/0MY96kTPDtzRBZZtuc+bf4GBJO5D1qIoaM/mqqqvEGGaXSEW+qSkQlj8V/7Zs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; c=relaxed/simple; bh=jvbL/2RiMhg7JLG9DBXG5C6oQ3baY2PtbvCk8gshE7A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YdWKXZ8/XD9LciNSOCOBHh410NRQlVf55iNtdXw/FXhCPCAGOhRdN+F74Bs5HuTtq5L6AclnhbcnpQgu5eT1iebuh3WWlQ0cN52YBlCsVfVTDbazTbf6IFuRJe/beGVgNP+t9d6OcfjooslNbuOAd1+PwD05BokPvs1c7GUMEdk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=phF9+0Q2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="phF9+0Q2" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7F08AC2BCFD; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964612; bh=jvbL/2RiMhg7JLG9DBXG5C6oQ3baY2PtbvCk8gshE7A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=phF9+0Q2K4HXelrK4K49nidam5whFox+Kjs9MzfpeY95KmUrrLLBxaaMO9ZzIniUL JcGJNuMA8EMYzu5MrMsCT0ofTWgv+VGl6rjgbQA0NE/Gvv7oyoadDjZI8jPuY1/JTK Y2AnkBcRvzNMMy1ADCVjT6cq2E06bk5ennI/TBQU1TxFyqrJNWmKPhxoMTKR9YEe4M CM7uv/yh51bqdJq7YGbKD4B8+qsEdC6dIbkIO4GIu3b/GuSLMgTe9fbwG5uiCkSByD 2eh6ChfJjprXR7Vs4WVbAgFgb4p85176q43ra0Rf3Mj3qYiTwwPF0KY2XoufJ9mgnt Ty7lEyWa2NKTw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68354C982F2; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:27 +0800 Subject: [PATCH v8 08/18] gpiolib: regmap: add write_data_after_dir quirk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-8-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=3092; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=fpAj3vMXjZmURWyfts5CtyfyhTDoS5mn512oJA6h2aY=; b=e+MsuppDlgpjoNWogF4SShQN6eYtdesHSzDj+4r/pX+nVj5fmsfe+JIJpzHDyZ0LZ8NJ/XwPo I2z4VDEPGc2DvMHBbmioeZ8u/yVtTANgbGaSMPr/HFraoL+ryizimzx X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Some controllers ignore data-register writes while a line is still an input. Optionally write the output value again after switching the direction, matching the existing PL061 behaviour. Signed-off-by: Long Zhao --- drivers/gpio/gpio-regmap.c | 19 +++++++++++++++++-- include/linux/gpio/regmap.h | 8 ++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index 51b4d69b8740..fbd4c753525a 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -31,6 +31,7 @@ struct gpio_regmap { unsigned int reg_clr_base; unsigned int reg_dir_in_base; unsigned int reg_dir_out_base; + bool write_data_after_dir; unsigned long *fixed_direction_mask; unsigned long *fixed_direction_output; =20 @@ -271,9 +272,21 @@ static int gpio_regmap_direction_output(struct gpio_ch= ip *chip, return ret; } =20 - gpio_regmap_set(chip, offset, value); + if (!gpio->write_data_after_dir) + gpio_regmap_set(chip, offset, value); =20 - return gpio_regmap_set_direction(chip, offset, true); + ret =3D gpio_regmap_set_direction(chip, offset, true); + if (ret) + return ret; + + /* + * Some controllers ignore data-register writes while the line is + * still an input. Write the output value after switching direction. + */ + if (gpio->write_data_after_dir) + gpio_regmap_set(chip, offset, value); + + return 0; } =20 void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio) @@ -376,6 +389,8 @@ struct gpio_regmap *gpio_regmap_register(const struct g= pio_regmap_config *config config->fixed_direction_output, chip->ngpio); } =20 + gpio->write_data_after_dir =3D config->write_data_after_dir; + /* if not set, assume there is only one register */ gpio->ngpio_per_reg =3D config->ngpio_per_reg; if (!gpio->ngpio_per_reg) diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h index 06255756710d..d7ffc12b00a2 100644 --- a/include/linux/gpio/regmap.h +++ b/include/linux/gpio/regmap.h @@ -48,6 +48,13 @@ struct regmap; * (Optional) Bitmap representing the fixed direction of * the GPIO lines. Useful when there are GPIO lines with a * fixed direction mixed together in the same register. + * @write_data_after_dir: + * (Optional) Write the output value again after + * switching a line to output in ->direction_output(). + * Needed for hardware which ignores data register + * writes while the line is configured as an input. + * This is a legacy quirk (e.g. ARM PL061); new hardware + * must not use it. Direction changes will glitch. * @drvdata: (Optional) Pointer to driver specific data which is * not used by gpio-remap but is provided "as is" to the * driver callback(s). @@ -94,6 +101,7 @@ struct gpio_regmap_config { unsigned int reg_dir_out_base; int reg_stride; int ngpio_per_reg; + bool write_data_after_dir; struct irq_domain *irq_domain; unsigned long *fixed_direction_mask; unsigned long *fixed_direction_output; --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C88DC360ED6; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; cv=none; b=eTXsG2+SWj3yJVoZXmCelp1r5bbDgERNNlXwneTfQXDmqg8eu4oFOl6KopdCNW+zf3hmI4FH4fShLGzdqUh4BiuMa571vUCJWfMEQFvc4AytBSX90NrH3io8wNW4+obED5wQ2zbpOsmup4eY0lbOvQmxROUfgvuwEljufRxdJ3k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964612; c=relaxed/simple; bh=gVLLIDHjbMni5VoIW3Uu4KnGYFcqhuw0LoFOcrTkdTk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XeoQ5OMsZpg4J8tblLBTEFNdfyof1I593HY5/9yZ6JNS1I/OA//8eNZK0nG9HquolOOfZw6WIQd+9S135PLjr2vRkR6PbCFKGVttWe2/nV7g6NDXOcEjpWTQdf4BI14JlUa8x18tbvDHPLvlu/T5bDfr/y6vGRFp6kYFnXkdKZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ODAkMBuq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ODAkMBuq" Received: by smtp.kernel.org (Postfix) with ESMTPS id 96AF6C2BCFF; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964612; bh=gVLLIDHjbMni5VoIW3Uu4KnGYFcqhuw0LoFOcrTkdTk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ODAkMBuq2GfUqTIyZBWh0GWwOaZOrNxpxlReyt6RQyuiBRamlFvboU4jccE3gdMmp BVpIzf0MhmiOlQ5naICb1EJ9bC124SKk1WJhc9EKjLV5zETM1EFb2G/1j87cSBwabl b7QxryX9I/5pD7VMZmEGl+2UlFUt4Ch/RzosZaA8b69+6zXTmi8D+Ymxcmx41HJMKw YstOGx3NtXmKBpdiycfX01NpdiEVqUG8q8OAlTQ/drYntByeCSB7XvMnBD9qgBo2ca mYjoQ1G4g8lgdsnu/VQVkHHwqdaRx53f2wykqY00FQBGb2+t7BG3JsG72NsU0ITQk1 cDvHHdy5Zc1hg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FF10C982F4; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:28 +0800 Subject: [PATCH v8 09/18] gpiolib: regmap: add gpio_regmap_get_chip() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-9-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=1405; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=cRhJj4Cmnrf+otvC27C8iAwNmJZQbquKFDy2qboyeNQ=; b=xlZYvrKjnFVcFpLds0vUYl/6sFDK38Bbl7y59QeayQws2YyeCYevlQXKOrV6SeYTdNPcO+CRG ztc9eLhtP9cDwNJ4nu/511CwNb1JR0ZD1va34zcQZLolhyIHV2lMqhM X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Let drivers that implement a custom irqchip retrieve the gpio_chip after registration. Signed-off-by: Long Zhao --- drivers/gpio/gpio-regmap.c | 6 ++++++ include/linux/gpio/regmap.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index fbd4c753525a..21e0993b89e2 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -295,6 +295,12 @@ void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio) } EXPORT_SYMBOL_GPL(gpio_regmap_get_drvdata); =20 +struct gpio_chip *gpio_regmap_get_chip(struct gpio_regmap *gpio) +{ + return &gpio->gpio_chip; +} +EXPORT_SYMBOL_GPL(gpio_regmap_get_chip); + /** * gpio_regmap_register() - Register a generic regmap GPIO controller * @config: configuration for gpio_regmap diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h index d7ffc12b00a2..6bc00b9775a5 100644 --- a/include/linux/gpio/regmap.h +++ b/include/linux/gpio/regmap.h @@ -128,5 +128,6 @@ void gpio_regmap_unregister(struct gpio_regmap *gpio); struct gpio_regmap *devm_gpio_regmap_register(struct device *dev, const struct gpio_regmap_config *config); void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio); +struct gpio_chip *gpio_regmap_get_chip(struct gpio_regmap *gpio); =20 #endif /* _LINUX_GPIO_REGMAP_H */ --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47A92366042; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964613; cv=none; b=fZoH35XnjeZS/73oR6yAXJgb5gXL/gEKqOA7G2ziQpxqNhAAuQuSFWri/R7lUUXBfARaCh1VmoN+ygCeaFsEpopUunY4EhUs8v7rnXmk97zjnGFNk6RZN8Kkw+2vDUOBiSz+Y01fyIrhbJQfAPeM+gfAO6uB3xBby5t+Feky4jg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964613; c=relaxed/simple; bh=IiAg44XTMe/C82ryz2ODqQii+pc3aBWmgtcjsuk5Nuk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pnOwhleeDUM7a05q1QMsldHH82x/6JtdhBjlhxhU4lM6dLhQj7G++9EiM+CAnhuXFgZdRI3JGZ1iWjfNFR7vxAhrrCFtyRzRg+Dd90mKGETWqA0K8DDN6AkXkEX3Qe0U+QDbpWktypFcEEznMYwsiGwr8Eor7HTiXTzs1afN1fw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ijrKui3Q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ijrKui3Q" Received: by smtp.kernel.org (Postfix) with ESMTPS id C02E8C2BCB3; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964612; bh=IiAg44XTMe/C82ryz2ODqQii+pc3aBWmgtcjsuk5Nuk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ijrKui3QDSfe4hlv1Pqwaa+1r55dluqykAnosyMyPt7myzeCL9Mq2IUV2oTiGgB98 XfYnufY+PkRhrxkU9KUvyj2EvpBJZ7QdthglIVcC6EiTjqNHF57VKouH39lRZKFhTq GfOIWLdG8G75C4TX95+bFAAQoIeKYEBe9QyPE5NPEly/SRvNvSs/YvmbHVGPhlbR6b 2EZQMztaaqQdSN1/regYTH2fIHbIP+vSCcb/v/hrkCoLGoBEdCzUaQT029ivXsGroT UAP9IkIOf+L/ztqstpDxGHWul1/4Ks155K4Hc7rPV1le3ZQ0NIir91kdlTRrJnNixL 4/uAQrgRzo9dQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6CC6C982F1; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:29 +0800 Subject: [PATCH v8 10/18] gpio: pl061: convert register access to regmap Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-10-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=11255; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=bNMGD8MihqEG4c46cw/A6tznIzR/bR90tX0r5+quMeU=; b=CA40djdf4mLPoJECiUp1UGpAicmpzmAXOncX6ZTWV28zd7TZ+RvUi4WcDgEu34RgjQvtee3mV Kppqg1dbZD7AXWvos3RwjvUaX/IBiGvfgT1tNI0mlNmycss7mXUNcTT X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Replace readb()/writeb() with a MMIO regmap while keeping the existing gpio_chip and girq irqchip. Use a raw spinlock so irq_ack() can run under the irq descriptor lock. Signed-off-by: Long Zhao --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-pl061.c | 134 ++++++++++++++++++++++++++++++------------= ---- 2 files changed, 89 insertions(+), 46 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f03c05288376..2a1487bd1a94 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -583,6 +583,7 @@ config GPIO_PL061 depends on ARM_AMBA || COMPILE_TEST select IRQ_DOMAIN select GPIOLIB_IRQCHIP + select REGMAP_MMIO help Say yes here to support the PrimeCell PL061 GPIO device. =20 diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 919cf86fd590..66aea0856bc4 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -19,9 +19,11 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -36,6 +38,7 @@ #define GPIOIC 0x41C =20 #define PL061_GPIO_NR 8 +#define PL061_DATA_OFFSET 2 =20 struct pl061_context_save_regs { u8 gpio_data; @@ -49,18 +52,49 @@ struct pl061_context_save_regs { struct pl061 { raw_spinlock_t lock; =20 - void __iomem *base; + struct regmap *regmap; struct gpio_chip gc; int parent_irq; =20 struct pl061_context_save_regs csave_regs; }; =20 +static bool pl061_is_data_reg(unsigned int reg) +{ + return is_power_of_2(reg) && + reg >=3D BIT(PL061_DATA_OFFSET) && + reg <=3D BIT(PL061_DATA_OFFSET + PL061_GPIO_NR - 1); +} + +static bool pl061_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case GPIOMIS: + case GPIOIC: + return true; + default: + return pl061_is_data_reg(reg); + } +} + +static const struct regmap_config pl061_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .reg_stride =3D 4, + .max_register =3D GPIOIC, + .volatile_reg =3D pl061_volatile_reg, + .fast_io =3D true, + .use_raw_spinlock =3D true, +}; + static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) { struct pl061 *pl061 =3D gpiochip_get_data(gc); + unsigned int gpiodir =3D 0; =20 - if (readb(pl061->base + GPIODIR) & BIT(offset)) + regmap_read(pl061->regmap, GPIODIR, &gpiodir); + + if (gpiodir & BIT(offset)) return GPIO_LINE_DIRECTION_OUT; =20 return GPIO_LINE_DIRECTION_IN; @@ -70,12 +104,9 @@ static int pl061_direction_input(struct gpio_chip *gc, = unsigned offset) { struct pl061 *pl061 =3D gpiochip_get_data(gc); unsigned long flags; - unsigned char gpiodir; =20 raw_spin_lock_irqsave(&pl061->lock, flags); - gpiodir =3D readb(pl061->base + GPIODIR); - gpiodir &=3D ~(BIT(offset)); - writeb(gpiodir, pl061->base + GPIODIR); + regmap_update_bits(pl061->regmap, GPIODIR, BIT(offset), 0); raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 return 0; @@ -86,19 +117,19 @@ static int pl061_direction_output(struct gpio_chip *gc= , unsigned offset, { struct pl061 *pl061 =3D gpiochip_get_data(gc); unsigned long flags; - unsigned char gpiodir; + unsigned int mask =3D BIT(offset); =20 raw_spin_lock_irqsave(&pl061->lock, flags); - writeb(!!value << offset, pl061->base + (BIT(offset + 2))); - gpiodir =3D readb(pl061->base + GPIODIR); - gpiodir |=3D BIT(offset); - writeb(gpiodir, pl061->base + GPIODIR); + regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), + !!value << offset); + regmap_update_bits(pl061->regmap, GPIODIR, mask, mask); =20 /* * gpio value is set again, because pl061 doesn't allow to set value of * a gpio pin before configuring it in OUT mode. */ - writeb(!!value << offset, pl061->base + (BIT(offset + 2))); + regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), + !!value << offset); raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 return 0; @@ -107,15 +138,19 @@ static int pl061_direction_output(struct gpio_chip *g= c, unsigned offset, static int pl061_get_value(struct gpio_chip *gc, unsigned offset) { struct pl061 *pl061 =3D gpiochip_get_data(gc); + unsigned int val =3D 0; + + regmap_read(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), &val); =20 - return !!readb(pl061->base + (BIT(offset + 2))); + return !!val; } =20 static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int = value) { struct pl061 *pl061 =3D gpiochip_get_data(gc); =20 - writeb(!!value << offset, pl061->base + (BIT(offset + 2))); + regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), + !!value << offset); =20 return 0; } @@ -126,8 +161,8 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) struct pl061 *pl061 =3D gpiochip_get_data(gc); int offset =3D irqd_to_hwirq(d); unsigned long flags; - u8 gpiois, gpioibe, gpioiev; - u8 bit =3D BIT(offset); + unsigned int gpiois =3D 0, gpioibe =3D 0, gpioiev =3D 0; + unsigned int bit =3D BIT(offset); =20 if (offset < 0 || offset >=3D PL061_GPIO_NR) return -EINVAL; @@ -145,9 +180,9 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) =20 raw_spin_lock_irqsave(&pl061->lock, flags); =20 - gpioiev =3D readb(pl061->base + GPIOIEV); - gpiois =3D readb(pl061->base + GPIOIS); - gpioibe =3D readb(pl061->base + GPIOIBE); + regmap_read(pl061->regmap, GPIOIEV, &gpioiev); + regmap_read(pl061->regmap, GPIOIS, &gpiois); + regmap_read(pl061->regmap, GPIOIBE, &gpioibe); =20 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { bool polarity =3D trigger & IRQ_TYPE_LEVEL_HIGH; @@ -199,9 +234,9 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) offset); } =20 - writeb(gpiois, pl061->base + GPIOIS); - writeb(gpioibe, pl061->base + GPIOIBE); - writeb(gpioiev, pl061->base + GPIOIEV); + regmap_write(pl061->regmap, GPIOIS, gpiois); + regmap_write(pl061->regmap, GPIOIBE, gpioibe); + regmap_write(pl061->regmap, GPIOIEV, gpioiev); =20 raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 @@ -211,6 +246,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) static void pl061_irq_handler(struct irq_desc *desc) { unsigned long pending; + unsigned int mis =3D 0; int offset; struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); struct pl061 *pl061 =3D gpiochip_get_data(gc); @@ -218,8 +254,9 @@ static void pl061_irq_handler(struct irq_desc *desc) =20 chained_irq_enter(irqchip, desc); =20 - pending =3D readb(pl061->base + GPIOMIS); - if (pending) { + regmap_read(pl061->regmap, GPIOMIS, &mis); + if (mis) { + pending =3D mis; for_each_set_bit(offset, &pending, PL061_GPIO_NR) generic_handle_domain_irq(gc->irq.domain, offset); @@ -233,11 +270,9 @@ static void pl061_irq_mask(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct pl061 *pl061 =3D gpiochip_get_data(gc); u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); - u8 gpioie; =20 raw_spin_lock(&pl061->lock); - gpioie =3D readb(pl061->base + GPIOIE) & ~mask; - writeb(gpioie, pl061->base + GPIOIE); + regmap_update_bits(pl061->regmap, GPIOIE, mask, 0); raw_spin_unlock(&pl061->lock); =20 gpiochip_disable_irq(gc, d->hwirq); @@ -248,13 +283,11 @@ static void pl061_irq_unmask(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct pl061 *pl061 =3D gpiochip_get_data(gc); u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); - u8 gpioie; =20 gpiochip_enable_irq(gc, d->hwirq); =20 raw_spin_lock(&pl061->lock); - gpioie =3D readb(pl061->base + GPIOIE) | mask; - writeb(gpioie, pl061->base + GPIOIE); + regmap_update_bits(pl061->regmap, GPIOIE, mask, mask); raw_spin_unlock(&pl061->lock); } =20 @@ -272,9 +305,7 @@ static void pl061_irq_ack(struct irq_data *d) struct pl061 *pl061 =3D gpiochip_get_data(gc); u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); =20 - raw_spin_lock(&pl061->lock); - writeb(mask, pl061->base + GPIOIC); - raw_spin_unlock(&pl061->lock); + regmap_write(pl061->regmap, GPIOIC, mask); } =20 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) @@ -308,15 +339,20 @@ static int pl061_probe(struct amba_device *adev, cons= t struct amba_id *id) struct device *dev =3D &adev->dev; struct pl061 *pl061; struct gpio_irq_chip *girq; + void __iomem *base; int ret, irq; =20 pl061 =3D devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); if (pl061 =3D=3D NULL) return -ENOMEM; =20 - pl061->base =3D devm_ioremap_resource(dev, &adev->res); - if (IS_ERR(pl061->base)) - return PTR_ERR(pl061->base); + base =3D devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pl061->regmap =3D devm_regmap_init_mmio(dev, base, &pl061_regmap_config); + if (IS_ERR(pl061->regmap)) + return PTR_ERR(pl061->regmap); =20 raw_spin_lock_init(&pl061->lock); pl061->gc.request =3D gpiochip_generic_request; @@ -335,7 +371,7 @@ static int pl061_probe(struct amba_device *adev, const = struct amba_id *id) /* * irq_chip support */ - writeb(0, pl061->base + GPIOIE); /* disable irqs */ + regmap_write(pl061->regmap, GPIOIE, 0); /* disable irqs */ irq =3D adev->irq[0]; if (!irq) dev_warn(&adev->dev, "IRQ support disabled\n"); @@ -366,14 +402,20 @@ static int pl061_probe(struct amba_device *adev, cons= t struct amba_id *id) static int pl061_suspend(struct device *dev) { struct pl061 *pl061 =3D dev_get_drvdata(dev); + unsigned int val =3D 0; int offset; =20 pl061->csave_regs.gpio_data =3D 0; - pl061->csave_regs.gpio_dir =3D readb(pl061->base + GPIODIR); - pl061->csave_regs.gpio_is =3D readb(pl061->base + GPIOIS); - pl061->csave_regs.gpio_ibe =3D readb(pl061->base + GPIOIBE); - pl061->csave_regs.gpio_iev =3D readb(pl061->base + GPIOIEV); - pl061->csave_regs.gpio_ie =3D readb(pl061->base + GPIOIE); + regmap_read(pl061->regmap, GPIODIR, &val); + pl061->csave_regs.gpio_dir =3D val; + regmap_read(pl061->regmap, GPIOIS, &val); + pl061->csave_regs.gpio_is =3D val; + regmap_read(pl061->regmap, GPIOIBE, &val); + pl061->csave_regs.gpio_ibe =3D val; + regmap_read(pl061->regmap, GPIOIEV, &val); + pl061->csave_regs.gpio_iev =3D val; + regmap_read(pl061->regmap, GPIOIE, &val); + pl061->csave_regs.gpio_ie =3D val; =20 for (offset =3D 0; offset < PL061_GPIO_NR; offset++) { if (pl061->csave_regs.gpio_dir & (BIT(offset))) @@ -398,10 +440,10 @@ static int pl061_resume(struct device *dev) pl061_direction_input(&pl061->gc, offset); } =20 - writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); - writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); - writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); - writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); + regmap_write(pl061->regmap, GPIOIS, pl061->csave_regs.gpio_is); + regmap_write(pl061->regmap, GPIOIBE, pl061->csave_regs.gpio_ibe); + regmap_write(pl061->regmap, GPIOIEV, pl061->csave_regs.gpio_iev); + regmap_write(pl061->regmap, GPIOIE, pl061->csave_regs.gpio_ie); =20 return 0; } --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 693F0366541; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964613; cv=none; b=N02JJkEhkDwmn7zdRpQM29csczZW233yjvxR5pltLQ+jZM753drRAXGyqxqwSJdPLJsO6emz9rSIhyhqR4L09Hv3i+LrBOl2WQtV8eN779RYd61ngFqGTJkPmAkErjkDJcIM7hCE9BUvtdkfupBlXE78tLJZT3A1vOpoxt98j5U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964613; c=relaxed/simple; bh=DHOOUWew6XqstWVudeHYH34B8AdGFHQzXLMLdRJhDzs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GPJf5kPjy/3SxxBMvwIxgS5kilBNac45ARHgFfXntdzMzsEYR6/RqZ1Tp+YHnsd27NzTCHxabrxVCyceB9K4ufHKynTfMLRO4eEPKYT4/0CoQmJj16kasnm/9vMI/Nnu+2NVVzvbUsxr/YF9weqBODZ4Y7eYvHQOFm2uCtnHAFQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rKiTDvXF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rKiTDvXF" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1488DC4AF15; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964613; bh=DHOOUWew6XqstWVudeHYH34B8AdGFHQzXLMLdRJhDzs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rKiTDvXFRXLfuvVDrn3FnKb+hYqV+OD/fAUANM6wBkL2z83o0nOg49Em5bZyuBti0 tjJ3zwEQEGAl7undb2nUmuZ6MNhcONTbkhCpk/f/hW6pf5cRdDV1pXoC+jjS97HZxJ vhlY+VhkVue/5cDNMkZW89kRuYrlnvar2AOpVyV+tKKs9Tab70SNUhabjq/AnqE1Fe VEWtethkt+8aom+QmVJ4pBc82Vdr1n9HoYtszz1iGsnTS2Nv0Ovxcuxwdu1FfpcEj9 H6Bp2EJWfcjjwUGCWaUdtiTt95XzXnRRkpefM7fkNLYOM/i9qldyK3klBM32hJ6b5a fToxGLMlVEkqQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE991C982DA; Mon, 21 Sep 2026 04:23:32 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:30 +0800 Subject: [PATCH v8 11/18] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-11-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=1319; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=nz51yActj1YXpv3NW2G+jZPYSgBHFOPI8W4g4YsvTL4=; b=uKCp/46nsRO5BF/rtCpHTEFHOuSWs4cyunvPht6xRRVU1PnHLtQLijpPhG92Ufs7PJYr/fp25 utNTH4rmibLDMpgHGX6Xy/HeqaUQTAPelYEYno50LWM3YnnwhTz8fx5 X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Use the standard IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH helpers instead of open-coded edge and level comparisons. Signed-off-by: Long Zhao Reviewed-by: Linus Walleij --- drivers/gpio/gpio-pl061.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 66aea0856bc4..2913daf46aff 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -167,9 +167,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) if (offset < 0 || offset >=3D PL061_GPIO_NR) return -EINVAL; =20 - if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && - (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) - { + if ((trigger & IRQ_TYPE_LEVEL_MASK) && (trigger & IRQ_TYPE_EDGE_BOTH)) { dev_err(gc->parent, "trying to configure line %d for both level and edge " "detection, choose one!\n", @@ -184,7 +182,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) regmap_read(pl061->regmap, GPIOIS, &gpiois); regmap_read(pl061->regmap, GPIOIBE, &gpioibe); =20 - if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + if (trigger & IRQ_TYPE_LEVEL_MASK) { bool polarity =3D trigger & IRQ_TYPE_LEVEL_HIGH; =20 /* Disable edge detection */ --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0F32368D40; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964613; cv=none; b=Xh+FYWfkcQjy0WKgNGvYVbdFpsJCt9q0nOfxpn1jIWzUxLNOrzzVHZzBnaZZblLwZb9SDTUmMdUw1FHW9SINYhxPXFe5NeTzhNEXYu6MOtZ+ByJ07DyrL8Aqp7YqBzLLRSryHULjDU28+uGUBW0OPFveDAwVZxM7yxJnn9X5d4o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964613; c=relaxed/simple; bh=wZJacq8lp2xyUvHx/P8R2wnBwb1XTZEAMLxLNmfihS8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s3VjI25MiP7P+CbbdnRGI8lgAeCSl2d2i7HGkI3KP0rjGBWZRpB3P0WmQq8QImVssRpD9pJGZeQhzw+epb5eb3K9x3Sjne8BW9CcN0sb77fZitPxWOv7IYY+H0Wu7uo5vWqjPe8pomzb7fykAZ4y1il8+JP/wpLXM5ZAZecOpWM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jyvixlXs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jyvixlXs" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5FD7DC4AF18; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964613; bh=wZJacq8lp2xyUvHx/P8R2wnBwb1XTZEAMLxLNmfihS8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=jyvixlXsv42CK6y6Vs7GUIBsNb/Oj7ZNwIaHWyxhFoMPJ2N6nU3KnnI4L4dS16Gqb 1mRweQrpsGkQK9ghR/R785FFAhEFbbvj54oQj3Dqvp91VRZ0yyB4uZDqLJ2xW7eVN7 irtkN2Ra8ZALN17584kl+5RYf2HF7YuY+AwMSqDG7Uf8JuQSQghQL9BUZ7aUVZH7xw 22683jDVVnkbtYJYSULnM2Tzsd93KoTuL3ufJblpfyFWS30BE4YwVV0EiIQPguigdB 4vcJ3Fm6/xV5oMLCn26IQ47KEhj49CQTt/VjVac6PVK98Y0FY69MRud/t2czhhKWbj +EWpCoFXOTLBQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C32EC982F4; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:31 +0800 Subject: [PATCH v8 12/18] gpio: pl061: use cleanup helpers for locks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-12-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=3385; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=ii3oagWoRbkwRTyfP9uldtzy1qla8tAAWfRUevUse2E=; b=gdrZwOZPCUMN1JNeNnP15TEcY5an0TzacNkglL5E7oj8FKI1dtcC9UZp9WqFecEqc5CAm688Q Q0uaB6zaTorDlEmU0Vf6+S4N/q7rtnbd8JEtV0Zq+kzwyKvga4GNKl3 X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Convert raw_spinlock critical sections to guard() from cleanup.h. Signed-off-by: Long Zhao Reviewed-by: Linus Walleij --- drivers/gpio/gpio-pl061.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 2913daf46aff..c821a5117eed 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -10,6 +10,7 @@ */ #include #include +#include #include #include #include @@ -103,11 +104,9 @@ static int pl061_get_direction(struct gpio_chip *gc, u= nsigned offset) static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) { struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned long flags; =20 - raw_spin_lock_irqsave(&pl061->lock, flags); + guard(raw_spinlock_irqsave)(&pl061->lock); regmap_update_bits(pl061->regmap, GPIODIR, BIT(offset), 0); - raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 return 0; } @@ -116,10 +115,9 @@ static int pl061_direction_output(struct gpio_chip *gc= , unsigned offset, int value) { struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned long flags; unsigned int mask =3D BIT(offset); =20 - raw_spin_lock_irqsave(&pl061->lock, flags); + guard(raw_spinlock_irqsave)(&pl061->lock); regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), !!value << offset); regmap_update_bits(pl061->regmap, GPIODIR, mask, mask); @@ -130,7 +128,6 @@ static int pl061_direction_output(struct gpio_chip *gc,= unsigned offset, */ regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), !!value << offset); - raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 return 0; } @@ -160,7 +157,6 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct pl061 *pl061 =3D gpiochip_get_data(gc); int offset =3D irqd_to_hwirq(d); - unsigned long flags; unsigned int gpiois =3D 0, gpioibe =3D 0, gpioiev =3D 0; unsigned int bit =3D BIT(offset); =20 @@ -176,7 +172,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) } =20 =20 - raw_spin_lock_irqsave(&pl061->lock, flags); + guard(raw_spinlock_irqsave)(&pl061->lock); =20 regmap_read(pl061->regmap, GPIOIEV, &gpioiev); regmap_read(pl061->regmap, GPIOIS, &gpiois); @@ -236,7 +232,6 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) regmap_write(pl061->regmap, GPIOIBE, gpioibe); regmap_write(pl061->regmap, GPIOIEV, gpioiev); =20 - raw_spin_unlock_irqrestore(&pl061->lock, flags); =20 return 0; } @@ -269,9 +264,8 @@ static void pl061_irq_mask(struct irq_data *d) struct pl061 *pl061 =3D gpiochip_get_data(gc); u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); =20 - raw_spin_lock(&pl061->lock); + guard(raw_spinlock)(&pl061->lock); regmap_update_bits(pl061->regmap, GPIOIE, mask, 0); - raw_spin_unlock(&pl061->lock); =20 gpiochip_disable_irq(gc, d->hwirq); } @@ -284,9 +278,8 @@ static void pl061_irq_unmask(struct irq_data *d) =20 gpiochip_enable_irq(gc, d->hwirq); =20 - raw_spin_lock(&pl061->lock); + guard(raw_spinlock)(&pl061->lock); regmap_update_bits(pl061->regmap, GPIOIE, mask, mask); - raw_spin_unlock(&pl061->lock); } =20 /** --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C75F436921B; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964613; cv=none; b=HWbaUHzDlEOTbh2tgLuqJkwTZYotnBHPkyU5yTyMpKJWIa7CuuQkJ3wlvSHicV72uSrQ9YSmhUM4LEnW34PbTMCWIB45Pkq20SocWFzE7G6AdEhrpUToXslRX2fln4G7MKaHY0jlrX/Ik4W9jkAjgM7rEDzQrB3lPSGRv0iqh2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964613; c=relaxed/simple; bh=vAVNxCy2lujT/Mz9zizBwtDlkr+zp6HCEu8hVGrQTJM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q4Ruc7IEvKhh5XXcrhw8yM5A0TwlMAvsM98lUB24tkxqVJUrJnZvVlB8z855FWv5+IZlWmteMvmd3GVjvmnwS/yUe87IubQIAxsamHGZE7I93BJH81chKsdRMpTT6xThXFjBW7Q1cxpAh8kOZ2JLABw7mQ4KSlML+zbKo39m3oI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gAQcPqs2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gAQcPqs2" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9A12DC2BCFA; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964613; bh=vAVNxCy2lujT/Mz9zizBwtDlkr+zp6HCEu8hVGrQTJM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gAQcPqs2jd2hBqW+8kxBbgv9/2YtN+SID90EJ0bxMYcz5s9pcRFwtkWyMU5XHx5f/ CofE1Iib3D7+cI5pYjDTld74dO8719NHECkRbDWhZOiq3AAFKVK1f/rAVHr0CvJBOz Zfi612ptTosdiv4t+FcmV7PlVGwTvFRs+xzT2Sh3JM8ygy++G0/ccsE8u2LKA8fdkC G4rk+Wpjp5+Io0Qv6xUXhPtgIK8qTxqO3n1mMDszGnwwHruC7W3yAh/sUh6ejPTSI8 FicwtwLj7JWCGy+VE47j9i/5owpsYosy+AwttIvtx11QXl4UddCqA5/x6AsmLcyYvN uBNVJ+J3pZidw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83D09C982F5; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:32 +0800 Subject: [PATCH v8 13/18] gpio: pl061: switch data path to gpio-regmap Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-13-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=20663; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=MP71CXfoORD6gdy8uA/zoAtI0dkVFGoChcqw6gDcx6M=; b=oXwzDxlLPCqgr9k2DI3ss8IyOx5jGhgm0EUTWTmAV7pgsHnQW3f3PYlWyXPj3aJTa4g2sugJ1 +xHmTokgNG9CVuIIizVGYbOjDxwyf7LSh3/3u2wh8jBzQtaCdthX0hN X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Keep a custom irqchip and irq domain. The gpio_chip is owned by gpio-regmap, so gpio_regmap_get_chip() is used to wire the domain. Check the chained-handler regmap_read() return and always run chained_irq_exit(). irq_type keeps the MMIO write style and uses cleanup helpers from the previous patch. irq_set_parent() nests the GPIO irq_desc under the AMBA parent for irq_set_wake() and lockdep; checked with PROVE_LOCKING on CV75. Signed-off-by: Long Zhao Reviewed-by: Linus Walleij --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-pl061.c | 485 +++++++++++++++++++++++++++---------------= ---- 2 files changed, 287 insertions(+), 199 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 2a1487bd1a94..55a129836158 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -583,6 +583,7 @@ config GPIO_PL061 depends on ARM_AMBA || COMPILE_TEST select IRQ_DOMAIN select GPIOLIB_IRQCHIP + select GPIO_REGMAP select REGMAP_MMIO help Say yes here to support the PrimeCell PL061 GPIO device. diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index c821a5117eed..604129a68948 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -12,155 +12,102 @@ #include #include #include -#include +#include #include -#include +#include #include #include #include #include #include +#include #include #include -#include #include #include #include -#include #include =20 -#define GPIODIR 0x400 -#define GPIOIS 0x404 -#define GPIOIBE 0x408 -#define GPIOIEV 0x40C -#define GPIOIE 0x410 -#define GPIORIS 0x414 -#define GPIOMIS 0x418 -#define GPIOIC 0x41C - #define PL061_GPIO_NR 8 #define PL061_DATA_OFFSET 2 =20 -struct pl061_context_save_regs { - u8 gpio_data; - u8 gpio_dir; - u8 gpio_is; - u8 gpio_ibe; - u8 gpio_iev; - u8 gpio_ie; +#define PL061_DIR 0x400 +#define PL061_IS 0x404 +#define PL061_IBE 0x408 +#define PL061_IEV 0x40c +#define PL061_IE 0x410 +#define PL061_MIS 0x418 +#define PL061_IC 0x41c + +struct pl061_regs { + unsigned int dat; + unsigned int dir; + unsigned int is; + unsigned int ibe; + unsigned int iev; + unsigned int ie; + unsigned int mis; + unsigned int ic; + unsigned int mask; + unsigned int enable; +}; + +struct pl061_drvdata { + const struct regmap_config *regmap_config; + const struct pl061_regs *regs; + unsigned int ngpio; + bool write_data_after_dir; + bool clear_irq_on_type; + bool pm; + int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base, + unsigned int offset, unsigned int *reg, + unsigned int *mask); }; =20 struct pl061 { raw_spinlock_t lock; =20 struct regmap *regmap; - struct gpio_chip gc; + const struct pl061_drvdata *data; + struct irq_domain *irq_domain; int parent_irq; =20 - struct pl061_context_save_regs csave_regs; + u32 saved_dat; }; =20 -static bool pl061_is_data_reg(unsigned int reg) -{ - return is_power_of_2(reg) && - reg >=3D BIT(PL061_DATA_OFFSET) && - reg <=3D BIT(PL061_DATA_OFFSET + PL061_GPIO_NR - 1); -} - -static bool pl061_volatile_reg(struct device *dev, unsigned int reg) -{ - switch (reg) { - case GPIOMIS: - case GPIOIC: - return true; - default: - return pl061_is_data_reg(reg); - } -} - -static const struct regmap_config pl061_regmap_config =3D { - .reg_bits =3D 16, - .val_bits =3D 8, - .reg_stride =3D 4, - .max_register =3D GPIOIC, - .volatile_reg =3D pl061_volatile_reg, - .fast_io =3D true, - .use_raw_spinlock =3D true, -}; - -static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) -{ - struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned int gpiodir =3D 0; - - regmap_read(pl061->regmap, GPIODIR, &gpiodir); - - if (gpiodir & BIT(offset)) - return GPIO_LINE_DIRECTION_OUT; - - return GPIO_LINE_DIRECTION_IN; -} - -static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) -{ - struct pl061 *pl061 =3D gpiochip_get_data(gc); - - guard(raw_spinlock_irqsave)(&pl061->lock); - regmap_update_bits(pl061->regmap, GPIODIR, BIT(offset), 0); - - return 0; -} - -static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, - int value) +static struct pl061 *pl061_from_gpio_chip(struct gpio_chip *gc) { - struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned int mask =3D BIT(offset); - - guard(raw_spinlock_irqsave)(&pl061->lock); - regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), - !!value << offset); - regmap_update_bits(pl061->regmap, GPIODIR, mask, mask); - - /* - * gpio value is set again, because pl061 doesn't allow to set value of - * a gpio pin before configuring it in OUT mode. - */ - regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), - !!value << offset); - - return 0; + return gpio_regmap_get_drvdata(gpiochip_get_data(gc)); } =20 -static int pl061_get_value(struct gpio_chip *gc, unsigned offset) +static unsigned int pl061_line_mask(struct pl061 *pl061, irq_hw_number_t h= wirq) { - struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned int val =3D 0; - - regmap_read(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), &val); - - return !!val; + return BIT(hwirq % pl061->data->ngpio); } =20 -static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int = value) +static int pl061_arm_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int= base, + unsigned int offset, unsigned int *reg, + unsigned int *mask) { - struct pl061 *pl061 =3D gpiochip_get_data(gc); - - regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), - !!value << offset); + if (base =3D=3D 0) + *reg =3D BIT(offset + PL061_DATA_OFFSET); + else + *reg =3D base; + *mask =3D BIT(offset); =20 return 0; } =20 -static int pl061_irq_type(struct irq_data *d, unsigned trigger) +static int pl061_irq_type(struct irq_data *d, unsigned int trigger) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); + const struct pl061_regs *regs =3D pl061->data->regs; int offset =3D irqd_to_hwirq(d); unsigned int gpiois =3D 0, gpioibe =3D 0, gpioiev =3D 0; unsigned int bit =3D BIT(offset); =20 - if (offset < 0 || offset >=3D PL061_GPIO_NR) + if (offset < 0 || offset >=3D pl061->data->ngpio) return -EINVAL; =20 if ((trigger & IRQ_TYPE_LEVEL_MASK) && (trigger & IRQ_TYPE_EDGE_BOTH)) { @@ -171,12 +118,11 @@ static int pl061_irq_type(struct irq_data *d, unsigne= d trigger) return -EINVAL; } =20 - guard(raw_spinlock_irqsave)(&pl061->lock); =20 - regmap_read(pl061->regmap, GPIOIEV, &gpioiev); - regmap_read(pl061->regmap, GPIOIS, &gpiois); - regmap_read(pl061->regmap, GPIOIBE, &gpioibe); + regmap_read(pl061->regmap, regs->iev, &gpioiev); + regmap_read(pl061->regmap, regs->is, &gpiois); + regmap_read(pl061->regmap, regs->ibe, &gpioibe); =20 if (trigger & IRQ_TYPE_LEVEL_MASK) { bool polarity =3D trigger & IRQ_TYPE_LEVEL_HIGH; @@ -228,10 +174,11 @@ static int pl061_irq_type(struct irq_data *d, unsigne= d trigger) offset); } =20 - regmap_write(pl061->regmap, GPIOIS, gpiois); - regmap_write(pl061->regmap, GPIOIBE, gpioibe); - regmap_write(pl061->regmap, GPIOIEV, gpioiev); - + regmap_write(pl061->regmap, regs->is, gpiois); + regmap_write(pl061->regmap, regs->ibe, gpioibe); + regmap_write(pl061->regmap, regs->iev, gpioiev); + if (pl061->data->clear_irq_on_type) + regmap_write(pl061->regmap, regs->ic, bit); =20 return 0; } @@ -240,32 +187,34 @@ static void pl061_irq_handler(struct irq_desc *desc) { unsigned long pending; unsigned int mis =3D 0; - int offset; + int offset, ret; struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); - struct pl061 *pl061 =3D gpiochip_get_data(gc); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); struct irq_chip *irqchip =3D irq_desc_get_chip(desc); =20 chained_irq_enter(irqchip, desc); =20 - regmap_read(pl061->regmap, GPIOMIS, &mis); + ret =3D regmap_read(pl061->regmap, pl061->data->regs->mis, &mis); + if (ret) + goto out; + if (mis) { pending =3D mis; - for_each_set_bit(offset, &pending, PL061_GPIO_NR) - generic_handle_domain_irq(gc->irq.domain, - offset); + for_each_set_bit(offset, &pending, pl061->data->ngpio) + generic_handle_domain_irq(pl061->irq_domain, offset); } =20 +out: chained_irq_exit(irqchip, desc); } =20 static void pl061_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); - u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); + unsigned int mask =3D pl061_line_mask(pl061, irqd_to_hwirq(d)); =20 - guard(raw_spinlock)(&pl061->lock); - regmap_update_bits(pl061->regmap, GPIOIE, mask, 0); + regmap_update_bits(pl061->regmap, pl061->data->regs->ie, mask, 0); =20 gpiochip_disable_irq(gc, d->hwirq); } @@ -273,13 +222,12 @@ static void pl061_irq_mask(struct irq_data *d) static void pl061_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); - u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); + unsigned int mask =3D pl061_line_mask(pl061, irqd_to_hwirq(d)); =20 gpiochip_enable_irq(gc, d->hwirq); =20 - guard(raw_spinlock)(&pl061->lock); - regmap_update_bits(pl061->regmap, GPIOIE, mask, mask); + regmap_update_bits(pl061->regmap, pl061->data->regs->ie, mask, mask); } =20 /** @@ -293,16 +241,16 @@ static void pl061_irq_unmask(struct irq_data *d) static void pl061_irq_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); - u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); + unsigned int mask =3D pl061_line_mask(pl061, irqd_to_hwirq(d)); =20 - regmap_write(pl061->regmap, GPIOIC, mask); + regmap_write(pl061->regmap, pl061->data->regs->ic, mask); } =20 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); =20 return irq_set_irq_wake(pl061->parent_irq, state); } @@ -314,7 +262,8 @@ static void pl061_irq_print_chip(struct irq_data *data,= struct seq_file *p) seq_puts(p, dev_name(gc->parent)); } =20 -static const struct irq_chip pl061_irq_chip =3D { +static const struct irq_chip pl061_irqchip =3D { + .name =3D "pl061", .irq_ack =3D pl061_irq_ack, .irq_mask =3D pl061_irq_mask, .irq_unmask =3D pl061_irq_unmask, @@ -325,64 +274,187 @@ static const struct irq_chip pl061_irq_chip =3D { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 +static int pl061_irq_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hwirq) +{ + struct gpio_chip *gc =3D d->host_data; + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); + + irq_set_chip_data(virq, gc); + irq_set_chip_and_handler(virq, &pl061_irqchip, handle_bad_irq); + irq_set_noprobe(virq); + irq_set_parent(virq, pl061->parent_irq); + + return 0; +} + +static void pl061_irq_domain_unmap(struct irq_domain *d, unsigned int virq) +{ + irq_set_chip_and_handler(virq, NULL, NULL); + irq_set_chip_data(virq, NULL); +} + +static const struct irq_domain_ops pl061_irq_domain_ops =3D { + .map =3D pl061_irq_domain_map, + .unmap =3D pl061_irq_domain_unmap, + .xlate =3D irq_domain_xlate_twothreecell, +}; + +static void pl061_remove_irq(void *data) +{ + struct pl061 *pl061 =3D data; + + irq_set_chained_handler_and_data(pl061->parent_irq, NULL, NULL); + + for (unsigned int i =3D 0; i < pl061->data->ngpio; i++) { + unsigned int virq; + + virq =3D irq_find_mapping(pl061->irq_domain, i); + if (virq) + irq_dispose_mapping(virq); + } + + irq_domain_remove(pl061->irq_domain); +} + +static bool pl061_arm_is_data_reg(unsigned int reg) +{ + return reg >=3D BIT(PL061_DATA_OFFSET) && + reg <=3D BIT(PL061_DATA_OFFSET + PL061_GPIO_NR - 1) && + is_power_of_2(reg); +} + +static bool pl061_arm_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case PL061_MIS: + case PL061_IC: + return true; + default: + return pl061_arm_is_data_reg(reg); + } +} + +static const struct regmap_config pl061_arm_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .reg_stride =3D 4, + .max_register =3D PL061_IC, + .volatile_reg =3D pl061_arm_volatile_reg, + .cache_type =3D REGCACHE_FLAT_S, + .fast_io =3D true, + .use_raw_spinlock =3D true, +}; + +static const struct pl061_regs pl061_arm_regs =3D { + .dir =3D PL061_DIR, + .is =3D PL061_IS, + .ibe =3D PL061_IBE, + .iev =3D PL061_IEV, + .ie =3D PL061_IE, + .mis =3D PL061_MIS, + .ic =3D PL061_IC, +}; + +static const struct pl061_drvdata pl061_arm =3D { + .regmap_config =3D &pl061_arm_regmap_config, + .regs =3D &pl061_arm_regs, + .ngpio =3D PL061_GPIO_NR, + .write_data_after_dir =3D true, + .pm =3D true, + .reg_mask_xlate =3D pl061_arm_reg_mask_xlate, +}; + static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev =3D &adev->dev; + const struct pl061_drvdata *data; + const struct pl061_regs *regs; + struct gpio_regmap_config config =3D {}; + struct gpio_regmap *gpio_regmap; + struct gpio_chip *gc; struct pl061 *pl061; - struct gpio_irq_chip *girq; void __iomem *base; int ret, irq; =20 + data =3D id->data; + if (!data) + return -ENODATA; + + regs =3D data->regs; + pl061 =3D devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); - if (pl061 =3D=3D NULL) + if (!pl061) return -ENOMEM; =20 + pl061->data =3D data; + raw_spin_lock_init(&pl061->lock); + base =3D devm_ioremap_resource(dev, &adev->res); if (IS_ERR(base)) return PTR_ERR(base); =20 - pl061->regmap =3D devm_regmap_init_mmio(dev, base, &pl061_regmap_config); + pl061->regmap =3D devm_regmap_init_mmio(dev, base, data->regmap_config); if (IS_ERR(pl061->regmap)) return PTR_ERR(pl061->regmap); =20 - raw_spin_lock_init(&pl061->lock); - pl061->gc.request =3D gpiochip_generic_request; - pl061->gc.free =3D gpiochip_generic_free; - pl061->gc.base =3D -1; - pl061->gc.get_direction =3D pl061_get_direction; - pl061->gc.direction_input =3D pl061_direction_input; - pl061->gc.direction_output =3D pl061_direction_output; - pl061->gc.get =3D pl061_get_value; - pl061->gc.set =3D pl061_set_value; - pl061->gc.ngpio =3D PL061_GPIO_NR; - pl061->gc.label =3D dev_name(dev); - pl061->gc.parent =3D dev; - pl061->gc.owner =3D THIS_MODULE; + if (regs->enable) { + ret =3D regmap_write(pl061->regmap, regs->enable, ~0U); + if (ret) + return ret; + } + if (regs->mask) { + ret =3D regmap_write(pl061->regmap, regs->mask, ~0U); + if (ret) + return ret; + } =20 /* * irq_chip support */ - regmap_write(pl061->regmap, GPIOIE, 0); /* disable irqs */ + regmap_write(pl061->regmap, regs->ie, 0); /* disable irqs */ + irq =3D adev->irq[0]; if (!irq) - dev_warn(&adev->dev, "IRQ support disabled\n"); + dev_warn(dev, "IRQ support disabled\n"); pl061->parent_irq =3D irq; =20 - girq =3D &pl061->gc.irq; - gpio_irq_chip_set_chip(girq, &pl061_irq_chip); - girq->parent_handler =3D pl061_irq_handler; - girq->num_parents =3D 1; - girq->parents =3D devm_kcalloc(dev, 1, sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] =3D irq; - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_bad_irq; - - ret =3D devm_gpiochip_add_data(dev, &pl061->gc, pl061); - if (ret) - return ret; + config.parent =3D dev; + config.regmap =3D pl061->regmap; + config.ngpio =3D data->ngpio; + config.reg_dat_base =3D GPIO_REGMAP_ADDR(regs->dat); + config.reg_set_base =3D GPIO_REGMAP_ADDR(regs->dat); + config.reg_dir_out_base =3D regs->dir; + config.reg_mask_xlate =3D data->reg_mask_xlate; + config.write_data_after_dir =3D data->write_data_after_dir; + config.drvdata =3D pl061; + + gpio_regmap =3D devm_gpio_regmap_register(dev, &config); + if (IS_ERR(gpio_regmap)) + return PTR_ERR(gpio_regmap); + + gc =3D gpio_regmap_get_chip(gpio_regmap); + + if (irq) { + pl061->irq_domain =3D irq_domain_create_linear(dev_fwnode(dev), + data->ngpio, + &pl061_irq_domain_ops, + gc); + if (!pl061->irq_domain) + return -ENOMEM; + + ret =3D gpiochip_irqchip_add_domain(gc, pl061->irq_domain); + if (ret) { + irq_domain_remove(pl061->irq_domain); + return ret; + } + + ret =3D devm_add_action_or_reset(dev, pl061_remove_irq, pl061); + if (ret) + return ret; + + irq_set_chained_handler_and_data(irq, pl061_irq_handler, gc); + } =20 amba_set_drvdata(adev, pl061); dev_info(dev, "PL061 GPIO chip registered\n"); @@ -390,28 +462,38 @@ static int pl061_probe(struct amba_device *adev, cons= t struct amba_id *id) return 0; } =20 +static void pl061_cache_ctrl_regs(struct pl061 *pl061, unsigned int *dir) +{ + const struct pl061_regs *regs =3D pl061->data->regs; + unsigned int val; + + regmap_read(pl061->regmap, regs->dir, dir); + regmap_read(pl061->regmap, regs->is, &val); + regmap_read(pl061->regmap, regs->ibe, &val); + regmap_read(pl061->regmap, regs->iev, &val); + regmap_read(pl061->regmap, regs->ie, &val); +} + static int pl061_suspend(struct device *dev) { struct pl061 *pl061 =3D dev_get_drvdata(dev); - unsigned int val =3D 0; - int offset; - - pl061->csave_regs.gpio_data =3D 0; - regmap_read(pl061->regmap, GPIODIR, &val); - pl061->csave_regs.gpio_dir =3D val; - regmap_read(pl061->regmap, GPIOIS, &val); - pl061->csave_regs.gpio_is =3D val; - regmap_read(pl061->regmap, GPIOIBE, &val); - pl061->csave_regs.gpio_ibe =3D val; - regmap_read(pl061->regmap, GPIOIEV, &val); - pl061->csave_regs.gpio_iev =3D val; - regmap_read(pl061->regmap, GPIOIE, &val); - pl061->csave_regs.gpio_ie =3D val; - - for (offset =3D 0; offset < PL061_GPIO_NR; offset++) { - if (pl061->csave_regs.gpio_dir & (BIT(offset))) - pl061->csave_regs.gpio_data |=3D - pl061_get_value(&pl061->gc, offset) << offset; + unsigned long dir_mask; + unsigned int dir =3D 0, val; + unsigned int offset; + + if (!pl061->data->pm) + return 0; + + pl061_cache_ctrl_regs(pl061, &dir); + + pl061->saved_dat =3D 0; + dir_mask =3D dir; + for_each_set_bit(offset, &dir_mask, pl061->data->ngpio) { + val =3D 0; + regmap_read_bypassed(pl061->regmap, + BIT(offset + PL061_DATA_OFFSET), + &val); + pl061->saved_dat |=3D val; } =20 return 0; @@ -420,23 +502,27 @@ static int pl061_suspend(struct device *dev) static int pl061_resume(struct device *dev) { struct pl061 *pl061 =3D dev_get_drvdata(dev); - int offset; + const struct pl061_regs *regs; + unsigned long dir_mask; + unsigned int dir =3D 0, offset; =20 - for (offset =3D 0; offset < PL061_GPIO_NR; offset++) { - if (pl061->csave_regs.gpio_dir & (BIT(offset))) - pl061_direction_output(&pl061->gc, offset, - pl061->csave_regs.gpio_data & - (BIT(offset))); - else - pl061_direction_input(&pl061->gc, offset); - } + if (!pl061->data->pm) + return 0; =20 - regmap_write(pl061->regmap, GPIOIS, pl061->csave_regs.gpio_is); - regmap_write(pl061->regmap, GPIOIBE, pl061->csave_regs.gpio_ibe); - regmap_write(pl061->regmap, GPIOIEV, pl061->csave_regs.gpio_iev); - regmap_write(pl061->regmap, GPIOIE, pl061->csave_regs.gpio_ie); + regs =3D pl061->data->regs; =20 - return 0; + regmap_read(pl061->regmap, regs->dir, &dir); + + regcache_mark_dirty(pl061->regmap); + regcache_sync_region(pl061->regmap, regs->dir, regs->dir); + + dir_mask =3D dir; + for_each_set_bit(offset, &dir_mask, pl061->data->ngpio) + regmap_write(pl061->regmap, + BIT(offset + PL061_DATA_OFFSET), + !!(pl061->saved_dat & BIT(offset)) << offset); + + return regcache_sync_region(pl061->regmap, regs->is, regs->ie); } =20 static DEFINE_SIMPLE_DEV_PM_OPS(pl061_dev_pm_ops, pl061_suspend, pl061_res= ume); @@ -445,6 +531,7 @@ static const struct amba_id pl061_ids[] =3D { { .id =3D 0x00041061, .mask =3D 0x000fffff, + .data =3D (void *)&pl061_arm, }, { 0, 0 }, }; --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 219D336B92C; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964614; cv=none; b=hphzNSUYXZnl2/V/0V/J/RZtFRDTBH7y4x4fsKIsq/wpt4lV6wzQ/nQjufBCUb0O+QEpLNu+LHPzucYm7pBC46SRgj3OThHjn1cv2MEDyXM/EcjeCv1KzzL1t4D/cX7ZgKJ+h+74owe2q6xnXpkaNrKmSJ0wogPeMMSoH0FDvow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964614; c=relaxed/simple; bh=ELqcw3LBSmBtItQm8aQ9QzI3Xq97N7afNTnfipf3dIo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=l2VA5EOuxzT0f736H6Ur60E/aYk4XWK4RvEW8x1/y/NEYFVwSPpFNLHWsHtdYlUtsNGNHTUpU7eL/a+XkhEVsF509eb6VXEZe7/MuoYM/sm6v5LH2s0Wm+oI6UnGaWE5ySmwy1Cvq09fBp6iEsKTwl1inU2AnN7kiUypZJduXGw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hkGrnjqN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hkGrnjqN" Received: by smtp.kernel.org (Postfix) with ESMTPS id D3174C2BD05; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964613; bh=ELqcw3LBSmBtItQm8aQ9QzI3Xq97N7afNTnfipf3dIo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hkGrnjqN2EScBr3rFVpYCEeHwdWf8lluL/mfolmfzaLQd+nKWGOHq6/UqRFJNHYHo HnCthIpUPc3ui/CRtWE3zu9uZMXkKxAvuYmPT18E3tHkGXCZ24kDn/piqp9gJEC2Nh SE5p4gUk3YhUDFYmnTx4jkXY3LarCfKrnjBRcBIQQHjTo8168MhPlH8RVr1/GSmexn mYe1FWAPeDhy1ZLIksE1T0MfC3FYWI09qfF7/YYs2iF+/TU0gojBbAve0ReOWklGy3 5BHW9cLdkMtEb0fy16ikJxpfs5AbCQU4YuJVLti3dDJ9aLWA0mKH0oluqfevwt42eU qNAq4xb4jYp9w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBEECC982F1; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:33 +0800 Subject: [PATCH v8 14/18] gpio: pl061: add Ambarella register-layout variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-14-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=3980; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=UJUD7yvQRDjUnxZn37u+jsf5HE3dcaqrKiM8weupWiY=; b=aqTvGbpbG0JFVzw6uqBtaNBvLqAtjHTQy6aHG8wAteDMBByBZz7cprSPfRRlH3juaq5VzSRDp 6E+eKojrlH8B7Dl98RytohYGgxKU8fs13hdrHdzAU/34rXsnlNtqTZC X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add a 32-bit, 32-line layout with DAT/DIR/IS/IBE/IEV/IE/MIS/IC plus MASK and ENABLE. Probe unmasks the bank and enables the controller. IRQ type changes also clear the pending bit. This derivative does not need write-after-direction or system suspend save/restore. Match the part with designer AMBA_VENDOR_AMBARELLA (JEP106 identity 0x68, bit 7 set) and part number 0x061. Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- drivers/gpio/gpio-pl061.c | 59 +++++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/amba/bus.h | 1 + 2 files changed, 60 insertions(+) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 604129a68948..fc7269837af4 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -39,6 +39,18 @@ #define PL061_MIS 0x418 #define PL061_IC 0x41c =20 +#define AMBARELLA_GPIO_NR 32 +#define AMBARELLA_DAT 0x00 +#define AMBARELLA_DIR 0x04 +#define AMBARELLA_IS 0x08 +#define AMBARELLA_IBE 0x0c +#define AMBARELLA_IEV 0x10 +#define AMBARELLA_IE 0x14 +#define AMBARELLA_MIS 0x20 +#define AMBARELLA_IC 0x24 +#define AMBARELLA_MASK 0x28 +#define AMBARELLA_ENABLE 0x2c + struct pl061_regs { unsigned int dat; unsigned int dir; @@ -335,6 +347,18 @@ static bool pl061_arm_volatile_reg(struct device *dev,= unsigned int reg) } } =20 +static bool pl061_ambarella_volatile_reg(struct device *dev, unsigned int = reg) +{ + switch (reg) { + case AMBARELLA_DAT: + case AMBARELLA_MIS: + case AMBARELLA_IC: + return true; + default: + return false; + } +} + static const struct regmap_config pl061_arm_regmap_config =3D { .reg_bits =3D 16, .val_bits =3D 8, @@ -346,6 +370,16 @@ static const struct regmap_config pl061_arm_regmap_con= fig =3D { .use_raw_spinlock =3D true, }; =20 +static const struct regmap_config pl061_ambarella_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D AMBARELLA_ENABLE, + .volatile_reg =3D pl061_ambarella_volatile_reg, + .fast_io =3D true, + .use_raw_spinlock =3D true, +}; + static const struct pl061_regs pl061_arm_regs =3D { .dir =3D PL061_DIR, .is =3D PL061_IS, @@ -356,6 +390,19 @@ static const struct pl061_regs pl061_arm_regs =3D { .ic =3D PL061_IC, }; =20 +static const struct pl061_regs pl061_ambarella_regs =3D { + .dat =3D AMBARELLA_DAT, + .dir =3D AMBARELLA_DIR, + .is =3D AMBARELLA_IS, + .ibe =3D AMBARELLA_IBE, + .iev =3D AMBARELLA_IEV, + .ie =3D AMBARELLA_IE, + .mis =3D AMBARELLA_MIS, + .ic =3D AMBARELLA_IC, + .mask =3D AMBARELLA_MASK, + .enable =3D AMBARELLA_ENABLE, +}; + static const struct pl061_drvdata pl061_arm =3D { .regmap_config =3D &pl061_arm_regmap_config, .regs =3D &pl061_arm_regs, @@ -365,6 +412,13 @@ static const struct pl061_drvdata pl061_arm =3D { .reg_mask_xlate =3D pl061_arm_reg_mask_xlate, }; =20 +static const struct pl061_drvdata pl061_ambarella =3D { + .regmap_config =3D &pl061_ambarella_regmap_config, + .regs =3D &pl061_ambarella_regs, + .ngpio =3D AMBARELLA_GPIO_NR, + .clear_irq_on_type =3D true, +}; + static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev =3D &adev->dev; @@ -533,6 +587,11 @@ static const struct amba_id pl061_ids[] =3D { .mask =3D 0x000fffff, .data =3D (void *)&pl061_arm, }, + { + .id =3D (AMBA_VENDOR_AMBARELLA << 12) | 0x061, + .mask =3D 0x000fffff, + .data =3D (void *)&pl061_ambarella, + }, { 0, 0 }, }; MODULE_DEVICE_TABLE(amba, pl061_ids); diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index 80a74cd2da7e..411533bfa61d 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -98,6 +98,7 @@ enum amba_vendor { AMBA_VENDOR_ST =3D 0x80, AMBA_VENDOR_QCOM =3D 0x51, AMBA_VENDOR_LSI =3D 0xb6, + AMBA_VENDOR_AMBARELLA =3D 0xe8, }; =20 extern const struct bus_type amba_bustype; --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 886A236F8EA; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964614; cv=none; b=soDQ96HZRYCUVnja3cp0aUptrzP+kLc1IoL3aT6BilNWyPNYA4dZn/25ZIlZo1xWb8uHf5hP1ED41cyw8gosU3rWsm/QEZyV3r66PX6Lcgazik97bKgtjC6eyYRt4u9IB0XOfDMsAAQt2MqFNpH4MT/rTK7Y0HFQofmdaETy0G4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964614; c=relaxed/simple; bh=+WMyT5QYNJ2+LJTTM6tk634ik9WZZSoCmnkpwqz0ObU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pTFGHzoqpIYAx67b7VlM/QKSYpswQn5L4z4Xb4cRgFc7XPRtDAZo9Bgs08N3bgsCbsdfRXP51yoiCX8NIABRU3eI7il6j/M1reqJhC/JE9VarvdCp8jo+OZLqKWafRmHbCUpyWsXfZ5gyz/eBwSBd4dR/pGhf3DAw4ciCP2ItgA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kBGCESco; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kBGCESco" Received: by smtp.kernel.org (Postfix) with ESMTPS id 09572C4AF12; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964614; bh=+WMyT5QYNJ2+LJTTM6tk634ik9WZZSoCmnkpwqz0ObU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kBGCEScoIpsyFInhGS3EGHeLQHNAn4u9KguMXBY0iFuniyYhye17lE71ExRK1W2Ew YKDXWfu5ZUIbQNzznDqF3ezRZ479tKlurKq6eSy7p+RTbBiaPvoUcPud9xaWjDUTzG TrQlMBadnBH513vJPm3aBetaI+FbcQF1ac2JPcWarg/WtU/6r3qbPXZEUBlGJ77i55 8hqHesuXxH0laJJ2+KWo3PLprkA4xpZOMq/67g/0oXWSK1pkHUgFuZQ24oQRJ1/W9H tPWJXnJmBL5E423vMwIFD6a6LqQIb3NdWfcuDtQF5QKxUQnJf4VKaQb75FEhSxYAVy RrPyEDc0Zg/YQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E55ACC982F6; Mon, 21 Sep 2026 04:23:33 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:34 +0800 Subject: [PATCH v8 15/18] pinctrl: ambarella: add CV75 pin controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-15-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=33272; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=kzm8lidRjLl/Ft5S5GTBOgsSYKQkEiOU0P3HBd9ofWw=; b=QWKj0Jf4B1Gmuy2FkvntVAr3nauBtjGv+WznA808O6WYRwrxR6ACjYOzJkq51tsRNb6QkX6ou 7MZPFgzNPiJDF8c3kVpVuuSf7A3x1XSpJxakcxcTt2k9wfsO1ex85X5 X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add an Ambarella pinmux-only pinctrl driver with CV75 function/group tables. GPIO is handled by the PL061 driver. Signed-off-by: Long Zhao --- drivers/pinctrl/Kconfig | 17 + drivers/pinctrl/Makefile | 2 + drivers/pinctrl/pinctrl-ambarella-cv75.c | 587 +++++++++++++++++++++++++++= ++++ drivers/pinctrl/pinctrl-ambarella.c | 533 ++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-ambarella.h | 40 +++ 5 files changed, 1179 insertions(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index c2cdd7b2c49b..08fbe3dc041b 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -37,6 +37,23 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. =20 +config PINCTRL_AMB + bool "Ambarella pin controller support" + depends on ARCH_AMBARELLA || COMPILE_TEST + depends on HAS_IOMEM + default y if ARCH_AMBARELLA + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIO_PL061 + select MFD_SYSCON + select PINCONF + select PINMUX + help + Say Y here to enable the Ambarella pinmux/pinconf controller. + GPIO is provided by the PL061 driver. + config PINCTRL_AMD bool "AMD GPIO pin control" depends on HAS_IOMEM diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index a35d71135abf..ce0825f4fc1b 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -10,6 +10,8 @@ obj-$(CONFIG_GENERIC_PINCONF) +=3D pinconf-generic.o obj-$(CONFIG_GENERIC_PINCTRL) +=3D pinctrl-generic.o obj-$(CONFIG_OF) +=3D devicetree.o =20 +obj-$(CONFIG_PINCTRL_AMB) +=3D pinctrl-ambarella.o +obj-$(CONFIG_PINCTRL_AMB) +=3D pinctrl-ambarella-cv75.o obj-$(CONFIG_PINCTRL_AMD) +=3D pinctrl-amd.o obj-$(CONFIG_PINCTRL_AMDISP) +=3D pinctrl-amdisp.o obj-$(CONFIG_PINCTRL_APPLE_GPIO) +=3D pinctrl-apple-gpio.o diff --git a/drivers/pinctrl/pinctrl-ambarella-cv75.c b/drivers/pinctrl/pin= ctrl-ambarella-cv75.c new file mode 100644 index 000000000000..eb25fd94ece8 --- /dev/null +++ b/drivers/pinctrl/pinctrl-ambarella-cv75.c @@ -0,0 +1,587 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ambarella CV75 pinctrl data + * + * Copyright (C) 2026, Ambarella, Inc. + */ + +#include +#include +#include + +#include + +#include "pinctrl-ambarella.h" + +#define CV75_EXPAND(...) __VA_ARGS__ +#define CV75_GROUP_PINS_ALTS(_name, _pin_list, _alt_list) \ + static const unsigned int cv75_##_name##_pins[] =3D { CV75_EXPAND _pin_li= st }; \ + static const u8 cv75_##_name##_alts[] =3D { CV75_EXPAND _alt_list }; \ + static const struct pingroup cv75_##_name##_grp =3D \ + PINCTRL_PINGROUP(#_name, cv75_##_name##_pins, \ + ARRAY_SIZE(cv75_##_name##_pins)); \ + static_assert(ARRAY_SIZE(cv75_##_name##_pins) =3D=3D \ + ARRAY_SIZE(cv75_##_name##_alts)) + +#define CV75_GROUP(_name) \ +{ \ + .grp =3D &cv75_##_name##_grp, \ + .alts =3D cv75_##_name##_alts, \ +} + +#define CV75_FUNCTION(_name) \ + PINCTRL_PINFUNCTION(#_name, cv75_##_name##_groups, ARRAY_SIZE(cv75_##_nam= e##_groups)) + +/* UART */ +CV75_GROUP_PINS_ALTS(uart0, (44, 45), (1, 1)); +CV75_GROUP_PINS_ALTS(uart1, (46, 47), (1, 1)); +CV75_GROUP_PINS_ALTS(uart1_flow, (48, 49), (1, 1)); +CV75_GROUP_PINS_ALTS(uart2_a, (46, 47), (2, 2)); +CV75_GROUP_PINS_ALTS(uart2_b, (50, 51), (2, 2)); +CV75_GROUP_PINS_ALTS(uart2_c, (66, 68), (2, 2)); +CV75_GROUP_PINS_ALTS(uart2_flow_a, (48, 49), (2, 2)); +CV75_GROUP_PINS_ALTS(uart2_flow_b, (65, 67), (3, 3)); +CV75_GROUP_PINS_ALTS(uart3_a, (70, 72), (3, 3)); +CV75_GROUP_PINS_ALTS(uart3_b, (80, 79), (3, 3)); +CV75_GROUP_PINS_ALTS(uart3_flow_a, (71, 69), (3, 3)); +CV75_GROUP_PINS_ALTS(uart3_flow_b, (81, 82), (3, 3)); +CV75_GROUP_PINS_ALTS(uart4_a, (29, 30), (3, 3)); +CV75_GROUP_PINS_ALTS(uart4_b, (76, 77), (3, 3)); +CV75_GROUP_PINS_ALTS(uart4_flow_a, (28, 31), (3, 3)); +CV75_GROUP_PINS_ALTS(uart4_flow_b, (74, 75), (3, 3)); + +/* Flash */ +CV75_GROUP_PINS_ALTS(snand, (79, 80, 81, 82, 83, 84), (1, 1, 1, 1, 1, 1)); +CV75_GROUP_PINS_ALTS(spinor, (79, 80, 81, 82, 83, 84, 85), + (2, 2, 2, 2, 2, 2, 2)); + +/* SD/MMC */ +CV75_GROUP_PINS_ALTS(sdmmc0_cd, (6), (1)); +CV75_GROUP_PINS_ALTS(sdmmc0_wp, (7), (1)); +CV75_GROUP_PINS_ALTS(sdmmc0_reset, (8), (1)); +CV75_GROUP_PINS_ALTS(sdmmc0_hs_sel, (93), (1)); +CV75_GROUP_PINS_ALTS(sdmmc0_1bit, (0, 4, 5), (1, 1, 1)); +CV75_GROUP_PINS_ALTS(sdmmc0_4bit, (0, 1, 2, 3, 4, 5), (1, 1, 1, 1, 1, 1)); +CV75_GROUP_PINS_ALTS(sdmmc1_cd, (15), (1)); +CV75_GROUP_PINS_ALTS(sdmmc1_wp, (16), (1)); +CV75_GROUP_PINS_ALTS(sdmmc1_reset, (17), (1)); +CV75_GROUP_PINS_ALTS(sdmmc1_hs_sel, (94), (1)); +CV75_GROUP_PINS_ALTS(sdmmc1_1bit, (9, 13, 14), (1, 1, 1)); +CV75_GROUP_PINS_ALTS(sdmmc1_4bit, (9, 10, 11, 12, 13, 14), (1, 1, 1, 1, 1,= 1)); + +/* Ethernet */ +CV75_GROUP_PINS_ALTS(enet_ext_osc_clk, (77), (1)); +CV75_GROUP_PINS_ALTS(enet_2nd_ref_clk_a, (78), (1)); +CV75_GROUP_PINS_ALTS(enet_2nd_ref_clk_b, (76), (2)); +CV75_GROUP_PINS_ALTS(enet0_ptp_pps_o, (74), (1)); +CV75_GROUP_PINS_ALTS(rgmii0, (62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, = 73, 75, 76), + (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)); +CV75_GROUP_PINS_ALTS(rmii0, (62, 63, 64, 67, 68, 71, 72, 73, 75), + (1, 1, 1, 1, 1, 1, 1, 1, 2)); + +/* I2C */ +CV75_GROUP_PINS_ALTS(i2c0_a, (67, 68), (2, 2)); +CV75_GROUP_PINS_ALTS(i2c0_b, (86, 87), (1, 1)); +CV75_GROUP_PINS_ALTS(i2c1_a, (22, 23), (2, 2)); +CV75_GROUP_PINS_ALTS(i2c1_b, (69, 70), (2, 2)); +CV75_GROUP_PINS_ALTS(i2c2, (88, 89), (1, 1)); +CV75_GROUP_PINS_ALTS(i2c3_a, (24, 25), (2, 2)); +CV75_GROUP_PINS_ALTS(i2c3_b, (48, 49), (3, 3)); +CV75_GROUP_PINS_ALTS(i2c3_c, (58, 59), (3, 3)); +CV75_GROUP_PINS_ALTS(i2cs_a, (19, 21), (2, 2)); +CV75_GROUP_PINS_ALTS(i2cs_b, (60, 61), (3, 3)); +CV75_GROUP_PINS_ALTS(i2cs_c, (71, 72), (2, 2)); +CV75_GROUP_PINS_ALTS(i2cs_d, (86, 87), (2, 2)); + +/* CAN, IR, WDT */ +CV75_GROUP_PINS_ALTS(can0, (50, 51), (1, 1)); +CV75_GROUP_PINS_ALTS(can1, (52, 53), (1, 1)); +CV75_GROUP_PINS_ALTS(ir, (18), (1)); +CV75_GROUP_PINS_ALTS(wdt_a, (20), (2)); +CV75_GROUP_PINS_ALTS(wdt_b, (27), (3)); +CV75_GROUP_PINS_ALTS(wdt_c, (39), (2)); +CV75_GROUP_PINS_ALTS(wdt_d, (83), (3)); +CV75_GROUP_PINS_ALTS(wdt_e, (85), (4)); +CV75_GROUP_PINS_ALTS(wdt_f, (90), (1)); + +/* I2S */ +CV75_GROUP_PINS_ALTS(i2s0, (54, 55, 56, 57), (1, 1, 1, 1)); +CV75_GROUP_PINS_ALTS(i2s1, (58, 59, 60, 61), (1, 1, 1, 1)); +CV75_GROUP_PINS_ALTS(dmic0, (54, 55), (2, 2)); + +/* PWM */ +CV75_GROUP_PINS_ALTS(pwm0, (40), (1)); +CV75_GROUP_PINS_ALTS(pwm1, (41), (1)); +CV75_GROUP_PINS_ALTS(pwm2, (42), (1)); +CV75_GROUP_PINS_ALTS(pwm3, (43), (1)); +CV75_GROUP_PINS_ALTS(pwm4_a, (19), (3)); +CV75_GROUP_PINS_ALTS(pwm4_b, (32), (4)); +CV75_GROUP_PINS_ALTS(pwm5_a, (20), (3)); +CV75_GROUP_PINS_ALTS(pwm5_b, (33), (4)); +CV75_GROUP_PINS_ALTS(pwm6_a, (21), (3)); +CV75_GROUP_PINS_ALTS(pwm6_b, (34), (4)); +CV75_GROUP_PINS_ALTS(pwm7_a, (22), (3)); +CV75_GROUP_PINS_ALTS(pwm7_b, (35), (4)); +CV75_GROUP_PINS_ALTS(pwm8_a, (23), (3)); +CV75_GROUP_PINS_ALTS(pwm8_b, (36), (4)); +CV75_GROUP_PINS_ALTS(pwm9_a, (24), (3)); +CV75_GROUP_PINS_ALTS(pwm9_b, (37), (4)); +CV75_GROUP_PINS_ALTS(pwm10_a, (25), (3)); +CV75_GROUP_PINS_ALTS(pwm10_b, (38), (4)); +CV75_GROUP_PINS_ALTS(pwm11_a, (26), (3)); +CV75_GROUP_PINS_ALTS(pwm11_b, (39), (4)); + +/* SPI */ +CV75_GROUP_PINS_ALTS(spi0, (19, 20, 21), (1, 1, 1)); +CV75_GROUP_PINS_ALTS(spi1, (24, 25, 26), (1, 1, 1)); +CV75_GROUP_PINS_ALTS(spi2, (28, 29, 30), (1, 1, 1)); +CV75_GROUP_PINS_ALTS(spi3_a, (32, 33, 34), (5, 5, 5)); +CV75_GROUP_PINS_ALTS(spi3_b, (40, 41, 43), (2, 2, 2)); +CV75_GROUP_PINS_ALTS(spi3_c, (58, 59, 60), (2, 2, 2)); +CV75_GROUP_PINS_ALTS(spi_slave_a, (24, 25, 26, 27), (4, 4, 4, 4)); +CV75_GROUP_PINS_ALTS(spi_slave_b, (28, 29, 30, 31), (2, 2, 2, 2)); +CV75_GROUP_PINS_ALTS(spi_slave_c, (36, 37, 38, 39), (5, 5, 5, 5)); +CV75_GROUP_PINS_ALTS(spi_slave_d, (50, 51, 52, 53), (3, 3, 3, 3)); +CV75_GROUP_PINS_ALTS(spi_slave_e, (81, 82, 83, 84), (4, 4, 4, 4)); + +/* VIN master sync */ +CV75_GROUP_PINS_ALTS(vin_master_sync_a, (91, 92), (1, 1)); +CV75_GROUP_PINS_ALTS(vin_master_sync_b, (91, 92), (2, 2)); +CV75_GROUP_PINS_ALTS(vin_master_sync_c, (40, 41), (3, 3)); +CV75_GROUP_PINS_ALTS(vin_master_sync_d, (46, 47), (3, 3)); +CV75_GROUP_PINS_ALTS(vin_master_sync_e, (79, 80), (4, 4)); +CV75_GROUP_PINS_ALTS(vsync0, (32), (1)); +CV75_GROUP_PINS_ALTS(vsync1, (33), (1)); +CV75_GROUP_PINS_ALTS(vsync2, (34), (1)); +CV75_GROUP_PINS_ALTS(vsync3, (35), (1)); +CV75_GROUP_PINS_ALTS(hsync0, (36), (1)); +CV75_GROUP_PINS_ALTS(hsync1, (37), (1)); + +static const struct amb_pinmux_group cv75_pin_groups[] =3D { + /* UART */ + CV75_GROUP(uart0), + CV75_GROUP(uart1), + CV75_GROUP(uart1_flow), + CV75_GROUP(uart2_a), + CV75_GROUP(uart2_b), + CV75_GROUP(uart2_c), + CV75_GROUP(uart2_flow_a), + CV75_GROUP(uart2_flow_b), + CV75_GROUP(uart3_a), + CV75_GROUP(uart3_b), + CV75_GROUP(uart3_flow_a), + CV75_GROUP(uart3_flow_b), + CV75_GROUP(uart4_a), + CV75_GROUP(uart4_b), + CV75_GROUP(uart4_flow_a), + CV75_GROUP(uart4_flow_b), + /* Flash */ + CV75_GROUP(snand), + CV75_GROUP(spinor), + /* SD/MMC */ + CV75_GROUP(sdmmc0_cd), + CV75_GROUP(sdmmc0_wp), + CV75_GROUP(sdmmc0_reset), + CV75_GROUP(sdmmc0_hs_sel), + CV75_GROUP(sdmmc0_1bit), + CV75_GROUP(sdmmc0_4bit), + CV75_GROUP(sdmmc1_cd), + CV75_GROUP(sdmmc1_wp), + CV75_GROUP(sdmmc1_reset), + CV75_GROUP(sdmmc1_hs_sel), + CV75_GROUP(sdmmc1_1bit), + CV75_GROUP(sdmmc1_4bit), + /* Ethernet */ + CV75_GROUP(enet_ext_osc_clk), + CV75_GROUP(enet_2nd_ref_clk_a), + CV75_GROUP(enet_2nd_ref_clk_b), + CV75_GROUP(enet0_ptp_pps_o), + CV75_GROUP(rgmii0), + CV75_GROUP(rmii0), + /* I2C */ + CV75_GROUP(i2c0_a), + CV75_GROUP(i2c0_b), + CV75_GROUP(i2c1_a), + CV75_GROUP(i2c1_b), + CV75_GROUP(i2c2), + CV75_GROUP(i2c3_a), + CV75_GROUP(i2c3_b), + CV75_GROUP(i2c3_c), + CV75_GROUP(i2cs_a), + CV75_GROUP(i2cs_b), + CV75_GROUP(i2cs_c), + CV75_GROUP(i2cs_d), + /* CAN, IR, WDT */ + CV75_GROUP(can0), + CV75_GROUP(can1), + CV75_GROUP(ir), + CV75_GROUP(wdt_a), + CV75_GROUP(wdt_b), + CV75_GROUP(wdt_c), + CV75_GROUP(wdt_d), + CV75_GROUP(wdt_e), + CV75_GROUP(wdt_f), + /* I2S */ + CV75_GROUP(i2s0), + CV75_GROUP(i2s1), + CV75_GROUP(dmic0), + /* PWM */ + CV75_GROUP(pwm0), + CV75_GROUP(pwm1), + CV75_GROUP(pwm2), + CV75_GROUP(pwm3), + CV75_GROUP(pwm4_a), + CV75_GROUP(pwm4_b), + CV75_GROUP(pwm5_a), + CV75_GROUP(pwm5_b), + CV75_GROUP(pwm6_a), + CV75_GROUP(pwm6_b), + CV75_GROUP(pwm7_a), + CV75_GROUP(pwm7_b), + CV75_GROUP(pwm8_a), + CV75_GROUP(pwm8_b), + CV75_GROUP(pwm9_a), + CV75_GROUP(pwm9_b), + CV75_GROUP(pwm10_a), + CV75_GROUP(pwm10_b), + CV75_GROUP(pwm11_a), + CV75_GROUP(pwm11_b), + /* SPI */ + CV75_GROUP(spi0), + CV75_GROUP(spi1), + CV75_GROUP(spi2), + CV75_GROUP(spi3_a), + CV75_GROUP(spi3_b), + CV75_GROUP(spi3_c), + CV75_GROUP(spi_slave_a), + CV75_GROUP(spi_slave_b), + CV75_GROUP(spi_slave_c), + CV75_GROUP(spi_slave_d), + CV75_GROUP(spi_slave_e), + /* VIN master sync */ + CV75_GROUP(vin_master_sync_a), + CV75_GROUP(vin_master_sync_b), + CV75_GROUP(vin_master_sync_c), + CV75_GROUP(vin_master_sync_d), + CV75_GROUP(vin_master_sync_e), + CV75_GROUP(vsync0), + CV75_GROUP(vsync1), + CV75_GROUP(vsync2), + CV75_GROUP(vsync3), + CV75_GROUP(hsync0), + CV75_GROUP(hsync1), +}; + +static const char * const cv75_uart0_groups[] =3D { + "uart0", +}; + +static const char * const cv75_uart1_groups[] =3D { + "uart1", + "uart1_flow", +}; + +static const char * const cv75_uart2_groups[] =3D { + "uart2_a", + "uart2_b", + "uart2_c", + "uart2_flow_a", + "uart2_flow_b", +}; + +static const char * const cv75_uart3_groups[] =3D { + "uart3_a", + "uart3_b", + "uart3_flow_a", + "uart3_flow_b", +}; + +static const char * const cv75_uart4_groups[] =3D { + "uart4_a", + "uart4_b", + "uart4_flow_a", + "uart4_flow_b", +}; + +static const char * const cv75_snand_groups[] =3D { + "snand", +}; + +static const char * const cv75_spinor_groups[] =3D { + "spinor", +}; + +static const char * const cv75_sdmmc0_groups[] =3D { + "sdmmc0_cd", + "sdmmc0_wp", + "sdmmc0_reset", + "sdmmc0_hs_sel", + "sdmmc0_1bit", + "sdmmc0_4bit", +}; + +static const char * const cv75_sdmmc1_groups[] =3D { + "sdmmc1_cd", + "sdmmc1_wp", + "sdmmc1_reset", + "sdmmc1_hs_sel", + "sdmmc1_1bit", + "sdmmc1_4bit", +}; + +static const char * const cv75_enet0_groups[] =3D { + "enet_ext_osc_clk", + "enet_2nd_ref_clk_a", + "enet_2nd_ref_clk_b", + "enet0_ptp_pps_o", + "rgmii0", + "rmii0", +}; + +static const char * const cv75_i2c0_groups[] =3D { + "i2c0_a", + "i2c0_b", +}; + +static const char * const cv75_i2c1_groups[] =3D { + "i2c1_a", + "i2c1_b", +}; + +static const char * const cv75_i2c2_groups[] =3D { + "i2c2", +}; + +static const char * const cv75_i2c3_groups[] =3D { + "i2c3_a", + "i2c3_b", + "i2c3_c", +}; + +static const char * const cv75_i2cs_groups[] =3D { + "i2cs_a", + "i2cs_b", + "i2cs_c", + "i2cs_d", +}; + +static const char * const cv75_can0_groups[] =3D { + "can0", +}; + +static const char * const cv75_can1_groups[] =3D { + "can1", +}; + +static const char * const cv75_ir_groups[] =3D { + "ir", +}; + +static const char * const cv75_wdt_groups[] =3D { + "wdt_a", + "wdt_b", + "wdt_c", + "wdt_d", + "wdt_e", + "wdt_f", +}; + +static const char * const cv75_i2s0_groups[] =3D { + "i2s0", +}; + +static const char * const cv75_i2s1_groups[] =3D { + "i2s1", +}; + +static const char * const cv75_dmic0_groups[] =3D { + "dmic0", +}; + +static const char * const cv75_pwm0_groups[] =3D { + "pwm0", +}; + +static const char * const cv75_pwm1_groups[] =3D { + "pwm1", +}; + +static const char * const cv75_pwm2_groups[] =3D { + "pwm2", +}; + +static const char * const cv75_pwm3_groups[] =3D { + "pwm3", +}; + +static const char * const cv75_pwm4_groups[] =3D { + "pwm4_a", + "pwm4_b", +}; + +static const char * const cv75_pwm5_groups[] =3D { + "pwm5_a", + "pwm5_b", +}; + +static const char * const cv75_pwm6_groups[] =3D { + "pwm6_a", + "pwm6_b", +}; + +static const char * const cv75_pwm7_groups[] =3D { + "pwm7_a", + "pwm7_b", +}; + +static const char * const cv75_pwm8_groups[] =3D { + "pwm8_a", + "pwm8_b", +}; + +static const char * const cv75_pwm9_groups[] =3D { + "pwm9_a", + "pwm9_b", +}; + +static const char * const cv75_pwm10_groups[] =3D { + "pwm10_a", + "pwm10_b", +}; + +static const char * const cv75_pwm11_groups[] =3D { + "pwm11_a", + "pwm11_b", +}; + +static const char * const cv75_spi0_groups[] =3D { + "spi0", +}; + +static const char * const cv75_spi1_groups[] =3D { + "spi1", +}; + +static const char * const cv75_spi2_groups[] =3D { + "spi2", +}; + +static const char * const cv75_spi3_groups[] =3D { + "spi3_a", + "spi3_b", + "spi3_c", +}; + +static const char * const cv75_spi_slave_groups[] =3D { + "spi_slave_a", + "spi_slave_b", + "spi_slave_c", + "spi_slave_d", + "spi_slave_e", +}; + +static const char * const cv75_vin_master_sync_groups[] =3D { + "vin_master_sync_a", + "vin_master_sync_b", + "vin_master_sync_c", + "vin_master_sync_d", + "vin_master_sync_e", +}; + +static const char * const cv75_vsync0_groups[] =3D { + "vsync0", +}; + +static const char * const cv75_vsync1_groups[] =3D { + "vsync1", +}; + +static const char * const cv75_vsync2_groups[] =3D { + "vsync2", +}; + +static const char * const cv75_vsync3_groups[] =3D { + "vsync3", +}; + +static const char * const cv75_hsync0_groups[] =3D { + "hsync0", +}; + +static const char * const cv75_hsync1_groups[] =3D { + "hsync1", +}; + +static const struct pinfunction cv75_pin_functions[] =3D { + CV75_FUNCTION(uart0), + CV75_FUNCTION(uart1), + CV75_FUNCTION(uart2), + CV75_FUNCTION(uart3), + CV75_FUNCTION(uart4), + CV75_FUNCTION(snand), + CV75_FUNCTION(spinor), + CV75_FUNCTION(sdmmc0), + CV75_FUNCTION(sdmmc1), + CV75_FUNCTION(enet0), + CV75_FUNCTION(i2c0), + CV75_FUNCTION(i2c1), + CV75_FUNCTION(i2c2), + CV75_FUNCTION(i2c3), + CV75_FUNCTION(i2cs), + CV75_FUNCTION(can0), + CV75_FUNCTION(can1), + CV75_FUNCTION(ir), + CV75_FUNCTION(wdt), + CV75_FUNCTION(i2s0), + CV75_FUNCTION(i2s1), + CV75_FUNCTION(dmic0), + CV75_FUNCTION(pwm0), + CV75_FUNCTION(pwm1), + CV75_FUNCTION(pwm2), + CV75_FUNCTION(pwm3), + CV75_FUNCTION(pwm4), + CV75_FUNCTION(pwm5), + CV75_FUNCTION(pwm6), + CV75_FUNCTION(pwm7), + CV75_FUNCTION(pwm8), + CV75_FUNCTION(pwm9), + CV75_FUNCTION(pwm10), + CV75_FUNCTION(pwm11), + CV75_FUNCTION(spi0), + CV75_FUNCTION(spi1), + CV75_FUNCTION(spi2), + CV75_FUNCTION(spi3), + CV75_FUNCTION(spi_slave), + CV75_FUNCTION(vin_master_sync), + CV75_FUNCTION(vsync0), + CV75_FUNCTION(vsync1), + CV75_FUNCTION(vsync2), + CV75_FUNCTION(vsync3), + CV75_FUNCTION(hsync0), + CV75_FUNCTION(hsync1), +}; + +const struct amb_pinctrl_data ambarella_cv75_pinctrl_data =3D { + .groups =3D cv75_pin_groups, + .functions =3D cv75_pin_functions, + .ngroups =3D ARRAY_SIZE(cv75_pin_groups), + .nfunctions =3D ARRAY_SIZE(cv75_pin_functions), + .nr_banks =3D 3, + .npins =3D 96, + .ds0 =3D { + 0x314, 0x320, 0x32c, + }, + .ds1 =3D { + 0x318, 0x324, 0x330, + }, + .ds2 =3D { + 0x31c, 0x328, 0x334, + }, + .pull_en =3D { + 0x60, 0x64, 0x68, + }, + .pull_dir =3D { + 0x7c, 0x80, 0x84, + }, + .have_ds2 =3D true, +}; diff --git a/drivers/pinctrl/pinctrl-ambarella.c b/drivers/pinctrl/pinctrl-= ambarella.c new file mode 100644 index 000000000000..83afef6a123f --- /dev/null +++ b/drivers/pinctrl/pinctrl-ambarella.c @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl driver for Ambarella SoCs + * + * Copyright (C) 2012-2026, Ambarella, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinmux.h" +#include "pinctrl-ambarella.h" + +#define IOMUX_REG(bank, n) (((bank) * 0xc) + ((n) * 4)) +#define IOMUX_CTRL_SET 0xf0 + +#define PINID_TO_BANK(p) ((p) >> 5) +#define PINID_TO_OFFSET(p) ((p) & 0x1f) + +struct amb_pinctrl { + struct pinctrl_desc desc; + void __iomem *iomux_base; + struct regmap *ds_regmap; + struct regmap *pull_regmap; + const struct amb_pinctrl_data *data; + struct device *dev; + struct pinctrl_dev *pctl; + spinlock_t lock; +}; + +static const int amb_ds1_ma[] =3D { 2, 4, 8, 12 }; +static const int amb_ds2_ma[] =3D { 3, 4, 6, 8, 9, 12 }; + +static const struct pinctrl_ops amb_pctrl_ops =3D { + .get_groups_count =3D pinctrl_generic_get_group_count, + .get_group_name =3D pinctrl_generic_get_group_name, + .get_group_pins =3D pinctrl_generic_get_group_pins, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinconf_generic_dt_free_map, +}; + +static void amb_iomux_commit(struct amb_pinctrl *ipc) +{ + writel(0x1, ipc->iomux_base + IOMUX_CTRL_SET); + writel(0x0, ipc->iomux_base + IOMUX_CTRL_SET); +} + +static void amb_pinmux_set_altfunc(struct amb_pinctrl *ipc, u32 bank, + u32 offset, u32 altfunc) +{ + if (bank >=3D ipc->data->nr_banks) + return; + + for (unsigned int i =3D 0; i < 3; i++) { + unsigned long data; + + data =3D readl_relaxed(ipc->iomux_base + IOMUX_REG(bank, i)); + __assign_bit(offset, &data, altfunc & BIT(i)); + writel_relaxed(data, ipc->iomux_base + IOMUX_REG(bank, i)); + } +} + +static int amb_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + struct amb_pinctrl *ipc =3D pinctrl_dev_get_drvdata(pctldev); + struct group_desc *grp; + const u8 *alts; + unsigned long flags; + + (void)selector; + + grp =3D pinctrl_generic_get_group(pctldev, group); + if (!grp || !grp->data) + return -EINVAL; + + alts =3D grp->data; + + spin_lock_irqsave(&ipc->lock, flags); + for (unsigned int i =3D 0; i < grp->grp.npins; i++) { + unsigned int pin =3D grp->grp.pins[i]; + + amb_pinmux_set_altfunc(ipc, PINID_TO_BANK(pin), + PINID_TO_OFFSET(pin), alts[i]); + } + amb_iomux_commit(ipc); + spin_unlock_irqrestore(&ipc->lock, flags); + + return 0; +} + +static int amb_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct amb_pinctrl *ipc =3D pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + + if (!range || !range->gc) + return -EINVAL; + + if (pin >=3D ipc->data->npins) + return -EINVAL; + + spin_lock_irqsave(&ipc->lock, flags); + amb_pinmux_set_altfunc(ipc, PINID_TO_BANK(pin), PINID_TO_OFFSET(pin), 0); + amb_iomux_commit(ipc); + spin_unlock_irqrestore(&ipc->lock, flags); + + return 0; +} + +static const struct pinmux_ops amb_pinmux_ops =3D { + .get_functions_count =3D pinmux_generic_get_function_count, + .get_function_name =3D pinmux_generic_get_function_name, + .get_function_groups =3D pinmux_generic_get_function_groups, + .set_mux =3D amb_pinmux_set_mux, + .gpio_request_enable =3D amb_pinmux_gpio_request_enable, + .strict =3D true, +}; + +static int amb_drive_strength_to_reg_ds1(u32 strength) +{ + for (unsigned int i =3D 0; i < ARRAY_SIZE(amb_ds1_ma); i++) { + if (amb_ds1_ma[i] =3D=3D strength) + return i; + } + + return -EINVAL; +} + +static int amb_drive_strength_to_reg_ds2(u32 strength) +{ + /* Hardware steps are 3, 4, 6, 8, 9, 12 mA; 5 and 7 are accepted aliases = */ + if (strength =3D=3D 5) + strength =3D 4; + else if (strength =3D=3D 7) + strength =3D 8; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(amb_ds2_ma); i++) { + if (amb_ds2_ma[i] =3D=3D strength) + return i; + } + + return -EINVAL; +} + +static int amb_drive_strength_to_reg(const struct amb_pinctrl *ipc, u32 st= rength) +{ + if (ipc->data->have_ds2) + return amb_drive_strength_to_reg_ds2(strength); + + return amb_drive_strength_to_reg_ds1(strength); +} + +static int amb_reg_to_drive_strength(const struct amb_pinctrl *ipc, u32 ds) +{ + if (ipc->data->have_ds2) { + if (ds >=3D ARRAY_SIZE(amb_ds2_ma)) + return -EINVAL; + return amb_ds2_ma[ds]; + } + + if (ds >=3D ARRAY_SIZE(amb_ds1_ma)) + return -EINVAL; + + return amb_ds1_ma[ds]; +} + +static int amb_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct amb_pinctrl *ipc =3D pinctrl_dev_get_drvdata(pctldev); + u32 bank =3D PINID_TO_BANK(pin); + u32 offset =3D PINID_TO_OFFSET(pin); + unsigned int mask =3D BIT(offset); + int ret; + + if (bank >=3D ipc->data->nr_banks) + return -EINVAL; + + for (unsigned int i =3D 0; i < num_configs; i++) { + enum pin_config_param param =3D pinconf_to_config_param(configs[i]); + u32 arg =3D pinconf_to_config_argument(configs[i]); + int ds; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret =3D regmap_assign_bits(ipc->pull_regmap, ipc->data->pull_en[bank], + mask, false); + if (ret) + return ret; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + ret =3D regmap_assign_bits(ipc->pull_regmap, ipc->data->pull_dir[bank], + mask, param =3D=3D PIN_CONFIG_BIAS_PULL_UP); + if (ret) + return ret; + ret =3D regmap_assign_bits(ipc->pull_regmap, ipc->data->pull_en[bank], + mask, true); + if (ret) + return ret; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + ds =3D amb_drive_strength_to_reg(ipc, arg); + if (ds < 0) + return ds; + if (ipc->data->have_ds2) { + ret =3D regmap_assign_bits(ipc->ds_regmap, ipc->data->ds0[bank], + mask, ds & BIT(0)); + if (ret) + return ret; + ret =3D regmap_assign_bits(ipc->ds_regmap, ipc->data->ds1[bank], + mask, ds & BIT(1)); + if (ret) + return ret; + ret =3D regmap_assign_bits(ipc->ds_regmap, ipc->data->ds2[bank], + mask, ds & BIT(2)); + if (ret) + return ret; + } else { + ret =3D regmap_assign_bits(ipc->ds_regmap, ipc->data->ds0[bank], + mask, ds & BIT(1)); + if (ret) + return ret; + ret =3D regmap_assign_bits(ipc->ds_regmap, ipc->data->ds1[bank], + mask, ds & BIT(0)); + if (ret) + return ret; + } + break; + default: + return -ENOTSUPP; + } + } + + return 0; +} + +static int amb_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret =3D pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); + if (ret) + return ret; + + for (unsigned int i =3D 0; i < npins; i++) { + ret =3D amb_pinconf_set(pctldev, pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static int amb_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct amb_pinctrl *ipc =3D pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param =3D pinconf_to_config_param(*config); + u32 bank =3D PINID_TO_BANK(pin); + u32 offset =3D PINID_TO_OFFSET(pin); + u32 pull_en, pull_dir, ds0, ds1, ds2, ds; + bool en, dir, b0, b1, b2; + int ret, strength; + + if (bank >=3D ipc->data->nr_banks) + return -EINVAL; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + ret =3D regmap_read(ipc->pull_regmap, ipc->data->pull_en[bank], + &pull_en); + if (ret) + return ret; + + ret =3D regmap_read(ipc->pull_regmap, ipc->data->pull_dir[bank], + &pull_dir); + if (ret) + return ret; + + en =3D !!(pull_en & BIT(offset)); + dir =3D !!(pull_dir & BIT(offset)); + + if (param =3D=3D PIN_CONFIG_BIAS_DISABLE) { + if (en) + return -EINVAL; + *config =3D pinconf_to_config_packed(param, 0); + return 0; + } + + if (!en) + return -EINVAL; + if (param =3D=3D PIN_CONFIG_BIAS_PULL_UP && !dir) + return -EINVAL; + if (param =3D=3D PIN_CONFIG_BIAS_PULL_DOWN && dir) + return -EINVAL; + + *config =3D pinconf_to_config_packed(param, 1); + return 0; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret =3D regmap_read(ipc->ds_regmap, ipc->data->ds0[bank], &ds0); + if (ret) + return ret; + + ret =3D regmap_read(ipc->ds_regmap, ipc->data->ds1[bank], &ds1); + if (ret) + return ret; + + b0 =3D !!(ds0 & BIT(offset)); + b1 =3D !!(ds1 & BIT(offset)); + if (ipc->data->have_ds2) { + ret =3D regmap_read(ipc->ds_regmap, ipc->data->ds2[bank], + &ds2); + if (ret) + return ret; + + b2 =3D !!(ds2 & BIT(offset)); + ds =3D (b2 << 2) | (b1 << 1) | b0; + } else { + ds =3D (b0 << 1) | b1; + } + + strength =3D amb_reg_to_drive_strength(ipc, ds); + if (strength < 0) + return strength; + + *config =3D pinconf_to_config_packed(param, strength); + return 0; + + default: + return -ENOTSUPP; + } +} + +static const struct pinconf_ops amb_pinconf_ops =3D { + .is_generic =3D true, + .pin_config_get =3D amb_pinconf_get, + .pin_config_set =3D amb_pinconf_set, + .pin_config_group_set =3D amb_pinconf_group_set, +}; + +static int amb_pinctrl_add_groups(struct amb_pinctrl *ipc) +{ + const struct amb_pinctrl_data *data =3D ipc->data; + + for (unsigned int i =3D 0; i < data->ngroups; i++) { + const struct amb_pinmux_group *g =3D &data->groups[i]; + int ret; + + if (!g->grp || !g->grp->name || !g->grp->pins || + !g->grp->npins || !g->alts) + return -EINVAL; + + for (unsigned int j =3D 0; j < g->grp->npins; j++) { + if (g->grp->pins[j] >=3D data->npins) + return -EINVAL; + } + + ret =3D pinctrl_generic_add_group(ipc->pctl, g->grp->name, + g->grp->pins, g->grp->npins, + (void *)g->alts); + if (ret < 0) + return ret; + } + + return 0; +} + +static int amb_pinctrl_add_functions(struct amb_pinctrl *ipc) +{ + const struct amb_pinctrl_data *data =3D ipc->data; + + for (unsigned int i =3D 0; i < data->nfunctions; i++) { + int ret; + + ret =3D pinmux_generic_add_pinfunction(ipc->pctl, + &data->functions[i], NULL); + if (ret < 0) + return ret; + } + + return 0; +} + +static int amb_pinctrl_register(struct amb_pinctrl *ipc) +{ + struct pinctrl_pin_desc *pindesc; + char **names; + int ret; + + pindesc =3D devm_kcalloc(ipc->dev, ipc->data->npins, sizeof(*pindesc), + GFP_KERNEL); + if (!pindesc) + return -ENOMEM; + + names =3D devm_kasprintf_strarray(ipc->dev, "io", ipc->data->npins); + if (!names) + return -ENOMEM; + + for (unsigned int pin =3D 0; pin < ipc->data->npins; pin++) { + pindesc[pin].number =3D pin; + pindesc[pin].name =3D names[pin]; + } + + ipc->desc.name =3D dev_name(ipc->dev); + ipc->desc.pins =3D pindesc; + ipc->desc.npins =3D ipc->data->npins; + ipc->desc.pctlops =3D &amb_pctrl_ops; + ipc->desc.pmxops =3D &amb_pinmux_ops; + ipc->desc.confops =3D &amb_pinconf_ops; + ipc->desc.owner =3D THIS_MODULE; + + ret =3D devm_pinctrl_register_and_init(ipc->dev, &ipc->desc, ipc, &ipc->p= ctl); + if (ret) + return ret; + + ret =3D amb_pinctrl_add_groups(ipc); + if (ret) + return ret; + + ret =3D amb_pinctrl_add_functions(ipc); + if (ret) + return ret; + + return pinctrl_enable(ipc->pctl); +} + +static int amb_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct amb_pinctrl *ipc; + int ret; + + ipc =3D devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL); + if (!ipc) + return -ENOMEM; + + ipc->dev =3D dev; + ipc->data =3D device_get_match_data(dev); + if (!ipc->data) + return dev_err_probe(dev, -ENODATA, "missing SoC data\n"); + + if (!ipc->data->nr_banks || ipc->data->nr_banks > AMBA_MAX_BANKS || + !ipc->data->npins || + !ipc->data->groups || !ipc->data->ngroups || + !ipc->data->functions || !ipc->data->nfunctions) + return dev_err_probe(dev, -EINVAL, "invalid SoC data\n"); + + ipc->iomux_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ipc->iomux_base)) + return PTR_ERR(ipc->iomux_base); + + ipc->ds_regmap =3D syscon_regmap_lookup_by_phandle(dev_of_node(dev), + "ambarella,drive-strength-syscon"); + if (IS_ERR(ipc->ds_regmap)) + return dev_err_probe(dev, PTR_ERR(ipc->ds_regmap), + "missing drive-strength syscon\n"); + + ipc->pull_regmap =3D syscon_regmap_lookup_by_phandle(dev_of_node(dev), + "ambarella,pull-syscon"); + if (IS_ERR(ipc->pull_regmap)) + return dev_err_probe(dev, PTR_ERR(ipc->pull_regmap), + "missing pull syscon\n"); + + spin_lock_init(&ipc->lock); + + ret =3D amb_pinctrl_register(ipc); + if (ret) + return dev_err_probe(dev, ret, "failed to register pinctrl\n"); + + platform_set_drvdata(pdev, ipc); + + return 0; +} + +static const struct of_device_id amb_pinctrl_dt_match[] =3D { + { + .compatible =3D "ambarella,cv75-pinctrl", + .data =3D &ambarella_cv75_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, amb_pinctrl_dt_match); + +static struct platform_driver amb_pinctrl_driver =3D { + .probe =3D amb_pinctrl_probe, + .driver =3D { + .name =3D "ambarella-pinctrl", + .of_match_table =3D amb_pinctrl_dt_match, + }, +}; + +static int __init amb_pinctrl_drv_register(void) +{ + return platform_driver_register(&amb_pinctrl_driver); +} +arch_initcall(amb_pinctrl_drv_register); + +MODULE_AUTHOR("Cao Rongrong "); +MODULE_DESCRIPTION("Ambarella SoC pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-ambarella.h b/drivers/pinctrl/pinctrl-= ambarella.h new file mode 100644 index 000000000000..37e9c420662c --- /dev/null +++ b/drivers/pinctrl/pinctrl-ambarella.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Ambarella pinctrl SoC data + * + * Copyright (C) 2012-2026, Ambarella, Inc. + */ + +#ifndef _PINCTRL_AMBARELLA_H +#define _PINCTRL_AMBARELLA_H + +#include + +#define AMBA_MAX_BANKS 8 + +struct pingroup; +struct pinfunction; + +struct amb_pinmux_group { + const struct pingroup *grp; + const u8 *alts; +}; + +struct amb_pinctrl_data { + const struct amb_pinmux_group *groups; + const struct pinfunction *functions; + unsigned int ngroups; + unsigned int nfunctions; + unsigned int nr_banks; + unsigned int npins; + unsigned int ds0[AMBA_MAX_BANKS]; + unsigned int ds1[AMBA_MAX_BANKS]; + unsigned int ds2[AMBA_MAX_BANKS]; + unsigned int pull_en[AMBA_MAX_BANKS]; + unsigned int pull_dir[AMBA_MAX_BANKS]; + bool have_ds2; +}; + +extern const struct amb_pinctrl_data ambarella_cv75_pinctrl_data; + +#endif /* _PINCTRL_AMBARELLA_H */ --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65490356771; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964614; cv=none; b=gWlO6FkMx8ucR+Z0tBzv2oRXiX21LxwgI7+sUhXRRMG86Bm6lcibWG4gDJ3oaBgKssLC6YFIyVhbZeur1oHO2sGL/Ja3jHcBEa+hIlIAx0NFbBRibOdffNHZ6uwlNRh8qIjW4yxrQRO6Rk7EpB6FyWc9HOoIchK1qHMWPeRVZwA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964614; c=relaxed/simple; bh=5GFqfQIbCg2UdEeRrw8f0OXijIQlOGnsXzu/vsVQh9g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Q4X3Pwz6H/sKajy/oRmBUc3SNDdPS5wjwl8yo61uodDNDdOlyPH0G80xWbuyKF1OmRWe3qa3OXCKvP/imXyuuzHVBUMJZ4jftsR5gpox1csdMTe2D0OiTl+5m42ENFKApdJHDHYG1eAiMYR9RHVYsZgvpDXUexkbzhjvaBa3ozs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Qg3xOG4G; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Qg3xOG4G" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3D4DDC4AF17; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964614; bh=5GFqfQIbCg2UdEeRrw8f0OXijIQlOGnsXzu/vsVQh9g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Qg3xOG4GIlp+dgIbRZOPp8I8kSys9o/MQieZT4I5M+5szZPFrO2LbyX6vGEbfuxS3 vxhL2zlh847Kfy78UH49eGIjMjLbdUwgRIBXRZpqLGBr/Gb7DGaARrIOxb5KpBYiFb BcRsabuyWMF4Q+lW1Rl2ctgyuJoczrEJSOHHJ4wOIGV+FM4XK99qkZF6AhF+9md5tn RpWS2CZQcwXykkE96QYk0XmaMzI1y9/ADPjUaY+ziIzmIbW07+D3yG5EYp3ZzOzjmo HofdHMHy7c3iyiax2ZxvxZcGzCYyy1I/aAFLSgWzPYPndSUpurfsGUNiQhkIXHPcz2 t7N2rMgz32dTA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2846BC982DA; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:35 +0800 Subject: [PATCH v8 16/18] serial: 8250_dw: add Ambarella CV75 quirks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-16-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964608; l=3394; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=r8t/FG9wW+i95rGWMVag4aWVspLRurIpWPfr+INLVog=; b=CQ2ycm49wgwpbFs89pTVhnJ24beBELoj5OXJpDsx5OH+Ig/6p77MRYZrAY3GJ4puVhb/THLb2 FP2iDhCh2g/DvqUvGKnCKtsf2nPlYqUgrr0prxJvY/gltzsRI1pGItU X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao The Ambarella CV75 UART is Ambarella IP, not a Synopsys DesignWare licensed block. At the register level it is close enough to DW APB UART that a full custom UART driver is unnecessary: reuse 8250_dw with a small platform quirk. Quirks: - keep IER ETOI (bit 5) set for RX timeout behaviour - skip set_rate; baud clock is managed outside the UART block Reviewed-by: Linus Walleij Reviewed-by: Andy Shevchenko Reviewed-by: Ilpo J=C3=A4rvinen Signed-off-by: Long Zhao --- drivers/tty/serial/8250/8250_dw.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/82= 50_dw.c index 5fba913f3301..06f03e893346 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -43,6 +43,9 @@ #define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1) #define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3) =20 +/* Ambarella IER: receive timeout interrupt enable */ +#define AMBARELLA_UART_IER_ETOI BIT(5) + /* Quirks */ #define DW_UART_QUIRK_OCTEON BIT(0) #define DW_UART_QUIRK_ARMADA_38X BIT(1) @@ -60,6 +63,7 @@ =20 struct dw8250_platform_data { u8 usr_reg; + u8 ier_mask; u32 cpr_value; unsigned int quirks; }; @@ -572,6 +576,25 @@ static void dw8250_prepare_rx_dma(struct uart_8250_por= t *p) dw8250_writel_ext(up, RZN1_UART_RDMACR, val); } =20 +static int dw8250_ier_mask_startup(struct uart_port *p) +{ + struct dw8250_data *d =3D to_dw8250_data(p->private_data); + struct uart_8250_port *up =3D up_to_u8250p(p); + int ret; + + ret =3D serial8250_do_startup(p); + if (ret) + return ret; + + /* + * Ambarella keeps variant IER bits (e.g. ETOI) set for correct RX + * timeout behaviour. + */ + up->ier |=3D d->pdata->ier_mask; + + return 0; +} + static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) { unsigned int quirks =3D data->pdata->quirks; @@ -606,6 +629,8 @@ static void dw8250_quirks(struct uart_port *p, struct d= w8250_data *data) p->serial_in =3D dw8250_serial_in32; data->uart_16550_compatible =3D true; } + if (data->pdata->ier_mask) + p->startup =3D dw8250_ier_mask_startup; } =20 static void dw8250_reset_control_assert(void *data) @@ -879,6 +904,12 @@ static const struct dw8250_platform_data dw8250_intc10= ee =3D { .quirks =3D DW_UART_QUIRK_IER_KICK, }; =20 +static const struct dw8250_platform_data dw8250_ambarella_cv75_data =3D { + .usr_reg =3D DW_UART_USR, + .ier_mask =3D AMBARELLA_UART_IER_ETOI, + .quirks =3D DW_UART_QUIRK_SKIP_SET_RATE, +}; + static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data =3D { .usr_reg =3D DW_UART_USR, .cpr_value =3D FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | @@ -890,6 +921,7 @@ static const struct dw8250_platform_data dw8250_ultrari= sc_dp1000_data =3D { =20 static const struct of_device_id dw8250_of_match[] =3D { { .compatible =3D "snps,dw-apb-uart", .data =3D &dw8250_dw_apb }, + { .compatible =3D "ambarella,cv75-uart", .data =3D &dw8250_ambarella_cv75= _data }, { .compatible =3D "cavium,octeon-3860-uart", .data =3D &dw8250_octeon_386= 0_data }, { .compatible =3D "marvell,armada-38x-uart", .data =3D &dw8250_armada_38x= _data }, { .compatible =3D "renesas,rzn1-uart", .data =3D &dw8250_renesas_rzn1_dat= a }, --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 958A8370AF5; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964614; cv=none; b=U4BYTljygIoi+7m2OgkQclyQxvGDexDMY+EY6RI9sdC2FWJLNbgqtpDm7ROMwT2flawZtMJR0Dg3dmg73pMS6Cheye3i4gXUJaAOzXxVTISplgoJ1lA5mDyw3DGCzwPnf6urglYueTGyXH8t2ggeJ01vSKCqDFmtz9Af/C0FxfE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964614; c=relaxed/simple; bh=+gPK4YaQ6wkQB/Gz2SEXT2tTE6dm0Abvvb1HwTdmHE8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AAdOBXKj5RS0dV+iF6yblrshS+cW0hjyZLhu7M6ZMYdQcye6v8p9HeKck+kNHIF63E/haWSYf0LRIbX7kyY6inHYmpWaD3OC2+DD+h1KQSoxjQb11X8dZ6dXwr26SAJ+7VZibndkIft/I3tLklIBMQvXuXUPq0YAntA+tl4u8M0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Bp6Jp7VO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Bp6Jp7VO" Received: by smtp.kernel.org (Postfix) with ESMTPS id 63E0FC2BCF7; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964614; bh=+gPK4YaQ6wkQB/Gz2SEXT2tTE6dm0Abvvb1HwTdmHE8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Bp6Jp7VOscJs3WC+7vImiwMwQgSQZgR+S36XmJ/ibfr4aAM9v22M26dWxBNjjEa91 FrsOWs+HTMQ3EKFQX3LuHdeu5VovL2UEK3YFY/07ZHklOaXZIpuW2e7ndvsrJzMEVZ 5JLjSqT3JH6XTABjZ1jxGULf/CR80vA/03lxohzjCpAcmw/QsQTpHHq94l1brodv6E CRCy/nl9LXz9bWW1bXaBL0wOFlWwILjFx+hcNHbSV2goTz2LAI8a0qfX7zhSBmWF4r /rvq7iGdCH62l9GVIUzED0Z4A6e6wmYrCo5L79Wzc0ZqLWxOjaA1R0Mnxw0CwzLw+T nmZjJAaSDZCOQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F60EC982F5; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:36 +0800 Subject: [PATCH v8 17/18] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-17-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964609; l=8107; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=DEAMc2vofaBUV896UxD87q9HiCotMrVdpC7L4SePgqQ=; b=pgJPV8YKnl4S63GOtoFvs0K6x7bXYd2qLBa0AUfE6vF4lsLH0VydCPZImuD97sLaqua+Bll3v +n/8DUgWdtBCku7se5JF5ZfX13PgzzEcSU2AsNHT6cbUhZNTW6LXO+k X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Enable ARCH_AMBARELLA and add a minimal CV75 SoC / EVK device tree for console bring-up with the RCT clocks, UART, pinctrl and GPIO banks. Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/ambarella/Makefile | 3 + arch/arm64/boot/dts/ambarella/cv75-evk.dts | 30 +++++ arch/arm64/boot/dts/ambarella/cv75.dtsi | 177 +++++++++++++++++++++++++= ++++ arch/arm64/configs/defconfig | 1 + 6 files changed, 218 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index d2acfac73003..16d7e3a4c2d6 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -26,6 +26,12 @@ config ARCH_SUNXI help This enables support for Allwinner sunxi based SoCs like the A64. =20 +config ARCH_AMBARELLA + bool "Ambarella SoC family" + select PINCTRL + help + This enables support for the ARM64 based Ambarella SoCs like CV75. + config ARCH_ALPINE bool "Annapurna Labs Alpine platform" select ALPINE_MSI if PCI diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index fc726b215f12..f1709eb5d915 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y +=3D airoha subdir-y +=3D allwinner subdir-y +=3D altera subdir-y +=3D amazon +subdir-y +=3D ambarella subdir-y +=3D amd subdir-y +=3D amlogic subdir-y +=3D apm diff --git a/arch/arm64/boot/dts/ambarella/Makefile b/arch/arm64/boot/dts/a= mbarella/Makefile new file mode 100644 index 000000000000..ddca3d7b18cc --- /dev/null +++ b/arch/arm64/boot/dts/ambarella/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_AMBARELLA) +=3D cv75-evk.dtb diff --git a/arch/arm64/boot/dts/ambarella/cv75-evk.dts b/arch/arm64/boot/d= ts/ambarella/cv75-evk.dts new file mode 100644 index 000000000000..42a0fe24b83b --- /dev/null +++ b/arch/arm64/boot/dts/ambarella/cv75-evk.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ambarella CV75 EVK board + */ + +/dts-v1/; + +#include "cv75.dtsi" + +/ { + model =3D "Ambarella CV75 EVK Board"; + compatible =3D "ambarella,cv75-evk", "ambarella,cv75"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D &uart0; + }; + + memory@200000 { + device_type =3D "memory"; + reg =3D <0x0 0x00200000 0x0 0x07e00000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ambarella/cv75.dtsi b/arch/arm64/boot/dts/= ambarella/cv75.dtsi new file mode 100644 index 000000000000..c36b6af48237 --- /dev/null +++ b/arch/arm64/boot/dts/ambarella/cv75.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ambarella CV75 SoC + * + * Boot peripheral: UART0 console. + * Clocks: a single ambarella,cv75-rct provider. + */ + +#include +#include + +/ { + compatible =3D "ambarella,cv75"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a76"; + device_type =3D "cpu"; + reg =3D <0x000>; + enable-method =3D "psci"; + }; + + cpu@1 { + compatible =3D "arm,cortex-a76"; + device_type =3D "cpu"; + reg =3D <0x100>; + enable-method =3D "psci"; + }; + }; + + osc: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "osc"; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ahb@ffe0000000 { + compatible =3D "simple-bus"; + reg =3D <0xff 0xe0000000 0x0 0x01000000>; + ranges =3D <0xe0000000 0xff 0xe0000000 0x01000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + s_scratchpad_syscon: scratchpad@e002e000 { + compatible =3D "ambarella,cv75-sec-scratchpad", "syscon"; + reg =3D <0xe002e000 0x1000>; + }; + }; + + apb@ffe4000000 { + compatible =3D "simple-bus"; + reg =3D <0xff 0xe4000000 0x0 0x01000000>; + ranges =3D <0xe4000000 0xff 0xe4000000 0x01000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + uart0: serial@e4000000 { + compatible =3D "ambarella,cv75-uart", "snps,dw-apb-uart"; + reg =3D <0xe4000000 0x1000>; + clocks =3D <&rct CV75_GCLK_UART0>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; + + status =3D "disabled"; + }; + + pinctrl: pinctrl@e4010000 { + compatible =3D "ambarella,cv75-pinctrl"; + reg =3D <0xe4010000 0x1000>; + ambarella,drive-strength-syscon =3D <&rct>; + ambarella,pull-syscon =3D <&s_scratchpad_syscon>; + + uart0_pins: uart0-pins { + function =3D "uart0"; + groups =3D "uart0"; + }; + }; + + gpio0: gpio@e4013000 { + compatible =3D "ambarella,cv75-gpio", "arm,primecell"; + reg =3D <0xe4013000 0x1000>; + clocks =3D <&rct CV75_GCLK_APB>; + clock-names =3D "apb_pclk"; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + arm,primecell-periphid =3D <0x000e8061>; + }; + + gpio1: gpio@e4014000 { + compatible =3D "ambarella,cv75-gpio", "arm,primecell"; + reg =3D <0xe4014000 0x1000>; + clocks =3D <&rct CV75_GCLK_APB>; + clock-names =3D "apb_pclk"; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + arm,primecell-periphid =3D <0x000e8061>; + }; + + gpio2: gpio@e4015000 { + compatible =3D "ambarella,cv75-gpio", "arm,primecell"; + reg =3D <0xe4015000 0x1000>; + clocks =3D <&rct CV75_GCLK_APB>; + clock-names =3D "apb_pclk"; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + arm,primecell-periphid =3D <0x000e8061>; + }; + }; + + rct: clock-controller@ffed080000 { + compatible =3D "ambarella,cv75-rct", "syscon"; + reg =3D <0xff 0xed080000 0x0 0x1000>; + clocks =3D <&osc>; + clock-names =3D "osc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + assigned-clocks =3D <&rct CV75_GCLK_UART0>; + assigned-clock-parents =3D <&osc>; + assigned-clock-rates =3D <24000000>; + }; + + gic: interrupt-controller@fff0101000 { + compatible =3D "arm,gic-400"; + reg =3D <0xff 0xf0101000 0x0 0x1000>, + <0xff 0xf0102000 0x0 0x2000>, + <0xff 0xf0104000 0x0 0x2000>, + <0xff 0xf0106000 0x0 0x2000>; + interrupt-controller; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; +}; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index ad3bd3d9507b..454f07a6a6a6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -36,6 +36,7 @@ CONFIG_CRASH_DUMP=3Dy CONFIG_ARCH_ACTIONS=3Dy CONFIG_ARCH_AIROHA=3Dy CONFIG_ARCH_SUNXI=3Dy +CONFIG_ARCH_AMBARELLA=3Dy CONFIG_ARCH_ALPINE=3Dy CONFIG_ARCH_APPLE=3Dy CONFIG_ARCH_ARTPEC=3Dy --=20 2.34.1 From nobody Thu Sep 24 20:03:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2AAF372EDE; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964614; cv=none; b=Jk0/KwkJlMFEzkha2C9g0VmOm3nYehPGXObLZwh4/eUys2TlBLBewrmruKeJ3rJDZ/VNOfUFCJsC/gQiW64351X9n8tMiI/VmU5f2pEeZm8E8rA+648Jainu25i9Ai7OyGUvXctvqjQqIQ/uQxNeBjPabpaF3LG/MVkrc9Pnhe4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789964614; c=relaxed/simple; bh=zgU3iQM72YbxnsGmykO32NltLNkwhLgTNSOphGXHrLE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BRJQ3aU5g8VuyeCAkyKqRuLDVwpzcImcOHp1VjZz182FMR4rauJOUUlZMb6Pn6G6rEIEXogGR82bjqJ2GJhQf5r6Smo3iuozQvRDrj9PgdIoRE+dXd+0CuduVqcyHIfOyE5Q7+l3ENylJmzd34XgExM7x2HMhb+B6RU3IKlCMxc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ERU9SdEM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ERU9SdEM" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9D0D8C2BD00; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789964614; bh=zgU3iQM72YbxnsGmykO32NltLNkwhLgTNSOphGXHrLE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ERU9SdEMeMctXWCW8214q8AQqnELC5pAedsn65NzsyUxEAqpZinG23NZeobCS/IzK Pu+CneDjxSCDr5xuwaKVFnyBv1aSZGrRqgP9FrPw9ZZCJHwsd5AE1mXTcHaBDZZDeY kgYecPX0BNQjKCcXzi8r+S0IbzTAVukfN7alUsH7Q3kBJFn5zFGIb0NGRyK6OBe1T3 O2s+FUNjpRoaTHRNehx+HqEcg5wnkA2MRWiUIhD2dabD9G2hRzz3DLqghkZRoGCi01 vx2WFB1zBCTrmM83AZCHX25k61qfHm2GL7LlWL/ZyfKups8fyXv3BuFQLUoyd4bQEf VWnRZgS0YFPlg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B5D2C982F1; Mon, 21 Sep 2026 04:23:34 +0000 (UTC) From: Long Zhao via B4 Relay Date: Mon, 21 Sep 2026 12:23:37 +0800 Subject: [PATCH v8 18/18] MAINTAINERS: add ARM/AMBARELLA SoC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-cv75-v5-v8-18-282ff5d98dda@ambarella.com> References: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789964609; l=1241; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=66/FpPmSuU75AtQewU8cj7mu+Qa/5qamx4Km8ySoeYo=; b=ZcB9Kw+0TS4NBh047YvqdlTucwksnHv6Jzs2vgmfTu+GGoB4zAkT3OgmRRaYANUW/Dvz7eMeK Z1K7boRmfs3DJVX054GrV5aiJrcQfiKsyKmk9I1NNu/oWYOSHaCDjXM X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add a maintainer entry covering Ambarella CV75 bindings, DTS and related drivers. Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- MAINTAINERS | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 803b60ad628f..59e5b32d7a02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2502,6 +2502,20 @@ F: drivers/clocksource/asm9260_timer.c F: drivers/rtc/rtc-asm9260.c F: drivers/watchdog/asm9260_wdt.c =20 +ARM/AMBARELLA SOC SUPPORT +M: Long Zhao +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: devicetree@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/arm/ambarella.yaml +F: Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml +F: Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml +F: arch/arm64/boot/dts/ambarella/ +F: drivers/clk/ambarella/ +F: drivers/pinctrl/pinctrl-ambarella* +F: include/dt-bindings/clock/ambarella,cv75-rct.h +N: ambarella + ARM/AMD PENSANDO ARM64 ARCHITECTURE M: Brad Larson L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.34.1