From nobody Thu Sep 24 17:55:41 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFE31503BFA; Mon, 21 Sep 2026 21:15:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790025310; cv=none; b=lfrh8rLih3NcfeobLJCEJdKSmoJycgSWfseip2HCcX/15+QV84s9qrs67WxzAJWuHzGbW+atbdO9XLIPrDYg977z8jSjLX+ExKbBr+9LZFwVAPHALAl2UkxpdiJq65AyaZmueqJATcBj2cl3yUn3cLdfdJj1QuS6Jn54nRObcfU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790025310; c=relaxed/simple; bh=+lY5BeFcwV5FB838TAcxY9ito2AIXwIBAsYU2ILeoMs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bEoBMU42jg2KLhfA2xenCHw6pWPmeYkjHs107fsodA96Amdes07GJVEcO5d79WvWAZCNiPIv0NCvTZGwIQGBzFw0e6zqly7WnYCFWldc6p4sd0+rFf/gXn0CDZ+HUP4DdoNW5iKabO3q7IPRFS9/hfz7FCetu0/VZTPVv5dOmzQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=mKqIvTJ/; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="mKqIvTJ/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1790025306; bh=+lY5BeFcwV5FB838TAcxY9ito2AIXwIBAsYU2ILeoMs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=mKqIvTJ/sugvQXhTC8/kxB6CBZ5I5cDM25m2Bf2hrBH7gmu4eFyohrMCaNGvDvLcB cWhSMHTSQ1UPOVKyun6a0jj3+vxSdrvAEjZjyyjbLjuXVq/Xxb+BsLT4T9gi990zZs 6fG6umLpV1VsTfCSs7P79z/CYAJhArU3CJfJgEydqOnfCU8G4B1x7cvBfVXau9KzRn 91jHb6O6OHlRU+f2w9C1npyg6A5Q14J33KdpYMnxtAiBVYmi5jCVUurs8nanm/vTya Uy0lIxnDaKlcoLsLgMZpqN9UXbd7n+j8sURCbuPaulLFqS1XFvD40Cxdk2WA7qcbOs OYkTIL1XO6i1g== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9715617E09ED; Mon, 21 Sep 2026 23:15:06 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 52352480029; Mon, 21 Sep 2026 23:15:06 +0200 (CEST) From: Sebastian Reichel Date: Mon, 21 Sep 2026 23:15:03 +0200 Subject: [PATCH v2 1/7] dt-bindings: clock: rk3576: add more DFI clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-b4-rockchip-dfi-rk3576-support-v2-1-04f847016321@collabora.com> References: <20260921-b4-rockchip-dfi-rk3576-support-v2-0-04f847016321@collabora.com> In-Reply-To: <20260921-b4-rockchip-dfi-rk3576-support-v2-0-04f847016321@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Sascha Hauer Cc: Nicolas Frattaroli , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=888; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=JMwGtADsjoZugYy5kca2WIyyIS8H1fB5ycX9ZpgOJ8Y=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqxnloifqvy9AhQN26uetADWeyOqzmmP2Wct u4nYUBzLv1Iq4kCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqsZ5aAAoJENju1/PI O/qazIYP/R/VOsf7acYrt4KZ3ThXy8nO6Fl2wJznbO6viavpiKYsJWM/oDs2U9sgE6ZbgqVB9XG HDwSvtCrc3LwjThSoLBTBqbsSzaEztULRi88blqHTes/kbDQc1NAY4AILwIPH2V15i8dS9PDH5m Q5TgWrop00jdkqaDFBkIJ7wmWTx+FTtjpVWdKyp5c4XO/Oxy0jyilRljKaG/lGGTGgBmx7MxmaK oe70ovVfVBwWSq38OTsAkT/2+GGdaKRc4NzVmRgEjd8+Slifk4bZHbf90NmsC77iNdMdD/6PJr1 GfRc/X/qSFxGpgFaGFdjo7kXK131hdBulYrpEy90jGNBhOEPbpQftnnjFTPAlIMZ9klZ3ze0Uhd 01oOLNPTnfvE/eUxzTaqwGx4Z/raKo14qfhRnXrjX6QVXg27SR9/5OSOkffhffVG98iOXvbtemF fFqLqHt2ZiXi86sbdMrlgbOGbXv7DItWrRIDx8TVNk6r6KZtV2v5Y3K6F4nYEval46wS9oDcaqF d9PNxJYNuRPjTA3DSL+oxwbNRCcGpDW7uZu26wsFYe89+/V7CINujP3ogdWd7uzSgKk/eM5jFwb y9oVj8GmRG8NX15OdfDKfWcuaPeMs7I8Z4k9R6O7e6Xbh0sU/iPrupEvVElrd36BlnrzwJ/72h6 9bXVwvvM6UbazdkMwOBkwuQ== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli When the RK3576 CRU DT binding got upstreamed, some DFI clocks were missed. Add identifiers for them. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- include/dt-bindings/clock/rockchip,rk3576-cru.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-b= indings/clock/rockchip,rk3576-cru.h index ded5ce42e62a..c5b74f2d8926 100644 --- a/include/dt-bindings/clock/rockchip,rk3576-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h @@ -604,4 +604,10 @@ #define CLK_FSPI0_TO_IO 576 #define CLK_FSPI1_TO_IO 577 =20 +/* Clocks that were missed initially */ +#define PCLK_DDR_MON_CH1 578 +#define TMCLK_DDR_MON_CH1 579 +#define CLK_DFI_CH0 580 +#define CLK_DFI_CH1 581 + #endif --=20 2.53.0 From nobody Thu Sep 24 17:55:41 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D01F050B429; Mon, 21 Sep 2026 21:15:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 21 Sep 2026 23:15:06 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 53CC148002F; Mon, 21 Sep 2026 23:15:06 +0200 (CEST) From: Sebastian Reichel Date: Mon, 21 Sep 2026 23:15:04 +0200 Subject: [PATCH v2 2/7] clk: rockchip: rk3576: add missing DFI clock branch Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260921-b4-rockchip-dfi-rk3576-support-v2-2-04f847016321@collabora.com> References: <20260921-b4-rockchip-dfi-rk3576-support-v2-0-04f847016321@collabora.com> In-Reply-To: <20260921-b4-rockchip-dfi-rk3576-support-v2-0-04f847016321@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Sascha Hauer Cc: Nicolas Frattaroli , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli RK3576 DFI has one pclk for each channel's monitor. However, mainline's clock tree does not model this second DDRMON PCLK gate, and got away with it so far because they both default to ungated and there is no upstream RK3576 DFI driver. Add a clock gate branch for it, and remove the CLK_IGNORE_UNUSED flag from its sibling. In opposite to RK3588 we can add a mandatory requirement for a clock reference to the RK3576 DFI DT binding. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- drivers/clk/rockchip/clk-rk3576.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-r= k3576.c index 2cdd667f4004..0c94e9db81c1 100644 --- a/drivers/clk/rockchip/clk-rk3576.c +++ b/drivers/clk/rockchip/clk-rk3576.c @@ -883,8 +883,10 @@ static struct rockchip_clk_branch rk3576_clk_branches[= ] __initdata =3D { COMPOSITE(PCLK_DDR_ROOT, "pclk_ddr_root", gpll_cpll_24m_p, CLK_IS_CRITICA= L, RK3576_CLKSEL_CON(76), 5, 2, MFLAGS, 0, 5, DFLAGS, RK3576_CLKGATE_CON(21), 0, GFLAGS), - GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", CLK_IGNORE_UN= USED, + GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", 0, RK3576_CLKGATE_CON(21), 1, GFLAGS), + GATE(PCLK_DDR_MON_CH1, "pclk_ddr_mon_ch1", "pclk_ddr_root", 0, + RK3576_CLKGATE_CON(21), 14, GFLAGS), COMPOSITE(HCLK_DDR_ROOT, "hclk_ddr_root", gpll_cpll_p, CLK_IGNORE_UNUSED, RK3576_CLKSEL_CON(77), 5, 1, MFLAGS, 0, 5, DFLAGS, RK3576_CLKGATE_CON(22), 11, GFLAGS), --=20 2.53.0 From nobody Thu Sep 24 17:55:41 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D00CD50AC1D; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli The RK3576 has DFI hardware for monitoring the DDR's bandwidth much like other rockchip SoCs do. Unlike the RK3588 however, it only has two memory channels, so only two per-channel pclks for DFI. Add a compatible for this SoC's variant, and add it to the conditionals at the bottom of the bindings file. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- .../bindings/devfreq/event/rockchip,dfi.yaml | 19 +++++++++++++++= ++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.y= aml b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml index 3450e28b4020..dcf3bbde3e8d 100644 --- a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml @@ -14,6 +14,7 @@ properties: enum: - rockchip,rk3399-dfi - rockchip,rk3568-dfi + - rockchip,rk3576-dfi - rockchip,rk3588-dfi =20 clocks: @@ -64,6 +65,24 @@ allOf: - clocks - clock-names =20 + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-dfi + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + minItems: 2 + maxItems: 2 + required: + - clocks + - clock-names + - if: properties: compatible: --=20 2.53.0 From nobody Thu Sep 24 17:55:41 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFFF850AC09; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli Like previous Rockchip SoCs RK3576 has DFI hardware to measure DDR bandwidth utilisation. Add the node for it to the SoC's DT. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index b0c0d3c8b1b1..197b8c3b76b4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1832,6 +1832,17 @@ qos_npu_m1ro: qos@27f22100 { reg =3D <0x0 0x27f22100 0x0 0x20>; }; =20 + dfi: dfi@2a000000 { + compatible =3D "rockchip,rk3576-dfi"; + reg =3D <0x0 0x2a000000 0x0 0x20000>; + clocks =3D <&cru PCLK_DDR_MON_CH0>, + <&cru PCLK_DDR_MON_CH1>; + clock-names =3D "pclk_ddr_mon_ch0", "pclk_ddr_mon_ch1"; + interrupts =3D , + ; + rockchip,pmu =3D <&pmu1_grf>; + }; + gmac0: ethernet@2a220000 { compatible =3D "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; reg =3D <0x0 0x2a220000 0x0 0x10000>; --=20 2.53.0 From nobody Thu Sep 24 17:55:41 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6956750B8D5; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A DDRMON in version 0x40 (found in RK3576) has two control registers, which moves the register addresses. Move the register offsets from the defines to the varaint struct to ease supporting the newer version. Signed-off-by: Sebastian Reichel --- drivers/devfreq/event/rockchip-dfi.c | 34 ++++++++++++++++++++++++--------= -- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/r= ockchip-dfi.c index 380361a231a2..8490219f61be 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -42,12 +42,6 @@ #define DDRMON_CTRL_TIMER_CNT_EN BIT(0) #define DDRMON_CTRL_LP5_BANK_MODE_MASK GENMASK(8, 7) =20 -#define DDRMON_CH0_WR_NUM 0x20 -#define DDRMON_CH0_RD_NUM 0x24 -#define DDRMON_CH0_COUNT_NUM 0x28 -#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c -#define DDRMON_CH1_COUNT_NUM 0x3c -#define DDRMON_CH1_DFI_ACCESS_NUM 0x40 =20 #define PERF_EVENT_CYCLES 0x0 #define PERF_EVENT_READ_BYTES 0x1 @@ -128,6 +122,10 @@ struct rockchip_dfi { * @clocks_optional: whether not finding the clocks is non-fatal. Set if t= he * DT binding for this variant didn't require clocks in = the * past, so that the driver remains compatible with old = DTs. + * @reg_write_access: register offset for writes access + * @reg_read_access: register offset for read access + * @reg_access: register offset for read/write access + * @reg_clock_cycles: register offset for clock cycles */ struct rockchip_dfi_variant { int (*init)(struct rockchip_dfi *dfi); @@ -137,6 +135,10 @@ struct rockchip_dfi_variant { const char * const *clk_names; unsigned int num_clks; bool clocks_optional; + u8 reg_write_access; + u8 reg_read_access; + u8 reg_access; + u8 reg_clock_cycles; }; =20 static int rockchip_dfi_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *ctr= l) @@ -275,13 +277,13 @@ static void rockchip_dfi_read_counters(struct rockchi= p_dfi *dfi, struct dmc_coun if (!(dfi->channel_mask & BIT(i))) continue; res->c[i].read_access =3D readl_relaxed(dfi_regs + - DDRMON_CH0_RD_NUM + i * dfi->variant->stride); + dfi->variant->reg_read_access + i * dfi->variant->stride); res->c[i].write_access =3D readl_relaxed(dfi_regs + - DDRMON_CH0_WR_NUM + i * dfi->variant->stride); + dfi->variant->reg_write_access + i * dfi->variant->stride); res->c[i].access =3D readl_relaxed(dfi_regs + - DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->variant->stride); + dfi->variant->reg_access + i * dfi->variant->stride); res->c[i].clock_cycles =3D readl_relaxed(dfi_regs + - DDRMON_CH0_COUNT_NUM + i * dfi->variant->stride); + dfi->variant->reg_clock_cycles + i * dfi->variant->stride); } } =20 @@ -829,6 +831,10 @@ static const struct rockchip_dfi_variant rk3399_varian= t =3D { .max_channels =3D 2, .clk_names =3D rk3399_clk_names, .num_clks =3D ARRAY_SIZE(rk3399_clk_names), + .reg_write_access =3D 0x20, + .reg_read_access =3D 0x24, + .reg_clock_cycles =3D 0x28, + .reg_access =3D 0x2c, }; =20 static const struct rockchip_dfi_variant rk3568_variant =3D { @@ -836,6 +842,10 @@ static const struct rockchip_dfi_variant rk3568_varian= t =3D { .stride =3D 0x0, .ctrl_single =3D true, .max_channels =3D 1, + .reg_write_access =3D 0x20, + .reg_read_access =3D 0x24, + .reg_clock_cycles =3D 0x28, + .reg_access =3D 0x2c, }; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Add support for the new control register layout found for DDRMON controllers having version 0x40. This prepares the driver for adding RK3576 support. Signed-off-by: Sebastian Reichel --- drivers/devfreq/event/rockchip-dfi.c | 85 ++++++++++++++++++++++++++------= ---- 1 file changed, 62 insertions(+), 23 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/r= ockchip-dfi.c index 8490219f61be..8ba97af78e3d 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -42,6 +42,19 @@ #define DDRMON_CTRL_TIMER_CNT_EN BIT(0) #define DDRMON_CTRL_LP5_BANK_MODE_MASK GENMASK(8, 7) =20 +#define DDRMON_CTRL0 0x04 +#define DDRMON_CTRL0_EXT_TRIGGER_EN BIT(6) +#define DDRMON_CTRL0_DDR4 BIT(5) +#define DDRMON_CTRL0_LPDDR4 BIT(4) +#define DDRMON_CTRL0_HARDWARE_EN BIT(3) +#define DDRMON_CTRL0_LPDDR23 BIT(2) +#define DDRMON_CTRL0_SOFTWARE_EN BIT(1) +#define DDRMON_CTRL0_TIMER_CNT_EN BIT(0) +#define DDRMON_CTRL0_HOT_RANK GENMASK(8, 7) + +#define DDRMON_CTRL1 0x08 +#define DDRMON_CTRL1_LPDDR5 BIT(0) +#define DDRMON_CTRL1_LP5_BANK_MODE_MASK GENMASK(2, 1) =20 #define PERF_EVENT_CYCLES 0x0 #define PERF_EVENT_READ_BYTES 0x1 @@ -143,8 +156,6 @@ struct rockchip_dfi_variant { =20 static int rockchip_dfi_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *ctr= l) { - u32 ddrmon_ver; - switch (dfi->ddr_type) { case ROCKCHIP_DDRTYPE_LPDDR2: case ROCKCHIP_DDRTYPE_LPDDR3: @@ -159,26 +170,43 @@ static int rockchip_dfi_ddrtype_to_ctrl(struct rockch= ip_dfi *dfi, u32 *ctrl) FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 0); break; case ROCKCHIP_DDRTYPE_LPDDR5: - ddrmon_ver =3D readl_relaxed(dfi->regs); - if (ddrmon_ver < 0x40) { - *ctrl =3D FIELD_PREP_WM16(DDRMON_CTRL_LPDDR23, 0) | - FIELD_PREP_WM16(DDRMON_CTRL_LPDDR4, 0) | - FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 1) | - FIELD_PREP_WM16(DDRMON_CTRL_LP5_BANK_MODE_MASK, - dfi->lp5_bank_mode); - break; - } - - /* - * As it is unknown whether the unpleasant special case - * behaviour used by the vendor kernel is needed for any - * shipping hardware, ask users to report if they have - * some of that hardware. - */ - dev_err(&dfi->edev->dev, - "unsupported DDRMON version 0x%04X, please let linux-rockchip know!\n", - ddrmon_ver); + *ctrl =3D FIELD_PREP_WM16(DDRMON_CTRL_LPDDR23, 0) | + FIELD_PREP_WM16(DDRMON_CTRL_LPDDR4, 0) | + FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 1) | + FIELD_PREP_WM16(DDRMON_CTRL_LP5_BANK_MODE_MASK, + dfi->lp5_bank_mode); + break; + default: + dev_err(&dfi->edev->dev, "unsupported memory type 0x%X\n", + dfi->ddr_type); return -EOPNOTSUPP; + } + + return 0; +} + +static int rockchip_dfi_v4_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *= ctrl0, u32 *ctrl1) +{ + switch (dfi->ddr_type) { + case ROCKCHIP_DDRTYPE_LPDDR2: + case ROCKCHIP_DDRTYPE_LPDDR3: + *ctrl0 =3D FIELD_PREP_WM16(DDRMON_CTRL0_LPDDR23, 1) | + FIELD_PREP_WM16(DDRMON_CTRL0_LPDDR4, 0); + *ctrl1 =3D FIELD_PREP_WM16(DDRMON_CTRL1_LPDDR5, 0); + break; + case ROCKCHIP_DDRTYPE_LPDDR4: + case ROCKCHIP_DDRTYPE_LPDDR4X: + *ctrl0 =3D FIELD_PREP_WM16(DDRMON_CTRL0_LPDDR23, 0) | + FIELD_PREP_WM16(DDRMON_CTRL0_LPDDR4, 1); + *ctrl1 =3D FIELD_PREP_WM16(DDRMON_CTRL1_LPDDR5, 0); + break; + case ROCKCHIP_DDRTYPE_LPDDR5: + *ctrl0 =3D FIELD_PREP_WM16(DDRMON_CTRL0_LPDDR23, 0) | + FIELD_PREP_WM16(DDRMON_CTRL0_LPDDR4, 0); + *ctrl1 =3D FIELD_PREP_WM16(DDRMON_CTRL1_LPDDR5, 1) | + FIELD_PREP_WM16(DDRMON_CTRL_LP5_BANK_MODE_MASK, + dfi->lp5_bank_mode); + break; default: dev_err(&dfi->edev->dev, "unsupported memory type 0x%X\n", dfi->ddr_type); @@ -188,11 +216,12 @@ static int rockchip_dfi_ddrtype_to_ctrl(struct rockch= ip_dfi *dfi, u32 *ctrl) return 0; } =20 + static int rockchip_dfi_enable(struct rockchip_dfi *dfi) { void __iomem *dfi_regs =3D dfi->regs; + u32 ctrl, ctrl1, ddrmon_ver; int i, ret =3D 0; - u32 ctrl; =20 mutex_lock(&dfi->mutex); =20 @@ -207,10 +236,16 @@ static int rockchip_dfi_enable(struct rockchip_dfi *d= fi) goto out; } =20 - ret =3D rockchip_dfi_ddrtype_to_ctrl(dfi, &ctrl); + ddrmon_ver =3D readl_relaxed(dfi->regs); + if (ddrmon_ver < 0x40) + ret =3D rockchip_dfi_ddrtype_to_ctrl(dfi, &ctrl); + else + ret =3D rockchip_dfi_v4_ddrtype_to_ctrl(dfi, &ctrl, &ctrl1); + if (ret) goto out; =20 + for (i =3D 0; i < dfi->variant->max_channels; i++) { =20 if (!(dfi->channel_mask & BIT(i))) @@ -225,6 +260,10 @@ static int rockchip_dfi_enable(struct rockchip_dfi *df= i) writel_relaxed(ctrl, dfi_regs + i * dfi->variant->stride + DDRMON_CTRL); =20 + if (ddrmon_ver >=3D 0x40) + writel_relaxed(ctrl1, dfi_regs + i * dfi->variant->stride + + DDRMON_CTRL1); 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Add RK3576 support to the DFI driver exposing the same functionality as found on previous chips. This uses the RK3588 init for getting the DRAM type info from the GRF registers. In contrast to RK3588 it uses a newer DDRMON controller IP, though (version 0x40). Co-developed-by: Nicolas Frattaroli Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- drivers/devfreq/event/rockchip-dfi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/r= ockchip-dfi.c index 8ba97af78e3d..a895e566b4b9 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -858,6 +858,10 @@ static const char * const rk3399_clk_names[] =3D { "pclk_ddr_mon", }; =20 +static const char * const rk3576_clk_names[] =3D { + "pclk_ddr_mon_ch0", "pclk_ddr_mon_ch1", +}; + static const char * const rk3588_clk_names[] =3D { "pclk_ddr_mon_ch0", "pclk_ddr_mon_ch1", "pclk_ddr_mon_ch2", "pclk_ddr_mon_ch3", @@ -887,6 +891,18 @@ static const struct rockchip_dfi_variant rk3568_varian= t =3D { .reg_access =3D 0x2c, }; =20 +static const struct rockchip_dfi_variant rk3576_variant =3D { + .init =3D rk3588_dfi_init, + .stride =3D 0x10000, + .max_channels =3D 2, + .clk_names =3D rk3576_clk_names, + .num_clks =3D ARRAY_SIZE(rk3576_clk_names), + .reg_write_access =3D 0x28, + .reg_read_access =3D 0x2c, + .reg_access =3D 0x34, + .reg_clock_cycles =3D 0x30, +}; + static const struct rockchip_dfi_variant rk3588_variant =3D { .init =3D rk3588_dfi_init, .stride =3D 0x4000, @@ -903,6 +919,7 @@ static const struct rockchip_dfi_variant rk3588_variant= =3D { static const struct of_device_id rockchip_dfi_id_match[] =3D { { .compatible =3D "rockchip,rk3399-dfi", .data =3D &rk3399_variant }, { .compatible =3D "rockchip,rk3568-dfi", .data =3D &rk3568_variant }, + { .compatible =3D "rockchip,rk3576-dfi", .data =3D &rk3576_variant }, { .compatible =3D "rockchip,rk3588-dfi", .data =3D &rk3588_variant }, { }, }; --=20 2.53.0