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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c3314313esm11180808eec.14.2026.09.20.01.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 01:49:42 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Dhruvin Rajpura , Anandu Krishnan E , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , Konrad Dybcio Subject: [PATCH v3 1/6] arm64: dts: qcom: nord: Add support for ADSP and CDSPs Date: Sun, 20 Sep 2026 16:49:15 +0800 Message-ID: <20260920084920.2201418-2-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260920084920.2201418-1-shengchao.guo@oss.qualcomm.com> References: <20260920084920.2201418-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: e0Ut7cec3kRMaljZh_1nB5GBdLy4TyD- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIwMDEyNiBTYWx0ZWRfX+Gw+HiyUYacj ZbsO3FHlvPN0jqrBVsf9CL+wVqQiBWtrPfqDJly5Lz7ltJYkxb0aI1rLmhDOas8XX9pz8ObYaHL gQBiKhYJALY5vDRXyB2tLWnpBu434y1TVIRK7ZX+IdXHg/GCwMML6eu513X2oTSj5ud4I0apiZn yqNxN/wOecfZZESfFRoBNTwse0O1Doqq30IctT8micfZTzKdQi1nRqfmYsYdV/BOQfL2tHpzX6G qbxiSeNH7YYBlQ1r8LhVwEigoqOZTf5J1tir7iBrRQoKjiNroQOAKEyjTeO6D7Kcx2Nbn8O4tSS MCLHQiXwqFj8y/jIRaiRdd/5FVQhZDGFIVGLXWIibpgkOUWdMxdGI5bSMONYY3j3cdXWOc+SJDA c8nSfOlxWaEZnKTLSLsDYJ/9dir9/w2CLq8ylOW6zfQq5LX/QvFQoGJUD1UPkVVOTY2h8hk+3+Q zzw8u+IZwsBZ8QW0sMw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIwMDEyNiBTYWx0ZWRfX7gvAZY4maI5Q nvKZYQcYh/oogkx5wIK4cd+19qWPSQa31UPKVET8kar3Xzr4d78nzphzg8zATOG4/lOfObmyhpZ +Neh8W+SVN4xmDik3j0M4FJ1ChQFjq0= X-Authority-Analysis: v=2.4 cv=BKAmP1QG c=1 sm=1 tr=0 ts=6aaf9e28 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=VXXG8FULNQTABRvIdlgA:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: e0Ut7cec3kRMaljZh_1nB5GBdLy4TyD- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-20_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 impostorscore=0 spamscore=0 malwarescore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609200126 Content-Type: text/plain; charset="utf-8" Add device tree nodes to support ADSP (HPASS DSP) and CDSPs remoteproc on Nord SoC. This includes: - SMEM memory reservation used by the inter-processor communication infrastructure - IPCC mailbox controller for inter-processor signalling - AOSS QMP node for load state power management - SMP2P nodes providing stop control and fault/crash interrupt signals - Remoteproc nodes with a GLINK edge and FastRPC compute contexts for userspace offload The embedded variant specific power domains, XO clock, and interconnect paths are filled in nord-embedded.dtsi. Reviewed-by: Konrad Dybcio Signed-off-by: Shawn Guo Reviewed-by: Abel Vesa --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 63 ++ arch/arm64/boot/dts/qcom/nord-ipcc.h | 144 ++++ arch/arm64/boot/dts/qcom/nord.dtsi | 885 ++++++++++++++++++++ 3 files changed, 1092 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/nord-ipcc.h diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/= dts/qcom/nord-embedded.dtsi index 568fe68cd185..c7ac2e66632e 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -363,6 +363,69 @@ &qupv3_2 { "s-ahb"; }; =20 +&remoteproc_adsp { + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + interconnects =3D <&hpass_ag_noc MASTER_HPASS_PROC_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names =3D "cx", + "mx"; +}; + +&remoteproc_cdsp0 { + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + interconnects =3D <&nsp_data_noc_0 MASTER_NSP0_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_NMXC>, + <&rpmhpd RPMHPD_NSP0>; + power-domain-names =3D "cx", + "mx", + "nsp"; +}; + +&remoteproc_cdsp1 { + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + interconnects =3D <&nsp_data_noc_1 MASTER_NSP1_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_NMXC>, + <&rpmhpd RPMHPD_NSP1>; + power-domain-names =3D "cx", + "mx", + "nsp"; +}; + +&remoteproc_cdsp2 { + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + interconnects =3D <&nsp_data_noc_2 MASTER_NSP2_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_NMXC>, + <&rpmhpd RPMHPD_NSP2>; + power-domain-names =3D "cx", + "mx", + "nsp"; +}; + +&remoteproc_cdsp3 { + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + interconnects =3D <&nsp_data_noc_3 MASTER_NSP3_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_NMXC>, + <&rpmhpd RPMHPD_NSP3>; + power-domain-names =3D "cx", + "mx", + "nsp"; +}; + &spi0 { clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; clock-names =3D "se"; diff --git a/arch/arm64/boot/dts/qcom/nord-ipcc.h b/arch/arm64/boot/dts/qco= m/nord-ipcc.h new file mode 100644 index 000000000000..8bf9b0875b6d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-ipcc.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DTS_NORD_IPCC_H +#define __DTS_NORD_IPCC_H + +/* Physical client IDs */ +#define IPCC_MPROC_AOP 0 +#define IPCC_MPROC_TZ 1 +#define IPCC_MPROC_ADSP0 2 +#define IPCC_MPROC_NSP0 3 +#define IPCC_MPROC_NSP1 4 +#define IPCC_MPROC_NSP2 5 +#define IPCC_MPROC_NSP3 6 +#define IPCC_MPROC_APSS_NS0 7 +#define IPCC_MPROC_APSS_NS1 8 +#define IPCC_MPROC_APSS_NS2 9 +#define IPCC_MPROC_APSS_NS3 10 +#define IPCC_MPROC_ADSP1 11 +#define IPCC_MPROC_ADSP2 12 +#define IPCC_MPROC_APSS_NS4 13 +#define IPCC_MPROC_SOCCP 15 +#define IPCC_MPROC_CPUCP 16 +#define IPCC_MPROC_A78CSS 17 +#define IPCC_MPROC_TMESS 18 +#define IPCC_MPROC_SAIL0 19 +#define IPCC_MPROC_SAIL1 20 +#define IPCC_MPROC_SAIL2 21 +#define IPCC_MPROC_SAIL3 22 +#define IPCC_MPROC_SAIL4 23 +#define IPCC_MPROC_SAIL5 24 + +#define IPCC_COMPUTE_L0_ADSP0 0 +#define IPCC_COMPUTE_L0_NSP0 1 +#define IPCC_COMPUTE_L0_NSP1 2 +#define IPCC_COMPUTE_L0_NSP2 3 +#define IPCC_COMPUTE_L0_NSP3 4 +#define IPCC_COMPUTE_L0_APSS_NS0 5 +#define IPCC_COMPUTE_L0_GPU0 6 +#define IPCC_COMPUTE_L0_APSS_NS1 7 +#define IPCC_COMPUTE_L0_APSS_NS2 8 +#define IPCC_COMPUTE_L0_APSS_NS3 9 +#define IPCC_COMPUTE_L0_CVP 10 +#define IPCC_COMPUTE_L0_ICP0 11 +#define IPCC_COMPUTE_L0_ICP1 12 +#define IPCC_COMPUTE_L0_VPU 13 +#define IPCC_COMPUTE_L0_DPU0 14 +#define IPCC_COMPUTE_L0_DPU1 15 +#define IPCC_COMPUTE_L0_ADSP1 16 +#define IPCC_COMPUTE_L0_ADSP2 17 +#define IPCC_COMPUTE_L0_APSS_NS4 18 +#define IPCC_COMPUTE_L0_SOCCP 20 +#define IPCC_COMPUTE_L0_SAIL0 21 +#define IPCC_COMPUTE_L0_SAIL1 22 +#define IPCC_COMPUTE_L0_SAIL2 23 +#define IPCC_COMPUTE_L0_SAIL3 24 +#define IPCC_COMPUTE_L0_SAIL4 25 +#define IPCC_COMPUTE_L0_SAIL5 26 +#define IPCC_COMPUTE_L0_IPA 27 +#define IPCC_COMPUTE_L0_GPU1 28 + +#define IPCC_COMPUTE_L1_ADSP0 0 +#define IPCC_COMPUTE_L1_NSP0 1 +#define IPCC_COMPUTE_L1_NSP1 2 +#define IPCC_COMPUTE_L1_NSP2 3 +#define IPCC_COMPUTE_L1_NSP3 4 +#define IPCC_COMPUTE_L1_APSS_NS0 5 +#define IPCC_COMPUTE_L1_GPU0 6 +#define IPCC_COMPUTE_L1_APSS_NS1 7 +#define IPCC_COMPUTE_L1_APSS_NS2 8 +#define IPCC_COMPUTE_L1_APSS_NS3 9 +#define IPCC_COMPUTE_L1_CVP 10 +#define IPCC_COMPUTE_L1_ICP0 11 +#define IPCC_COMPUTE_L1_ICP1 12 +#define IPCC_COMPUTE_L1_VPU 13 +#define IPCC_COMPUTE_L1_DPU0 14 +#define IPCC_COMPUTE_L1_DPU1 15 +#define IPCC_COMPUTE_L1_ADSP1 16 +#define IPCC_COMPUTE_L1_ADSP2 17 +#define IPCC_COMPUTE_L1_APSS_NS4 18 +#define IPCC_COMPUTE_L1_SOCCP 20 +#define IPCC_COMPUTE_L1_SAIL0 21 +#define IPCC_COMPUTE_L1_SAIL1 22 +#define IPCC_COMPUTE_L1_SAIL2 23 +#define IPCC_COMPUTE_L1_SAIL3 24 +#define IPCC_COMPUTE_L1_SAIL4 25 +#define IPCC_COMPUTE_L1_SAIL5 26 +#define IPCC_COMPUTE_L1_IPA 27 +#define IPCC_COMPUTE_L1_GPU1 28 + +#define IPCC_PERIPH_ADSP0 0 +#define IPCC_PERIPH_NSP0 1 +#define IPCC_PERIPH_NSP1 2 +#define IPCC_PERIPH_NSP2 3 +#define IPCC_PERIPH_NSP3 4 +#define IPCC_PERIPH_APSS_NS0 5 +#define IPCC_PERIPH_PCIE0 6 +#define IPCC_PERIPH_PCIE1 7 +#define IPCC_PERIPH_APSS_NS1 8 +#define IPCC_PERIPH_APSS_NS2 9 +#define IPCC_PERIPH_APSS_NS3 10 +#define IPCC_PERIPH_ADSP1 11 +#define IPCC_PERIPH_ADSP2 12 +#define IPCC_PERIPH_APSS_NS4 13 + +#define IPCC_FENCE_ADSP0 0 +#define IPCC_FENCE_NSP0 1 +#define IPCC_FENCE_NSP1 2 +#define IPCC_FENCE_NSP2 3 +#define IPCC_FENCE_NSP3 4 +#define IPCC_FENCE_APSS_NS0 5 +#define IPCC_FENCE_GPU0 6 +#define IPCC_FENCE_APSS_NS1 7 +#define IPCC_FENCE_APSS_NS2 8 +#define IPCC_FENCE_APSS_NS3 9 +#define IPCC_FENCE_CVP 10 +#define IPCC_FENCE_ICP0 11 +#define IPCC_FENCE_ICP1 12 +#define IPCC_FENCE_CAM_ENG0 13 +#define IPCC_FENCE_CAM_ENG1 14 +#define IPCC_FENCE_CAM_ENG2 15 +#define IPCC_FENCE_CAM_ENG3 16 +#define IPCC_FENCE_CAM_ENG4 17 +#define IPCC_FENCE_CAM_ENG5 18 +#define IPCC_FENCE_CAM_ENG6 19 +#define IPCC_FENCE_CAM_ENG7 20 +#define IPCC_FENCE_CAM_ENG8 21 +#define IPCC_FENCE_CAM_ENG9 22 +#define IPCC_FENCE_CAM_ENG10 23 +#define IPCC_FENCE_CAM_ENG11 24 +#define IPCC_FENCE_CAM_ENG12 25 +#define IPCC_FENCE_VPU 26 +#define IPCC_FENCE_DPU0 27 +#define IPCC_FENCE_DPU1 28 +#define IPCC_FENCE_ADSP1 29 +#define IPCC_FENCE_ADSP2 30 +#define IPCC_FENCE_APSS_NS4 31 +#define IPCC_FENCE_SOCCP 33 +#define IPCC_FENCE_IPA 34 +#define IPCC_FENCE_GPU1 35 + +#endif diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/= nord.dtsi index e0496fd40c30..d413341eac41 100644 --- a/arch/arm64/boot/dts/qcom/nord.dtsi +++ b/arch/arm64/boot/dts/qcom/nord.dtsi @@ -4,6 +4,9 @@ */ =20 #include +#include + +#include "nord-ipcc.h" =20 / { interrupt-parent =3D <&intc>; @@ -685,6 +688,13 @@ qdss_apps_mem: qdss-apps-region@87b00000 { no-map; }; =20 + smem_mem: smem@89b00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x89b00000 0x0 0x400000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + global_sync_mem: global-sync-region@89f00000 { reg =3D <0x0 0x89f00000 0x0 0x400000>; no-map; @@ -902,6 +912,117 @@ dump_mem: mem-dump-region { }; }; =20 + smp2p-adsp { + compatible =3D "qcom,smp2p"; + interrupts-extended =3D <&ipcc0 IPCC_MPROC_ADSP0 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_ADSP0 + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,smem =3D <443>, <429>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp0 { + compatible =3D "qcom,smp2p"; + interrupts-extended =3D <&ipcc0 IPCC_MPROC_NSP0 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_NSP0 IPCC_MPROC_SIGNAL_SMP2P>; + qcom,smem =3D <94>, <432>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_cdsp0_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp0_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp1 { + compatible =3D "qcom,smp2p"; + interrupts-extended =3D <&ipcc0 IPCC_MPROC_NSP1 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; + qcom,smem =3D <617>, <616>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <69>; + + smp2p_cdsp1_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp1_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp2 { + compatible =3D "qcom,smp2p"; + interrupts-extended =3D <&ipcc0 IPCC_MPROC_NSP2 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_NSP2 IPCC_MPROC_SIGNAL_SMP2P>; + qcom,smem =3D <617>, <616>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <133>; + + smp2p_cdsp2_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp2_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp3 { + compatible =3D "qcom,smp2p"; + interrupts-extended =3D <&ipcc0 IPCC_MPROC_NSP3 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_NSP3 IPCC_MPROC_SIGNAL_SMP2P>; + qcom,smem =3D <617>, <616>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <197>; + + smp2p_cdsp3_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp3_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + soc: soc@0 { compatible =3D "simple-bus"; #address-cells =3D <2>; @@ -1518,6 +1639,104 @@ tcsr: syscon@1f60000 { reg =3D <0x0 0x01f60000 0x0 0xa0000>; }; =20 + remoteproc_adsp: remoteproc@4c00000 { + compatible =3D "qcom,nord-adsp-pas"; + reg =3D <0x0 0x04c00000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + memory-region =3D <&hpass_dsp0_mem>, + <&hpass_dsp0_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc0 IPCC_MPROC_ADSP0 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_ADSP0 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid =3D <2>; + label =3D "adsp"; + + fastrpc { + compatible =3D "qcom,nord-fastrpc", + "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "adsp"; + memory-region =3D <&hpass_rpc_remote_heap_mem>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu_0 0x09e3 0x0000>, + <&apps_smmu_0 0x0a43 0x0020>, + <&apps_smmu_0 0x0a63 0x0020>, + <&apps_smmu_0 0x0a83 0x0000>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu_0 0x09e4 0x0000>, + <&apps_smmu_0 0x0a44 0x0020>, + <&apps_smmu_0 0x0a64 0x0020>, + <&apps_smmu_0 0x0a84 0x0000>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu_0 0x09e5 0x0000>, + <&apps_smmu_0 0x0a45 0x0020>, + <&apps_smmu_0 0x0a65 0x0020>, + <&apps_smmu_0 0x0a85 0x0000>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu_0 0x09e6 0x0000>, + <&apps_smmu_0 0x0a46 0x0020>, + <&apps_smmu_0 0x0a66 0x0020>, + <&apps_smmu_0 0x0a86 0x0000>; + dma-coherent; + }; + }; + }; + }; + + ipcc0: mailbox@9007000 { + compatible =3D "qcom,nord-ipcc", + "qcom,ipcc"; + reg =3D <0x0 0x09007000 0x0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,nord-pdc", "qcom,pdc"; @@ -1637,6 +1856,16 @@ tsens7: thermal-sensor@c233000 { #thermal-sensor-cells =3D <1>; }; =20 + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,nord-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + interrupts-extended =3D <&ipcc0 IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + #clock-cells =3D <0>; + }; + tlmm: pinctrl@f100000 { compatible =3D "qcom,nord-tlmm"; reg =3D <0x0 0x0f100000 0x0 0xc0000>; @@ -2071,6 +2300,662 @@ watchdog@17826000 { clocks =3D <&sleep_clk>; interrupts =3D ; }; + + remoteproc_cdsp0: remoteproc@1f300000 { + compatible =3D "qcom,nord-cdsp0-pas"; + reg =3D <0x0 0x1f300000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp0_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + memory-region =3D <&cdsp0_mem>, + <&q6_cdsp0_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_cdsp0_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc0 IPCC_MPROC_NSP0 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_NSP0 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid =3D <5>; + label =3D "cdsp"; + + fastrpc { + compatible =3D "qcom,nord-fastrpc", + "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "cdsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu_2 0x0301 0x0040>, + <&apps_smmu_2 0x0341 0x0040>, + <&apps_smmu_2 0x0361 0x0000>; + dma-coherent; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu_2 0x0302 0x0040>, + <&apps_smmu_2 0x0342 0x0040>, + <&apps_smmu_2 0x0362 0x0000>; + dma-coherent; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu_2 0x0303 0x0040>, + <&apps_smmu_2 0x0343 0x0040>, + <&apps_smmu_2 0x0363 0x0000>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu_2 0x0304 0x0040>, + <&apps_smmu_2 0x0344 0x0040>, + <&apps_smmu_2 0x0364 0x0000>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu_2 0x0305 0x0000>, + <&apps_smmu_2 0x0345 0x0020>, + <&apps_smmu_2 0x0365 0x0020>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu_2 0x0306 0x0040>, + <&apps_smmu_2 0x0346 0x0040>, + <&apps_smmu_2 0x0366 0x0000>; + dma-coherent; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + iommus =3D <&apps_smmu_2 0x0307 0x0040>, + <&apps_smmu_2 0x0347 0x0040>, + <&apps_smmu_2 0x0367 0x0000>; + dma-coherent; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + iommus =3D <&apps_smmu_2 0x0308 0x0040>, + <&apps_smmu_2 0x0348 0x0040>, + <&apps_smmu_2 0x0368 0x0000>; + dma-coherent; + }; + + compute-cb@9 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <9>; + iommus =3D <&apps_smmu_2 0x0309 0x0040>, + <&apps_smmu_2 0x0349 0x0040>, + <&apps_smmu_2 0x0369 0x0000>; + dma-coherent; + }; + + compute-cb@10 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <10>; + iommus =3D <&apps_smmu_2 0x030a 0x0040>, + <&apps_smmu_2 0x034a 0x0040>, + <&apps_smmu_2 0x036a 0x0000>; + dma-coherent; + }; + + compute-cb@11 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <11>; + iommus =3D <&apps_smmu_2 0x030b 0x0040>, + <&apps_smmu_2 0x034b 0x0040>, + <&apps_smmu_2 0x036b 0x0000>; + dma-coherent; + }; + + compute-cb@12 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <12>; + iommus =3D <&apps_smmu_2 0x030c 0x0040>, + <&apps_smmu_2 0x034c 0x0040>, + <&apps_smmu_2 0x036c 0x0000>; + dma-coherent; + }; + + compute-cb@13 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <13>; + iommus =3D <&apps_smmu_2 0x030d 0x0000>, + <&apps_smmu_2 0x034d 0x0020>, + <&apps_smmu_2 0x036d 0x0020>; + dma-coherent; + }; + }; + }; + }; + + remoteproc_cdsp1: remoteproc@1f700000 { + compatible =3D "qcom,nord-cdsp1-pas"; + reg =3D <0x0 0x1f700000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp1_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + memory-region =3D <&cdsp1_mem>, + <&q6_cdsp1_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_cdsp1_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc0 IPCC_MPROC_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid =3D <69>; + label =3D "cdsp"; + + fastrpc { + compatible =3D "qcom,nord-fastrpc", + "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "cdsp1"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu_2 0x0701 0x0040>, + <&apps_smmu_2 0x0741 0x0040>, + <&apps_smmu_2 0x0761 0x0000>; + dma-coherent; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu_2 0x0702 0x0040>, + <&apps_smmu_2 0x0742 0x0040>, + <&apps_smmu_2 0x0762 0x0000>; + dma-coherent; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu_2 0x0703 0x0040>, + <&apps_smmu_2 0x0743 0x0040>, + <&apps_smmu_2 0x0763 0x0000>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu_2 0x0704 0x0040>, + <&apps_smmu_2 0x0744 0x0040>, + <&apps_smmu_2 0x0764 0x0000>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu_2 0x0705 0x0000>, + <&apps_smmu_2 0x0745 0x0020>, + <&apps_smmu_2 0x0765 0x0020>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu_2 0x0706 0x0040>, + <&apps_smmu_2 0x0746 0x0040>, + <&apps_smmu_2 0x0766 0x0000>; + dma-coherent; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + iommus =3D <&apps_smmu_2 0x0707 0x0040>, + <&apps_smmu_2 0x0747 0x0040>, + <&apps_smmu_2 0x0767 0x0000>; + dma-coherent; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + iommus =3D <&apps_smmu_2 0x0708 0x0040>, + <&apps_smmu_2 0x0748 0x0040>, + <&apps_smmu_2 0x0768 0x0000>; + dma-coherent; + }; + + compute-cb@9 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <9>; + iommus =3D <&apps_smmu_2 0x0709 0x0040>, + <&apps_smmu_2 0x0749 0x0040>, + <&apps_smmu_2 0x0769 0x0000>; + dma-coherent; + }; + + compute-cb@10 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <10>; + iommus =3D <&apps_smmu_2 0x070a 0x0040>, + <&apps_smmu_2 0x074a 0x0040>, + <&apps_smmu_2 0x076a 0x0000>; + dma-coherent; + }; + + compute-cb@11 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <11>; + iommus =3D <&apps_smmu_2 0x070b 0x0040>, + <&apps_smmu_2 0x074b 0x0040>, + <&apps_smmu_2 0x076b 0x0000>; + dma-coherent; + }; + + compute-cb@12 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <12>; + iommus =3D <&apps_smmu_2 0x070c 0x0040>, + <&apps_smmu_2 0x074c 0x0040>, + <&apps_smmu_2 0x076c 0x0000>; + dma-coherent; + }; + + compute-cb@13 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <13>; + iommus =3D <&apps_smmu_2 0x070d 0x0000>, + <&apps_smmu_2 0x074d 0x0020>, + <&apps_smmu_2 0x076d 0x0020>; + dma-coherent; + }; + }; + }; + }; + + remoteproc_cdsp2: remoteproc@1fb00000 { + compatible =3D "qcom,nord-cdsp2-pas"; + reg =3D <0x0 0x1fb00000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 501 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp2_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp2_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp2_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp2_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp2_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + memory-region =3D <&cdsp2_mem>, + <&q6_cdsp2_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_cdsp2_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc0 IPCC_MPROC_NSP2 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_NSP2 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid =3D <133>; + label =3D "cdsp"; + + fastrpc { + compatible =3D "qcom,nord-fastrpc", + "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "cdsp2"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu_2 0x0b01 0x0040>, + <&apps_smmu_2 0x0b41 0x0040>, + <&apps_smmu_2 0x0b61 0x0000>; + dma-coherent; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu_2 0x0b02 0x0040>, + <&apps_smmu_2 0x0b42 0x0040>, + <&apps_smmu_2 0x0b62 0x0000>; + dma-coherent; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu_2 0x0b03 0x0040>, + <&apps_smmu_2 0x0b43 0x0040>, + <&apps_smmu_2 0x0b63 0x0000>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu_2 0x0b04 0x0040>, + <&apps_smmu_2 0x0b44 0x0040>, + <&apps_smmu_2 0x0b64 0x0000>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu_2 0x0b05 0x0000>, + <&apps_smmu_2 0x0b45 0x0020>, + <&apps_smmu_2 0x0b65 0x0020>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu_2 0x0b06 0x0040>, + <&apps_smmu_2 0x0b46 0x0040>, + <&apps_smmu_2 0x0b66 0x0000>; + dma-coherent; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + iommus =3D <&apps_smmu_2 0x0b07 0x0040>, + <&apps_smmu_2 0x0b47 0x0040>, + <&apps_smmu_2 0x0b67 0x0000>; + dma-coherent; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + iommus =3D <&apps_smmu_2 0x0b08 0x0040>, + <&apps_smmu_2 0x0b48 0x0040>, + <&apps_smmu_2 0x0b68 0x0000>; + dma-coherent; + }; + + compute-cb@9 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <9>; + iommus =3D <&apps_smmu_2 0x0b09 0x0040>, + <&apps_smmu_2 0x0b49 0x0040>, + <&apps_smmu_2 0x0b69 0x0000>; + dma-coherent; + }; + + compute-cb@10 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <10>; + iommus =3D <&apps_smmu_2 0x0b0a 0x0040>, + <&apps_smmu_2 0x0b4a 0x0040>, + <&apps_smmu_2 0x0b6a 0x0000>; + dma-coherent; + }; + + compute-cb@11 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <11>; + iommus =3D <&apps_smmu_2 0x0b0b 0x0040>, + <&apps_smmu_2 0x0b4b 0x0040>, + <&apps_smmu_2 0x0b6b 0x0000>; + dma-coherent; + }; + + compute-cb@12 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <12>; + iommus =3D <&apps_smmu_2 0x0b0c 0x0040>, + <&apps_smmu_2 0x0b4c 0x0040>, + <&apps_smmu_2 0x0b6c 0x0000>; + dma-coherent; + }; + + compute-cb@13 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <13>; + iommus =3D <&apps_smmu_2 0x0b0d 0x0000>, + <&apps_smmu_2 0x0b4d 0x0020>, + <&apps_smmu_2 0x0b6d 0x0020>; + dma-coherent; + }; + }; + }; + }; + + remoteproc_cdsp3: remoteproc@1ff00000 { + compatible =3D "qcom,nord-cdsp3-pas"; + reg =3D <0x0 0x1ff00000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 505 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp3_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp3_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp3_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp3_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp3_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + memory-region =3D <&cdsp3_mem>, + <&q6_cdsp3_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_cdsp3_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc0 IPCC_MPROC_NSP3 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_MPROC_NSP3 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid =3D <197>; + label =3D "cdsp"; + + fastrpc { + compatible =3D "qcom,nord-fastrpc", + "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "cdsp3"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu_2 0x0f01 0x0040>, + <&apps_smmu_2 0x0f41 0x0040>, + <&apps_smmu_2 0x0f61 0x0000>; + dma-coherent; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu_2 0x0f02 0x0040>, + <&apps_smmu_2 0x0f42 0x0040>, + <&apps_smmu_2 0x0f62 0x0000>; + dma-coherent; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu_2 0x0f03 0x0040>, + <&apps_smmu_2 0x0f43 0x0040>, + <&apps_smmu_2 0x0f63 0x0000>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu_2 0x0f04 0x0040>, + <&apps_smmu_2 0x0f44 0x0040>, + <&apps_smmu_2 0x0f64 0x0000>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu_2 0x0f05 0x0000>, + <&apps_smmu_2 0x0f45 0x0020>, + <&apps_smmu_2 0x0f65 0x0020>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu_2 0x0f06 0x0040>, + <&apps_smmu_2 0x0f46 0x0040>, + <&apps_smmu_2 0x0f66 0x0000>; + dma-coherent; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + iommus =3D <&apps_smmu_2 0x0f07 0x0040>, + <&apps_smmu_2 0x0f47 0x0040>, + <&apps_smmu_2 0x0f67 0x0000>; + dma-coherent; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + iommus =3D <&apps_smmu_2 0x0f08 0x0040>, + <&apps_smmu_2 0x0f48 0x0040>, + <&apps_smmu_2 0x0f68 0x0000>; + dma-coherent; + }; + + compute-cb@9 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <9>; + iommus =3D <&apps_smmu_2 0x0f09 0x0040>, + <&apps_smmu_2 0x0f49 0x0040>, + <&apps_smmu_2 0x0f69 0x0000>; + dma-coherent; + }; + + compute-cb@10 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <10>; + iommus =3D <&apps_smmu_2 0x0f0a 0x0040>, + <&apps_smmu_2 0x0f4a 0x0040>, + <&apps_smmu_2 0x0f6a 0x0000>; + dma-coherent; + }; + + compute-cb@11 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <11>; + iommus =3D <&apps_smmu_2 0x0f0b 0x0040>, + <&apps_smmu_2 0x0f4b 0x0040>, + <&apps_smmu_2 0x0f6b 0x0000>; + dma-coherent; + }; + + compute-cb@12 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <12>; + iommus =3D <&apps_smmu_2 0x0f0c 0x0040>, + <&apps_smmu_2 0x0f4c 0x0040>, + <&apps_smmu_2 0x0f6c 0x0000>; + dma-coherent; + }; + + compute-cb@13 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <13>; + iommus =3D <&apps_smmu_2 0x0f0d 0x0000>, + <&apps_smmu_2 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c3314313esm11180808eec.14.2026.09.20.01.49.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 01:49:46 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Dhruvin Rajpura , Anandu Krishnan E , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , Abel Vesa , Konrad Dybcio Subject: [PATCH v3 2/6] arm64: dts: qcom: nord-rrd: Enable ADSP and CDSPs Date: Sun, 20 Sep 2026 16:49:16 +0800 Message-ID: <20260920084920.2201418-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260920084920.2201418-1-shengchao.guo@oss.qualcomm.com> References: <20260920084920.2201418-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: DGZUi0H5d3t5TFiQ2cO3674sFHBrP4yG X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIwMDEyNiBTYWx0ZWRfXxSBktEYm4dEK 4jdD+hu20E0M3VWq+KYzKva97KZAlGteN8wAlD9nuSGlJGJnoDnwTRjjALKiRhi8xrZJEtKdElA bj8aglzzaJa04G/9+NVPLsZqu4YdMjU= X-Authority-Analysis: v=2.4 cv=YqWa1IYX c=1 sm=1 tr=0 ts=6aaf9e2c cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=UZuJur8GfllDSyYqWHAA:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIwMDEyNiBTYWx0ZWRfX2IBC2Q5UDxe/ ukL+4GIQUjUp53AjfgUnwO+x7NkUF7/o6pu0yg92sQO6V4lXry0fhan5TgoUHoaDL+SyvvpI5Go d131bFmSW/EoeiRAkq3+pfM4/1K0mCAG0eKd1A+1bYlgCoPQHe+QEhVYpQ23soVTpk+YlQNwR2v o3hSMgql6Rhkp2KDiQh/7Erb76RFKWakSHnnFlGTbXOgGw2LGZ39CbQtjQWtx+QCimJWfuvVXDe vcuUC1igtVtCqJVlgoDm3g/4KI+r1Jj8G1cu1ThVchxM+vEFBuMTEFyMjn3ftCD3A3JTjrzqmQC Oqu1skluBiIPWR8HGn7psLWci1dMl6AxMA8rBhvcuWOKvlc7+IwLKD4V1Nnl7iGYrJ91weZ66rZ dvpbGMEnqXN7fTppTiPJg5bRwjGQ7dH6PVXa/Yopha7kMBGgcOe6gfBYUUWCVmyBrTI5oFuclOx mXAaQCi39HCCMNzAt9A== X-Proofpoint-GUID: DGZUi0H5d3t5TFiQ2cO3674sFHBrP4yG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-20_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609200126 Content-Type: text/plain; charset="utf-8" Enable ADSP (HPASS DSP) and CDSPs remoteproc on the Nord RRD board. Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-rrd.dts | 35 +++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qc= om/nord-rrd.dts index 3673003c8b21..e4c3aee441c2 100644 --- a/arch/arm64/boot/dts/qcom/nord-rrd.dts +++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts @@ -393,6 +393,41 @@ &qupv3_2 { status =3D "okay"; }; =20 +&remoteproc_adsp { + firmware-name =3D "qcom/nord/adsp.mbn", + "qcom/nord/adsp_dtbs.elf"; + + status =3D "okay"; +}; + +&remoteproc_cdsp0 { + firmware-name =3D "qcom/nord/cdsp.mbn", + "qcom/nord/cdsp_dtbs.elf"; + + status =3D "okay"; +}; + +&remoteproc_cdsp1 { + firmware-name =3D "qcom/nord/cdsp1.mbn", + "qcom/nord/cdsp1_dtbs.elf"; + + status =3D "okay"; +}; + +&remoteproc_cdsp2 { + firmware-name =3D "qcom/nord/cdsp2.mbn", + "qcom/nord/cdsp2_dtbs.elf"; + + status =3D "okay"; +}; + +&remoteproc_cdsp3 { + firmware-name =3D "qcom/nord/cdsp3.mbn", + "qcom/nord/cdsp3_dtbs.elf"; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c3314313esm11180808eec.14.2026.09.20.01.49.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 01:49:51 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Dhruvin Rajpura , Anandu Krishnan E , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski , Abel Vesa , Konrad Dybcio , Shawn Guo Subject: [PATCH v3 3/6] arm64: dts: qcom: nord: Add the SPMI PMIC arbiter Date: Sun, 20 Sep 2026 16:49:17 +0800 Message-ID: <20260920084920.2201418-4-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260920084920.2201418-1-shengchao.guo@oss.qualcomm.com> References: <20260920084920.2201418-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIwMDEyNiBTYWx0ZWRfX9yvAgglFH86i db5AnhHI486LuNQQzxM6a+tXJMQjiNsF/hiM5s9VhUq53O0TE0YXRUBmmziYYeIiomqVq1z8JNf dm35WZvT+nGXy8D9QRSKplOcfzI2qTD7vfmwpQSC4N57Mfzzam6SANc8zvYMqJjI6N0GasBAJ/6 2cD10NQcUPptaR0eR07XJOhO7LlT9+EPOtXSmW+hTzEbGV7UZtKGT5dqQWdohcDsLc5Qx0dBpOb Nj6nd+831BMVLq0QwqDAE++ORMJLGAkXydt5jA7LWjJeo/01T7UHTy/6E6DrjABqgH8yoCoGlnz YOHgrvK3H8xN0yOokE9cvdIvOI0M+0e6xx6VTXtFmVYj5ZRJe6HHfzr7P0RFypGUW2V1azc83aY tha7yC/wUffdD4LZTCDYSjlJzwMh2XJMsWqbO7KrR4xxa+1TNQWtJgDeF5XHB9P8OJd3l6yAUdg A/4FBH1qWM6cOdwOi4Q== X-Proofpoint-GUID: Mn3J3g-aXkjLTYuZB6pM1Prt-8pKZThS X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIwMDEyNiBTYWx0ZWRfXy0oEpGCHpLCC ZiXaTaxQeb9Z3UY76N0BZD12CYQpdBu9TujYCTwwgcD16KC53t+Iy6Nyo4auh0VEPWeWQoZK3mh uurU2FUeRHYbFNWhFU6jQhvW+xX/yKM= X-Proofpoint-ORIG-GUID: Mn3J3g-aXkjLTYuZB6pM1Prt-8pKZThS X-Authority-Analysis: v=2.4 cv=XegcX455 c=1 sm=1 tr=0 ts=6aaf9e30 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=pTKKwl7rlpcWqDfdxRsA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-20_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 adultscore=0 spamscore=0 phishscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609200126 Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Add the SPMI PMIC Arbiter node for the Nord platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/= nord.dtsi index d413341eac41..926ccf3bbe4e 100644 --- a/arch/arm64/boot/dts/qcom/nord.dtsi +++ b/arch/arm64/boot/dts/qcom/nord.dtsi @@ -1866,6 +1866,28 @@ IPCC_MPROC_SIGNAL_GLINK_QMP #clock-cells =3D <0>; }; =20 + spmi_bus: spmi@c400000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x400000>, + <0x0 0x0c440000 0x0 0x80000>, + <0x0 0x0c4c0000 0x0 0x10000>, + <0x0 0x0c42d000 0x0 0x4000>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + interrupt-controller; + #interrupt-cells =3D <4>; + #address-cells =3D <2>; + #size-cells =3D <0>; + qcom,channel =3D <0>; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c3314313esm11180808eec.14.2026.09.20.01.49.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 01:49:55 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Dhruvin Rajpura , Anandu Krishnan E , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dhruvin Rajpura , Konrad Dybcio , Shawn Guo Subject: [PATCH v3 4/6] arm64: dts: qcom: nord: Add PMAU0102 and PMM8650AU PMIC support Date: Sun, 20 Sep 2026 16:49:18 +0800 Message-ID: <20260920084920.2201418-5-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260920084920.2201418-1-shengchao.guo@oss.qualcomm.com> References: <20260920084920.2201418-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIwMDEyNiBTYWx0ZWRfX40J7kKXiXlrS ULR9+nDZB3LJNsoaEBUT2tICF2z0aW4HSdmgytdTESN+5XQkFUmMFCog9KC4KcugVdXESWCvMnY IgZ+ryqH/Jb5TKyier+kFD/1S0YsXGg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIwMDEyNiBTYWx0ZWRfX3Ib25jinM+3B sbhIr4nOnrWpUfWL912qYkhxPSj+nLBJGbjrrjUpE2HfRUsFViNe+Z6pSkVRYJ5Y9MMZLPtf9Qq 5+rqqRojcJXtxVkz3iMOI5294N1L7EGRRYTOB3HFw8XsHHz9zTCjOQWgnhnJ0RipphDhXAvKwzu FPToySIF6U0JE3VNjrBod24nGrqaAagpxtg2h+cCgfQzRT9eML3be7vpLM32/Y04DOaDP9RbNdJ P2AMxgvwW2duoSaD7ub9UKwEs4ZsB4OPYS2Z09A0f5h/JVxYhaFXdLJfghkc1dQ4MfcKc8I6nM4 ofKn1aZD1OUiLBBk0Ccnk5xtudv2OiV3ja/sZ2Adne4xB/gtvZCp0Qx+EX0i0vPUbIiq2QpgBT2 r83T37QFaJKnYin0ecbHzeOefU/E1GYnq3DGUeGrQjj25Gmqe6IxvTtyFjZaIUJBaq4vEGUEuJg po0I1LlgsWaKJHzxrZA== X-Proofpoint-ORIG-GUID: AN0YlEPtgGOcktju54V7zRiQO6RniZK3 X-Proofpoint-GUID: AN0YlEPtgGOcktju54V7zRiQO6RniZK3 X-Authority-Analysis: v=2.4 cv=QKv91QLL c=1 sm=1 tr=0 ts=6aaf9e35 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=hucZloQI8G6bWT6_XmMA:9 a=U2nuDi6JAHPDsfF0:21 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-20_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 spamscore=0 bulkscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609200126 Content-Type: text/plain; charset="utf-8" From: Dhruvin Rajpura The Nord platform is supplied by two families of PMICs on the SPMI bus: eight PMAU0102 devices on USIDs 4 to 11, and one PMM8650AU on USID 0. Add one dtsi per PMIC type, following the established one-file-per-PMIC convention, and include both of them from nord-rrd.dts. The eight PMAU0102 instances are labelled pmau0102_e through pmau0102_l after their board designators. Each one provides a GPIO controller, an ADC, and an MBG (Master Bandgap) temperature monitor that reads its die temperature through a DIE_TEMP ADC channel. The monitors use the qcom,pmau0102-mbg-tm compatible with qcom,pm8775-mbg-tm as fallback, and each is hooked up to a thermal zone. PMM8650AU is the same die as PMM8654AU, so pmm8650au_a reuses the existing pmm8654au ompatibles while the file is named after the part actually populated on the board. It provides PON with a power key, a RTC, and a GPIO controller. The resin is described but left disabled, for boards that wire it up to enable. Signed-off-by: Dhruvin Rajpura Acked-by: Konrad Dybcio Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-rrd.dts | 2 + arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi | 543 +++++++++++++++++++ arch/arm64/boot/dts/qcom/pmm8650au-nord.dtsi | 54 ++ 3 files changed, 599 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmm8650au-nord.dtsi diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qc= om/nord-rrd.dts index e4c3aee441c2..c547963371b4 100644 --- a/arch/arm64/boot/dts/qcom/nord-rrd.dts +++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts @@ -9,6 +9,8 @@ #include =20 #include "nord-embedded.dtsi" +#include "pmau0102-nord.dtsi" +#include "pmm8650au-nord.dtsi" =20 / { model =3D "Qualcomm Technologies, Inc. IQ10 RRD"; diff --git a/arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi b/arch/arm64/boot/= dts/qcom/pmau0102-nord.dtsi new file mode 100644 index 000000000000..47ea145f4abb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi @@ -0,0 +1,543 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +#include "qcom-adc5-gen3.h" + +&spmi_bus { + pmau0102_e: pmic@4 { + compatible =3D "qcom,pmau0102", "qcom,spmi-pmic"; + reg =3D <0x4 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmau0102_e_mbg_temp: temperature-sensor@d700 { + compatible =3D "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm"; + reg =3D <0xd700>; + interrupts-extended =3D <&spmi_bus 0x4 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels =3D <&pmau0102_e_adc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pmau0102_e_adc: adc@7200 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x7200>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts-extended =3D <&spmi_bus 0x4 0x72 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells =3D <1>; + + channel@400 { + reg =3D ; + label =3D "pmau0102_e_ref_gnd"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@401 { + reg =3D ; + label =3D "pmau0102_e_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@403 { + reg =3D ; + label =3D "pmau0102_e_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + }; + + pmau0102_e_gpios: gpio@8800 { + compatible =3D "qcom,pmau0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmau0102_e_gpios 0 0 12>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmau0102_f: pmic@5 { + compatible =3D "qcom,pmau0102", "qcom,spmi-pmic"; + reg =3D <0x5 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmau0102_f_mbg_temp: temperature-sensor@d700 { + compatible =3D "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm"; + reg =3D <0xd700>; + interrupts-extended =3D <&spmi_bus 0x5 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels =3D <&pmau0102_f_adc ADC5_GEN3_DIE_TEMP(5)>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pmau0102_f_adc: adc@7200 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x7200>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts-extended =3D <&spmi_bus 0x5 0x72 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells =3D <1>; + + channel@500 { + reg =3D ; + label =3D "pmau0102_f_ref_gnd"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@501 { + reg =3D ; + label =3D "pmau0102_f_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@503 { + reg =3D ; + label =3D "pmau0102_f_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + }; + + pmau0102_f_gpios: gpio@8800 { + compatible =3D "qcom,pmau0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmau0102_f_gpios 0 0 12>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmau0102_g: pmic@6 { + compatible =3D "qcom,pmau0102", "qcom,spmi-pmic"; + reg =3D <0x6 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmau0102_g_mbg_temp: temperature-sensor@d700 { + compatible =3D "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm"; + reg =3D <0xd700>; + interrupts-extended =3D <&spmi_bus 0x6 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels =3D <&pmau0102_g_adc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pmau0102_g_adc: adc@7200 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x7200>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts-extended =3D <&spmi_bus 0x6 0x72 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells =3D <1>; + + channel@600 { + reg =3D ; + label =3D "pmau0102_g_ref_gnd"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@601 { + reg =3D ; + label =3D "pmau0102_g_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@603 { + reg =3D ; + label =3D "pmau0102_g_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + }; + + pmau0102_g_gpios: gpio@8800 { + compatible =3D "qcom,pmau0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmau0102_g_gpios 0 0 12>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmau0102_h: pmic@7 { + compatible =3D "qcom,pmau0102", "qcom,spmi-pmic"; + reg =3D <0x7 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmau0102_h_mbg_temp: temperature-sensor@d700 { + compatible =3D "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm"; + reg =3D <0xd700>; + interrupts-extended =3D <&spmi_bus 0x7 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels =3D <&pmau0102_h_adc ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pmau0102_h_adc: adc@7200 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x7200>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts-extended =3D <&spmi_bus 0x7 0x72 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells =3D <1>; + + channel@700 { + reg =3D ; + label =3D "pmau0102_h_ref_gnd"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@701 { + reg =3D ; + label =3D "pmau0102_h_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@703 { + reg =3D ; + label =3D "pmau0102_h_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + }; + + pmau0102_h_gpios: gpio@8800 { + compatible =3D "qcom,pmau0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmau0102_h_gpios 0 0 12>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmau0102_i: pmic@8 { + compatible =3D "qcom,pmau0102", "qcom,spmi-pmic"; + reg =3D <0x8 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmau0102_i_mbg_temp: temperature-sensor@d700 { + compatible =3D "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm"; + reg =3D <0xd700>; + interrupts-extended =3D <&spmi_bus 0x8 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels =3D <&pmau0102_i_adc ADC5_GEN3_DIE_TEMP(8)>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pmau0102_i_adc: adc@7200 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x7200>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts-extended =3D <&spmi_bus 0x8 0x72 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells =3D <1>; + + channel@800 { + reg =3D ; + label =3D "pmau0102_i_ref_gnd"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@801 { + reg =3D ; + label =3D "pmau0102_i_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@803 { + reg =3D ; + label =3D "pmau0102_i_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + }; + + pmau0102_i_gpios: gpio@8800 { + compatible =3D "qcom,pmau0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmau0102_i_gpios 0 0 12>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmau0102_j: pmic@9 { + compatible =3D "qcom,pmau0102", "qcom,spmi-pmic"; + reg =3D <0x9 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmau0102_j_mbg_temp: temperature-sensor@d700 { + compatible =3D "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm"; + reg =3D <0xd700>; + interrupts-extended =3D <&spmi_bus 0x9 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels =3D <&pmau0102_j_adc ADC5_GEN3_DIE_TEMP(9)>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pmau0102_j_adc: adc@7200 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x7200>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts-extended =3D <&spmi_bus 0x9 0x72 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells =3D <1>; + + channel@900 { + reg =3D ; + label =3D "pmau0102_j_ref_gnd"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@901 { + reg =3D ; + label =3D "pmau0102_j_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@903 { + reg =3D ; + label =3D "pmau0102_j_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + }; + + pmau0102_j_gpios: gpio@8800 { + compatible =3D "qcom,pmau0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmau0102_j_gpios 0 0 12>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmau0102_k: pmic@a { + compatible =3D "qcom,pmau0102", "qcom,spmi-pmic"; + reg =3D <0xa SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmau0102_k_mbg_temp: temperature-sensor@d700 { + compatible =3D "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm"; + reg =3D <0xd700>; + interrupts-extended =3D <&spmi_bus 0xa 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels =3D <&pmau0102_k_adc ADC5_GEN3_DIE_TEMP(0xa)>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pmau0102_k_adc: adc@7200 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x7200>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts-extended =3D <&spmi_bus 0xa 0x72 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells =3D <1>; + + channel@a00 { + reg =3D ; + label =3D "pmau0102_k_ref_gnd"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@a01 { + reg =3D ; + label =3D "pmau0102_k_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@a03 { + reg =3D ; + label =3D "pmau0102_k_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + }; + + pmau0102_k_gpios: gpio@8800 { + compatible =3D "qcom,pmau0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmau0102_k_gpios 0 0 12>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmau0102_l: pmic@b { + compatible =3D "qcom,pmau0102", "qcom,spmi-pmic"; + reg =3D <0xb SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmau0102_l_mbg_temp: temperature-sensor@d700 { + compatible =3D "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm"; + reg =3D <0xd700>; + interrupts-extended =3D <&spmi_bus 0xb 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels =3D <&pmau0102_l_adc ADC5_GEN3_DIE_TEMP(0xb)>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pmau0102_l_adc: adc@7200 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x7200>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts-extended =3D <&spmi_bus 0xb 0x72 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells =3D <1>; + + channel@b00 { + reg =3D ; + label =3D "pmau0102_l_ref_gnd"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@b01 { + reg =3D ; + label =3D "pmau0102_l_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@b03 { + reg =3D ; + label =3D "pmau0102_l_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + }; + + pmau0102_l_gpios: gpio@8800 { + compatible =3D "qcom,pmau0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmau0102_l_gpios 0 0 12>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; + +/ { + thermal-zones { + pmau0102_e_thermal: pmau0102-e-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmau0102_e_mbg_temp>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmau0102_f_thermal: pmau0102-f-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmau0102_f_mbg_temp>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmau0102_g_thermal: pmau0102-g-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmau0102_g_mbg_temp>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmau0102_h_thermal: pmau0102-h-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmau0102_h_mbg_temp>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmau0102_i_thermal: pmau0102-i-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmau0102_i_mbg_temp>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmau0102_j_thermal: pmau0102-j-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmau0102_j_mbg_temp>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmau0102_k_thermal: pmau0102-k-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmau0102_k_mbg_temp>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pmau0102_l_thermal: pmau0102-l-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmau0102_l_mbg_temp>; + + trips { + trip0 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmm8650au-nord.dtsi b/arch/arm64/boot= /dts/qcom/pmm8650au-nord.dtsi new file mode 100644 index 000000000000..1282e5bae591 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmm8650au-nord.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +&spmi_bus { + pmm8650au_a: pmic@0 { + compatible =3D "qcom,pmm8654au", "qcom,spmi-pmic"; + reg =3D <0x0 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmm8650au_a_pon: pon@1200 { + compatible =3D "qcom,pmm8654au-pon", "qcom,pmk8350-pon"; + reg =3D <0x1200>, <0x800>; + reg-names =3D "hlos", "pbs"; + + pmm8650au_a_pon_pwrkey: pwrkey { + compatible =3D "qcom,pmm8654au-pwrkey", "qcom,pmk8350-pwrkey"; + interrupts-extended =3D <&spmi_bus 0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code =3D ; + debounce =3D <15625>; + }; + + pmm8650au_a_pon_resin: resin { + compatible =3D "qcom,pmm8654au-resin", "qcom,pmk8350-resin"; + interrupts-extended =3D <&spmi_bus 0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + debounce =3D <15625>; + status =3D "disabled"; + }; + }; + + pmm8650au_a_rtc: rtc@6100 { + compatible =3D "qcom,pmm8654au-rtc", "qcom,pmk8350-rtc"; + reg =3D <0x6100>, <0x6200>; + reg-names =3D "rtc", "alarm"; + interrupts-extended =3D <&spmi_bus 0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pmm8650au_a_gpios: gpio@8800 { + compatible =3D "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; 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Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index f93027caddb4..07ce0fab5ea9 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -413,6 +413,7 @@ properties: - enum: - qcom,iq10-rrd - qcom,sa8797p-ride + - qcom,sa8797p-ride-embedded - const: qcom,nord =20 - description: Qualcomm Technologies, Inc. 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c3314313esm11180808eec.14.2026.09.20.01.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 01:50:03 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Dhruvin Rajpura , Anandu Krishnan E , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski , Abel Vesa , Konrad Dybcio , Shawn Guo Subject: [PATCH v3 6/6] arm64: dts: qcom: Add initial support for Nord Ride Embedded board Date: Sun, 20 Sep 2026 16:49:20 +0800 Message-ID: <20260920084920.2201418-7-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260920084920.2201418-1-shengchao.guo@oss.qualcomm.com> References: <20260920084920.2201418-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: JgzZX03-LHnbALskEqD8xR_14jU7tBEF X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIwMDEyNiBTYWx0ZWRfX1+XC/y5htRpN SAwQSSAO43CSo0QZkQ7bcPW1Aw5wKE2a2Y6gGuvf0D5giZRhLjeuZiEABZ49TMzl4Fpdv6DCXAd KqHnqNY6SyVwfr8mWbz9PG1k5AYNdzY= X-Authority-Analysis: v=2.4 cv=YqWa1IYX c=1 sm=1 tr=0 ts=6aaf9e3d cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=23L8-64gBmTLm0DN3gAA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIwMDEyNiBTYWx0ZWRfX76CuecqtVGuo yVXA0cEpe8ce01VbLZblURRRwZzHk/Q4M6i6xsP1xGOOJfNY/zwkx3TqHbVUcSM/QlZNCvWDTKV bcxReSJztEjtBZ9qe9motgCvp6PJmvTinYcH/I7vjj8paIgPlDhDV1wkxYuoXwjBTHFTIcRjpBI Ul20U8m4OnrOgvZW5pw/XV8cx1jWwA2QZ2Hxzthc+IX8Qq/5CywuOBdpL+BmZVoznxG6KDBdA4F GAmZT7Oeai1SjXXLYwg8ICOcNt9MhhlFBP7MNu2MfTrBNo6KN3YqcXBByb9BBQZl41o4HtvIIZ0 RbF4dr/aogSQSHNFne2LwTez4244nfNqqRqclysG8ykXzlSXEIiWXMxKmR0rFb/HepyBP12DFrK zhjrd2FgPnAS0TiMHiEv3ujgBT9/un8jo6sp0TXg9/Y8E6oFplPOv0+VVgk9hcrVgr1r/VcvjY1 z9F6h9K7mtfdc4fQuUQ== X-Proofpoint-GUID: JgzZX03-LHnbALskEqD8xR_14jU7tBEF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-20_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609200126 Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Add the initial device tree for the Nord Ride Embedded board, the non-SCMI variant of the SA8797P automotive Ride board. Enable the debug UART, UFS storage, the ADSP and CDSP remote processors, and describe the board regulators supplied by the on-board PMICs. Signed-off-by: Bartosz Golaszewski Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/nord-ride-embedded.dts | 442 ++++++++++++++++++ 2 files changed, 443 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/nord-ride-embedded.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 347897b5a514..1fedf8899a5c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -167,6 +167,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-sony-xperia-yoshin= o-maple.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D nord-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D nord-ride-embedded.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D nord-rrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D purwa-iot-evk.dtb =20 diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/b= oot/dts/qcom/nord-ride-embedded.dts new file mode 100644 index 000000000000..09ee525764ef --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include + +#include "nord-embedded.dtsi" +#include "pmau0102-nord.dtsi" +#include "pmm8650au-nord.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. SA8797P Ride Embedded"; + compatible =3D "qcom,sa8797p-ride-embedded", "qcom,nord"; + + aliases { + serial0 =3D &uart15; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + }; +}; + +&apps_rsc { + /* PMIC A - Kobra_MM (PMM8650AU) - SID 0x0, Bus E0 */ + regulators-0 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "A_E0"; + + vreg_l4a_1p2: ldo4 { + regulator-name =3D "vreg_l4a_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name =3D "vreg_l6a_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a_1p2: ldo7 { + regulator-name =3D "vreg_l7a_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a_1p8: ldo8 { + regulator-name =3D "vreg_l8a_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s1a_vdd2h_l: smps1 { + regulator-name =3D "vreg_s1a_vdd2h_l"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s3a_1p8: smps3 { + regulator-name =3D "vreg_s3a_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s5a_mv: smps5 { + regulator-name =3D "vreg_s5a_mv"; + regulator-min-microvolt =3D <1328000>; + regulator-max-microvolt =3D <1370000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s6a_vddq_l: smps6 { + regulator-name =3D "vreg_s6a_vddq_l"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <570000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + /* PMIC E - Kai_MV - SID 0x4, Bus E0 */ + regulators-1 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "E_E0"; + + vreg_l1e_0p9: ldo1 { + regulator-name =3D "vreg_l1e_0p9"; + regulator-min-microvolt =3D <936000>; + regulator-max-microvolt =3D <936000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name =3D "vreg_l2e_0p9"; + regulator-min-microvolt =3D <936000>; + regulator-max-microvolt =3D <936000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3e_1p8: ldo3 { + regulator-name =3D "vreg_l3e_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + /* PMIC F - Kai_MV - SID 0x5, Bus E0 */ + regulators-2 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "F_E0"; + + vreg_l1f_vdd2l: ldo1 { + regulator-name =3D "vreg_l1f_vdd2l"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3f_vdd1: ldo3 { + regulator-name =3D "vreg_l3f_vdd1"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s7f_lv_sub: smps7 { + regulator-name =3D "vreg_s7f_lv_sub"; + regulator-min-microvolt =3D <1036000>; + regulator-max-microvolt =3D <1136000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s8f_vddq_h: smps8 { + regulator-name =3D "vreg_s8f_vddq_h"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <570000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + /* PMIC G - Kai_MV - SID 0x6, Bus E0 */ + regulators-3 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "G_E0"; + + vreg_l2g_0p7: ldo2 { + regulator-name =3D "vreg_l2g_0p7"; + regulator-min-microvolt =3D <752000>; + regulator-max-microvolt =3D <752000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s5g_vdd2h_h: smps5 { + regulator-name =3D "vreg_s5g_vdd2h_h"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1150000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + }; + + /* PMIC H - Kai_MV - SID 0x7, Bus E0 */ + regulators-4 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "H_E0"; + + vreg_l1h_0p9: ldo1 { + regulator-name =3D "vreg_l1h_0p9"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2h_1p2: ldo2 { + regulator-name =3D "vreg_l2h_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + /* PMIC I - Kai_MV - SID 0x8, Bus E0 */ + regulators-5 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "I_E0"; + + vreg_l1i_0p9: ldo1 { + regulator-name =3D "vreg_l1i_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name =3D "vreg_l2i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3i_2p5: ldo3 { + regulator-name =3D "vreg_l3i_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + /* PMIC K - Kai_MV - SID 0xA, Bus E0 */ + regulators-6 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "K_E0"; + + vreg_l1k_vdd2l: ldo1 { + regulator-name =3D "vreg_l1k_vdd2l"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2k_0p9: ldo2 { + regulator-name =3D "vreg_l2k_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3k_vdd1: ldo3 { + regulator-name =3D "vreg_l3k_vdd1"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + /* PMIC L - Kai_MV - SID 0xB, Bus E0 */ + regulators-7 { + compatible =3D "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id =3D "L_E0"; + + vreg_l3l_1p8: ldo3 { + regulator-name =3D "vreg_l3l_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&qupv3_0 { + firmware-name =3D "qcom/nord/qupv3fw.elf"; + + status =3D "okay"; +}; + +&qupv3_1 { + firmware-name =3D "qcom/nord/qupv3fw.elf"; + + status =3D "okay"; +}; + +&qupv3_2 { + firmware-name =3D "qcom/nord/qupv3fw.elf"; + + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/nord/adsp.mbn", + "qcom/nord/adsp_dtbs.elf"; + + status =3D "okay"; +}; + +&remoteproc_cdsp0 { + firmware-name =3D "qcom/nord/cdsp.mbn", + "qcom/nord/cdsp_dtbs.elf"; + + status =3D "okay"; +}; + +&remoteproc_cdsp1 { + firmware-name =3D "qcom/nord/cdsp1.mbn", + "qcom/nord/cdsp1_dtbs.elf"; + + status =3D "okay"; +}; + +&remoteproc_cdsp2 { + firmware-name =3D "qcom/nord/cdsp2.mbn", + "qcom/nord/cdsp2_dtbs.elf"; + + status =3D "okay"; +}; + +&remoteproc_cdsp3 { + firmware-name =3D "qcom/nord/cdsp3.mbn", + "qcom/nord/cdsp3_dtbs.elf"; + + status =3D "okay"; +}; + +&uart15 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 181 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l3i_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l2i_1p2>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1i_0p9>; + vdda-pll-supply =3D <&vreg_l2h_1p2>; + + status =3D "okay"; +}; --=20 2.43.0