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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4881f4d7861sm6103834fac.1.2026.09.20.12.45.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 12:45:40 -0700 (PDT) From: James Hilliard Date: Sun, 20 Sep 2026 13:45:27 -0600 Subject: [PATCH net-next v4 1/6] net: phylink: allow stopping a suspended instance Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-submit-h616-emac1-v1-v4-1-8347dfe2eb7d@gmail.com> References: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> In-Reply-To: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> To: Richard Genoud , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , Russell King , Christian Marangi , Andrew Lunn , Heiner Kallweit , Tiezhu Yang , Huacai Chen Cc: Maxime Ripard , Alastair D'Silva , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, James Hilliard X-Mailer: b4 0.15.2 A MAC which cannot restore its hardware after system sleep may need to close the network device instead of calling phylink_resume(). Without MAC Wake-on-LAN, phylink_suspend() has already stopped the PHY and PCS, so another phylink_stop() repeats their shutdown. With MAC Wake-on-LAN, the saved link-up state still needs a matching mac_link_down(), and leaving PHYLINK_DISABLE_MAC_WOL set prevents a subsequent start from resolving the link. Allow phylink_stop() to finish shutdown directly from either suspended state. Leave an already stopped instance alone. For MAC Wake-on-LAN, stop resolution, drain pending resolve work, complete the deferred link-down and clear the WoL disable bit while retaining the stopped bit. This does not restart the PHY, reconfigure the MAC or bring its link up. Signed-off-by: James Hilliard --- drivers/net/phy/phylink.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 390d3eb3e6f7..8ecf2dec3a7d 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -2615,11 +2615,17 @@ EXPORT_SYMBOL_GPL(phylink_start); * * This will synchronously bring down the link if the link is not already * down (in other words, it will trigger a mac_link_down() method call.) + * It may also be called after phylink_suspend() if the MAC cannot resume + * and the network device must be closed instead. */ void phylink_stop(struct phylink *pl) { ASSERT_RTNL(); =20 + /* phylink_suspend() already stops the link without MAC WoL. */ + if (test_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state)) + return; + if (pl->sfp_bus) sfp_upstream_stop(pl->sfp_bus); if (pl->phydev) @@ -2632,6 +2638,16 @@ void phylink_stop(struct phylink *pl) =20 phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_STOPPED); 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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4881f4d7861sm6103834fac.1.2026.09.20.12.45.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 12:45:42 -0700 (PDT) From: James Hilliard Date: Sun, 20 Sep 2026 13:45:28 -0600 Subject: [PATCH net-next v4 2/6] net: stmmac: close the interface after a failed MTU reopen Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-submit-h616-emac1-v1-v4-2-8347dfe2eb7d@gmail.com> References: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> In-Reply-To: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> To: Richard Genoud , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , Russell King , Christian Marangi , Andrew Lunn , Heiner Kallweit , Tiezhu Yang , Huacai Chen Cc: Maxime Ripard , Alastair D'Silva , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, James Hilliard X-Mailer: b4 0.15.2 An MTU change stops the data path and then reopens it using a newly allocated DMA configuration. If reopening fails, the new allocation is freed while the netdev remains up and priv->dma_conf retains copies of the freed pointers. A subsequent close repeats NAPI disable and IRQ and DMA-resource teardown. It can hang in napi_disable() or access resources which have already been freed. Track successful opens of the data path separately from the netdev's administrative state. Clear that state when releasing the data path and skip a second release after a failed reopen. Close the netdev through the network core on the MTU error path, so the PHY attachment and runtime-PM reference are released and the interface is marked down. A subsequent open can then allocate fresh resources and retry normally. Keep successful MTU changes on the existing path, retaining the PHY attachment and runtime-PM reference. Allocation failures before stopping the original data path still leave the running interface unchanged. Fixes: 3470079687448 ("net: ethernet: stmicro: stmmac: permit MTU change wi= th interface up") Signed-off-by: James Hilliard --- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/eth= ernet/stmicro/stmmac/stmmac.h index 4fc96b317d79..363872ff00d6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -281,6 +281,8 @@ struct stmmac_priv { struct mutex lock; =20 struct stmmac_dma_conf dma_conf; + /* Paired __stmmac_open()/__stmmac_release(), serialized by RTNL. */ + bool opened; =20 /* Generic channel for NAPI */ struct stmmac_channel channel[STMMAC_CH_MAX]; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index bf9e7e4cb1c3..89b773370894 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4212,6 +4212,7 @@ static int __stmmac_open(struct net_device *dev, stmmac_enable_all_queues(priv); netif_tx_start_all_queues(priv->dev); stmmac_enable_all_dma_irq(priv); + priv->opened =3D true; =20 return 0; =20 @@ -4287,6 +4288,11 @@ static void __stmmac_release(struct net_device *dev) struct stmmac_priv *priv =3D netdev_priv(dev); u8 chan; =20 + /* A failed MTU reopen has already released the data path. */ + if (!priv->opened) + return; + priv->opened =3D false; + /* Stop and disconnect the PHY */ phylink_stop(priv->phylink); =20 @@ -6212,6 +6218,10 @@ static int stmmac_change_mtu(struct net_device *dev,= int new_mtu) if (ret) { free_dma_desc_resources(priv, dma_conf); kfree(dma_conf); + /* Finish closing the PHY and PM state, but do not repeat + * the data-path teardown after the failed reopen. + */ + netif_close(dev); netdev_err(priv->dev, "failed reopening the interface after MTU change\= n"); return ret; } --=20 2.53.0 From nobody Thu Sep 24 20:33:43 2026 Received: from mail-oa2-f12.google.com (mail-oa2-f12.google.com [74.125.231.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0690489FB5 for ; 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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4881f4d7861sm6103834fac.1.2026.09.20.12.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 12:45:43 -0700 (PDT) From: James Hilliard Date: Sun, 20 Sep 2026 13:45:29 -0600 Subject: [PATCH net-next v4 3/6] net: stmmac: close the interface after failed hardware resume Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-submit-h616-emac1-v1-v4-3-8347dfe2eb7d@gmail.com> References: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> In-Reply-To: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> To: Richard Genoud , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , Russell King , Christian Marangi , Andrew Lunn , Heiner Kallweit , Tiezhu Yang , Huacai Chen Cc: Maxime Ripard , Alastair D'Silva , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, James Hilliard X-Mailer: b4 0.15.2 System suspend disables NAPI and suspends phylink but retains the IRQs and DMA resources. If hardware setup fails during resume, the interface remains administratively up with NAPI still disabled. Closing it later calls napi_disable() a second time and can hang indefinitely. On hardware-setup or timestamping failure, stop DMA and disable the MAC, then release the suspended data path without repeating NAPI disable. Stop phylink directly from its suspended state rather than restarting the link on hardware which failed to resume. Drop the driver mutex before teardown, retaining RTNL across cleanup and network-core close. Close the netdev to detach the PHY, release its runtime-PM reference and clear its administrative state. Reattach the now-down netdev so a later open can allocate new resources and retry. Preserve the original resume error and leave successful resume unchanged. Fixes: 6896c2449a18 ("net: stmmac: Check stmmac_hw_setup() in stmmac_resume= ()") Signed-off-by: James Hilliard --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index 89b773370894..18630ae62316 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4283,7 +4283,7 @@ static int stmmac_open(struct net_device *dev) return ret; } =20 -static void __stmmac_release(struct net_device *dev) +static void __stmmac_release(struct net_device *dev, bool napi_disabled) { struct stmmac_priv *priv =3D netdev_priv(dev); u8 chan; @@ -4296,7 +4296,9 @@ static void __stmmac_release(struct net_device *dev) /* Stop and disconnect the PHY */ phylink_stop(priv->phylink); =20 - stmmac_disable_all_queues(priv); + /* Suspend has already disabled NAPI when hardware resume fails. */ + if (!napi_disabled) + stmmac_disable_all_queues(priv); =20 for (chan =3D 0; chan < priv->plat->tx_queues_to_use; chan++) hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); @@ -4335,7 +4337,7 @@ static int stmmac_release(struct net_device *dev) if (device_may_wakeup(priv->device)) phylink_speed_down(priv->phylink, false); =20 - __stmmac_release(dev); + __stmmac_release(dev, false); =20 stmmac_legacy_serdes_power_down(priv); phylink_disconnect_phy(priv->phylink); @@ -6212,7 +6214,7 @@ static int stmmac_change_mtu(struct net_device *dev, = int new_mtu) return PTR_ERR(dma_conf); } =20 - __stmmac_release(dev); + __stmmac_release(dev, false); =20 ret =3D __stmmac_open(dev, dma_conf); if (ret) { @@ -8415,7 +8417,7 @@ int stmmac_resume(struct device *dev) ret =3D stmmac_hw_setup(ndev); if (ret < 0) { netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); - goto error_unlock; + goto error_stop_dma; } =20 if (priv->ptp_enabled) { @@ -8454,9 +8456,13 @@ int stmmac_resume(struct device *dev) error_stop_dma: stmmac_stop_all_dma(priv); stmmac_mac_set(priv, priv->ioaddr, false); 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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4881f4d7861sm6103834fac.1.2026.09.20.12.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 12:45:45 -0700 (PDT) From: James Hilliard Date: Sun, 20 Sep 2026 13:45:30 -0600 Subject: [PATCH net-next v4 4/6] net: stmmac: sun8i: reset the MAC after PHY initialization Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-submit-h616-emac1-v1-v4-4-8347dfe2eb7d@gmail.com> References: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> In-Reply-To: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> To: Richard Genoud , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , Russell King , Christian Marangi , Andrew Lunn , Heiner Kallweit , Tiezhu Yang , Huacai Chen Cc: Maxime Ripard , Alastair D'Silva , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, James Hilliard X-Mailer: b4 0.15.2 The MAC software reset needs a running receive clock from the PHY. Resetting the MAC at the end of probe therefore fails when the PHY driver has not been loaded or its probe has deferred on a missing supplier. The failure removes the MAC and its MDIO bus, so loading the missing driver later cannot recover the interface without reprobing the MAC. Perform the software reset in the DMA reset callback instead. The stmmac core calls it during hardware setup after attaching and initializing the PHY, and resumes a suspended PHY before reopening or resuming the MAC. Mask interrupts before requesting the reset and retain the existing DMA and interrupt-register clearing even if the reset times out. Return reset errors through the normal hardware-setup error path. Remove the unconditional reset from probe. Keep the separate H3 MDIO-mux reset after switching the mux and powering the selected PHY, since it is needed to latch the selected interface before MDIO accesses. Signed-off-by: James Hilliard --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 53 +++++++++++--------= ---- 1 file changed, 26 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-sun8i.c index 48c52eb96233..9598c386bb21 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -269,11 +269,33 @@ static const struct emac_variant emac_variant_h6 =3D { #define SYSCON_ETCS_EXT_GMII 0x1 #define SYSCON_ETCS_INT_GMII 0x2 =20 +static int sun8i_dwmac_reset(void __iomem *ioaddr) +{ + u32 v; + + v =3D readl(ioaddr + EMAC_BASIC_CTL1); + writel(v | 0x01, ioaddr + EMAC_BASIC_CTL1); + + /* The timeout was previously set to 10ms, but some board (OrangePI0) + * need more if no cable plugged. 100ms seems OK + */ + return readl_poll_timeout(ioaddr + EMAC_BASIC_CTL1, v, + !(v & 0x01), 100, 100000); +} + /* sun8i_dwmac_dma_reset() - reset the EMAC * Called from stmmac via stmmac_dma_ops->reset */ static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) { + int ret; + + writel(0, ioaddr + EMAC_INT_EN); + + /* The PHY receive clock must be running for the reset to complete. */ + ret =3D sun8i_dwmac_reset(ioaddr); + + /* Leave DMA and interrupts disabled even if the reset timed out. */ writel(0, ioaddr + EMAC_RX_CTL1); writel(0, ioaddr + EMAC_TX_CTL1); writel(0, ioaddr + EMAC_RX_FRM_FLT); @@ -281,7 +303,7 @@ static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) writel(0, ioaddr + EMAC_TX_DESC_LIST); writel(0, ioaddr + EMAC_INT_EN); writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); - return 0; + return ret; } =20 /* sun8i_dwmac_dma_init() - initialize the EMAC @@ -738,27 +760,6 @@ static void sun8i_dwmac_flow_ctrl(struct mac_device_in= fo *hw, writel(v, ioaddr + EMAC_TX_FLOW_CTL); } =20 -static int sun8i_dwmac_reset(struct stmmac_priv *priv) -{ - u32 v; - int err; - - v =3D readl(priv->ioaddr + EMAC_BASIC_CTL1); - writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); - - /* The timeout was previously set to 10ms, but some board (OrangePI0) - * need more if no cable plugged. 100ms seems OK - */ - err =3D readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, - !(v & 0x01), 100, 100000); - - if (err) { - dev_err(priv->device, "EMAC reset timeout\n"); - return err; - } - return 0; -} - /* Search in mdio-mux node for internal PHY node and get its clk/reset */ static int get_ephy_nodes(struct stmmac_priv *priv) { @@ -895,7 +896,9 @@ static int mdio_mux_syscon_switch_fn(int current_child,= int desired_child, /* After changing syscon value, the MAC need reset or it will * use the last value (and so the last PHY set). */ - ret =3D sun8i_dwmac_reset(priv); + ret =3D sun8i_dwmac_reset(priv->ioaddr); + if (ret) + dev_err(priv->device, "EMAC reset timeout\n"); } return ret; } @@ -1217,10 +1220,6 @@ static int sun8i_dwmac_probe(struct platform_device = *pdev) dev_err(&pdev->dev, "Failed to register mux\n"); goto dwmac_mux; } - } else { - ret =3D sun8i_dwmac_reset(priv); - if (ret) - goto dwmac_remove; } =20 pm_runtime_put(&pdev->dev); --=20 2.53.0 From nobody Thu Sep 24 20:33:43 2026 Received: from mail-oa2-f12.google.com (mail-oa2-f12.google.com [74.125.231.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 360B048C3F2 for ; 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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4881f4d7861sm6103834fac.1.2026.09.20.12.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 12:45:47 -0700 (PDT) From: James Hilliard Date: Sun, 20 Sep 2026 13:45:31 -0600 Subject: [PATCH net-next v4 5/6] dt-bindings: net: allwinner: add H616 EMAC1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-submit-h616-emac1-v1-v4-5-8347dfe2eb7d@gmail.com> References: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> In-Reply-To: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> To: Richard Genoud , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , Russell King , Christian Marangi , Andrew Lunn , Heiner Kallweit , Tiezhu Yang , Huacai Chen Cc: Maxime Ripard , Alastair D'Silva , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, James Hilliard X-Mailer: b4 0.15.2 The H616 secondary EMAC uses a separate system-control clock register and supports only RMII at 10/100 Mbps. Add its distinct compatible without an older fallback, since using the primary EMAC clock register would not work. Constrain the PHY interface mode to RMII, matching the hardware. Reviewed-by: Alastair D'Silva Tested-by: Alastair D'Silva Signed-off-by: James Hilliard --- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 13 +++++++++= ++++ Documentation/devicetree/bindings/net/snps,dwmac.yaml | 2 ++ 2 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 323a669fa982..2cae0133b3cd 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -21,6 +21,7 @@ select: - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac + - allwinner,sun50i-h616-emac1 - allwinner,sun55i-a523-gmac200 required: - compatible @@ -33,6 +34,7 @@ properties: - const: allwinner,sun8i-r40-gmac - const: allwinner,sun8i-v3s-emac - const: allwinner,sun50i-a64-emac + - const: allwinner,sun50i-h616-emac1 - items: - enum: - allwinner,sun20i-d1-emac @@ -91,6 +93,17 @@ required: =20 allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-h616-emac1 + + then: + properties: + phy-mode: + const: rmii + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 0ff9e3284a06..3fa6e17c3d12 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -57,6 +57,7 @@ properties: - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac + - allwinner,sun50i-h616-emac1 - amlogic,meson6-dwmac - amlogic,meson8b-dwmac - amlogic,meson8m2-dwmac @@ -623,6 +624,7 @@ allOf: - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac + - allwinner,sun50i-h616-emac1 - loongson,ls2k-dwmac - loongson,ls7a-dwmac - ingenic,jz4775-mac --=20 2.53.0 From nobody Thu Sep 24 20:33:43 2026 Received: from mail-oa2-f12.google.com (mail-oa2-f12.google.com [74.125.231.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5044348EBC0 for ; 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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4881f4d7861sm6103834fac.1.2026.09.20.12.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 12:45:49 -0700 (PDT) From: James Hilliard Date: Sun, 20 Sep 2026 13:45:32 -0600 Subject: [PATCH net-next v4 6/6] net: stmmac: sun8i: add support for Allwinner H616 EMAC1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-submit-h616-emac1-v1-v4-6-8347dfe2eb7d@gmail.com> References: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> In-Reply-To: <20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com> To: Richard Genoud , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , Russell King , Christian Marangi , Andrew Lunn , Heiner Kallweit , Tiezhu Yang , Huacai Chen Cc: Maxime Ripard , Alastair D'Silva , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, James Hilliard , Andre Przywara X-Mailer: b4 0.15.2 The H616 secondary EMAC uses a separate system-control clock register and supports only RMII at 10/100 Mbps. It connects internally to the co-packaged AC200 or AC300 EPHY and has no external PHY pins. Add an EMAC1 variant using the dedicated register and enable only RMII. Leave PHY initialization to the PHY driver instead of using the H3 internal-PHY controls. No RX or TX clock delays are configured for this RMII-only variant. Co-developed-by: Richard Genoud Signed-off-by: Richard Genoud Reviewed-by: Maxime Chevallier Reviewed-by: Andre Przywara Reviewed-by: Alastair D'Silva Tested-by: Alastair D'Silva Signed-off-by: James Hilliard --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-sun8i.c index 9598c386bb21..0ea1860cf203 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -81,6 +81,13 @@ static const struct reg_field sun8i_syscon_reg_field =3D= { .msb =3D 31, }; =20 +/* EMAC1 clock register @ 0x34 in the "system control" address range */ +static const struct reg_field sun8i_syscon_reg_field_emac1 =3D { + .reg =3D 0x34, + .lsb =3D 0, + .msb =3D 31, +}; + /* EMAC clock register @ 0x164 in the CCU address range */ static const struct reg_field sun8i_ccu_reg_field =3D { .reg =3D 0x164, @@ -143,6 +150,13 @@ static const struct emac_variant emac_variant_h6 =3D { .tx_delay_max =3D 7, }; =20 +static const struct emac_variant emac_variant_h616_emac1 =3D { + .syscon_field =3D &sun8i_syscon_reg_field_emac1, + /* The co-packaged AC200/AC300 PHY does not use the H3 PHY controls. */ + .soc_has_internal_phy =3D false, + .support_rmii =3D true, +}; + #define EMAC_BASIC_CTL0 0x00 #define EMAC_BASIC_CTL1 0x04 #define EMAC_INT_STA 0x08 @@ -1277,6 +1291,8 @@ static const struct of_device_id sun8i_dwmac_match[] = =3D { .data =3D &emac_variant_a64 }, { .compatible =3D "allwinner,sun50i-h6-emac", .data =3D &emac_variant_h6 }, + { .compatible =3D "allwinner,sun50i-h616-emac1", + .data =3D &emac_variant_h616_emac1 }, { } }; MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); --=20 2.53.0