From nobody Thu Sep 24 21:19:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 564B23F0A9F; Sun, 20 Sep 2026 12:02:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789905772; cv=none; b=IPkaw0bpP5PWL8feJqKZkp10HdZ5oeR0HxYLx6dIY71qGtBPYTQFCL3dEwPLed5OKhEuS9wsYB4tWek+ns3J6jP9kHBFqpLB4nj5UT8gZY4KrWf1IsrXdQ79Mum8FcuSUL+/jUtKbkxblm4J0+R4Tg3wfDmqZt2Lh6PbXlmiiSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789905772; c=relaxed/simple; bh=65YAMN2jMQMexn5NWqF+IkOHdXASL5XZWp1AxPHJhCM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ue6eyk8/LsGoj7X38dmzfQVAmLo3Qnc4DhSs572VVvC4Sm5QBOeiCEKh6AbD09QZPbT6GAg0dJa81uHJVNpUHthtRKxKba1K8YhgwjWGRDR8JoecMenwJ6B7W2eCu5C5ssm9XAwBh12DyAXM79+uQ7qwSnrbV7IlBGRNvsGgFfM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gn2Z2oPC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gn2Z2oPC" Received: by smtp.kernel.org (Postfix) with ESMTPS id 05DCBC2BCFA; Sun, 20 Sep 2026 12:02:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789905772; bh=65YAMN2jMQMexn5NWqF+IkOHdXASL5XZWp1AxPHJhCM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gn2Z2oPCTHQp1xXDPmD7CnuXhRHnwxKrF6wKhBHx9FLzRywzrpe2RRHP373pv/jfv XqH6elbTVNo/EWLD0k9W/4LqKVzVcgO8vpG7CwYuhGoJB7oao0A5QYBua5HGus2DlI 4uFKvtZs5uyrNs+E06nxnuMs3vEPeY+ISLFfg73aul4DMHcCmOSYQSqclIIc3DY/C/ up1AyjbIc0YWZjiRqwTbffC5ggcr/ILf9blsDdg43+ipFKlFvAlHJkifDmRrNV0R/Q IzWNMqjDmd9bqNnIlisXEAKXqa2eFVl2dszvFNcOqgCk6pTbTzOzQNIcuv4A+S2y+u DeDl95G6KhhFg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB532C982E1; Sun, 20 Sep 2026 12:02:51 +0000 (UTC) From: Keguang Zhang via B4 Relay Date: Sun, 20 Sep 2026 20:02:06 +0800 Subject: [PATCH v4 1/3] pwm: loongson: Fix low pulse buffer register handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-pwm-loongson-fix-v4-1-41b36b3c6497@gmail.com> References: <20260920-pwm-loongson-fix-v4-0-41b36b3c6497@gmail.com> In-Reply-To: <20260920-pwm-loongson-fix-v4-0-41b36b3c6497@gmail.com> To: Binbin Zhou , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Keguang Zhang , stable@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789905770; l=3560; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=xKFzA7ifd9ad2V7j06rPSJKnO6U/pybJmXR1kEqgFyQ=; b=y8wE0196pS/du7+GBxEgVSLhccaqg8LjJTqC1XqDDjw6D+7r7m6O6j6Fo/KKUozmgUH9/vrh6 mZrYZ1OATAmBcW4aaB/bj0EDJIF3FFNdEt8nwnhCX5t7i7q9pAMq9ce X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang The Loongson PWM register at offset 0x4 is documented as the Low Pulse Buffer Register, which stores the low pulse width rather than the duty cycle. However, this register was incorrectly defined and treated as a duty-cycle register. As a result, the duty cycle and low pulse cycle are swapped in the generated PWM waveform. Program the low pulse (period - duty) into the register and adjust pwm_loongson_get_state() accordingly when reconstructing the duty cycle. Fixes: 2b62c89448dd ("pwm: Add Loongson PWM controller support") Cc: stable@vger.kernel.org Signed-off-by: Keguang Zhang --- drivers/pwm/pwm-loongson.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/pwm/pwm-loongson.c b/drivers/pwm/pwm-loongson.c index 98c809bde2b3..7af5d4ce1060 100644 --- a/drivers/pwm/pwm-loongson.c +++ b/drivers/pwm/pwm-loongson.c @@ -33,7 +33,7 @@ #include =20 /* Loongson PWM registers */ -#define LOONGSON_PWM_REG_DUTY 0x4 /* Low Pulse Buffer Register */ +#define LOONGSON_PWM_REG_LOW 0x4 /* Low Pulse Buffer Register */ #define LOONGSON_PWM_REG_PERIOD 0x8 /* Pulse Period Buffer Register */ #define LOONGSON_PWM_REG_CTRL 0xc /* Control Register */ =20 @@ -120,20 +120,20 @@ static int pwm_loongson_enable(struct pwm_chip *chip,= struct pwm_device *pwm) static int pwm_loongson_config(struct pwm_chip *chip, struct pwm_device *p= wm, u64 duty_ns, u64 period_ns) { - u64 duty, period; + u64 low, duty, period; struct pwm_loongson_ddata *ddata =3D to_pwm_loongson_ddata(chip); =20 - /* duty =3D duty_ns * ddata->clk_rate / NSEC_PER_SEC */ - duty =3D mul_u64_u64_div_u64(duty_ns, ddata->clk_rate, NSEC_PER_SEC); - if (duty > U32_MAX) - duty =3D U32_MAX; - /* period =3D period_ns * ddata->clk_rate / NSEC_PER_SEC */ period =3D mul_u64_u64_div_u64(period_ns, ddata->clk_rate, NSEC_PER_SEC); if (period > U32_MAX) period =3D U32_MAX; =20 - pwm_loongson_writel(ddata, duty, LOONGSON_PWM_REG_DUTY); + /* duty =3D duty_ns * ddata->clk_rate / NSEC_PER_SEC */ + duty =3D mul_u64_u64_div_u64_roundup(duty_ns, ddata->clk_rate, NSEC_PER_S= EC); + duty =3D min(duty, period); + low =3D period - duty; + + pwm_loongson_writel(ddata, low, LOONGSON_PWM_REG_LOW); pwm_loongson_writel(ddata, period, LOONGSON_PWM_REG_PERIOD); =20 return 0; @@ -168,15 +168,20 @@ static int pwm_loongson_apply(struct pwm_chip *chip, = struct pwm_device *pwm, static int pwm_loongson_get_state(struct pwm_chip *chip, struct pwm_device= *pwm, struct pwm_state *state) { - u32 duty, period, ctrl; + u32 low, period, ctrl; struct pwm_loongson_ddata *ddata =3D to_pwm_loongson_ddata(chip); =20 - duty =3D pwm_loongson_readl(ddata, LOONGSON_PWM_REG_DUTY); + low =3D pwm_loongson_readl(ddata, LOONGSON_PWM_REG_LOW); period =3D pwm_loongson_readl(ddata, LOONGSON_PWM_REG_PERIOD); ctrl =3D pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); =20 - /* duty & period have a max of 2^32, so we can't overflow */ - state->duty_cycle =3D DIV64_U64_ROUND_UP((u64)duty * NSEC_PER_SEC, ddata-= >clk_rate); + /* low & period have a max of 2^32 - 1, so we can't overflow */ + if (low >=3D period) + state->duty_cycle =3D 0; + else + state->duty_cycle =3D + DIV64_U64_ROUND_UP((u64)(period - low) * NSEC_PER_SEC, ddata->clk_ra= te); + state->period =3D DIV64_U64_ROUND_UP((u64)period * NSEC_PER_SEC, ddata->c= lk_rate); state->polarity =3D (ctrl & LOONGSON_PWM_CTRL_REG_INVERT) ? PWM_POLARITY_= INVERSED : PWM_POLARITY_NORMAL; --=20 2.43.0 From nobody Thu Sep 24 21:19:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5641C3E5EF8; Sun, 20 Sep 2026 12:02:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789905772; cv=none; b=Ul2ZbD8fGKMjLsNeDFBaysYW2y5ruRc6SopCixFkVBDjHLvysd5w+5obVnMm18RM4HjRA3JpPhvaeqzPJqq2iVU1A5r4n6tvgesEPUO8i9e1iPMrdOUd1oSQ+LGO6oK9yo1zU58sJjljRjlnw2eyj+9UGgQ/LytmmZiAplfqLt8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789905772; c=relaxed/simple; bh=EmlQF7MKA+mSQxHFuLAhipdko6cuIMhOh4NeHmdUiNQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fSSGcW8CRZEhUgLuGJi9agpRoAZxOLG0KkHQ3e1FFD2gBuHn6+Y/MCO6Cw0a3ydC3VBCwxn+63hTfFqzaQh8MooA7Hssc5UEJ0dBPvZlFtrAlnYchnWxEYow2Cv2XpAsJELr6zI+4LBHpFh+EAdvbh7Tl4xvsvifr3MAq6pJI1g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UoNB6j/S; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UoNB6j/S" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1404BC2BCF6; Sun, 20 Sep 2026 12:02:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789905772; bh=EmlQF7MKA+mSQxHFuLAhipdko6cuIMhOh4NeHmdUiNQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UoNB6j/Sig6nuLWPcm+RHSGZ8zYCe7G7aIUU6lYpRikjQMtou0c3S4Gza9rungwfK g4JaKV19jIun6G3vG7OMBOarxbOl83sILFwatqqzJtMRZNyUW1PrVJ22PPIcG9NnTm ygpHEnyCpcMqqeOOCbouLiR1whwxP01A/nrrzXcgXBmnwElCVy87waiNTYjBn4XUfM 0RE2ddWTVtAiF7cVpOo5Z+kisvz/Ttj7zh6IUPs+kNbhN1samBpt9bRG1OhfsoZkUX +l+f6S0Erp/ojp9dfC4mvCsaaNwXYO6oji4Y94S3XYrZX44DnnxqFUv+UuSxv1oMa2 oLRaYJZvbWdJQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9EA6C982EB; Sun, 20 Sep 2026 12:02:51 +0000 (UTC) From: Keguang Zhang via B4 Relay Date: Sun, 20 Sep 2026 20:02:07 +0800 Subject: [PATCH v4 2/3] pwm: loongson: Reset the counters before enabling PWM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-pwm-loongson-fix-v4-2-41b36b3c6497@gmail.com> References: <20260920-pwm-loongson-fix-v4-0-41b36b3c6497@gmail.com> In-Reply-To: <20260920-pwm-loongson-fix-v4-0-41b36b3c6497@gmail.com> To: Binbin Zhou , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Keguang Zhang , stable@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789905770; l=1375; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=NyDNTlsnJdK4cl0ga4IeWZLMrmPfP3DVW7yBKqicjC4=; b=/Ly+hsfIlgz3pdAE1Sn8R2ixiFAUhwfEbv8E/4H2cjhVMkTojBjj4aAHFVbxAza5y5pS40oEg fvjNVzJg++YCwVn/bKGFN38eCoq0TFqK34L+aGve13mcv+iqyi0Gy61 X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang The PWM controller may retain its initial hardware state when the driver binds. Reset the counters before enabling to ensure that the PWM starts from a known state. Fixes: 2b62c89448dd ("pwm: Add Loongson PWM controller support") Fixes: 0de9b836a3bc ("pwm: loongson: Reload PWM configuration through count= er reset") Cc: stable@vger.kernel.org Suggested-by: Uwe Kleine-K=C3=B6nig Signed-off-by: Keguang Zhang --- drivers/pwm/pwm-loongson.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pwm/pwm-loongson.c b/drivers/pwm/pwm-loongson.c index 7af5d4ce1060..977d867bdb8a 100644 --- a/drivers/pwm/pwm-loongson.c +++ b/drivers/pwm/pwm-loongson.c @@ -110,6 +110,14 @@ static int pwm_loongson_enable(struct pwm_chip *chip, = struct pwm_device *pwm) struct pwm_loongson_ddata *ddata =3D to_pwm_loongson_ddata(chip); =20 val =3D pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); + + /* + * Ensure that the values of LOW and PERIOD are sampled into + * the shadow register when the hardware starts running. + */ + if (!(val & LOONGSON_PWM_CTRL_REG_RST)) + pwm_loongson_writel(ddata, val | LOONGSON_PWM_CTRL_REG_RST, LOONGSON_PWM= _REG_CTRL); + val &=3D ~LOONGSON_PWM_CTRL_REG_RST; val |=3D LOONGSON_PWM_CTRL_REG_EN; pwm_loongson_writel(ddata, val, LOONGSON_PWM_REG_CTRL); --=20 2.43.0 From nobody Thu Sep 24 21:19:37 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 563003D9691; Sun, 20 Sep 2026 12:02:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789905772; cv=none; b=dVx3H+JWbSvAS624FqVJ7b/8umGMC8a3eCwzMs3cJihD5Udfee7VecBNrI6y0rQYvW724neu8FldJ3NfBesZrnJ4A4fBuMuP4fOn5qjpBDb/y8Q/HwCotKqLw+MSZ1vLSmcuog9Ml+QJ39phVyM8FpV4wIl4k+OcvnYoYWlrSYM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789905772; c=relaxed/simple; bh=jxDt2zEfr+Z875on6vZ1E8Zc9mlwzhUL++PYpDz4v1I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K7qZe/PCdGV/CEnqid70UBvwGw3OVSzTtPDDoLi28Sx2NpXqR6+cEKX9lMRrm59CvUdU5huWiCnyoMbFb0GjQQtYPTsywBS1cI3ZdZ29mUJoUAdaWmK8s3DdhdTuWzLoJadozX8drV5Xt9tsOV9SevB+db2G26z2geQix7OCEKg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cd5T8QNZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cd5T8QNZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 221A7C2BCFC; Sun, 20 Sep 2026 12:02:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789905772; bh=jxDt2zEfr+Z875on6vZ1E8Zc9mlwzhUL++PYpDz4v1I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cd5T8QNZA6b0H4NimcwnGNtLaFKeO31mT5ufjQnNH5priiGnhTqfa1eN0Uqsk1Ri7 F3M4baP5EA+SjRU+vvc4mwL6fuQ0Tzfe3bjjy/IVzU5c+yS6NI0k3Wwg+dK9rxU/aX bkM5cR0cvTKyu9SJOwVN5zofHiGnA01o68L12fiIwy/ybLEarWCzMVDv5NtgHR7e3g Ntl3kF3XNlnJ48teIp7kr3psEAi4lODmFCuODl6IgPFJ/pbFtH5XaJOL+zOKLLYTrd RZNBYYeP9CALSwi6LfEy84aKhL4sfZWcXgXQWv+fGxUhNgjOjgGC/RcHHkM+jvEhid h/lyD9ADRf2OQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0553FC982DA; Sun, 20 Sep 2026 12:02:52 +0000 (UTC) From: Keguang Zhang via B4 Relay Date: Sun, 20 Sep 2026 20:02:08 +0800 Subject: [PATCH v4 3/3] pwm: loongson: Use field helpers for period validation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-pwm-loongson-fix-v4-3-41b36b3c6497@gmail.com> References: <20260920-pwm-loongson-fix-v4-0-41b36b3c6497@gmail.com> In-Reply-To: <20260920-pwm-loongson-fix-v4-0-41b36b3c6497@gmail.com> To: Binbin Zhou , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Keguang Zhang X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789905770; l=1574; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=y8tF/NQwV1xqRjbBFvvs1zZHcp9ww6rdG1gubXIGg+c=; b=MNU+K3C3DUDWEDrHPWSs95S3BRoARMbgu6OZqgwmWf09utvFBtGkD5IStGw3Sf60SWihY9VU/ neEUbOoSwltApQclCphLn2VZeqhCD/W/mVyNVZwEr9CobdvVNOBeJwG X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang Use FIELD_FIT() to validate the calculated period value and FIELD_MAX() to get the maximum value allowed by the 32-bit period field. Signed-off-by: Keguang Zhang --- drivers/pwm/pwm-loongson.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-loongson.c b/drivers/pwm/pwm-loongson.c index 977d867bdb8a..178a7a69a11c 100644 --- a/drivers/pwm/pwm-loongson.c +++ b/drivers/pwm/pwm-loongson.c @@ -22,6 +22,7 @@ */ =20 #include +#include #include #include #include @@ -37,6 +38,8 @@ #define LOONGSON_PWM_REG_PERIOD 0x8 /* Pulse Period Buffer Register */ #define LOONGSON_PWM_REG_CTRL 0xc /* Control Register */ =20 +#define LOONGSON_PWM_PERIOD_MASK GENMASK(31, 0) + /* Control register bits */ #define LOONGSON_PWM_CTRL_REG_EN BIT(0) /* Counter Enable Bit */ #define LOONGSON_PWM_CTRL_REG_OE BIT(3) /* Pulse Output Enable Control Bi= t, Valid Low */ @@ -133,8 +136,8 @@ static int pwm_loongson_config(struct pwm_chip *chip, s= truct pwm_device *pwm, =20 /* period =3D period_ns * ddata->clk_rate / NSEC_PER_SEC */ period =3D mul_u64_u64_div_u64(period_ns, ddata->clk_rate, NSEC_PER_SEC); - if (period > U32_MAX) - period =3D U32_MAX; + if (!FIELD_FIT(LOONGSON_PWM_PERIOD_MASK, period)) + period =3D FIELD_MAX(LOONGSON_PWM_PERIOD_MASK); =20 /* duty =3D duty_ns * ddata->clk_rate / NSEC_PER_SEC */ duty =3D mul_u64_u64_div_u64_roundup(duty_ns, ddata->clk_rate, NSEC_PER_S= EC); --=20 2.43.0