From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE5AC394497; Sun, 20 Sep 2026 11:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903073; cv=none; b=f5YBbd8UXxLftIMJ5cOqye+OXATcZfH1GqCei0WYFH/Alfl+kqXl0GqBzA0xGQT/QFA5y2IbcIpZRHfvBRFosulnTa9ko/+XN/Yga0BEaoHF1g59laC+CxcvFmvhic468nkcw0CGxpjeJjvdlFxtoni7HAZ5hqrFZJ8z/WG/l4E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903073; c=relaxed/simple; bh=4Obo9XjIF0UkNH8AWri0rSIBncxG4P+FKPM/rfdlUYk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qC0M1cYmUOpl00+2UzSRt6F3UkpXBhya471HJySdFUHlU+URgzPnE0AfsZkFpPNEZxJuFqJB1oifV0gksNXl0yob5hB1a3iHo+EoRL2rx0hRxPw/pFjS3EPrsOv2yXgzoZWDyG698jrH1OH3FPdwMuj22B8LMpdRDpKBXz1YhL8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=Rbb9uuT2; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="Rbb9uuT2" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36O088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:08 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=zmfuG+7dS3FcYFGM455cq0LUuDyDjiU3XUc0eMviZCU=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902968; v=1; b=Rbb9uuT2coqtm36v3HFjEpsHy109ixacCKT60ybmEKoONtVBGERz59oyiX3u5XxY Nma9hoGUvVDmoja+DjQvk+sNqNSWLKoqcM2ArLaMGNYoDoc4jip/vbGUPDlrGmqz DFD1RakXFcgskRGnehj8HJvj57cpwxvUSDBLZSVRn25zNiYvG2jvIKjZLpSrzna9 pDdTR2WK10H7spQslASJEmH9/eCQ/ELMSV/BaGILp16EhoKQdSnYXYrWpjdl5Y1U Xa9yR1Z5RHKG7AAYXo3MOBQUJuWfzgeXG41fS9KqPDO8C56J8dDDf0E/6vn5eZtk R7cL0QnNJIUIC9M4sKia0Q== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:42 +0900 Subject: [PATCH v11 01/21] KVM: arm64: Serialize repeated vCPU initialization Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-1-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2195; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=4Obo9XjIF0UkNH8AWri0rSIBncxG4P+FKPM/rfdlUYk=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A8n8r0rTYp6ra6+1enjkVaabcdZRtfpWJt1LKbX1P 3y+TyjtKGVhEONikBVTZEkp2s2tEV37qTAhvgVmDisTyBAGLk4BmEiqJSPDAtm29tsRrGpuc2Z1 m3xMeaQqangs43/ld/kfNkl6s7ctY2S45Xx9ftg7N+2qCilDYdPfc6xXT17CG9W00dfK8tELW2s +AA== X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C The initial KVM_ARM_VCPU_INIT path holds config_lock while resetting the vCPU, but repeated initialization of an existing vCPU does not. As a result, reset_mdcr() can race with VM-wide PMU configuration and overwrite MDCR_EL2 with a stale counter count. Take config_lock around the repeated-init checks and reset. The vCPU ioctl already holds vcpu->mutex, matching the established lock ordering. Fixes: c8823e51b534 ("KVM: arm64: Fix MDCR_EL2.HPMN reset value") Closes: https://sashiko.dev/#/patchset/20260710-hybrid-v8-0-621409f3a592@rs= g.ci.i.u-tokyo.ac.jp?part=3D1 Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- arch/arm64/kvm/arm.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index b0de4ea7dc39..997f24f5fb91 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1691,29 +1691,26 @@ static int __kvm_vcpu_set_target(struct kvm_vcpu *v= cpu, { unsigned long features =3D init->features[0]; struct kvm *kvm =3D vcpu->kvm; - int ret =3D -EINVAL; + int ret; =20 - mutex_lock(&kvm->arch.config_lock); + lockdep_assert_held(&kvm->arch.config_lock); =20 if (test_bit(KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED, &kvm->arch.flags) && kvm_vcpu_init_changed(vcpu, init)) - goto out_unlock; + return -EINVAL; =20 bitmap_copy(kvm->arch.vcpu_features, &features, KVM_VCPU_MAX_FEATURES); =20 ret =3D kvm_setup_vcpu(vcpu); if (ret) - goto out_unlock; + return ret; =20 /* Now we know what it is, we can reset it. */ kvm_reset_vcpu(vcpu); =20 set_bit(KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED, &kvm->arch.flags); vcpu_set_flag(vcpu, VCPU_INITIALIZED); - ret =3D 0; -out_unlock: - mutex_unlock(&kvm->arch.config_lock); - return ret; + return 0; } =20 static int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, @@ -1729,6 +1726,8 @@ static int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, if (ret) return ret; =20 + guard(mutex)(&vcpu->kvm->arch.config_lock); + if (!kvm_vcpu_initialized(vcpu)) return __kvm_vcpu_set_target(vcpu, init); =20 --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 109353F58CC; Sun, 20 Sep 2026 11:17:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="v+YAKWhf" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36P088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:08 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=iyM9QAloEsP9dHXX9S9zolMEUPTEvUttQXAYPXDanF8=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902969; v=1; b=v+YAKWhfBB78+5AU9ZHlXoG3gxkYyh6DL1SgC6gfBMXlZNow03UMiA/sNIwqc7Oc Sfcd2egNf1+9fSzZBu681vnt97fEd2XLEAWU72bi50UkAHQCDuEbSP046N8EuV1p FYhZAj2b5xjBxNs3uPLl05FdzwbH9z7r1zaIwSaaOYhY90jC94id9ExOQF0yrdoT 6pCsCuJSiX3r2PB1c7P11UHB2OMsLBmYxGLZOINOD8zvqcM8MeNQ8t0h79XR3ohp f2JQYTYiDlQcb9u5g4cR9d65hVwWN1AnhQ0FeRbXVU2e4Dqvz+zc7EEZRpz+q1EV mFwfm1fvkjTHZ9OIDqFl6g== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:43 +0900 Subject: [PATCH v11 02/21] KVM: arm64: PMU: Stop updating MDCR_EL2.HPMN Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-2-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2373; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=ZwHCND4TvpKjwaPcx6aqpVFdzyPHWHl27WcGIFnygC4=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6Aym2Riq1U5xdzYqWRnS9laxp2HBDj//Fqd8dFy5Pu 5U180VbRykLgxgXg6yYIktK0W5ujejaT4UJ8S0wc1iZQIYwcHEKwETaNRn+SufGvOjd3+tY9Ffz 57ooEYFNNU829QTzdK99XHJbLdf/HCPDs1trD/1VVCp6dvBf/GpXbfb2BiHfl4ZTzpZobbgS9eo nDwA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C KVM allows userspace to write any value to MDCR_EL2.HPMN. However, kvm_arm_set_nr_counters() rewrites HPMN for every vCPU whenever userspace changes the PMU or its counter count. This can discard a value previously restored with KVM_SET_ONE_REG. The architecture only defines HPMN's value on warm reset. Stop rewriting it after vCPU initialization and update nr_pmu_counters directly instead. reset_mdcr() continues to initialize HPMN from the counter count current at KVM_ARM_VCPU_INIT. Fixes: c8823e51b534 ("KVM: arm64: Fix MDCR_EL2.HPMN reset value") Closes: https://sashiko.dev/#/patchset/20260706-hybrid-v8-0-de459617b59d%40= rsg.ci.i.u-tokyo.ac.jp?part=3D6 Assisted-by: Codex:gpt-5.5 Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- arch/arm64/kvm/pmu-emul.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 5b1af7e2176f..832dd145af2a 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -1035,30 +1035,12 @@ u8 kvm_arm_pmu_get_max_counters(struct kvm *kvm) return bitmap_weight(arm_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS); } =20 -static void kvm_arm_set_nr_counters(struct kvm *kvm, unsigned int nr) -{ - kvm->arch.nr_pmu_counters =3D nr; - - /* Reset MDCR_EL2.HPMN behind the vcpus' back... */ - if (test_bit(KVM_ARM_VCPU_HAS_EL2, kvm->arch.vcpu_features)) { - struct kvm_vcpu *vcpu; - unsigned long i; - - kvm_for_each_vcpu(i, vcpu, kvm) { - u64 val =3D __vcpu_sys_reg(vcpu, MDCR_EL2); - val &=3D ~MDCR_EL2_HPMN; - val |=3D FIELD_PREP(MDCR_EL2_HPMN, kvm->arch.nr_pmu_counters); - __vcpu_assign_sys_reg(vcpu, MDCR_EL2, val); - } - } -} - static void kvm_arm_set_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) { lockdep_assert_held(&kvm->arch.config_lock); =20 kvm->arch.arm_pmu =3D arm_pmu; - kvm_arm_set_nr_counters(kvm, kvm_arm_pmu_get_max_counters(kvm)); + kvm->arch.nr_pmu_counters =3D kvm_arm_pmu_get_max_counters(kvm); } =20 /** @@ -1136,7 +1118,7 @@ static int kvm_arm_pmu_v3_set_nr_counters(struct kvm_= vcpu *vcpu, unsigned int n) if (n > kvm_arm_pmu_get_max_counters(kvm)) return -EINVAL; =20 - kvm_arm_set_nr_counters(kvm, n); + kvm->arch.nr_pmu_counters =3D n; return 0; } =20 --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D6FE3FCB10; Sun, 20 Sep 2026 11:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-3-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1162; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=MrNqsf8vl79pbAxP49QCfE5TLu/s5O9EUAaIBtYYaqg=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A6mrD1z5vilWVrfGcs7FU0/+ayX3nOlcpnzU2NNdb 1d2Xp9RRykLgxgXg6yYIktK0W5ujejaT4UJ8S0wc1iZQIYwcHEKwESsrzD892bUPfGsa2OmuNom TpF0vhDW8NcsfcuYXugWzBe2vGc9neGfJctU3as6p2cUnTneJXuy7sbuJSrnltjsjJMLqW70cyv gBwA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C PMU configuration is VM-scoped, but SET_NR_COUNTERS can be issued through any vCPU. Checking only whether that vCPU's PMU has been initialized allows userspace to change the counter count through an idle sibling after another vCPU has run. Reject the attribute once any vCPU has run. This keeps the VM-wide implemented counter mask and the PMCR_EL0.N value stable after guest execution begins. Fixes: b7628c797376 ("KVM: arm64: Allow userspace to limit the number of PM= U counters for EL2 VMs") Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- arch/arm64/kvm/pmu-emul.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 832dd145af2a..950b7a349659 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -1112,6 +1112,9 @@ static int kvm_arm_pmu_v3_set_nr_counters(struct kvm_= vcpu *vcpu, unsigned int n) { struct kvm *kvm =3D vcpu->kvm; =20 + if (kvm_vm_has_ran_once(kvm)) + return -EBUSY; + if (!kvm->arch.arm_pmu) return -EINVAL; =20 --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 975DE3FE34D; Sun, 20 Sep 2026 11:17:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903072; cv=none; b=XEQprAlvxqDNM0sRMS+Bxw+d51cKiAi4UjMHP1PNUU9OxJhc/rRiVFrsIu3lFZzSaiJjcYsDB6HfqoIy/9WmSErRmRKgVMdn5+8kVonTVza+4Gd+SJnKXb20xz59/ZQJAwARr9QB7zzqp1PgBG/U/yIZRUIyGu0YCpEP+8wcTNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903072; c=relaxed/simple; bh=7qyZ3yw8xwXvroToHAs5qx3zfIpA0akFceWmVOkFa8E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=r/IBu5mxqT5sVfcD7ju098K58dYaF0vgUmQrgPlElVcxHbc2ErAoz1bTy3CinBOIwuz7Z2xmS2B5CcMLJKQOD2E5mkT6GszgBzN2b0TWnfuym/Q5BjkG0iP8/lgRWp+1ZzybDokEO6xnTWn6/6z5eXNgvhyooyM7pBp5Cfd/7EM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=swLXvuxC; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="swLXvuxC" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36R088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:09 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=CpstWXsEGNxvTAnG53+JLBqVzfY5FoROk7Pvi0Mk+sY=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902970; v=1; b=swLXvuxCmaz8hB04AEW2oFrcON647nR1UZTKe4ffJumEjp8MwV04mAcw7Tszh5kk rIR4jQq2ERwzr3gHkpCW8a4XMpn/b0O/7or2OjHupmFhUHQaG04SlEx2aKcTQv+C eBnAvwCtAlI881VIIebctlKfQPILNl6dRbCuPMELx0Wdu1AAZR9wO+naO366C7BT I1eWgTPvMegh3THZvdq7orqHnUt/MeP8ZDF65Vfuh5ZRMVTQiATHXOFH25lvHuEF 1j7sxL2da5EF+ei3qtnc3hq8y54tJzMEEdLcZUk4gvaPgCFpSNyxGEMThPCWESMK 6qaXH5Qy00xhxk8BOH7kpg== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:45 +0900 Subject: [PATCH v11 04/21] KVM: arm64: selftests: Test SET_NR_COUNTERS after first run Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-4-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3449; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=7qyZ3yw8xwXvroToHAs5qx3zfIpA0akFceWmVOkFa8E=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A2lXr+g7PReYfHOn6usjIZ/dmvRe1F09wP3FpOeE3 9l5R7lcOkpZGMS4GGTFFFlSinZza0TXfipMiG+BmcPKBDKEgYtTACYSvpzhv9tLz/1h7+6p8CiL MO7inyL9vfzY2p8dzsLpJ7sF2R5VXWb4K/w1d+XRP88/m8rJORQ/Y9YuEbTuLtA7O/fsp/8KXS6 u3AA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C Add a regression test that runs one vCPU and then tries to change the VM-scoped PMU counter count through an idle sibling. Verify that SET_NR_COUNTERS fails with EBUSY once any vCPU has run. Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Akihiko Odaki --- .../selftests/kvm/arm64/vpmu_counter_access.c | 47 ++++++++++++++++++= ++-- 1 file changed, 43 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c b/tool= s/testing/selftests/kvm/arm64/vpmu_counter_access.c index 22223395969e..05135bcdb462 100644 --- a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c +++ b/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c @@ -443,11 +443,10 @@ static void destroy_vpmu_vm(void) kvm_vm_free(vpmu_vm.vm); } =20 -static void run_vcpu(struct kvm_vcpu *vcpu, u64 pmcr_n) +static void run_vcpu(struct kvm_vcpu *vcpu) { struct ucall uc; =20 - vcpu_args_set(vcpu, 1, pmcr_n); vcpu_run(vcpu); switch (get_ucall(vcpu, &uc)) { case UCALL_ABORT: @@ -461,6 +460,11 @@ static void run_vcpu(struct kvm_vcpu *vcpu, u64 pmcr_n) } } =20 +static void guest_code_done(void) +{ + GUEST_DONE(); +} + static void test_create_vpmu_vm_with_nr_counters(unsigned int nr_counters,= bool expect_fail) { struct kvm_vcpu *vcpu; @@ -503,7 +507,8 @@ static void run_access_test(u64 pmcr_n) /* Save the initial sp to restore them later to run the guest again */ sp =3D vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1)); =20 - run_vcpu(vcpu, pmcr_n); + vcpu_args_set(vcpu, 1, pmcr_n); + run_vcpu(vcpu); =20 /* * Reset and re-initialize the vCPU, and run the guest code again to @@ -516,7 +521,8 @@ static void run_access_test(u64 pmcr_n) vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), sp); vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (u64)guest_code); =20 - run_vcpu(vcpu, pmcr_n); + vcpu_args_set(vcpu, 1, pmcr_n); + run_vcpu(vcpu); =20 destroy_vpmu_vm(); } @@ -622,6 +628,37 @@ static bool kvm_supports_nr_counters_attr(void) return supported; } =20 +static void test_set_nr_counters_after_vcpu_run(void) +{ + struct kvm_vcpu *running_vcpu, *stopped_vcpu; + unsigned int nr_counters =3D 0; + struct kvm_vcpu_init init; + struct kvm_vm *vm; + int ret; + u64 irq =3D 23; + + vm =3D vm_create(2); + vm_ioctl(vm, KVM_ARM_PREFERRED_TARGET, &init); + init.features[0] |=3D BIT(KVM_ARM_VCPU_PMU_V3); + running_vcpu =3D aarch64_vcpu_add(vm, 0, &init, guest_code_done); + stopped_vcpu =3D aarch64_vcpu_add(vm, 1, &init, guest_code_done); + kvm_arch_vm_finalize_vcpus(vm); + + vcpu_device_attr_set(running_vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_IRQ, &irq); + vcpu_device_attr_set(running_vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_INIT, NULL); + run_vcpu(running_vcpu); + + ret =3D __vcpu_device_attr_set(stopped_vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERS, + &nr_counters); + TEST_ASSERT(ret =3D=3D -1 && errno =3D=3D EBUSY, + KVM_IOCTL_ERROR(KVM_SET_DEVICE_ATTR, ret)); + + kvm_vm_free(vm); +} + int main(void) { u64 i, pmcr_n; @@ -630,6 +667,8 @@ int main(void) TEST_REQUIRE(kvm_supports_vgic_v3()); TEST_REQUIRE(kvm_supports_nr_counters_attr()); =20 + test_set_nr_counters_after_vcpu_run(); + pmcr_n =3D get_pmcr_n_limit(); for (i =3D 0; i <=3D pmcr_n; i++) { run_access_test(i); --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09039409270; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-5-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2094; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=qrWSZiXd3NGTtjPsYculaMGwRl4ZEKcQtXcXafdCzEE=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A2mzvy3l7FFbOK3uPIvZ5NgboX8TJF+0xXw6bfBi5 bUG0y6RjlIWBjEuBlkxRZaUot3cGtG1nwoT4ltg5rAygQxh4OIUgIloVzD8T0kvrXlxb/ESN/1V 6kbsy0umtcrf/Mv7Q+ez+arnrJ0pUxn+uxSz7Fm/62ta4SHWexOD/ovXNdfeZfWtqVhqlVuunPi bBQA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C MDCR_EL2.HPMN reserves event counters for EL2. Their bits in the PMU counter-enable, interrupt-enable, and overflow-status registers must read as zero at lower exception levels. The guest access handlers already mask writes, but return the raw bitmap on reads, exposing EL2-reserved state to the nested guest. Apply the accessible counter mask to reads in all three handlers, covering both SET and CLR aliases. Leave the stored state and userspace migration accesses unchanged so EL2-reserved bits remain preserved. Fixes: 9a1c58cfefb0 ("KVM: arm64: nv: Adjust range of accessible PMCs accor= ding to HPMN") Closes: https://sashiko.dev/#/patchset/20260914-hybrid-v10-0-92788053a691@r= sg.ci.i.u-tokyo.ac.jp?part=3D6 Assisted-by: Codex:gpt-6-astra Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/sys_regs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 40927a4d4409..68339eb8a2bb 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1362,7 +1362,7 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, =20 kvm_pmu_reprogram_counter_mask(vcpu, val); } else { - p->regval =3D __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); + p->regval =3D __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; } =20 return true; @@ -1386,7 +1386,7 @@ static bool access_pminten(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, /* accessing PMINTENCLR_EL1 */ __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, &=3D, ~val); } else { - p->regval =3D __vcpu_sys_reg(vcpu, PMINTENSET_EL1); + p->regval =3D __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; } =20 return true; @@ -1466,7 +1466,7 @@ static bool access_pmovs(struct kvm_vcpu *vcpu, struc= t sys_reg_params *p, /* accessing PMOVSCLR_EL0 */ __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=3D, ~(p->regval & mask)); } else { - p->regval =3D __vcpu_sys_reg(vcpu, PMOVSSET_EL0); + p->regval =3D __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; } =20 return true; --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55DA63EFFA6; Sun, 20 Sep 2026 11:17:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903074; cv=none; b=YCaFx1MV7qS7P2mNia9lF0QMNILrZVna4GvpQCVnFxR9+VH4k/g4FxUTLT8HINGcI5E9HzYl4q1QO+VngpwiLk5oMEB0UmPwu1ixpmDKRiN3aT85jImNzCf7nkuodq39W1L+BaAG/kXEFDWOWxh/6E97UvyCRN7Wv3EbUd4ridg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903074; c=relaxed/simple; bh=OkvBLyzd2QOHEMuSfHYwvhh6JbY910F/L4YLee/eXFI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c/HEQz8uBJjvZrAx8Wf5ezmPlEPOXk+mctqn1f1VUc+Q6MJ0AVOuCXYk3qfXCJq545wufIfYlJuv3l5DjXatzHV4lbTA0+kZrNe8YHXzuP6XdZILmmtYh6lkd52NHiFLVcAE6/u808MJG23uogatiigjsPw0lT8qa6eMmODIBvc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=DZ7tb1Zg; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="DZ7tb1Zg" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36T088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:10 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=ZW/Tdj3bVLx1UwE3X/hNQWAdAvY+Hiob2QqqnLyGvfE=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902971; v=1; b=DZ7tb1Zg7KJa7r9NzOcrdVSkBeYjnnHwOMG/8kMHjjYtgwSxzHF53V29mspJ0tEr 43zUWR1U/DxM7/AwCtqitnPnYdtAE/WOA2lW2VvQJbzk5oAwIbX0HucRH3/Xuilr PRIruXe/v04gCEvdJHFHWWtb8+hIDGN/aQnJqYAemIZKjAVZIRyEkobgwoc6m69P pSMjp4wIuNx6Iud63Cs3nV7QUDggBRa41RzEkLL21HFgBAXN9Q9i2E8XFL8m//Vq zG9m8wJ28I/8bMBa6fohZU78V3SsARSwpSEurQPL5KWJGaEfBzr0IZKIYJmDLp5W 5k65ECzCRmKoUn9OUYKqDg== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:47 +0900 Subject: [PATCH v11 06/21] KVM: arm64: PMU: Keep implemented counter mask EL-independent Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-6-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1575; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=OkvBLyzd2QOHEMuSfHYwvhh6JbY910F/L4YLee/eXFI=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A+nXOiXZp7lr/YvNnvj95sVnjqpq9dVP8yzKXaZ+2 lDsfL+no5SFQYyLQVZMkSWlaDe3RnTtp8KE+BaYOaxMIEMYuDgFYCJxcgz/NCL+829oKJn7QtpR 9uUCT96dh3+xsz+QNFx9SCp914OV7YwMbwI0OAINj9Vv2sIltv9Rh9eXs9e+cRrfv2AvVmZdYCT GAQA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C kvm_pmu_implemented_counter_mask() derives the counter count from kvm_vcpu_read_pmcr(). For a nested vCPU outside EL2, PMCR_EL0.N reflects MDCR_EL2.HPMN instead of the VM-wide counter count. Consequently, processing a PMU reload while the saved context is L2 can clear and fail to recreate state for counters reserved for EL2. Build the implemented counter mask from nr_pmu_counters instead. Keep the EL-dependent HPMN restriction in kvm_pmu_accessible_counter_mask(), where it controls guest access. Fixes: 600f6fa5c90c ("KVM: arm64: Let kvm_vcpu_read_pmcr() return an EL-dep= endent value for PMCR_EL0.N") Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- arch/arm64/kvm/pmu-emul.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 950b7a349659..a5ccb6ae44d5 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -317,12 +317,12 @@ u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *= vcpu) =20 u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu) { - u64 val =3D FIELD_GET(ARMV8_PMU_PMCR_N, kvm_vcpu_read_pmcr(vcpu)); + u64 n =3D vcpu->kvm->arch.nr_pmu_counters; =20 - if (val =3D=3D 0) + if (n =3D=3D 0) return BIT(ARMV8_PMU_CYCLE_IDX); else - return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX); + return GENMASK(n - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX); } =20 static void kvm_pmc_enable_perf_event(struct kvm_pmc *pmc) --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E9D63DD87B; Sun, 20 Sep 2026 11:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903071; cv=none; b=s9sAtXmRL2l+Gc+yLELXgV6BlZdVeHPvP7e/77Yiecj9VBS8fmsjSOrErqikWhDSRuX4GIYKC4FfqWGbYtwoa5hUy8wGHLjROsVJCjwTW1fbN3W7afA0PcLddmsxVbmDwgnDBXEIVizJIYwgjuqXwnHVUwN1PaVvV4h6NagqEjk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903071; c=relaxed/simple; bh=zZgZ4E/7GvFKuRnHJ2O0skLAFoIrn8uGNQ0FHJ7QW/M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oXxuqfOl1Q81GgsCTJqCzKexcBct/7orXk1s1wQ1HbSKC4CnSso/bf1HSkLZU07dVFCuLvLrmJNhvsYgR7r1JYv15sVe0AhpZ30dWwZ/71Z7gQre19BCpVY055HUQTsz5fs9vrL12NjG1ypioT98JQ63EzFoSomRN+6VqDKdYKM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=mqipogMp; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="mqipogMp" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36U088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:11 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=DENRYgHAK3UACZwCFLPZe6QgWQYGpL5JlKUCkqC2eUQ=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902971; v=1; b=mqipogMpdwv5y4nALGP1s4wqzmH16k0QVrhFGGlFiLRlCyCSrTyGGs1r8pU2BAVe E2pwMLcFyuFR2D3cFj5r5l0cXhNouctZUFeN9G0s/WXA1faDTo2ZJNa1bmx//RGr Qy+RPckKnBbO5VMtOoGZrs7eBn8fN/39JAwqy0UgvTA5g43rMnyGa5TPTKvlbl0K TEbr1ZMXwy6G/mkTXPw03XdCmI9pBLUfnqwsET2/droxm45mxjr1K0AEi2NfqVJf LHJccJyBLi0n2oGm8xYNRHUbQ95THja5mMcelaTp2SJlhUJGg+IJtawNglPQyXHJ WRBxicyoTibH+cRXllTu8A== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:48 +0900 Subject: [PATCH v11 07/21] KVM: arm64: PMU: Preserve EL2 bitmap state during migration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-7-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1745; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=zZgZ4E/7GvFKuRnHJ2O0skLAFoIrn8uGNQ0FHJ7QW/M=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6AxkhNiGPimMcPsxK9hDTS9zdwxF/T3CK/51pajkms TMaup51lLIwiHExyIopsqQU7ebWiK79VJgQ3wIzh5UJZAgDF6cATMRkHSNDz1TW7Tedhc5aeW7k Yi+M6wlh4f0qVXnqrobHhmLld7cFGRnOsHs/qWa6kmfS/erL/y4tr37+LpPKR+7vrt3Tcdrr+Io NAA== X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C KVM_GET_ONE_REG and KVM_SET_ONE_REG transfer raw vCPU state for migration. Masking PMU bitmap registers with counters accessible at the current EL drops EL2-reserved bits when the vCPU is stopped in EL1 or EL0. Use the implemented counter mask for these userspace accesses so the complete bitmap state survives migration. Guest register accesses continue to use the accessible counter mask. Assisted-by: Codex:gpt-5.6-sol Fixes: 9a1c58cfefb0 ("KVM: arm64: nv: Adjust range of accessible PMCs accor= ding to HPMN") Closes: https://sashiko.dev/#/patchset/20260720-hybrid-v9-0-2b713ca1b5dc@rs= g.ci.i.u-tokyo.ac.jp?part=3D5 Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/sys_regs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 68339eb8a2bb..1481dd5c99a8 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1326,7 +1326,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu,= struct sys_reg_params *p, =20 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, = u64 val) { - u64 mask =3D kvm_pmu_accessible_counter_mask(vcpu); + u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); =20 __vcpu_assign_sys_reg(vcpu, r->reg, val & mask); kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); @@ -1336,7 +1336,7 @@ static int set_pmreg(struct kvm_vcpu *vcpu, const str= uct sys_reg_desc *r, u64 va =20 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, = u64 *val) { - u64 mask =3D kvm_pmu_accessible_counter_mask(vcpu); + u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); =20 *val =3D __vcpu_sys_reg(vcpu, r->reg) & mask; return 0; --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EB0F3F413E; Sun, 20 Sep 2026 11:17:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903070; cv=none; b=hXFOYs+tgs3jFF2k5IpaVgPnxfB8YhMen0HQrDVG4MJPYafCo2PY2XxPX8z1yxkAH22npjRb8Ttqdyz1w76Emy10MgzKpx3Ff0lxSyVAJYh3NoW0Kaf5xncY2AOiaNX3+w8UutPfK/PX9ex0F5BtSxYcyw0W1INt4vwZVuqpTgY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903070; c=relaxed/simple; bh=SdD7QKCPzHpguy40o7rYhu+tBzjzpk28GiGdpXJQFh8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=scG7eRfLfGaOw8tfkJqDssfApGOOyVzZdTb+lMqnBjSqDSuIEI4yFIYmruAXWm6WmWYDsKaYF457AQQCgEj4lThlmGQHn9gtVSCgwJVrGQ8ASTMsgiQX1tY7GxwEwVSd8W63CHjzQSpC66kU1oNJro3OKh8KvH0OBhWLM0bAxPQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=X2oaeVfx; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="X2oaeVfx" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36V088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:11 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=QcYwkKg0EnciG/3+VJYlWGWl/x9B81dAxeYRS4KaIBc=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902972; v=1; b=X2oaeVfxSYXc1L08PH182vqPfSKgjIFM6u1YkSiADOqBOBNuLPBTYaNm7OIAST8o itmJ2FVb4gn6LXNQB+XLMHkCPF+m6seBINGdINZ3fJ6EZxh/b+A5+aiVJ6av0Daq vYfsPv4qM27O4sAvDqSogxEgdQ7wAfForxfWBkZwoqcVH6Vd+o5pPu1TjkxaPUXo VMj/iWuwQw5UTJ9gUnQ6X8JdJYsOs4E2ofm+c38RXY/CC5hSEo5389NBU3ydFFm5 ZzdjExLn5JD5G6lcHbmt1fK1ofpQPx6FXzXnzengfkqWWoasyRcAUdPQThNUQDAQ gcno27do6srUEHIzMLZNGg== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:49 +0900 Subject: [PATCH v11 08/21] Revert "KVM: arm64: PMU: Reload when resetting" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-8-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3326; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=SdD7QKCPzHpguy40o7rYhu+tBzjzpk28GiGdpXJQFh8=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A5l3bOt9p00LXH7K+YlsZ19ik0tHe+D8LyeVS/law 5293kp2lLIwiHExyIopsqQU7ebWiK79VJgQ3wIzh5UJZAgDF6cATOTSRYY/PNvqa9fmNSbHrtrL byy48w7PYT5/PoHdh1X173AeiZSOYmToPfXn+a5bm/LZuJdUzHHxkLxidvG69NG+9okls0WWb/7 GAwA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C This reverts commit fe53538069bb4f625bc8734103ba044a83138fea. Restore PMU event teardown before system-register reset so existing perf events cannot retain configuration from the previous run. All counters are disabled by the reset PMCR_EL0 and MDCR_EL2 values, so reset does not need to request a PMU reload. Assisted-by: Codex:gpt-6-astra Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/pmu-emul.c | 14 ++++++++++++++ arch/arm64/kvm/reset.c | 3 +++ arch/arm64/kvm/sys_regs.c | 3 --- include/kvm/arm_pmu.h | 2 ++ 4 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index a5ccb6ae44d5..14fcdbdb4587 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -258,6 +258,20 @@ void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) pmu->pmc[i].idx =3D i; } =20 +/** + * kvm_pmu_vcpu_reset - reset pmu state for cpu + * @vcpu: The vcpu pointer + * + */ +void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) +{ + unsigned long mask =3D kvm_pmu_implemented_counter_mask(vcpu); + int i; + + for_each_set_bit(i, &mask, 32) + kvm_pmu_stop_counter(kvm_vcpu_idx_to_pmc(vcpu, i)); +} + /** * kvm_pmu_vcpu_destroy - free perf event of PMU for cpu * @vcpu: The vcpu pointer diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 10eb7249aa9e..adcb460a5287 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -185,6 +185,9 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu) vcpu->arch.reset_state.reset =3D false; spin_unlock(&vcpu->arch.mp_state_lock); =20 + /* Reset PMU outside of the non-preemptible section */ + kvm_pmu_vcpu_reset(vcpu); + preempt_disable(); loaded =3D (vcpu->cpu !=3D -1); if (loaded) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1481dd5c99a8..75624725adf1 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -5388,9 +5388,6 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) } =20 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); - - if (kvm_vcpu_has_pmu(vcpu)) - kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); } =20 /** diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 6b4a118d17ca..51f5e4ca3326 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -48,6 +48,7 @@ u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcp= u); u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu); u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1); void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu); +void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu); void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu); void kvm_pmu_reprogram_counter_mask(struct kvm_vcpu *vcpu, u64 val); void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu); @@ -125,6 +126,7 @@ static inline u64 kvm_pmu_accessible_counter_mask(struc= t kvm_vcpu *vcpu) return 0; } static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {} +static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {} static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {} static inline void kvm_pmu_reprogram_counter_mask(struct kvm_vcpu *vcpu, u= 64 val) {} static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {} --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 238893FD137; Sun, 20 Sep 2026 11:17:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="UIVtESW1" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36W088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:12 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=oO8ZjRFXZ0qt7IgcgpYC4Wj+eVf2OYiOjkCtfATq4V8=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902972; v=1; b=UIVtESW1R1rtJeUqvKjAMoxDo1sq+7UuT6yJyyle0ylezbtTKp70ifBwRgOHVlfJ kAuA2Q4/JYA0taKRGgGlsTfRLJHZReK487jUn0FIJwXnkmQuQCeOk6VDNevkFJOF vtUnVqbAiOoo5sgtINBJFOlCH0brWmDTAAs8PtqWWTnrvop7HYBopRzkkb09mmwh Pm3xnn98VCDTMKSDQyo+ddIZsNKiK318avXMpa5kEUX3SQM4onLAa2oGsy+mYeIm nK4QCsD4tDFL1JglycNrvPoxkp792MFvSV7Nl5N0nlxmkI0q3jK4lO3/bKa28s0i 8GQtVYbSKI4kIgbWOWYWMA== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:50 +0900 Subject: [PATCH v11 09/21] KVM: arm64: PMU: Recreate events after MDCR_EL2 changes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-9-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6379; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=+1MHjEcho65DrRBCEyZyzH1H5cMIdbCh4zca1DnceGU=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A5kaPy9Y6TrOuvir57K0fmjY0Y9vVj5NCWJgXtgtu bRoykamjlIWBjEuBlkxRZaUot3cGtG1nwoT4ltg5rAygQxh4OIUgImsv8nI8M16c/G23f1MUUye XlaKTU58hh8jt2+7vOhwweN1ITHRmxj+OzHuueDw5/7r65u//V1f1zE9bHH3F8G8p1JlBrM32vw /xQ8A X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C MDCR_EL2.HPMN changes which counters are reserved for EL2 and thus which enable control, event filter, and overflow width apply. HPMD changes EL2 filtering, while HLP changes the overflow width and sample period. The existing guest MDCR_EL2 handling only requests a PMU reload for HPME. Reloading enables or disables existing perf events, but does not rebuild events whose attributes have become stale. Generic userspace writes through KVM_SET_ONE_REG do not request a reload at all. Add a deferred event-recreation request that stops existing events before reprogramming counters on the vCPU thread. Use a common helper for guest and userspace writes. Recreate events after HPMN, HPMD, or HLP changes. This preserves counter values. Defer event creation to the vCPU thread instead of an arbitrary ioctl thread. Use a setter-only accessor so register restore gains these side effects without changing generic reads or rejecting register values. Fixes: fe827f916662 ("KVM: arm64: nv: Honor MDCR_EL2.HPME") Fixes: 8a34979030f6 ("KVM: arm64: nv: Apply EL2 event filtering when in hyp= context") Fixes: 16535d55e91f ("KVM: arm64: nv: Honor MDCR_EL2.HLP") Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- arch/arm64/kvm/pmu-emul.c | 29 +++++++++++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 22 ++++++++++++++-------- include/kvm/arm_pmu.h | 5 +++++ 3 files changed, 48 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 14fcdbdb4587..a8449e533070 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -585,6 +585,12 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu,= u64 val) kvm_pmu_counter_increment(vcpu, val, ARMV8_PMUV3_PERFCTR_SW_INCR); } =20 +void kvm_pmu_request_recreate(struct kvm_vcpu *vcpu) +{ + vcpu->arch.pmu.events_need_recreate =3D true; + kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); +} + /** * kvm_pmu_handle_pmcr - handle PMCR register * @vcpu: The vcpu pointer @@ -620,6 +626,20 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 va= l) } } =20 +void kvm_pmu_apply_mdcr(struct kvm_vcpu *vcpu, u64 old, u64 val) +{ + u64 changed =3D old ^ val; + + /* + * HPMN determines which counters HPMD and HLP apply to. Changes to + * these fields require new perf event filters and sample periods. + */ + if (changed & (MDCR_EL2_HPMN | MDCR_EL2_HPMD | MDCR_EL2_HLP)) + kvm_pmu_request_recreate(vcpu); + else if (changed & MDCR_EL2_HPME) + kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); +} + static bool kvm_pmu_counter_is_enabled(struct kvm_pmc *pmc) { struct kvm_vcpu *vcpu =3D kvm_pmc_to_vcpu(pmc); @@ -914,7 +934,16 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmc= eid1) =20 void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu) { + struct kvm_pmu *pmu =3D &vcpu->arch.pmu; u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); + int i; + + if (pmu->events_need_recreate) { + for (i =3D 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) + kvm_pmu_stop_counter(kvm_vcpu_idx_to_pmc(vcpu, i)); + + pmu->events_need_recreate =3D false; + } =20 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=3D, mask); __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, &=3D, mask); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 75624725adf1..7dd2cafce247 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -3114,17 +3114,22 @@ static bool access_mdcr(struct kvm_vcpu *vcpu, } =20 __vcpu_assign_sys_reg(vcpu, MDCR_EL2, val); - - /* - * Request a reload of the PMU to enable/disable the counters - * affected by HPME. - */ - if ((old ^ val) & MDCR_EL2_HPME) - kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); + kvm_pmu_apply_mdcr(vcpu, old, val); =20 return true; } =20 +static int set_mdcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + u64 val) +{ + u64 old =3D __vcpu_sys_reg(vcpu, MDCR_EL2); + + __vcpu_assign_sys_reg(vcpu, MDCR_EL2, val); + kvm_pmu_apply_mdcr(vcpu, old, val); + + return 0; +} + static bool access_ras(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -3836,7 +3841,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { EL2_REG_FILTERED(SCTLR2_EL2, access_vm_reg, reset_val, 0, sctlr2_el2_visibility), EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), - EL2_REG(MDCR_EL2, access_mdcr, reset_mdcr, 0), + SYS_REG_USER_FILTER(MDCR_EL2, access_mdcr, reset_mdcr, 0, + NULL, set_mdcr, el2_visibility), EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), EL2_REG_VNCR(HSTR_EL2, reset_val, 0), EL2_REG_VNCR_FILT(HFGRTR_EL2, fgt_visibility), diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 51f5e4ca3326..2fe73ad50e4e 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -32,6 +32,7 @@ struct kvm_pmu { struct kvm_pmc pmc[KVM_ARMV8_PMU_MAX_COUNTERS]; int irq_num; bool created; + bool events_need_recreate; }; =20 struct arm_pmu_entry { @@ -56,7 +57,9 @@ void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu); bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu); bool kvm_pmu_update_run(struct kvm_vcpu *vcpu); void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val); +void kvm_pmu_request_recreate(struct kvm_vcpu *vcpu); void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val); +void kvm_pmu_apply_mdcr(struct kvm_vcpu *vcpu, u64 old, u64 val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, u64 select_idx); void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu); @@ -137,7 +140,9 @@ static inline bool kvm_pmu_should_notify_user(struct kv= m_vcpu *vcpu) } static inline bool kvm_pmu_update_run(struct kvm_vcpu *vcpu) { return fals= e; } static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 v= al) {} +static inline void kvm_pmu_request_recreate(struct kvm_vcpu *vcpu) {} static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {} +static inline void kvm_pmu_apply_mdcr(struct kvm_vcpu *vcpu, u64 old, u64 = val) {} static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, u64 select_idx) {} static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD994407CD0; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-10-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=4845; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=ncqwVTRhMLVZJ0R7zoNIvotfazATWustdO6AcQZbKCg=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A1nbD2+6XGiSMVvgcofTt4mv6hYccT3LvzekQCb4t qb3W0nzjlIWBjEuBlkxRZaUot3cGtG1nwoT4ltg5rAygQxh4OIUgInMKmNk2G+/pCIq+bWFV60t dwVH1ElrS3+H6V93VL0+nsL7SXbNFUaGZQ57Di/9k/haovnAyep3ultufa1LrnNUjbk338cnryq SBwA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C PMCR_EL0.LC and PMCR_EL0.LP control whether cycle and event counters overflow at 32 or 64 bits. They therefore determine the sample period of each backing perf event. Guest and userspace writes do not recreate existing events. Changing either bit after an event has been created leaves its old sample period in place, resulting in an incorrect overflow point. Request event recreation when either bit changes. Preserve the existing reload behavior for PMCR_EL0.E and other userspace writes. Fixes: c82d28cbf1d4 ("KVM: arm64: PMU: Distinguish between 64bit counter an= d 64bit overflow") Fixes: 11af4c37165e ("KVM: arm64: PMU: Implement PMUv3p5 long counter suppo= rt") Closes: https://sashiko.dev/#/patchset/20260720-hybrid-v9-0-2b713ca1b5dc@rs= g.ci.i.u-tokyo.ac.jp?part=3D6 Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/pmu-emul.c | 18 ++++++++++++++---- arch/arm64/kvm/sys_regs.c | 3 ++- include/kvm/arm_pmu.h | 2 ++ 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index a8449e533070..86a02fd4cfb8 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -591,6 +591,17 @@ void kvm_pmu_request_recreate(struct kvm_vcpu *vcpu) kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); } =20 +void kvm_pmu_apply_pmcr(struct kvm_vcpu *vcpu, u64 old, u64 val, bool forc= e_reload) +{ + u64 changed =3D old ^ val; + + /* Reload the PMU if the write affects the backing perf events. */ + if (changed & (ARMV8_PMU_PMCR_LC | ARMV8_PMU_PMCR_LP)) + kvm_pmu_request_recreate(vcpu); + else if (force_reload || (changed & ARMV8_PMU_PMCR_E)) + kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); +} + /** * kvm_pmu_handle_pmcr - handle PMCR register * @vcpu: The vcpu pointer @@ -598,19 +609,18 @@ void kvm_pmu_request_recreate(struct kvm_vcpu *vcpu) */ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) { + u64 old =3D __vcpu_sys_reg(vcpu, PMCR_EL0); int i; =20 /* Fixup PMCR_EL0 to reconcile the PMU version and the LP bit */ if (!kvm_has_feat(vcpu->kvm, ID_AA64DFR0_EL1, PMUVer, V3P5)) val &=3D ~ARMV8_PMU_PMCR_LP; =20 - /* Request a reload of the PMU to enable/disable affected counters */ - if ((__vcpu_sys_reg(vcpu, PMCR_EL0) ^ val) & ARMV8_PMU_PMCR_E) - kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); - /* The reset bits don't indicate any state, and shouldn't be saved. */ __vcpu_assign_sys_reg(vcpu, PMCR_EL0, (val & ~(ARMV8_PMU_PMCR_C | ARMV8_P= MU_PMCR_P))); =20 + kvm_pmu_apply_pmcr(vcpu, old, __vcpu_sys_reg(vcpu, PMCR_EL0), false); + if (val & ARMV8_PMU_PMCR_C) kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0); =20 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7dd2cafce247..6786311e9b7d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1517,6 +1517,7 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const stru= ct sys_reg_desc *r, { u8 new_n =3D FIELD_GET(ARMV8_PMU_PMCR_N, val); struct kvm *kvm =3D vcpu->kvm; + u64 old =3D __vcpu_sys_reg(vcpu, r->reg); =20 mutex_lock(&kvm->arch.config_lock); =20 @@ -1549,7 +1550,7 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const stru= ct sys_reg_desc *r, val |=3D ARMV8_PMU_PMCR_LC; =20 __vcpu_assign_sys_reg(vcpu, r->reg, val); - kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); + kvm_pmu_apply_pmcr(vcpu, old, val, true); =20 return 0; } diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 2fe73ad50e4e..fca00f7f4c0a 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -58,6 +58,7 @@ bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu); bool kvm_pmu_update_run(struct kvm_vcpu *vcpu); void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val); void kvm_pmu_request_recreate(struct kvm_vcpu *vcpu); +void kvm_pmu_apply_pmcr(struct kvm_vcpu *vcpu, u64 old, u64 val, bool forc= e_reload); void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val); void kvm_pmu_apply_mdcr(struct kvm_vcpu *vcpu, u64 old, u64 val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, @@ -141,6 +142,7 @@ static inline bool kvm_pmu_should_notify_user(struct kv= m_vcpu *vcpu) static inline bool kvm_pmu_update_run(struct kvm_vcpu *vcpu) { return fals= e; } static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 v= al) {} static inline void kvm_pmu_request_recreate(struct kvm_vcpu *vcpu) {} +static inline void kvm_pmu_apply_pmcr(struct kvm_vcpu *vcpu, u64 old, u64 = val, bool force_reload) {} static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {} static inline void kvm_pmu_apply_mdcr(struct kvm_vcpu *vcpu, u64 old, u64 = val) {} static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1DD239BFE1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-11-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2412; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=6LLUznzO4H71nxemjRzGDOIgWidAJRt3Eg0+EfeUiB0=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A9lq2m9e1C2vl1fuF/VoCf+qfjIzIZqpwuI5z0oJu YmCoc86SlkYxLgYZMUUWVKKdnNrRNd+KkyIb4GZw8oEMoSBi1MAJuI3gZFhD++U1cs+xfPHn/F8 eMjx/Fnm4uesVZMcL+/dMVs/NGiGPcM/o4pbi1OXOcQbiUrclZsol1/guEX91V3eEqMYP9WGfmk mAA== X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C KVM_SET_ONE_REG writes to PMEVTYPERn_EL0 and PMCCFILTR_EL0 use the generic raw system register assignment. If a backing perf event already exists, it keeps its old event selection and privilege filters. Add a setter that preserves the raw userspace register value and requests deferred event recreation. This rebuilds the event on the vCPU thread without changing values returned by KVM_GET_ONE_REG or applying guest-write masking. Fixes: 9feb21ac57d5 ("arm64: KVM: Add access handler for event type registe= r") Closes: https://sashiko.dev/#/patchset/20260720-hybrid-v9-0-2b713ca1b5dc@rs= g.ci.i.u-tokyo.ac.jp?part=3D6 Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/sys_regs.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 6786311e9b7d..5a44bd5530ff 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1334,6 +1334,15 @@ static int set_pmreg(struct kvm_vcpu *vcpu, const st= ruct sys_reg_desc *r, u64 va return 0; } =20 +static int set_pmu_evtyper(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *r, u64 val) +{ + __vcpu_assign_sys_reg(vcpu, r->reg, val); + kvm_pmu_request_recreate(vcpu); + + return 0; +} + static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, = u64 *val) { u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); @@ -1584,7 +1593,7 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const stru= ct sys_reg_desc *r, /* Macro to expand the PMEVTYPERn_EL0 register */ #define PMU_PMEVTYPER_EL0(n) \ { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ - .reset =3D reset_pmevtyper, \ + .reset =3D reset_pmevtyper, .set_user =3D set_pmu_evtyper, \ .access =3D access_pmu_evtyper, .reg =3D (PMEVTYPER0_EL0 + n), } =20 /* Macro to expand the AMU counter and type registers*/ @@ -3833,7 +3842,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { * in 32bit mode. Here we choose to reset it as zero for consistency. */ { PMU_SYS_REG(PMCCFILTR_EL0), .access =3D access_pmu_evtyper, - .reset =3D reset_val, .reg =3D PMCCFILTR_EL0, .val =3D 0 }, + .reset =3D reset_val, .reg =3D PMCCFILTR_EL0, .val =3D 0, + .set_user =3D set_pmu_evtyper }, =20 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93A972C15A0; Sun, 20 Sep 2026 11:17:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903070; cv=none; b=BSfIU1+oFegvU3sx5CuKRNUacUOz0wLxWCktX830hmIebXuNwIP6TeI7NMuN+mdHiH3lBrHtFNPqRKF//V3EdbZbGNTsSeK2HoGzhBmdigHpx7le1d97TkJzxEmXRdBtR3PQvO0AgDgb3k2iXrEfcbdijxxL2jQK5T7XGHPcUXw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903070; c=relaxed/simple; bh=0gFY16czEJJdVIZNruax1OboJIq4DgiNXWKP5yi8iWI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lmqzrr1VfU9wjO+TLF0D1P/nNw6M7Cs1clxPB2VSc5LwxEGSUZOtAIS0b82sf/Z6icPpKTXi2bgbHj2txxpNC7pNfOxLpdfL0NS8E3zaKUXOX94QEnSp4DnrbU8eGz9p9aNlrr4qMMY+atnZC8yx+LSzSNYup0GgxLIAToOxJNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=wST8YOyR; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="wST8YOyR" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36Z088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:13 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=sdoc/fNZ3/8mGQaouIvfU+D4x9tivmX8+zHcMnaA4Lw=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902974; v=1; b=wST8YOyR3tflDV0qWGSbQkBzHm4onY042T/KqofQhCB5cWfqGvfpNd5RBrSR27PV x4VwM13HbqRhBGbMatvO+wdb5lkv8zzNcz5z9zvSDZNeS3ubmspV3KFExUs6vDLM k87ziOa7mu+q0LXMd/649Qw7zrvqcTOYqxOZtTKWZJxO4aNbWfIdbglB+CF7Yenz /JEuQfB7ZRbxEagYCnhjn6UbdF/zzLHWyselof44mUATFIbmB96swxsgT2Q0NTQd GtfrQSVaowIFAiZxTS3/F7qyXqUFibYhtnVppXk3rgTsfPjn7B/Q20JjvOljBiDc RgaklXn9JtNC3WyECw5VYw== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:53 +0900 Subject: [PATCH v11 12/21] tools headers: Use u* types for bitfield helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-12-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3005; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=0gFY16czEJJdVIZNruax1OboJIq4DgiNXWKP5yi8iWI=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6Azkr16mpCGi+jGqJeMRluOH4S0b256HPtjbkfKyZe uq4wc5THaUsDGJcDLJiiiwpRbu5NaJrPxUmxLfAzGFlAhnCwMUpABPZu5Dhf9Vtsyn6b5hdXPlP lF3ivvf7A9uliJbSRK2thtf/GczapcXIMOFIV+fjKn5n05+b+epZmY/5vPXOCnqUPH/6kRshmiu 1+QA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C Commit 9486aa387716 ("perf tools: Fix 64 bit integer format strings") defined the tools-local u64 as uint64_t so that PRI*64 format macros match its underlying C type. On architectures where uint64_t and __u64 are distinct types, however, ____MAKE_OP() still gives the u64_* helpers an __u64 interface. Teach ____MAKE_OP() to accept the helper name and storage type separately. Keep endian helpers on __le* and __be*, and generate the native helpers using the tools-local u* types. Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- tools/include/linux/bitfield.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/tools/include/linux/bitfield.h b/tools/include/linux/bitfield.h index ddf81f24956b..1c633343d576 100644 --- a/tools/include/linux/bitfield.h +++ b/tools/include/linux/bitfield.h @@ -142,32 +142,32 @@ static __always_inline u64 field_mask(u64 field) return field / field_multiplier(field); } #define field_max(field) ((typeof(field))field_mask(field)) -#define ____MAKE_OP(type,base,to,from) \ -static __always_inline __##type type##_encode_bits(base v, base field) \ +#define ____MAKE_OP(name,type,base,to,from) \ +static __always_inline type name##_encode_bits(base v, base field) \ { \ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ __field_overflow(); \ return to((v & field_mask(field)) * field_multiplier(field)); \ } \ -static __always_inline __##type type##_replace_bits(__##type old, \ - base val, base field) \ +static __always_inline type name##_replace_bits(type old, \ + base val, base field) \ { \ - return (old & ~to(field)) | type##_encode_bits(val, field); \ + return (old & ~to(field)) | name##_encode_bits(val, field); \ } \ -static __always_inline void type##p_replace_bits(__##type *p, \ +static __always_inline void name##p_replace_bits(type *p, \ base val, base field) \ { \ - *p =3D (*p & ~to(field)) | type##_encode_bits(val, field); \ + *p =3D (*p & ~to(field)) | name##_encode_bits(val, field); \ } \ -static __always_inline base type##_get_bits(__##type v, base field) \ +static __always_inline base name##_get_bits(type v, base field) \ { \ return (from(v) & field)/field_multiplier(field); \ } -#define __MAKE_OP(size) \ - ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \ - ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \ - ____MAKE_OP(u##size,u##size,,) -____MAKE_OP(u8,u8,,) +#define __MAKE_OP(size) \ + ____MAKE_OP(le##size,__le##size,u##size,cpu_to_le##size,le##size##_to_cpu= ) \ + ____MAKE_OP(be##size,__be##size,u##size,cpu_to_be##size,be##size##_to_cpu= ) \ + ____MAKE_OP(u##size,u##size,u##size,,) +____MAKE_OP(u8,u8,u8,,) __MAKE_OP(16) __MAKE_OP(32) __MAKE_OP(64) --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 229F63F9263; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-13-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=5050; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=Tfgm9WXcmRxelzdJdDKljVp7Ced7YFV3TbgyJMrdSII=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A7kd4QLLu3UnPROc6DXX/OoquWsl9m3FR2NtamRi3 JQaXlzqKGVhEONikBVTZEkp2s2tEV37qTAhvgVmDisTyBAGLk4BmMjiAwz/S6Y3hIeZ+5tv/Xwn pVVP2WFZw+1XrMeDd6m0N/+uWHUsm5Fh5crFHjYNCnMc0pOX1zX9YlaNjosvLLDcKdq02idxeSs /AA== X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C Add MDCR_EL2 coverage to vpmu_counter_access when EL2 is available. For each configured PMCR_EL0.N value, verify that an arbitrary HPMN value, including one above the configured counter count, round-trips through KVM_SET_ONE_REG and survives SET_NR_COUNTERS. Also verify that HPME can be toggled without disturbing HPMN and that KVM_ARM_VCPU_INIT resets HPMN from the configured count. Assisted-by: Codex:gpt-5.5 Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- .../selftests/kvm/arm64/vpmu_counter_access.c | 90 ++++++++++++++++++= ++-- 1 file changed, 85 insertions(+), 5 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c b/tool= s/testing/selftests/kvm/arm64/vpmu_counter_access.c index 05135bcdb462..73b4f1870d3d 100644 --- a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c +++ b/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c @@ -25,6 +25,14 @@ /* The cycle counter bit position that's common among the PMU registers */ #define ARMV8_PMU_CYCLE_IDX 31 =20 +#ifndef MDCR_EL2_HPMN +#define MDCR_EL2_HPMN GENMASK_ULL(4, 0) +#endif + +#ifndef MDCR_EL2_HPME +#define MDCR_EL2_HPME BIT_ULL(7) +#endif + struct vpmu_vm { struct kvm_vm *vm; struct kvm_vcpu *vcpu; @@ -465,15 +473,12 @@ static void guest_code_done(void) GUEST_DONE(); } =20 -static void test_create_vpmu_vm_with_nr_counters(unsigned int nr_counters,= bool expect_fail) +static void set_nr_counters(struct kvm_vcpu *vcpu, + unsigned int nr_counters, bool expect_fail) { - struct kvm_vcpu *vcpu; unsigned int prev; int ret; =20 - create_vpmu_vm(guest_code); - vcpu =3D vpmu_vm.vcpu; - prev =3D get_pmcr_n(vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0))); =20 ret =3D __vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, @@ -485,6 +490,17 @@ static void test_create_vpmu_vm_with_nr_counters(unsig= ned int nr_counters, bool nr_counters, prev); else TEST_ASSERT(!ret, KVM_IOCTL_ERROR(KVM_SET_DEVICE_ATTR, ret)); +} + +static void test_create_vpmu_vm_with_nr_counters(unsigned int nr_counters, + bool expect_fail) +{ + struct kvm_vcpu *vcpu; + + create_vpmu_vm(guest_code); + vcpu =3D vpmu_vm.vcpu; + + set_nr_counters(vcpu, nr_counters, expect_fail); =20 vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, KVM_ARM_VCPU_PMU_V3_= INIT, NULL); } @@ -589,6 +605,69 @@ static void run_pmregs_validity_test(u64 pmcr_n) destroy_vpmu_vm(); } =20 +static void run_mdcr_el2_validity_test(u64 pmcr_n) +{ + struct kvm_vcpu_init init; + struct kvm_vcpu *vcpu; + u64 expected_mdcr, mdcr; + + pr_debug("MDCR_EL2 test with pmcr_n %lu\n", pmcr_n); + + create_vpmu_vm(guest_code); + if (!vm_supports_el2(vpmu_vm.vm)) { + destroy_vpmu_vm(); + return; + } + + vcpu =3D vpmu_vm.vcpu; + + mdcr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MDCR_EL2)); + expected_mdcr =3D u64_replace_bits(mdcr, FIELD_MAX(MDCR_EL2_HPMN), + MDCR_EL2_HPMN); + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MDCR_EL2), + expected_mdcr); + + mdcr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MDCR_EL2)); + TEST_ASSERT(mdcr =3D=3D expected_mdcr, + "MDCR_EL2 was not properly updated after HPMN write (expected 0x%lx,= got 0x%lx)", + expected_mdcr, mdcr); + + set_nr_counters(vcpu, pmcr_n, false); + + mdcr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MDCR_EL2)); + TEST_ASSERT(mdcr =3D=3D expected_mdcr, + "MDCR_EL2 changed after PMU_V3_SET_NR_COUNTERS (expected 0x%lx, got = 0x%lx)", + expected_mdcr, mdcr); + + vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_INIT, NULL); + + mdcr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MDCR_EL2)); + TEST_ASSERT(mdcr =3D=3D expected_mdcr, + "MDCR_EL2 changed after PMU_V3_INIT (expected 0x%lx, got 0x%lx)", + expected_mdcr, mdcr); + + expected_mdcr =3D mdcr ^ MDCR_EL2_HPME; + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MDCR_EL2), + expected_mdcr); + + mdcr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MDCR_EL2)); + TEST_ASSERT(mdcr =3D=3D expected_mdcr, + "MDCR_EL2 was not properly updated after HPME write (expected 0x%lx,= got 0x%lx)", + expected_mdcr, mdcr); + + kvm_get_default_vcpu_target(vpmu_vm.vm, &init); + init.features[0] |=3D (1 << KVM_ARM_VCPU_PMU_V3); + aarch64_vcpu_setup(vcpu, &init); + + mdcr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MDCR_EL2)); + TEST_ASSERT(FIELD_GET(MDCR_EL2_HPMN, mdcr) =3D=3D pmcr_n, + "MDCR_EL2.HPMN is not reset after INIT (expected %lu, got %lu)", + pmcr_n, FIELD_GET(MDCR_EL2_HPMN, mdcr)); + + destroy_vpmu_vm(); +} + /* * Create a guest with one vCPU, and attempt to set the PMCR_EL0.N for * the vCPU to @pmcr_n, which is larger than the host value. @@ -673,6 +752,7 @@ int main(void) for (i =3D 0; i <=3D pmcr_n; i++) { run_access_test(i); run_pmregs_validity_test(i); + run_mdcr_el2_validity_test(i); } =20 for (i =3D pmcr_n + 1; i < ARMV8_PMU_MAX_COUNTERS; i++) --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26C953FCB10; Sun, 20 Sep 2026 11:22:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903346; cv=none; b=oq1dJRcQAiwinGvN99s+x37QvRCFhS+5roenxb9/92Z5cFMC6TpTCrwvhZWOHdvLVK20uV7FI33rMJ8QEeEyI42np6rLrzJh9cNimjzZgP/HirhFcfEvMcB4HK9KNmndfIVXnx+3GAsSwW8DL/vSz6PptaOL8UNxmO8AHASGbzk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903346; c=relaxed/simple; bh=3wHsuhm1EOsX6FnaaZCz7S9AObKXD0J2nrSu7LVseb8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Sun, 20 Sep 2026 20:16:14 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=xY3f7CW2k+sxURpCWyIEkta47r/Ail7h0q2vhhuON5Y=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902975; v=1; b=mInm2XTuQIO9C+YXeqfebcOFmmo0frr1Zm8g8p5z6Jq7UKBcwKjgVAAMFAfVJiUd xBenMftkF3iNMlA9lfJY3+/fWwDb25KsqHMCkpJxfIgzhWjYEBbHTAvPC4LvdadC HvvXchwGjR19oAIws8ZLHbg0Oi6lIWRSVuFi7nXBPkFJ3LuA9Ug+B8Rup7Sia7o+ D0wcK8iqvjULQE2aTFv9oRsuQT/wCajOsPxekCfr6Hz6kwxXBQIM1SXQNu/1Abt3 Mty7ERJ9aLaBleu2qmxKWuIyf/Lc0dLr8W57cIzhjjc5Eq71ClnHRD4nzz5BCieM xBbespM5NLD2jRJLBXhs9g== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:55 +0900 Subject: [PATCH v11 14/21] arm64: errata: Require Apple IMPDEF PMUv3 traps on all CPUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-14-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2262; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=3wHsuhm1EOsX6FnaaZCz7S9AObKXD0J2nrSu7LVseb8=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A7lnUxVOBxxlDNxw5oBdoJXrzRyT78vT9ioa8B0NP PU2+VpCRykLgxgXg6yYIktK0W5ujejaT4UJ8S0wc1iZQIYwcHEKwEQ+xDP896rZWnpzyrw5Iu9n 6q4y753/ZV/N7VDRi8oTLF7G1P8xfMXwT50rRNB9npSOKMParUeWf9G515Jh7jF7GafQ9MRvXSd 3cAAA X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C KVM relies on ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS as a system-wide precondition for PMUv3 emulation on affected Apple CPUs. A local CPU erratum is too weak for that: once the workaround is enabled, a late CPU that misses it may still be onlined. Make the workaround an all-early-CPU capability instead. The matcher is still local because it depends on MIDR_EL1, but the capability is only advertised if all early CPUs match. A late CPU that misses an advertised capability is therefore rejected. Although kept in the errata capability table, this capability describes optional trap support, not a workaround required for safe CPU operation. Therefore, a late CPU can safely match the capability even when the system does not advertise it. On these CPUs, ID_AA64DFR0_EL1.PMUVer =3D=3D 0xf means the Arm-architected PMUv3 is not implemented. Without the system capability, KVM does not advertise PMUv3, and direct accesses to architected PMUv3 registers remain UNDEFINED. HACR_EL2[56] only makes those accesses trap to EL2 so KVM can emulate PMUv3; leaving it clear does not make them access Apple's native PMU. The native Apple PMU uses separate implementation-defined system register encodings, which KVM independently traps with HCR_EL2.TIDCP. Allowing a late CPU with extra HACR_EL2 trap support therefore does not expose host PMU state to a guest. Fixes: bed9b8ec8c71 ("KVM: arm64: Advertise PMUv3 if IMPDEF traps are prese= nt") Assisted-by: Codex:gpt-5.5 Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- arch/arm64/kernel/cpu_errata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index b33dccfafaf8..3dc598a9fdd2 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -1020,7 +1020,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = =3D { { .desc =3D "Apple IMPDEF PMUv3 Traps", .capability =3D ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS, - .type =3D ARM64_CPUCAP_LOCAL_CPU_ERRATUM, + .type =3D ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, .matches =3D has_impdef_pmuv3, .cpu_enable =3D cpu_enable_impdef_pmuv3_traps, }, --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 628D73DDB03; Sun, 20 Sep 2026 11:17:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903076; cv=none; b=cSA4mzjL7hdtr/oQ0gBXZUoWhiosMmGviHe9UMcvtUX8GOdgMIx9DryUCCDOArdiHyH/fupXsvf8y7LqARpYSNk0KFlOBvrGxEwp4dKr876wWJV9Hy2sS5Arv6RtPBqLPEDIT8H+NeJbZ5eXOULWz+tzQv0KWn775A37o3BSz+k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903076; c=relaxed/simple; bh=B4dzm7ewjeuKN1a1PN2bUUK6vcNWIu32kozfRCLd2Po=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tIzKDxCzNA9h4r51W81pm8S2BLfi65T7vRwZKLR4srwLeKlaSn07rsz7chvAb1FYBFxdpaRnYbXlHT3qq6X1Qj6PQ1I0+67fZBUCJaAtjmgntBZyQ4T7B5/GiF3vIxRsVhmbLLHn8zVdciMWnUHDcclC69uKUjcH03VusW8FGps= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=oIHGjcGo; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="oIHGjcGo" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36c088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:15 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=GWp1qZjKZJDBgpGF1xqb2F0C/RBOoHyL11jPLC8n4jE=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902975; v=1; b=oIHGjcGoZs8L8idyNxvQRy4DBmOkG1C+oz6eKCuD2GT+YGuCFF4A60sdJgGVnQZN PP+AeuXNFbNOW2SG456aYFwD1DRuhuy0y6OokG3I+1drSG7NyvEswH+Cq5Dnx4rC KoQi36jDonppgWwNMOdUNvbnvgkKm9sP1FzsJrVh7vVSzAoCMpFGMsCGMZImXL9b JPKvgdqLr5EaoZ0vDw9n+qrmHerbWxhi7ZAUIp/o9ZpI6y58cUuzFE9ulpMxy6UV tnp8ft2FIep8yluOYwFc8ZypmFrSmYdC8PDYYpZ5FpzomBvVx4+x2mnkSsCIZDjR 69pOg41qFlH74QY+iV8iqQ== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:56 +0900 Subject: [PATCH v11 15/21] KVM: arm64: Don't clear vcpu->cpu in kvm_arch_vcpu_put() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-15-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2532; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=Wo4YX+JLn2zPeTcpRRl6wn6Y1qLLImnsb8pkey2lNzQ=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A3mKc0N+9P78tqUzc2vVk7nLwm4m1dgWR/9iWT+rK TqmU62go5SFQYyLQVZMkSWlaDe3RnTtp8KE+BaYOaxMIEMYuDgFYCL7DBj+h6Wn3HuesGXSm685 Au+T6j1jlD5J3rF6Pefceyb2C7cLzzP8D7198Pr5eFbf2qK0BzZ/Ko4sk/lx4/4EZq/qHsvQo0u VmQA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C From: Oliver Upton commit e9b152cb957c ("arm/arm64: kvm: Set vcpu->cpu to -1 on vcpu_put") reset vcpu->cpu in order for the VGIC to determine if there was any vCPU running at the time of access. The VGIC has gone through an entire rewrite since then, and with commit 7d450e282171 ("KVM: arm/arm64: vgic-new: Add userland access to VGIC dist registers") the user accessors just grab all vCPU mutexes instead. Drop this remaining vestige such that kvm_arch_vcpu_load() can properly detect a CPU migration. While at it, rework kvm_reset_vcpu() to do a much more pedantic check that the provided vCPU is actually what's running on the present CPU. Signed-off-by: Oliver Upton Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- arch/arm64/kvm/arm.c | 1 - arch/arm64/kvm/reset.c | 16 +++++++++++----- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 997f24f5fb91..55b07926ce2e 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -767,7 +767,6 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) kvm_arm_vmid_clear_active(); =20 vcpu_clear_on_unsupported_cpu(vcpu); - vcpu->cpu =3D -1; } =20 static void __kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index adcb460a5287..db794d50fa18 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -178,7 +178,8 @@ static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) void kvm_reset_vcpu(struct kvm_vcpu *vcpu) { struct vcpu_reset_state reset_state; - bool loaded; + struct kvm_vcpu *running; + bool loaded =3D false; =20 spin_lock(&vcpu->arch.mp_state_lock); reset_state =3D vcpu->arch.reset_state; @@ -188,10 +189,16 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu) /* Reset PMU outside of the non-preemptible section */ kvm_pmu_vcpu_reset(vcpu); =20 - preempt_disable(); - loaded =3D (vcpu->cpu !=3D -1); - if (loaded) + guard(preempt)(); + + running =3D kvm_get_running_vcpu(); + if (running) { + if (KVM_BUG_ON(running !=3D vcpu, vcpu->kvm)) + return; + + loaded =3D true; kvm_arch_vcpu_put(vcpu); + } =20 if (!kvm_arm_vcpu_sve_finalized(vcpu)) { if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE)) @@ -218,7 +225,6 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu) =20 if (loaded) kvm_arch_vcpu_load(vcpu, smp_processor_id()); - preempt_enable(); } =20 u32 kvm_get_pa_bits(struct kvm *kvm) --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DC14403123; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-16-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2743; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=qU8my+fu/3h0TRdwxXVNmhO46L1Vz0X7hgje4jBeoj4=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A/myusF1M84lx17jfJO1YVO9+xKBDLGeRtmmV9NsC gQb2j53lLIwiHExyIopsqQU7ebWiK79VJgQ3wIzh5UJZAgDF6cATKTkAiPDItZGR6HnDUGLaj8U nDp08slKw1VpNk+O6zAt7DNcfFLMhJHh5ESf7vJt83rqPs2+vsj4ftnDORs/FmcEmk9N/SDWLXO WGwA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C Convert the list of PMUs to a RCU-protected list that has primitives to avoid read-side contention. Assisted-by: Codex:gpt-5.5 Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- arch/arm64/kvm/pmu-emul.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 86a02fd4cfb8..335d712cc9c5 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -7,9 +7,9 @@ #include #include #include -#include #include #include +#include #include #include #include @@ -17,6 +17,10 @@ =20 #define PERF_ATTR_CFG1_COUNTER_64BIT BIT(0) =20 +/* + * arm_pmus is append-only. kvm_supports_guest_pmuv3() feeds persistent + * VM state, so a true result must remain valid after the check. + */ static LIST_HEAD(arm_pmus); static DEFINE_MUTEX(arm_pmus_lock); =20 @@ -26,7 +30,6 @@ static bool kvm_pmu_counter_is_enabled(struct kvm_pmc *pm= c); =20 bool kvm_supports_guest_pmuv3(void) { - guard(mutex)(&arm_pmus_lock); return !list_empty(&arm_pmus); } =20 @@ -833,7 +836,7 @@ void kvm_host_pmu_init(struct arm_pmu *pmu) return; =20 entry->arm_pmu =3D pmu; - list_add_tail(&entry->entry, &arm_pmus); + list_add_tail_rcu(&entry->entry, &arm_pmus); } =20 static struct arm_pmu *kvm_pmu_probe_armpmu(void) @@ -842,7 +845,7 @@ static struct arm_pmu *kvm_pmu_probe_armpmu(void) struct arm_pmu *pmu; int cpu; =20 - guard(mutex)(&arm_pmus_lock); + guard(rcu)(); =20 /* * It is safe to use a stale cpu to iterate the list of PMUs so long as @@ -862,7 +865,7 @@ static struct arm_pmu *kvm_pmu_probe_armpmu(void) * carried here. */ cpu =3D raw_smp_processor_id(); - list_for_each_entry(entry, &arm_pmus, entry) { + list_for_each_entry_rcu(entry, &arm_pmus, entry) { pmu =3D entry->arm_pmu; =20 if (cpumask_test_cpu(cpu, &pmu->supported_cpus)) @@ -1128,9 +1131,9 @@ static int kvm_arm_pmu_v3_set_pmu(struct kvm_vcpu *vc= pu, int pmu_id) int ret =3D -ENXIO; =20 lockdep_assert_held(&kvm->arch.config_lock); - mutex_lock(&arm_pmus_lock); + guard(rcu)(); =20 - list_for_each_entry(entry, &arm_pmus, entry) { + list_for_each_entry_rcu(entry, &arm_pmus, entry) { arm_pmu =3D entry->arm_pmu; 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Sun, 20 Sep 2026 20:16:16 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=a4q4eE1hSPqoFF9hVD5Vo9NtpihGBtcqgrIHYR9lIyM=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902976; v=1; b=ZYMoxdrqvxa0H67UyJl08C4EYujvBJAPsqb4qoc0GJYpSBcjN0XNrbeTwSiF8IQi QUlq614nwQGEyVFyPP7v85/9Xewx40o7/xvUwy86Dpao+E3Z/iCWV8hA11vHIkQk lmsd5AZjV+7elTYCxK8LG9oZmGlfGEbYE3Quc8vj3W6mz/d95edaL4Gv2pNN8aCP E00t1ZadUUpxiM1/VFVXVHjRJwx/UA883I26GpeWVymz7J+9T5IFaennv46diynz LkxK8gvZ0j/N1cyaeG+vkly+FHbGViB9O12Lg3RCXDDAuGIxpvaNf/4kdOVmekvP PK11yHHENYq0p0yNrz0Inw== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:58 +0900 Subject: [PATCH v11 17/21] KVM: arm64: PMU: Pass the pPMU to kvm_map_pmu_event() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-17-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1503; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=tjUetPIPNmPZFFuAWauSmYCWvYFAQD9PAEnjIoNhXmI=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6AwXes2TvOOQlfXAp67j90Hn6vgWPLX9XJpnNXK76U Onc/wXpHaUsDGJcDLJiiiwpRbu5NaJrPxUmxLfAzGFlAhnCwMUpABPhNGb479qtMdn29rq43vdb Ns7KiX31Y/vU/GAdw4PnOM1Tzu8PPcbwTyd0bdMahl4Hv08LXN0jYr7lCXs8XOe2527Y9DfaXkz PeAE= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C Replace the VM argument with the pPMU used for event creation. The current caller still passes the VM's default pPMU, but this removes the implicit lookup from kvm_map_pmu_event() so later changes can map events against the pPMU selected for an individual vCPU. Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- arch/arm64/kvm/pmu-emul.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 335d712cc9c5..72b042e5c360 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -696,10 +696,8 @@ static bool kvm_pmc_counts_at_el2(struct kvm_pmc *pmc) return kvm_pmc_read_evtreg(pmc) & ARMV8_PMU_INCLUDE_EL2; } =20 -static int kvm_map_pmu_event(struct kvm *kvm, unsigned int eventsel) +static int kvm_map_pmu_event(struct arm_pmu *pmu, unsigned int eventsel) { - struct arm_pmu *pmu =3D kvm->arch.arm_pmu; - /* * The CPU PMU likely isn't PMUv3; let the driver provide a mapping * for the guest's PMUv3 event ID. @@ -751,7 +749,7 @@ static void kvm_pmu_create_perf_event(struct kvm_pmc *p= mc) * Don't create an event if we're running on hardware that requires * PMUv3 event translation and we couldn't find a valid mapping. */ - eventsel =3D kvm_map_pmu_event(vcpu->kvm, eventsel); + eventsel =3D kvm_map_pmu_event(vcpu->kvm->arch.arm_pmu, eventsel); if (eventsel < 0) return; =20 --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D896402B99; Sun, 20 Sep 2026 11:17:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903078; cv=none; b=VSwS2dyF65+Mhb6HHZnXyt9daKf8sioM0mKtt9DR7EHauD7bdgZ0BaP+OFx5AnWQYZqZnyRLqE+0ItDCE7MxDBaYqRzWwsZO4BYY6pkjvSQlLtgPjCmHzvKZr222AyrcwAwYPhZWN14NqDzCmp1xYjjSD9vN6gwAk9O8xSoTdt0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903078; c=relaxed/simple; bh=xEWxbBZGUjPYlzg4Xr8/yHzALhSurwMXAGDpDFsHDG4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lH2hnfDOTbuVOi2unBh8d8KQW2OMwE5H7wRonovbSqI+61d6GETSHytlo/EcUJsR8VJMYWtI3H68RBXNnenrYdJTgTTGf0z7QBSA+pE2xEB/FmFWiXBcdQwRqM5t4Y/gm/pmYNPp/LuEPRzVlsvbbGL3m/e1HmkpD0VEaHtRRlM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=OJJVMnrx; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="OJJVMnrx" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36f088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:16 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=+2D3XC//PXEj3eDv40Gbahf5dAWuKc/ExUhJEz+Wh54=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902977; v=1; b=OJJVMnrxeC53WpNkLlXng9twP6VYuQ/JoGFuBUbI+92aGfH/slaGnULjiyVMSldf efgrYqaTF9l0UlZExxiy0SoEV4eb7tllylg84VTpKsXVCRI72i1UX1Q9nDY2UI7h 8n7ZfpMbsolrr5ewER7q3PBuo8+aKOndD11ihYKZ33Tp/aEAc05MwrVr+XD0lEhl cIbC49RedRspbqSlDWuVKD8MFgArPlpYE9A0+s+PJSpAKp7E906ZjzUxZ8JdhHet qV/tJ3V9vTI3ZTx+tKm2557K8TbxM8NoEMLeGmlipXJnfPLCAegFyk494y04M01F I8VZAdxh/rrlAVBkLV19Uw== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:15:59 +0900 Subject: [PATCH v11 18/21] KVM: arm64: PMU: Pass the target CPU to kvm_pmu_probe_armpmu() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-18-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=4142; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=xEWxbBZGUjPYlzg4Xr8/yHzALhSurwMXAGDpDFsHDG4=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6AwUnJU9VHZgVv3lncJW29cWqhqBy7916DirG5xzur AiYy/uto5SFQYyLQVZMkSWlaDe3RnTtp8KE+BaYOaxMIEMYuDgFYCI9ogx/JZ2WROXdvLDk/dIv 9etCNtQZ2T3XSu+aHXnfbsOzVbv+WzMyTH8bNHGO69q5cwUEUh8+m2/1YdrGnbtWK098o3VFQfC dOQ8A X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C kvm_pmu_probe_armpmu() currently samples the current CPU internally, which ties the helper to default PMU selection. Move that policy to kvm_arm_set_default_pmu() by passing raw_smp_processor_id() from the caller, and make the helper search for the pPMU covering an explicit CPU. Move the helper above kvm_pmu_create_perf_event() so later code can reuse it when creating PMU events for a VCPU's current pCPU. This preserves the existing default PMU selection behavior while preparing fixed-counters-only mode to select a pPMU at runtime. Signed-off-by: Akihiko Odaki Reviewed-by: Fuad Tabba --- arch/arm64/kvm/pmu-emul.c | 72 +++++++++++++++++++++++--------------------= ---- 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 72b042e5c360..a303752c5e61 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -708,6 +708,23 @@ static int kvm_map_pmu_event(struct arm_pmu *pmu, unsi= gned int eventsel) return eventsel; } =20 +static struct arm_pmu *kvm_pmu_probe_armpmu(int cpu) +{ + struct arm_pmu_entry *entry; + struct arm_pmu *pmu; + + guard(rcu)(); + + list_for_each_entry_rcu(entry, &arm_pmus, entry) { + pmu =3D entry->arm_pmu; + + if (cpumask_test_cpu(cpu, &pmu->supported_cpus)) + return pmu; + } + + return NULL; +} + /** * kvm_pmu_create_perf_event - create a perf event for a counter * @pmc: Counter context @@ -837,42 +854,6 @@ void kvm_host_pmu_init(struct arm_pmu *pmu) list_add_tail_rcu(&entry->entry, &arm_pmus); } =20 -static struct arm_pmu *kvm_pmu_probe_armpmu(void) -{ - struct arm_pmu_entry *entry; - struct arm_pmu *pmu; - int cpu; - - guard(rcu)(); - - /* - * It is safe to use a stale cpu to iterate the list of PMUs so long as - * the same value is used for the entirety of the loop. Given this, and - * the fact that no percpu data is used for the lookup there is no need - * to disable preemption. - * - * It is still necessary to get a valid cpu, though, to probe for the - * default PMU instance as userspace is not required to specify a PMU - * type. In order to uphold the preexisting behavior KVM selects the - * PMU instance for the core during vcpu init. A dependent use - * case would be a user with disdain of all things big.LITTLE that - * affines the VMM to a particular cluster of cores. - * - * In any case, userspace should just do the sane thing and use the UAPI - * to select a PMU type directly. But, be wary of the baggage being - * carried here. - */ - cpu =3D raw_smp_processor_id(); - list_for_each_entry_rcu(entry, &arm_pmus, entry) { - pmu =3D entry->arm_pmu; - - if (cpumask_test_cpu(cpu, &pmu->supported_cpus)) - return pmu; - } - - return NULL; -} - static u64 __compute_pmceid(struct arm_pmu *pmu, bool pmceid1) { u32 hi[2], lo[2]; @@ -1112,7 +1093,24 @@ static void kvm_arm_set_pmu(struct kvm *kvm, struct = arm_pmu *arm_pmu) */ int kvm_arm_set_default_pmu(struct kvm *kvm) { - struct arm_pmu *arm_pmu =3D kvm_pmu_probe_armpmu(); + /* + * It is safe to use a stale cpu to iterate the list of PMUs so long as + * the same value is used for the entirety of the loop. Given this, and + * the fact that no percpu data is used for the lookup there is no need + * to disable preemption. + * + * It is still necessary to get a valid cpu, though, to probe for the + * default PMU instance as userspace is not required to specify a PMU + * type. In order to uphold the preexisting behavior KVM selects the + * PMU instance for the core during vcpu init. A dependent use + * case would be a user with disdain of all things big.LITTLE that + * affines the VMM to a particular cluster of cores. + * + * In any case, userspace should just do the sane thing and use the UAPI + * to select a PMU type directly. But, be wary of the baggage being + * carried here. + */ + struct arm_pmu *arm_pmu =3D kvm_pmu_probe_armpmu(raw_smp_processor_id()); =20 if (!arm_pmu) return -ENODEV; --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77872404BD4; Sun, 20 Sep 2026 11:17:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903075; cv=none; b=jhIZ4JzSfAKVcsSdI6b9KjKv6hUKNgZBTKVv4Byq8hz+Hliss2Vw7h4Kxbi7OVc5xPMehTV9tND87VQdyiOGzxQUdXxa4upzvpETxL88O0Q4JUc1f01PDjIXBhG0ltB0J2nowa0JJoQxNDazX/MLtR1vSW0puX9usi3rVrah4AU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903075; c=relaxed/simple; bh=07g7Wsnxy7TV71yYjMKtl6l/jv8TXnMqlazGTus0lG4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z+dfK8643v/o9ciC59uHDa8mTzfm6DhJS9+g4lUB8mqRnkOMEak1xCJGHnz4v1HfoyBSFeXPNzo9sGpkLZphkaSp37/GAo1rChs0bDQMnBtfy9cBx4XtiA+JBI3Q0gv3psNFmwNtM1krVkbIQmSMnm1Vrx4UGzMnqEsA2eoNaYY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=kodpUlKs; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="kodpUlKs" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36g088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:17 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=8iwQDxRfrOAjdLEnj6KqRv2uciFkrG85NKoY1Q5Ne64=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902977; v=1; b=kodpUlKskgJDYfgFYWg/SDs1zojEj+vAHqhdwVsBSFcoiu19swkP4YohevElDlpw idIF6OliQqAukZrtr+qT+F97ppYV4l14eNumGhTt+fJa/HxHb5wZoz49LfqFAYDK IlD37vtgNQmaD5SeeOhawR9aXac7HOewgnifUALoOotPYLozJKcN4FZjs7Hh+3nl 6wattudp6JzMHJ70S0NB6MamVVAfIv7MxuU+WI0RSP9CXxAXEnumtpxWsh1G/jJJ 1tHQlMbIuAhGHgyRQD7Pt/NYGb5jG5wMyBObJ9Mtw413fpifYjcp0ka86rLsI6jL T3fevnJLFuowCuKLindWKQ== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:16:00 +0900 Subject: [PATCH v11 19/21] KVM: arm64: PMU: Implement fixed-counters-only emulation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-19-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=8244; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=07g7Wsnxy7TV71yYjMKtl6l/jv8TXnMqlazGTus0lG4=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A4UWPwwz+YoP+p378f99InMC40/BpPhH57TfJKpO9 Lz9vlCvo5SFQYyLQVZMkSWlaDe3RnTtp8KE+BaYOaxMIEMYuDgFYCKHUhj+GSxJSYyd7lhsPUHp OPfhTxdZozmtXkp69J113mnOdOVtLcN/Fzftn+d3PJ9TaMZ7XzTsaLark8eW8ANXonZufcF0X7q LDwA= X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C Add internal state for PMUv3 emulation without programmable event counters. When fixed-counters-only mode is active, KVM reports no programmable counters and hides PMCEID, avoiding event-counter state whose behavior can depend on the selected hardware PMU. The cycle counter still uses a host perf event. Unlike the normal PMU path, fixed-counters-only mode may create that event from the hardware PMU attached to the VCPU's current pCPU. If the VCPU later loads on a pCPU that is not covered by the existing event's PMU, request a PMU reload so the cycle counter can be recreated against the new pCPU's PMU. Keep this affinity check limited to fixed-counters-only VMs; the normal programmable-counter mode continues to use the VM-wide PMU and does not need per-load reload decisions. Registered pPMUs must cover every CPU on which fixed-counters-only emulation runs. On ACPI systems, a CPU brought online after PMU probing may have an unregistered PMU implementation. Full coverage is also not guaranteed when ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS is present. Fixed-counters-only emulation is not supported once a vCPU runs on an uncovered CPU. If event creation detects such a CPU, warn and add TAINT_CPU_OUT_OF_SPEC. Add a separate internal flag for explicit userspace PMU selection. The UAPI wiring added later will use it to keep explicit PMU selection and fixed-counters-only mode mutually exclusive while still allowing fixed-counters-only mode to replace the default PMU selected during KVM_ARM_VCPU_INIT. The UAPI wiring that sets the fixed-counters-only flag and records explicit PMU selection is added later in the series. Assisted-by: Codex:gpt-5.5 Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/kvm_host.h | 4 +++ arch/arm64/kvm/arm.c | 2 ++ arch/arm64/kvm/pmu-emul.c | 60 ++++++++++++++++++++++++++++++++++-= ---- include/kvm/arm_pmu.h | 2 ++ 4 files changed, 61 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 766c5cb32f54..d273bfc4cbaf 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -367,6 +367,10 @@ struct kvm_arch { #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS 10 /* Unhandled SEAs are taken to userspace */ #define KVM_ARCH_FLAG_EXIT_SEA 11 + /* PMUv3 is emulated with an explicitly specified hardware PMU */ +#define KVM_ARCH_FLAG_PMU_V3_EXPLICIT 12 + /* PMUv3 is emulated without programmable event counters */ +#define KVM_ARCH_FLAG_PMU_V3_FIXED_COUNTERS_ONLY 13 unsigned long flags; =20 /* VM-wide vCPU feature set */ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 55b07926ce2e..4b1f06a36055 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -665,6 +665,7 @@ static bool kvm_vcpu_should_clear_twe(struct kvm_vcpu *= vcpu) void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { struct kvm_s2_mmu *mmu; + int last_cpu =3D vcpu->cpu; int *last_ran; =20 if (is_protected_kvm_enabled()) @@ -714,6 +715,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) if (has_vhe()) kvm_vcpu_load_vhe(vcpu); kvm_arch_vcpu_load_fp(vcpu); + kvm_vcpu_load_pmu(vcpu, last_cpu); kvm_vcpu_pmu_restore_guest(vcpu); if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index a303752c5e61..9c1e2f3e41db 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -83,6 +83,11 @@ u64 kvm_pmu_evtyper_mask(struct kvm *kvm) return mask; } =20 +static bool kvm_pmu_fixed_counters_only(struct kvm *kvm) +{ + return test_bit(KVM_ARCH_FLAG_PMU_V3_FIXED_COUNTERS_ONLY, &kvm->arch.flag= s); +} + /** * kvm_pmc_is_64bit - determine if counter is 64bit * @pmc: counter context @@ -725,14 +730,10 @@ static struct arm_pmu *kvm_pmu_probe_armpmu(int cpu) return NULL; } =20 -/** - * kvm_pmu_create_perf_event - create a perf event for a counter - * @pmc: Counter context - */ -static void kvm_pmu_create_perf_event(struct kvm_pmc *pmc) +static void kvm_pmu_create_perf_event_with_pmu(struct kvm_pmc *pmc, + struct arm_pmu *arm_pmu) { struct kvm_vcpu *vcpu =3D kvm_pmc_to_vcpu(pmc); - struct arm_pmu *arm_pmu =3D vcpu->kvm->arch.arm_pmu; struct perf_event *event; struct perf_event_attr attr; int eventsel; @@ -766,7 +767,7 @@ static void kvm_pmu_create_perf_event(struct kvm_pmc *p= mc) * Don't create an event if we're running on hardware that requires * PMUv3 event translation and we couldn't find a valid mapping. */ - eventsel =3D kvm_map_pmu_event(vcpu->kvm->arch.arm_pmu, eventsel); + eventsel =3D kvm_map_pmu_event(arm_pmu, eventsel); if (eventsel < 0) return; =20 @@ -811,6 +812,32 @@ static void kvm_pmu_create_perf_event(struct kvm_pmc *= pmc) pmc->perf_event =3D event; } =20 +/** + * kvm_pmu_create_perf_event - create a perf event for a counter + * @pmc: Counter context + */ +static void kvm_pmu_create_perf_event(struct kvm_pmc *pmc) +{ + struct kvm_vcpu *vcpu =3D kvm_pmc_to_vcpu(pmc); + struct arm_pmu *arm_pmu =3D vcpu->kvm->arch.arm_pmu; + + if (kvm_pmu_fixed_counters_only(vcpu->kvm)) { + do { + arm_pmu =3D kvm_pmu_probe_armpmu(READ_ONCE(vcpu->cpu)); + + if (!arm_pmu) { + pr_warn_once("kvm: Unsupported PMU variation detected.\n"); + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + return; + } + + kvm_pmu_create_perf_event_with_pmu(pmc, arm_pmu); + } while (!cpumask_test_cpu(READ_ONCE(vcpu->cpu), &arm_pmu->supported_cpu= s)); + } else { + kvm_pmu_create_perf_event_with_pmu(pmc, arm_pmu); + } +} + /** * kvm_pmu_set_counter_event_type - set selected counter to monitor some e= vent * @vcpu: The vcpu pointer @@ -897,6 +924,13 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmc= eid1) u64 val, mask =3D 0; int base, i, nr_events; =20 + /* + * Hide the hardware PMU's event set to keep PMCEID stable across + * physical CPU migration. + */ + if (kvm_pmu_fixed_counters_only(vcpu->kvm)) + return 0; + if (!pmceid1) { val =3D compute_pmceid0(vcpu); base =3D 0; @@ -924,6 +958,15 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmc= eid1) return val & mask; } =20 +void kvm_vcpu_load_pmu(struct kvm_vcpu *vcpu, int last_cpu) +{ + if (!kvm_pmu_fixed_counters_only(vcpu->kvm) || vcpu->cpu =3D=3D last_cpu = || last_cpu =3D=3D -1) + return; + + if (kvm_pmu_probe_armpmu(vcpu->cpu) !=3D kvm_pmu_probe_armpmu(last_cpu)) + kvm_pmu_request_recreate(vcpu); +} + void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu) { struct kvm_pmu *pmu =3D &vcpu->arch.pmu; @@ -1048,6 +1091,9 @@ u8 kvm_arm_pmu_get_max_counters(struct kvm *kvm) { struct arm_pmu *arm_pmu =3D kvm->arch.arm_pmu; =20 + if (kvm_pmu_fixed_counters_only(kvm)) + return 0; + /* * Under KVM_ARM_VCPU_PMU_V3_STRICT no PMU exists until userspace sets * one, so this can be reached before arm_pmu is set. Report no diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index fca00f7f4c0a..33d81461f5cd 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -63,6 +63,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val); void kvm_pmu_apply_mdcr(struct kvm_vcpu *vcpu, u64 old, u64 val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, u64 select_idx); +void kvm_vcpu_load_pmu(struct kvm_vcpu *vcpu, int last_cpu); void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu); int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); @@ -176,6 +177,7 @@ static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *v= cpu, bool pmceid1) static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {} static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {} static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {} +static inline void kvm_vcpu_load_pmu(struct kvm_vcpu *vcpu, int last_cpu) = {} static inline void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu) {} static inline u8 kvm_arm_pmu_get_pmuver_limit(void) { --=20 2.55.0 From nobody Thu Sep 24 21:21:25 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D3F13FA5EF; Sun, 20 Sep 2026 11:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903070; cv=none; b=MfHgB/JsDyfvJCHXS5tN1fJ9PoKMJIXz/Ir2/7gb0JKaWPr9o7m7kycTbiwXDm3UzdToOiqFB/Mjh3ZazoHqoeV9LIKKOw96VJ8MpeznD7itRh7GzmhnBxVNAfziI2iK8sAA3YYl+zED0BvaLRginjBL0TLTeFcsrdmiy9gBTC8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789903070; c=relaxed/simple; bh=H2g4538IfXd2kheuqnE5Mr24KkazPziDTCFj6z5rfZc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ixRqQM306uwBw4l/WfdZTawl3fgyOiScxyB67IinQob328EI54omYvWuikDEc4q4w+yMhnSybbGQLUlEJKf5X+0AVt6uEEh+rirJ1zRc1C0bNdXugWUITmf7eh3hKOreWKhI3onQr2XUXJdR6OsCe5TNp/TANc7w96AMu1bKvcU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=tj50jvEo; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="tj50jvEo" Received: from [192.168.10.153] (p865013-ipoe.ipoe.ocn.ne.jp [153.242.222.12]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 68KBG36h088236 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Sun, 20 Sep 2026 20:16:17 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=FmUmPMIGOPuKi9K6lwCbOkYFQrg2Rso9aQclWwVUFGU=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1789902978; v=1; b=tj50jvEoYItTWxs392XVQV/Mhj+zzOFgf21ioC/d8qE5/df2sf77ymKtO6wo0l+F InWA+iyGWaGnn46Xk3GN9296Jxinhj2U4mqNWmFPA98BGKPntQFzwYDqJ59PWLVX ozBCIyap7TdpOI1NuPZjo2RIg0iT1E+ynko26kGfZNk/gITCkFeGyxWFTUbomUau VwVsfj+i43suVGT8P07r9bYUM5TV7rsdmouzNGdukFZiNaJAH7mceb2ONn+GFCU5 vH6gcAepMB24fgmf+FquSkRIjsEnDG9oKP0KjXeU9A4v1EjeOq+YhYLRIKypq18W NolkxNshDZjk1ZHVW+sTJA== From: Akihiko Odaki Date: Sun, 20 Sep 2026 20:16:01 +0900 Subject: [PATCH v11 20/21] KVM: arm64: PMU: Introduce FIXED_COUNTERS_ONLY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-20-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=10538; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=H2g4538IfXd2kheuqnE5Mr24KkazPziDTCFj6z5rfZc=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A0WlBzYFfeNVUtJlvJgzMaiHfdLOR3fdjeWdwlc9+ iig1+fcUcrCIMbFICumyJJStJtbI7r2U2FCfAvMHFYmkCEMXJwCMBEJdYY/XBH10zblK6ca/7Jg PSjdLLnDQuCFZvDql6kBlptssnX+MvwPWp8xcwbHI54JSYmsaVY6K7yX7sxZeEyhIzP1/zXbhA8 sAA== X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C Introduce the KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY attribute to create a "fixed-counters-only" PMU. Much like KVM_ARM_VCPU_PMU_V3_IRQ and other read-write attributes, this attribute provides a getter that facilitates kernel and userspace debugging/testing. Allow strict PMUv3 vCPUs to initialize the PMU after selecting fixed-counters-only mode, without selecting a VM-wide hardware PMU. Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Akihiko Odaki --- Documentation/virt/kvm/api.rst | 8 +++++-- Documentation/virt/kvm/devices/vcpu.rst | 42 ++++++++++++++++++++++++++---= ---- arch/arm64/include/uapi/asm/kvm.h | 1 + arch/arm64/kvm/pmu-emul.c | 34 ++++++++++++++++++++++---- tools/arch/arm64/include/uapi/asm/kvm.h | 1 + 5 files changed, 71 insertions(+), 15 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 1a90598901c5..a6aef405ef87 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -3531,9 +3531,13 @@ Possible features: =20 * Userspace must explicitly select a PMU implementation before initializing the PMU or configuring a PMU event filter + (KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY also satisfies the + initialization requirement; event filtering remains unavailable + in that mode) =20 - * If the PMU implements FEAT_PMUv3p4, PMMIR_EL1.SLOTS provides the - hardware value of the underlying implementation + * If a hardware PMU is selected and implements FEAT_PMUv3p4, + PMMIR_EL1.SLOTS provides its hardware value. In fixed-counters-only + mode, PMMIR_EL1 reads as zero =20 * Writes to PMCR_EL0.N via KVM_SET_ONE_REG are ignored =20 diff --git a/Documentation/virt/kvm/devices/vcpu.rst b/Documentation/virt/k= vm/devices/vcpu.rst index a3f20a4ee4b1..41f6d708ff43 100644 --- a/Documentation/virt/kvm/devices/vcpu.rst +++ b/Documentation/virt/kvm/devices/vcpu.rst @@ -53,9 +53,9 @@ Returns: =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -EEXIST Interrupt number already used -ENODEV PMUv3 not supported or GIC not initialized - -ENXIO PMUv3 not supported, missing VCPU feature, missing - hardware PMU, or interrupt number not set (non-GICv5 - guests, only) + -ENXIO PMUv3 not supported, missing VCPU feature, + neither hardware PMU nor FIXED_COUNTERS_ONLY selected, + or interrupt number not set (non-GICv5 guests only) -EBUSY PMUv3 already initialized =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -64,7 +64,8 @@ virtual GIC implementation, this must be done after initi= alizing the in-kernel irqchip. =20 When the KVM_ARM_VCPU_PMU_V3_STRICT vCPU feature is enabled this must be d= one -after selecting a hardware PMU. +after selecting a hardware PMU or enabling +KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY. =20 1.3 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_FILTER ----------------------------------------- @@ -78,7 +79,8 @@ after selecting a hardware PMU. -ENODEV PMUv3 not supported or GIC not initialized -ENXIO PMUv3 not properly configured or in-kernel irqchip not configured as required prior to calling this attribute - -EBUSY PMUv3 already initialized or a VCPU has already run + -EBUSY PMUv3 already initialized, a VCPU has already run or + FIXED_COUNTERS_ONLY has already been set -EINVAL Invalid filter range =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -123,14 +125,14 @@ after selecting a hardware PMU. =20 :Returns: =20 - =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -EBUSY PMUv3 already initialized, a VCPU has already run or - an event filter has already been set + an event filter or FIXED_COUNTERS_ONLY has already been = set -EFAULT Error accessing the PMU identifier -ENXIO PMU not found -ENODEV PMUv3 not supported or GIC not initialized -ENOMEM Could not allocate memory - =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 Request that the VCPU uses the specified hardware PMU when creating guest = events for the purpose of PMU emulation. The PMU identifier can be read from the = "type" @@ -172,6 +174,30 @@ explicitly selected, or the number of counters is out = of range for the selected PMU. Selecting a new PMU cancels the effect of setting this attribute. =20 +1.6 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY +------------------------------------------------------ + +:Parameters: no additional parameter in kvm_device_attr.addr + +:Returns: + + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D + -EBUSY PMUv3 already initialized, a VCPU has already run, + an event filter has already been set or + a hardware PMU has already been specified + -ENXIO Attempted to get before setting + -ENODEV Attempted to set while PMUv3 not supported + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D + +If set, KVM emulates PMUv3 without programmable event counters. + +With KVM_ARM_VCPU_PMU_V3_STRICT, enabling this attribute satisfies the +PMU selection requirement for KVM_ARM_VCPU_PMU_V3_INIT. + +When this attribute is enabled, the vCPU can run on any physical CPU +that has a PMU, regardless of the underlying implementation. This +attribute is VM-scoped. + 2. GROUP: KVM_ARM_VCPU_TIMER_CTRL =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index 65ee09bd1463..7a6a0af14f5a 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -453,6 +453,7 @@ struct kvm_vgic_v5_ist { #define KVM_ARM_VCPU_PMU_V3_FILTER 2 #define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 #define KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERS 4 +#define KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY 5 #define KVM_ARM_VCPU_TIMER_CTRL 1 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 9c1e2f3e41db..ebb648eabdc6 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -1017,8 +1017,8 @@ int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu) =20 static int kvm_arm_pmu_v3_init(struct kvm_vcpu *vcpu) { - /* Only possible when using KVM_ARM_VCPU_PMU_V3_STRICT */ - if (!vcpu->kvm->arch.arm_pmu) + /* Strict PMUv3 requires a hardware PMU or fixed-counters-only mode. */ + if (!vcpu->kvm->arch.arm_pmu && !kvm_pmu_fixed_counters_only(vcpu->kvm)) return -ENXIO; =20 if (irqchip_in_kernel(vcpu->kvm)) { @@ -1153,8 +1153,8 @@ int kvm_arm_set_default_pmu(struct kvm *kvm) * affines the VMM to a particular cluster of cores. * * In any case, userspace should just do the sane thing and use the UAPI - * to select a PMU type directly. But, be wary of the baggage being - * carried here. + * to select a PMU type directly, or request fixed-counters-only + * emulation. But, be wary of the baggage being carried here. */ struct arm_pmu *arm_pmu =3D kvm_pmu_probe_armpmu(raw_smp_processor_id()); =20 @@ -1179,11 +1179,13 @@ static int kvm_arm_pmu_v3_set_pmu(struct kvm_vcpu *= vcpu, int pmu_id) arm_pmu =3D entry->arm_pmu; if (arm_pmu->pmu.type =3D=3D pmu_id) { if (kvm_vm_has_ran_once(kvm) || + kvm_pmu_fixed_counters_only(kvm) || (kvm->arch.pmu_filter && kvm->arch.arm_pmu !=3D arm_pmu)) { ret =3D -EBUSY; break; } =20 + set_bit(KVM_ARCH_FLAG_PMU_V3_EXPLICIT, &kvm->arch.flags); kvm_arm_set_pmu(kvm, arm_pmu); cpumask_copy(kvm->arch.supported_cpus, &arm_pmu->supported_cpus); =20 @@ -1205,6 +1207,22 @@ static int kvm_arm_pmu_v3_set_pmu(struct kvm_vcpu *v= cpu, int pmu_id) return ret; } =20 +static int kvm_arm_pmu_v3_set_pmu_fixed_counters_only(struct kvm_vcpu *vcp= u) +{ + struct kvm *kvm =3D vcpu->kvm; + + lockdep_assert_held(&kvm->arch.config_lock); + + if (kvm_vm_has_ran_once(kvm) || kvm->arch.pmu_filter || + test_bit(KVM_ARCH_FLAG_PMU_V3_EXPLICIT, &kvm->arch.flags)) + return -EBUSY; + + set_bit(KVM_ARCH_FLAG_PMU_V3_FIXED_COUNTERS_ONLY, &kvm->arch.flags); + kvm->arch.nr_pmu_counters =3D 0; + + return 0; +} + static int kvm_arm_pmu_v3_set_nr_counters(struct kvm_vcpu *vcpu, unsigned = int n) { struct kvm *kvm =3D vcpu->kvm; @@ -1282,7 +1300,7 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, st= ruct kvm_device_attr *attr) filter.action !=3D KVM_PMU_EVENT_DENY)) return -EINVAL; =20 - if (kvm_vm_has_ran_once(kvm)) + if (kvm_vm_has_ran_once(kvm) || kvm_pmu_fixed_counters_only(kvm)) return -EBUSY; =20 if (!kvm->arch.arm_pmu) @@ -1330,6 +1348,8 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, st= ruct kvm_device_attr *attr) =20 return kvm_arm_pmu_v3_set_nr_counters(vcpu, n); } + case KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY: + return kvm_arm_pmu_v3_set_pmu_fixed_counters_only(vcpu); case KVM_ARM_VCPU_PMU_V3_INIT: return kvm_arm_pmu_v3_init(vcpu); } @@ -1356,6 +1376,9 @@ int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu, st= ruct kvm_device_attr *attr) irq =3D vcpu->arch.pmu.irq_num; return put_user(irq, uaddr); } + case KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY: + if (kvm_pmu_fixed_counters_only(vcpu->kvm)) + return 0; } =20 return -ENXIO; @@ -1369,6 +1392,7 @@ int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, st= ruct kvm_device_attr *attr) case KVM_ARM_VCPU_PMU_V3_FILTER: case KVM_ARM_VCPU_PMU_V3_SET_PMU: case KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERS: + case KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY: if (kvm_vcpu_has_pmu(vcpu)) return 0; } diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/inc= lude/uapi/asm/kvm.h index 9998252ea8ec..ec428d9f4ab4 100644 --- a/tools/arch/arm64/include/uapi/asm/kvm.h +++ b/tools/arch/arm64/include/uapi/asm/kvm.h @@ -452,6 +452,7 @@ struct kvm_vgic_v5_ist { #define KVM_ARM_VCPU_PMU_V3_FILTER 2 #define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 #define KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERS 4 +#define KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY 5 #define KVM_ARM_VCPU_TIMER_CTRL 1 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 --=20 2.55.0 From nobody Thu Sep 24 21:21:26 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8ECBA403B18; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260920-hybrid-v11-21-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> References: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260920-hybrid-v11-0-03618771b0e1@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Shuah Khan , Yury Norov , Rasmus Villemoes , Steffen Eiden , Andrew Jones , Fuad Tabba , Mark Rutland , Sean Christopherson , Shannon Zhao , Randy Dunlap , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=11665; i=odaki@rsg.ci.i.u-tokyo.ac.jp; h=from:subject:message-id; bh=z4iUiM9bC55rfw6jduOct1366YhypIYol3KPCgIE8E8=; b=owGbwMvMwCWmMbc20y1CyJDxtFoSQ9b6A8VvJ3Qf+/Dv8eKyjJOhy///YDpYOX+l8BO51bM2P /vzPn6+XkcpC4MYF4OsmCJLStFubo3o2k+FCfEtMHNYmUCGMHBxCsBEZm1iZPijnHTtUdfBDQFp D6qd0zlfRjZNS6pJYIvXXHw2eFJa+yaG/1HvK5isJxUJVDypvCfvP8k+02lJoVLr7QkcIqJG02T O8QMA X-Developer-Key: i=odaki@rsg.ci.i.u-tokyo.ac.jp; a=openpgp; fpr=AEDC03C9AF734F2EC26A7BFFA4BAEAA73536753C Assert the following: - FIXED_COUNTERS_ONLY is unset at initialization. - FIXED_COUNTERS_ONLY can be set. - Setting an event filter when FIXED_COUNTERS_ONLY has already been set results in EBUSY. - Setting FIXED_COUNTERS_ONLY when an event filter has already been set results in EBUSY. - Setting FIXED_COUNTERS_ONLY when a VCPU has already run results in EBUSY. Also verify that strict PMUv3 initialization requires a PMU selection and succeeds after selecting fixed-counters-only mode. Run the existing PMU and MDCR_EL2 tests in fixed-only mode. Verify that enabling the mode preserves the userspace MDCR_EL2 value until a subsequent KVM_ARM_VCPU_INIT resets HPMN to zero. Assisted-by: Codex:gpt-5.5 Signed-off-by: Akihiko Odaki --- .../selftests/kvm/arm64/vpmu_counter_access.c | 202 +++++++++++++++++= +--- 1 file changed, 173 insertions(+), 29 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c b/tool= s/testing/selftests/kvm/arm64/vpmu_counter_access.c index 73b4f1870d3d..637653f7a25b 100644 --- a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c +++ b/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c @@ -411,12 +411,7 @@ static void create_vpmu_vm(void *guest_code) { struct kvm_vcpu_init init; u8 pmuver, ec; - u64 dfr0, irq =3D 23; - struct kvm_device_attr irq_attr =3D { - .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, - .attr =3D KVM_ARM_VCPU_PMU_V3_IRQ, - .addr =3D (u64)&irq, - }; + u64 dfr0; =20 /* The test creates the vpmu_vm multiple times. Ensure a clean state */ memset(&vpmu_vm, 0, sizeof(vpmu_vm)); @@ -442,8 +437,6 @@ static void create_vpmu_vm(void *guest_code) TEST_ASSERT(pmuver !=3D ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver >=3D ID_AA64DFR0_EL1_PMUVer_IMP, "Unexpected PMUVER (0x%x) on the vCPU with PMUv3", pmuver); - - vcpu_ioctl(vpmu_vm.vcpu, KVM_SET_DEVICE_ATTR, &irq_attr); } =20 static void destroy_vpmu_vm(void) @@ -493,13 +486,22 @@ static void set_nr_counters(struct kvm_vcpu *vcpu, } =20 static void test_create_vpmu_vm_with_nr_counters(unsigned int nr_counters, + bool fixed_counters_only, bool expect_fail) { struct kvm_vcpu *vcpu; + u64 irq =3D 23; =20 create_vpmu_vm(guest_code); vcpu =3D vpmu_vm.vcpu; =20 + if (fixed_counters_only) + vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY, NULL); + + vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_IRQ, &irq); + set_nr_counters(vcpu, nr_counters, expect_fail); =20 vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, KVM_ARM_VCPU_PMU_V3_= INIT, NULL); @@ -509,15 +511,15 @@ static void test_create_vpmu_vm_with_nr_counters(unsi= gned int nr_counters, * Create a guest with one vCPU, set the PMCR_EL0.N for the vCPU to @pmcr_= n, * and run the test. */ -static void run_access_test(u64 pmcr_n) +static void run_access_test(u64 pmcr_n, bool fixed_counters_only) { u64 sp; struct kvm_vcpu *vcpu; struct kvm_vcpu_init init; =20 - pr_debug("Test with pmcr_n %lu\n", pmcr_n); + pr_debug("Test with pmcr_n %lu, fixed_counters_only %d\n", pmcr_n, fixed_= counters_only); =20 - test_create_vpmu_vm_with_nr_counters(pmcr_n, false); + test_create_vpmu_vm_with_nr_counters(pmcr_n, fixed_counters_only, false); vcpu =3D vpmu_vm.vcpu; =20 /* Save the initial sp to restore them later to run the guest again */ @@ -553,14 +555,14 @@ static struct pmreg_sets validity_check_reg_sets[] = =3D { * Create a VM, and check if KVM handles the userspace accesses of * the PMU register sets in @validity_check_reg_sets[] correctly. */ -static void run_pmregs_validity_test(u64 pmcr_n) +static void run_pmregs_validity_test(u64 pmcr_n, bool fixed_counters_only) { int i; struct kvm_vcpu *vcpu; u64 set_reg_id, clr_reg_id, reg_val; u64 valid_counters_mask, max_counters_mask; =20 - test_create_vpmu_vm_with_nr_counters(pmcr_n, false); + test_create_vpmu_vm_with_nr_counters(pmcr_n, fixed_counters_only, false); vcpu =3D vpmu_vm.vcpu; =20 valid_counters_mask =3D get_counters_mask(pmcr_n); @@ -605,13 +607,15 @@ static void run_pmregs_validity_test(u64 pmcr_n) destroy_vpmu_vm(); } =20 -static void run_mdcr_el2_validity_test(u64 pmcr_n) +static void run_mdcr_el2_validity_test(u64 pmcr_n, bool fixed_counters_onl= y) { struct kvm_vcpu_init init; struct kvm_vcpu *vcpu; u64 expected_mdcr, mdcr; + u64 irq =3D 23; =20 - pr_debug("MDCR_EL2 test with pmcr_n %lu\n", pmcr_n); + pr_debug("MDCR_EL2 test with pmcr_n %lu, fixed_counters_only %d\n", + pmcr_n, fixed_counters_only); =20 create_vpmu_vm(guest_code); if (!vm_supports_el2(vpmu_vm.vm)) { @@ -632,6 +636,16 @@ static void run_mdcr_el2_validity_test(u64 pmcr_n) "MDCR_EL2 was not properly updated after HPMN write (expected 0x%lx,= got 0x%lx)", expected_mdcr, mdcr); =20 + if (fixed_counters_only) { + vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY, NULL); + + mdcr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MDCR_EL2)); + TEST_ASSERT(mdcr =3D=3D expected_mdcr, + "MDCR_EL2 changed after PMU_V3_FIXED_COUNTERS_ONLY (expected 0x%lx,= got 0x%lx)", + expected_mdcr, mdcr); + } + set_nr_counters(vcpu, pmcr_n, false); =20 mdcr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MDCR_EL2)); @@ -639,6 +653,9 @@ static void run_mdcr_el2_validity_test(u64 pmcr_n) "MDCR_EL2 changed after PMU_V3_SET_NR_COUNTERS (expected 0x%lx, got = 0x%lx)", expected_mdcr, mdcr); =20 + vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_IRQ, &irq); + vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, KVM_ARM_VCPU_PMU_V3_INIT, NULL); =20 @@ -673,11 +690,11 @@ static void run_mdcr_el2_validity_test(u64 pmcr_n) * the vCPU to @pmcr_n, which is larger than the host value. * The attempt should fail as @pmcr_n is too big to set for the vCPU. */ -static void run_error_test(u64 pmcr_n) +static void run_error_test(u64 pmcr_n, bool fixed_counters_only) { pr_debug("Error test with pmcr_n %lu (larger than the host)\n", pmcr_n); =20 - test_create_vpmu_vm_with_nr_counters(pmcr_n, true); + test_create_vpmu_vm_with_nr_counters(pmcr_n, fixed_counters_only, true); destroy_vpmu_vm(); } =20 @@ -738,25 +755,152 @@ static void test_set_nr_counters_after_vcpu_run(void) kvm_vm_free(vm); } =20 -int main(void) +static void test_config(u64 pmcr_n, bool fixed_counters_only) +{ + u64 i; + + for (i =3D 0; i <=3D pmcr_n; i++) { + run_access_test(i, fixed_counters_only); + run_pmregs_validity_test(i, fixed_counters_only); + run_mdcr_el2_validity_test(i, fixed_counters_only); + } + + for (i =3D pmcr_n + 1; i < ARMV8_PMU_MAX_COUNTERS; i++) + run_error_test(i, fixed_counters_only); +} + +static void test_fixed_counters_only_strict(void) +{ + struct kvm_vcpu_init init; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + u64 irq =3D 23; + int ret; + + if (!kvm_has_cap(KVM_CAP_ARM_PMU_V3_STRICT)) + return; + + vm =3D vm_create(1); + kvm_get_default_vcpu_target(vm, &init); + init.features[0] |=3D BIT(KVM_ARM_VCPU_PMU_V3) | + BIT(KVM_ARM_VCPU_PMU_V3_STRICT); + vcpu =3D aarch64_vcpu_add(vm, 0, &init, guest_code_done); + kvm_arch_vm_finalize_vcpus(vm); + vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_IRQ, &irq); + + /* STRICT still requires a PMU selection before initialization. */ + ret =3D __vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_INIT, NULL); + TEST_ASSERT(ret =3D=3D -1 && errno =3D=3D ENXIO, + KVM_IOCTL_ERROR(KVM_SET_DEVICE_ATTR, ret)); + + vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY, NULL); + vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_INIT, NULL); + + kvm_vm_free(vm); +} + +static void test_fixed_counters_only(void) { - u64 i, pmcr_n; + struct kvm_pmu_event_filter filter =3D { .nevents =3D 0 }; + struct kvm_vm *vm; + struct kvm_vcpu *running_vcpu; + struct kvm_vcpu *stopped_vcpu; + struct kvm_vcpu_init init; + int ret; + u64 irq =3D 23; + + create_vpmu_vm(guest_code); + ret =3D __vcpu_has_device_attr(vpmu_vm.vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY); + if (ret) { + TEST_ASSERT(ret =3D=3D -1 && errno =3D=3D ENXIO, + KVM_IOCTL_ERROR(KVM_HAS_DEVICE_ATTR, ret)); + destroy_vpmu_vm(); + return; + } + + /* Assert that FIXED_COUNTERS_ONLY is unset at initialization. */ + ret =3D __vcpu_device_attr_get(vpmu_vm.vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY, NULL); + TEST_ASSERT(ret =3D=3D -1 && errno =3D=3D ENXIO, + KVM_IOCTL_ERROR(KVM_GET_DEVICE_ATTR, ret)); + + /* Assert that setting FIXED_COUNTERS_ONLY succeeds. */ + vcpu_device_attr_set(vpmu_vm.vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY, NULL); + + /* Assert that FIXED_COUNTERS_ONLY is set. */ + vcpu_device_attr_get(vpmu_vm.vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY, NULL); + + /* + * Setting an event filter when FIXED_COUNTERS_ONLY has already been set + * results in EBUSY. + */ + ret =3D __vcpu_device_attr_set(vpmu_vm.vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FILTER, &filter); + TEST_ASSERT(ret =3D=3D -1 && errno =3D=3D EBUSY, + KVM_IOCTL_ERROR(KVM_SET_DEVICE_ATTR, ret)); + + destroy_vpmu_vm(); + + create_vpmu_vm(guest_code); + + /* + * Assert that setting FIXED_COUNTERS_ONLY when an event filter has + * already been set results in EBUSY. + */ + vcpu_device_attr_set(vpmu_vm.vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FILTER, &filter); + + ret =3D __vcpu_device_attr_set(vpmu_vm.vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY, NULL); + TEST_ASSERT(ret =3D=3D -1 && errno =3D=3D EBUSY, + KVM_IOCTL_ERROR(KVM_SET_DEVICE_ATTR, ret)); + + destroy_vpmu_vm(); + + /* + * Assert that setting FIXED_COUNTERS_ONLY when a VCPU has already run + * results in EBUSY. + */ + vm =3D vm_create(2); + vm_ioctl(vm, KVM_ARM_PREFERRED_TARGET, &init); + init.features[0] |=3D (1 << KVM_ARM_VCPU_PMU_V3); + running_vcpu =3D aarch64_vcpu_add(vm, 0, &init, guest_code_done); + stopped_vcpu =3D aarch64_vcpu_add(vm, 1, &init, guest_code_done); + kvm_arch_vm_finalize_vcpus(vm); + vcpu_device_attr_set(running_vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_IRQ, &irq); + vcpu_device_attr_set(running_vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_INIT, NULL); + run_vcpu(running_vcpu); + + ret =3D __vcpu_device_attr_set(stopped_vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, + KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY, NULL); + TEST_ASSERT(ret =3D=3D -1 && errno =3D=3D EBUSY, + KVM_IOCTL_ERROR(KVM_SET_DEVICE_ATTR, ret)); + + kvm_vm_free(vm); + + test_fixed_counters_only_strict(); =20 + test_config(0, true); +} + +int main(void) +{ TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_PMU_V3)); TEST_REQUIRE(kvm_supports_vgic_v3()); TEST_REQUIRE(kvm_supports_nr_counters_attr()); =20 test_set_nr_counters_after_vcpu_run(); - - pmcr_n =3D get_pmcr_n_limit(); - for (i =3D 0; i <=3D pmcr_n; i++) { - run_access_test(i); - run_pmregs_validity_test(i); - run_mdcr_el2_validity_test(i); - } - - for (i =3D pmcr_n + 1; i < ARMV8_PMU_MAX_COUNTERS; i++) - run_error_test(i); + test_config(get_pmcr_n_limit(), false); + test_fixed_counters_only(); =20 return 0; } --=20 2.55.0