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Suggested-by: Krishna Kurapati Fixes: 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615") Cc: stable@vger.kernel.org Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/p= hy-qcom-qusb2.c index 2e5fdb620cb2..fc516b7cf5fa 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -347,12 +347,11 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg =3D= { static const struct qusb2_phy_cfg qcs615_phy_cfg =3D { .tbl =3D qcs615_init_tbl, .tbl_num =3D ARRAY_SIZE(qcs615_init_tbl), - .regs =3D ipq6018_regs_layout, + .regs =3D msm8996_regs_layout, =20 .disable_ctrl =3D (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), .mask_core_ready =3D PLL_LOCKED, - /* autoresume not used */ - .autoresume_en =3D BIT(0), + .autoresume_en =3D BIT(3), }; =20 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg =3D { --=20 2.47.3 From nobody Thu Sep 24 21:19:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BADAC146D5A for ; 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Instead of programming a fake register bit (BIT(0) of TEST1, while the QUSB2 platforms on that platform should use BIT(3) of TEST_CTRL), explicitly disable autoresume programming on these devices via the flag in the platform data. Fixes: 2cfbe6765b7a ("phy: qcom-qusb2: add QUSB2 support for IPQ6018") Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/p= hy-qcom-qusb2.c index fc516b7cf5fa..a1de05a83128 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -294,6 +294,7 @@ struct qusb2_phy_cfg { unsigned int mask_core_ready; unsigned int disable_ctrl; unsigned int autoresume_en; + bool autoresume_disable; =20 /* true if PHY has PLL_TEST register to select clk_scheme */ bool has_pll_test; @@ -341,6 +342,7 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg =3D { .disable_ctrl =3D POWER_DOWN, .mask_core_ready =3D PLL_LOCKED, /* autoresume not used */ + .autoresume_disable =3D true, .autoresume_en =3D BIT(0), }; =20 @@ -687,7 +689,7 @@ static int __maybe_unused qusb2_phy_runtime_suspend(str= uct device *dev) } =20 /* enable phy auto-resume only if device is connected on bus */ - if (qphy->mode !=3D PHY_MODE_INVALID) { + if (qphy->mode !=3D PHY_MODE_INVALID && !cfg->autoresume_disable) { qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], cfg->autoresume_en); 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Some verions of the QUSB2 PHY have it in the TEST1 register, while on the others it is a part of the TEST_CTRL register. When adding support for autoresume bit, the code attempted to simplify the handling of those registers, putting both registers to the TEST1 layout entry. In the end, ipq6018_regs_layout ended up correctly definig TEST1 register at 0x98 (because platforms using that layout didn't use autoresume), while msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1 layout entry. Update the platform data to specify the register to be used for autoresume handling, define both TEST1 and TEST_CTRL registers and merge ipq6018_regs_layout and msm8996_regs_layout which become identical afterwards. Fixes: 891a96f65ac3 ("phy: qcom-qusb2: Add support for runtime PM") Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 48 +++++++++++++++----------------= ---- 1 file changed, 21 insertions(+), 27 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/p= hy-qcom-qusb2.c index a1de05a83128..101c0820023d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -131,8 +131,13 @@ enum qusb2phy_reg_layout { QUSB2PHY_PORT_TUNE5, QUSB2PHY_PORT_TEST1, QUSB2PHY_PORT_TEST2, + QUSB2PHY_PORT_TEST_CTRL, QUSB2PHY_PORT_POWERDOWN, QUSB2PHY_INTR_CTRL, + + /* layout of the autoresume bit */ + QUSB2PHY_AUTORESUME_REG, + QUSB2PHY_AUTORESUME_BIT, }; =20 static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] =3D { @@ -164,19 +169,6 @@ static const struct qusb2_phy_init_tbl qcs615_init_tbl= [] =3D { QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), }; =20 -static const unsigned int ipq6018_regs_layout[] =3D { - [QUSB2PHY_PLL_STATUS] =3D 0x38, - [QUSB2PHY_PORT_TUNE1] =3D 0x80, - [QUSB2PHY_PORT_TUNE2] =3D 0x84, - [QUSB2PHY_PORT_TUNE3] =3D 0x88, - [QUSB2PHY_PORT_TUNE4] =3D 0x8C, - [QUSB2PHY_PORT_TUNE5] =3D 0x90, - [QUSB2PHY_PORT_TEST1] =3D 0x98, - [QUSB2PHY_PORT_TEST2] =3D 0x9C, - [QUSB2PHY_PORT_POWERDOWN] =3D 0xB4, - [QUSB2PHY_INTR_CTRL] =3D 0xBC, -}; - static const unsigned int msm8996_regs_layout[] =3D { [QUSB2PHY_PLL_STATUS] =3D 0x38, [QUSB2PHY_PORT_TUNE1] =3D 0x80, @@ -184,10 +176,14 @@ static const unsigned int msm8996_regs_layout[] =3D { [QUSB2PHY_PORT_TUNE3] =3D 0x88, [QUSB2PHY_PORT_TUNE4] =3D 0x8c, [QUSB2PHY_PORT_TUNE5] =3D 0x90, - [QUSB2PHY_PORT_TEST1] =3D 0xb8, + [QUSB2PHY_PORT_TEST1] =3D 0x98, [QUSB2PHY_PORT_TEST2] =3D 0x9c, + [QUSB2PHY_PORT_TEST_CTRL] =3D 0xb8, [QUSB2PHY_PORT_POWERDOWN] =3D 0xb4, [QUSB2PHY_INTR_CTRL] =3D 0xbc, + + [QUSB2PHY_AUTORESUME_REG] =3D 0xb8, /* TEST_CTRL */ + [QUSB2PHY_AUTORESUME_BIT] =3D BIT(3), }; =20 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] =3D { @@ -217,6 +213,9 @@ static const unsigned int msm8998_regs_layout[] =3D { [QUSB2PHY_PORT_TEST2] =3D 0x250, [QUSB2PHY_PORT_POWERDOWN] =3D 0x210, [QUSB2PHY_INTR_CTRL] =3D 0x22c, + + [QUSB2PHY_AUTORESUME_REG] =3D 0x24c, /* TEST1 */ + [QUSB2PHY_AUTORESUME_BIT] =3D BIT(0), }; =20 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] =3D { @@ -259,6 +258,9 @@ static const unsigned int qusb2_v2_regs_layout[] =3D { [QUSB2PHY_PORT_TEST2] =3D 0x258, [QUSB2PHY_PORT_POWERDOWN] =3D 0x210, [QUSB2PHY_INTR_CTRL] =3D 0x230, + + [QUSB2PHY_AUTORESUME_REG] =3D 0x254, /* TEST1 */ + [QUSB2PHY_AUTORESUME_BIT] =3D BIT(0), }; =20 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] =3D { @@ -293,7 +295,6 @@ struct qusb2_phy_cfg { const unsigned int *regs; unsigned int mask_core_ready; unsigned int disable_ctrl; - unsigned int autoresume_en; bool autoresume_disable; =20 /* true if PHY has PLL_TEST register to select clk_scheme */ @@ -318,7 +319,6 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg =3D { .se_clk_scheme_default =3D true, .disable_ctrl =3D (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), .mask_core_ready =3D PLL_LOCKED, - .autoresume_en =3D BIT(3), }; =20 static const struct qusb2_phy_cfg msm8998_phy_cfg =3D { @@ -330,20 +330,18 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg =3D= { .mask_core_ready =3D CORE_READY_STATUS, .has_pll_override =3D true, .se_clk_scheme_default =3D true, - .autoresume_en =3D BIT(0), .update_tune1_with_efuse =3D true, }; =20 static const struct qusb2_phy_cfg ipq6018_phy_cfg =3D { .tbl =3D ipq6018_init_tbl, .tbl_num =3D ARRAY_SIZE(ipq6018_init_tbl), - .regs =3D ipq6018_regs_layout, + .regs =3D msm8996_regs_layout, =20 .disable_ctrl =3D POWER_DOWN, .mask_core_ready =3D PLL_LOCKED, /* autoresume not used */ .autoresume_disable =3D true, - .autoresume_en =3D BIT(0), }; =20 static const struct qusb2_phy_cfg qcs615_phy_cfg =3D { @@ -353,7 +351,6 @@ static const struct qusb2_phy_cfg qcs615_phy_cfg =3D { =20 .disable_ctrl =3D (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), .mask_core_ready =3D PLL_LOCKED, - .autoresume_en =3D BIT(3), }; =20 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg =3D { @@ -366,7 +363,6 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg =3D { .mask_core_ready =3D CORE_READY_STATUS, .has_pll_override =3D true, .se_clk_scheme_default =3D true, - .autoresume_en =3D BIT(0), .update_tune1_with_efuse =3D true, }; =20 @@ -379,7 +375,6 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg =3D { .se_clk_scheme_default =3D false, .disable_ctrl =3D (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), .mask_core_ready =3D PLL_LOCKED, - .autoresume_en =3D BIT(3), }; =20 static const struct qusb2_phy_cfg shikra_phy_cfg =3D { @@ -402,7 +397,6 @@ static const struct qusb2_phy_cfg sm6115_phy_cfg =3D { .se_clk_scheme_default =3D true, .disable_ctrl =3D (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), .mask_core_ready =3D PLL_LOCKED, - .autoresume_en =3D BIT(3), }; =20 static const char * const qusb2_phy_vreg_names[] =3D { @@ -690,11 +684,11 @@ static int __maybe_unused qusb2_phy_runtime_suspend(s= truct device *dev) =20 /* enable phy auto-resume only if device is connected on bus */ if (qphy->mode !=3D PHY_MODE_INVALID && !cfg->autoresume_disable) { - qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], - cfg->autoresume_en); + unsigned int reg =3D cfg->regs[QUSB2PHY_AUTORESUME_REG]; + + qusb2_setbits(qphy->base, reg, cfg->regs[QUSB2PHY_AUTORESUME_BIT]); /* Autoresume bit has to be toggled in order to enable it */ - qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], - cfg->autoresume_en); + qusb2_clrbits(qphy->base, reg, cfg->regs[QUSB2PHY_AUTORESUME_BIT]); } =20 if (!qphy->has_se_clk_scheme) --=20 2.47.3