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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v8 01/11] net: stmmac: move XPCS lifetime management to platform drivers Date: Sat, 19 Sep 2026 20:51:08 +0800 Message-ID: <20260919125119.2107089-2-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current XPCS creation logic in stmmac_pcs_setup() is problematic for several reasons. First, if a device tree specifies a "pcs-handle" but no select_pcs() callback is provided by the platform driver, the created XPCS cannot be used by phylink for PCS operations. The framework requires select_pcs() to return the PCS to the core, so the pcs-handle property becomes effectively useless for link management without the matching callback. The XPCS is still consulted by stmmac_phylink_setup() and stmmac_init_phy(), which makes the configuration silently half-working rather than clearly broken. Second, and more critically, when a platform driver sets pcs_init() and creates an XPCS inside that callback, the common code afterwards still runs unconditionally and overwrites priv->hw->xpcs with the local xpcs variable, which stays NULL. The platform driver has no way to prevent this override because the common code runs after the platform-specific initialization. After commit 93f84152e4ae ("net: stmmac: clean up stmmac_mac_select_pcs()"), the common code no longer falls back to priv->hw->phylink_pcs if select_pcs() is not set. This change reinforces that each platform must manage its own PCS life cycle explicitly, but the XPCS creation code in stmmac_pcs_setup() was not updated to match this new expectation, leaving a gap where platform drivers have no clean way to take control of XPCS creation. Address all of these issues by simplifying the existing pcs_init() and pcs_exit() dispatch in stmmac_pcs_setup() and stmmac_pcs_clean(). The common stmmac_pcs_setup() now calls plat->pcs_init() if present, and stmmac_pcs_clean() calls plat->pcs_exit() if present, removing the confusing and error-prone XPCS creation logic from the common code. Platforms that do not need an XPCS simply leave the callbacks as NULL and no change in behavior occurs. Platforms that do need an XPCS can now create it with the exact configuration they require, including wrapping it with custom phylink_pcs_ops when necessary. Note that this also removes the generic "pcs-handle" parsing from the common code. A glue that does not set pcs_init() now leaves priv->hw->xpcs as NULL, and "pcs-handle" becomes a no-op for it. No in-tree platform relies on this path: every DTS that pairs a dwmac node with a PCS goes through a glue that sets pcs_init() (Intel, Renesas, RZ/N1, SoCFPGA, Rockchip). The Intel mGbE glue is updated to create its XPCS inside its own pcs_init() implementation, and the renesas-gbeth, rzn1 and socfpga pcs_exit() callbacks now explicitly clear priv->hw->phylink_pcs after destroying the PCS to avoid dangling pointer references. Reviewed-by: Maxime Chevallier Signed-off-by: Coia Prant --- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 44 +++++++++++++++++-- .../stmicro/stmmac/dwmac-renesas-gbeth.c | 7 ++- .../net/ethernet/stmicro/stmmac/dwmac-rzn1.c | 7 ++- .../ethernet/stmicro/stmmac/dwmac-socfpga.c | 7 ++- .../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 39 +++------------- 5 files changed, 62 insertions(+), 42 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-intel.c index f5f9fa67ecd77..4308dccbf2570 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -603,13 +603,47 @@ static void common_default_data(struct plat_stmmacene= t_data *plat) plat->mdio_bus_data->needs_reset =3D true; } =20 +static int intel_mgbe_pcs_init(struct stmmac_priv *priv) +{ + struct fwnode_handle *devnode, *pcsnode; + struct dw_xpcs *xpcs; + int addr; + + devnode =3D dev_fwnode(priv->device); + + if (fwnode_property_present(devnode, "pcs-handle")) { + pcsnode =3D fwnode_find_reference(devnode, "pcs-handle", 0); + xpcs =3D xpcs_create_fwnode(pcsnode); + fwnode_handle_put(pcsnode); + } else { + addr =3D ffs(priv->plat->mdio_bus_data->pcs_mask) - 1; + xpcs =3D xpcs_create_mdiodev(priv->mii, addr); + } + + if (IS_ERR(xpcs)) + return PTR_ERR(xpcs); + + xpcs_config_eee_mult_fact(xpcs, priv->plat->mult_fact_100ns); + + priv->hw->xpcs =3D xpcs; + return 0; +} + +static void intel_mgbe_pcs_exit(struct stmmac_priv *priv) +{ + if (!priv->hw->xpcs) + return; + + xpcs_destroy(priv->hw->xpcs); + priv->hw->xpcs =3D NULL; +} + static struct phylink_pcs *intel_mgbe_select_pcs(struct stmmac_priv *priv, phy_interface_t interface) { - /* plat->mdio_bus_data->has_xpcs has been set true, so there - * should always be an XPCS. The original code would always - * return this if present. - */ + if (!priv->hw->xpcs) + return NULL; + return xpcs_to_phylink_pcs(priv->hw->xpcs); } =20 @@ -733,6 +767,8 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, plat->phy_interface =3D=3D PHY_INTERFACE_MODE_1000BASEX) { plat->mdio_bus_data->pcs_mask =3D BIT_U32(INTEL_MGBE_XPCS_ADDR); plat->default_an_inband =3D true; + plat->pcs_init =3D intel_mgbe_pcs_init; + plat->pcs_exit =3D intel_mgbe_pcs_exit; plat->select_pcs =3D intel_mgbe_select_pcs; } =20 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c b/dr= ivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c index 19f34e18bfef2..9af32c26f9c14 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c @@ -81,8 +81,11 @@ static int renesas_gmac_pcs_init(struct stmmac_priv *pri= v) =20 static void renesas_gmac_pcs_exit(struct stmmac_priv *priv) { - if (priv->hw->phylink_pcs) - miic_destroy(priv->hw->phylink_pcs); + if (!priv->hw->phylink_pcs) + return; + + miic_destroy(priv->hw->phylink_pcs); + priv->hw->phylink_pcs =3D NULL; } =20 static struct phylink_pcs *renesas_gmac_select_pcs(struct stmmac_priv *pri= v, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rzn1.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac-rzn1.c index 13634965bc19a..01df4776edb3f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rzn1.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rzn1.c @@ -35,8 +35,11 @@ static int rzn1_dwmac_pcs_init(struct stmmac_priv *priv) =20 static void rzn1_dwmac_pcs_exit(struct stmmac_priv *priv) { - if (priv->hw->phylink_pcs) - miic_destroy(priv->hw->phylink_pcs); + if (!priv->hw->phylink_pcs) + return; + + miic_destroy(priv->hw->phylink_pcs); + priv->hw->phylink_pcs =3D NULL; } =20 static struct phylink_pcs *rzn1_dwmac_select_pcs(struct stmmac_priv *priv, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 1d7f0a57d2889..6d4bc1fe8f751 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -539,8 +539,11 @@ static int socfpga_dwmac_pcs_init(struct stmmac_priv *= priv) =20 static void socfpga_dwmac_pcs_exit(struct stmmac_priv *priv) { - if (priv->hw->phylink_pcs) - lynx_pcs_destroy(priv->hw->phylink_pcs); + if (!priv->hw->phylink_pcs) + return; + + lynx_pcs_destroy(priv->hw->phylink_pcs); + priv->hw->phylink_pcs =3D NULL; } =20 static struct phylink_pcs *socfpga_dwmac_select_pcs(struct stmmac_priv *pr= iv, diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_mdio.c index afe98ff5bdcb0..7396b68899c66 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -426,35 +426,14 @@ int stmmac_mdio_reset(struct mii_bus *bus) int stmmac_pcs_setup(struct net_device *ndev) { struct stmmac_priv *priv =3D netdev_priv(ndev); - struct fwnode_handle *devnode, *pcsnode; - struct dw_xpcs *xpcs =3D NULL; - int addr, ret; - - devnode =3D dev_fwnode(priv->device); - - if (priv->plat->pcs_init) { - ret =3D priv->plat->pcs_init(priv); - } else if (fwnode_property_present(devnode, "pcs-handle")) { - pcsnode =3D fwnode_find_reference(devnode, "pcs-handle", 0); - xpcs =3D xpcs_create_fwnode(pcsnode); - fwnode_handle_put(pcsnode); - ret =3D PTR_ERR_OR_ZERO(xpcs); - } else if (priv->plat->mdio_bus_data && - priv->plat->mdio_bus_data->pcs_mask) { - addr =3D ffs(priv->plat->mdio_bus_data->pcs_mask) - 1; - xpcs =3D xpcs_create_mdiodev(priv->mii, addr); - ret =3D PTR_ERR_OR_ZERO(xpcs); - } else { + int ret; + + if (!priv->plat->pcs_init) return 0; - } =20 + ret =3D priv->plat->pcs_init(priv); if (ret) - return dev_err_probe(priv->device, ret, "No xPCS found\n"); - - if (xpcs) - xpcs_config_eee_mult_fact(xpcs, priv->plat->mult_fact_100ns); - - priv->hw->xpcs =3D xpcs; + return dev_err_probe(priv->device, ret, "Failed to initialize PCS\n"); =20 return 0; } @@ -463,14 +442,10 @@ void stmmac_pcs_clean(struct net_device *ndev) { struct stmmac_priv *priv =3D netdev_priv(ndev); =20 - if (priv->plat->pcs_exit) - priv->plat->pcs_exit(priv); - - if (!priv->hw->xpcs) + if (!priv->plat->pcs_exit) return; =20 - xpcs_destroy(priv->hw->xpcs); - priv->hw->xpcs =3D NULL; + priv->plat->pcs_exit(priv); } =20 struct stmmac_clk_rate { --=20 2.47.3 From nobody Thu Sep 24 22:17:45 2026 Received: from mail-pz2-f7.google.com (mail-pz2-f7.google.com [74.125.228.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75BB43D4125 for ; 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Sat, 19 Sep 2026 05:52:00 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877aa0026b2sm991805b3a.44.2026.09.19.05.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 05:51:59 -0700 (PDT) From: Coia Prant To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v8 02/11] dt-bindings: phy: rockchip: naneng-combphy: add rockchip,sgmii-mac-sel property Date: Sat, 19 Sep 2026 20:51:09 +0800 Message-ID: <20260919125119.2107089-3-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On RK3568, the SGMII interface can be routed to either GMAC0 or GMAC1 via the pipe_sgmii_mac_sel bit in the pipe GRF registers. Add the optional "rockchip,sgmii-mac-sel" property to allow the device tree to select which GMAC controller is used for SGMII. The property takes a value of 0 (GMAC0) or 1 (GMAC1). The hardware reset value is 1 (GMAC1), but this can be overridden by setting the property to 0 for boards where SGMII is connected to GMAC0. This is necessary for boards such as the Ariaboard Photonicat, where the SGMII interface is connected to GMAC0 and needs to be explicitly configured. Signed-off-by: Coia Prant --- .../bindings/phy/phy-rockchip-naneng-combphy.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-comb= phy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combph= y.yaml index 379b08bd9e97a..8e898bce9af73 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -80,6 +80,15 @@ properties: description: Some additional pipe settings are accessed through GRF regs. =20 + rockchip,sgmii-mac-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + default: 1 + description: + Select gmac0 or gmac1 to be used as SGMII controller. + The hardware reset value is GMAC1 (1). Set this to 0 to route + SGMII to GMAC0. + "#phy-cells": const: 1 =20 @@ -105,6 +114,10 @@ allOf: maxItems: 1 reset-names: maxItems: 1 + rockchip,sgmii-mac-sel: true + else: + properties: + rockchip,sgmii-mac-sel: false - if: properties: compatible: --=20 2.47.3 From nobody Thu Sep 24 22:17:45 2026 Received: from mail-pz2-f7.google.com (mail-pz2-f7.google.com [74.125.228.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1DA3547054 for ; Sat, 19 Sep 2026 12:52:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.228.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789822330; cv=none; b=k9sG8soCxYv7LulbfFGupL951xGnNFEZmB5F6MSNThf198Nao4lQCPmiBXmJAngG6fV3LPbNIoFVL1FUQpulMHzSmkvaqflldjOr/zQVliWk5pchXdLhzItUQjMTtRJde2GHsa5suQLmH5jArG4s+Qi/g5HR65uAumkwo/CkmNU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789822330; c=relaxed/simple; bh=kq0vt9SckJqy94uGlHWiGVuBk0MckU/fwsg6pcjJXHQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=numyKP0MfBbFsxaXvKwM7GG/lsTny1xhB0uVhkwQoFx6H2Ciz1uE9qekDeW7v6iT+LzD4/OShtdbgipRmmc3dEWznbOsN0jHxB38acPNp9ZrEeiG4tBkW2Wl4P/Om5HGDlpii7qbTnQJOkRESJIqeeg+Juk5M6EDk5tz7b3PreA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Jdxqjq0V; arc=none smtp.client-ip=74.125.228.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Jdxqjq0V" Received: by mail-pz2-f7.google.com with SMTP id 41be03b00d2f7-cc4b166d0dbso508953a12.1 for ; Sat, 19 Sep 2026 05:52:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1789822328; x=1790427128; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=8Rz7MTGiT2Oa/TzTvQEqnIct/KOrKk64RBkMgo9sxQM=; b=Jdxqjq0VmMwRp50c0qY+wBHZAWv90bRotdqMAKzhysvWLI19x4ncF//WIjaGl79/YK S+oLZeavTd0M2vL9pdExRV3Rs2e0ioLc7ESD1DQKZ2d9qmcyj5BU60a4gMmSaQrRszTG Qb4ruo7B20u1To5PeC6wOX0JD6v+3vparHN4StCnD0HjEhoyZ30JtIKIC2V0qPIj+IS3 8npN/VJHe5afnbeYPjgvBcW9oQO1ufQ8fLefOaaMtLRJCNmcM3/5x/ev3H2ot7JUNofE L2FEoMFmGuvsKRr8oGAF6pSeo5zV2HXkq3McHY6cPpmSyH4Mf8EZZsn+6QgGY5XpmE58 m+cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1789822328; x=1790427128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=8Rz7MTGiT2Oa/TzTvQEqnIct/KOrKk64RBkMgo9sxQM=; b=yUhJarzsEIcqJwaSTP4vPnRIlOWiPcdTO7afgUi25aZOPXoJRi1yoXWYyCHKmGfuia 34zn9xjAje4v5IA70C6aknDx3FtVfqDOm4ZD7BPn3TlqGD+3d9EWkRyKZbHyEV7KDOq7 uwLUpOzA+Jcg4z4q4DpmYgEOlxPkPOGpkUN9qzkGV+15DB1f0Ey3VFGsNG6du5QiWRvu 7PvwjX95E6mBis8u4ao2S1suHR2+922d1WtNOJgp8bUojtqz+FGKsgtMEODVgYGl+gqb M5Mvvv6NsvlN3SsbGhgGVnm3nzBHsiQfe+BxFLQZxAX6R0pLOfsVVLD020MrXKT+LSKp mr5Q== X-Forwarded-Encrypted: i=1; AKwUvBxnMMhx0lgNv9YCSlRuHhojPjN5fgjCI1HZBbsdrGGurOe2iSA2rwxzEisViaDlsENX/N6HO0qVUcTAb7Q=@vger.kernel.org X-Gm-Message-State: AFuF++konVTLe0LImBVaWus1px1pUnloMF83FcEvpHwqMdTHclPQu2OE RB/l5yjO4BFyV5EuD4os3+FgLQuRp8Ph5z3oct0qnpXFLXzBXsjKHclq X-Gm-Gg: AYBFou3Qtg7ps0N13tHd6scHctEW+A+qiyCgBY2xoUTCuMul/tBipsxvpPGiUB8k4XL zse2T+S0hRLdYv1HI+c5We/uOB7VUU/9QBSDEWoaSaQURdDDLaD8qAo8lRi/TyZIAuLYZ+rN7FS GWP75eCuG2hbi22bE//DFcjwtzg83aOl+Q0MvSkE0BLkpkrHSpXW3EJFKEZxbFLTx8nrloItSIF dYP/DHHtyxFwYp8FtufhgRy2RMb9qbg9gUnLg9OsPcuTwlwWM7lc9EDfXbotWWBKi6susxAIpib D2nIFmOQp9IooVUxVQKf2st1NL4bAi0cHYsVAzDdwzT3aO8PYxC5Tf6wVVr39cTenNfkpPPWyah SAjiX8MT3hUDFvR4OaDzK+79pIYF+E9epC1QTy0+z3FYqBMAjJZpbT+bImnFcEEE2DgRoMHrwOz IBw0FEgBnNSJcZLKDcF5wlQ9sHaFYC2n1+c3gt7uuQ0gY5dINL9fHK3B1vGhE9TC2Gwo8hixE= X-Received: by 2002:a05:6a00:3a02:b0:868:f29f:67c9 with SMTP id d2e1a72fcca58-874dcbee984mr8960818b3a.9.1789822328120; Sat, 19 Sep 2026 05:52:08 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877aa0026b2sm991805b3a.44.2026.09.19.05.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 05:52:07 -0700 (PDT) From: Coia Prant To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v8 03/11] phy: rockchip: naneng-combphy: add SGMII MAC selection for RK3568 Date: Sat, 19 Sep 2026 20:51:10 +0800 Message-ID: <20260919125119.2107089-4-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On RK3568, the SGMII interface can be routed to either GMAC0 or GMAC1 via the GRF register pipe_sgmii_mac_sel. Add support for this selection by introducing the "rockchip,sgmii-mac-sel" DT property. From the RK3568 TRM (Part1, Page 229), the PIPE_GRF_XPCS_CON0 bit 1 (pipe_sgmii_mac_sel) is defined as: 0: SGMII routed to GMAC0 1: SGMII routed to GMAC1 The hardware reset value is 1 (GMAC1). If the property is set to 0, the driver routes SGMII to GMAC0; if set to 1 (or omitted), it remains at GMAC1. This is necessary for boards such as the Ariaboard Photonicat, which uses the SGMII interface connected to GMAC0. Out-of-range values are rejected by dtschema, so the driver does not duplicate the range check. Link: https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%= 20Part1%20V1.1-20210301.pdf (Page 229) Signed-off-by: Coia Prant --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/p= hy/rockchip/phy-rockchip-naneng-combphy.c index 7843356a4dd47..7b867e7520064 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -186,6 +186,7 @@ struct rockchip_combphy_grfcfg { struct combphy_reg pipe_xpcs_phy_ready; struct combphy_reg pipe_pcie1l0_sel; struct combphy_reg pipe_pcie1l1_sel; + struct combphy_reg pipe_sgmii_mac_sel; struct combphy_reg u3otg0_port_en; struct combphy_reg u3otg1_port_en; }; @@ -212,6 +213,7 @@ struct rockchip_combphy_priv { bool enable_ssc; bool ext_refclk; struct clk *refclk; + u32 sgmii_mac_sel; }; =20 static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, @@ -375,6 +377,9 @@ static int rockchip_combphy_parse_dt(struct device *dev= , struct rockchip_combphy =20 priv->ext_refclk =3D device_property_present(dev, "rockchip,ext-refclk"); =20 + priv->sgmii_mac_sel =3D 1; + device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &priv->sgmii_mac_= sel); + priv->phy_rst =3D devm_reset_control_get_exclusive(dev, "phy"); /* fallback to old behaviour */ if (PTR_ERR(priv->phy_rst) =3D=3D -ENOENT) @@ -873,6 +878,8 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_p= riv *priv) break; =20 case PHY_TYPE_SGMII: + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_sgmii_mac_sel, + priv->sgmii_mac_sel > 0); rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, = true); rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true= ); rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); @@ -984,6 +991,7 @@ static const struct rockchip_combphy_grfcfg rk3568_comb= phy_grfcfgs =3D { .con3_for_sata =3D { 0x000c, 15, 0, 0x00, 0x4407 }, /* pipe-grf */ .pipe_con0_for_sata =3D { 0x0000, 15, 0, 0x00, 0x2220 }, + .pipe_sgmii_mac_sel =3D { 0x0040, 1, 1, 0x00, 0x01 }, .pipe_xpcs_phy_ready =3D { 0x0040, 2, 2, 0x00, 0x01 }, .u3otg0_port_en =3D { 0x0104, 15, 0, 0x0181, 0x1100 }, .u3otg1_port_en =3D { 0x0144, 15, 0, 0x0181, 0x1100 }, --=20 2.47.3 From nobody Thu Sep 24 22:17:45 2026 Received: from mail-pz2-f2.google.com (mail-pz2-f2.google.com [74.125.228.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F10073D668F for ; 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Sat, 19 Sep 2026 05:52:16 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877aa0026b2sm991805b3a.44.2026.09.19.05.52.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 05:52:14 -0700 (PDT) From: Coia Prant To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v8 04/11] dt-bindings: net: pcs: add rockchip,rk3568-xpcs support Date: Sat, 19 Sep 2026 20:51:11 +0800 Message-ID: <20260919125119.2107089-5-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree binding documentation for the Synopsys DesignWare XPCS integrated on the Rockchip RK3568 SoC. The XPCS is accessed over the APB3 bus and internally connected to a Naneng Combo SerDes PHY. It supports 1000BASE-X, SGMII, and QSGMII modes, with four MII ports. The four MII ports are described as ethernet-pcs-mii@N child nodes, consumed by the Rockchip XPCS glue driver later in this series. phys and phy-names are required because dtbs_check only validates required properties for enabled nodes. The SerDes link is a board-level design choice (combphy1 on some boards, combphy2 on others), so these properties must be provided by the board device tree, not the SoC dtsi. The CRU reset lines (SRST_XPCS*) are intentionally not described: no in-tree user requests them, and bring-up relies on the PD_PIPE power domain, the SerDes PHY and the in-IP soft reset. They can be added later as optional without breaking ABI. Signed-off-by: Coia Prant --- .../net/pcs/rockchip,rk3568-xpcs.yaml | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/rockchip,rk35= 68-xpcs.yaml diff --git a/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs= .yaml b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml new file mode 100644 index 0000000000000..703fcff0e3f70 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/rockchip,rk3568-xpcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3568 Synopsys DesignWare Ethernet PCS + +maintainers: + - Coia Prant + +description: | + Rockchip RK3568 SoC integrates a Synopsys DesignWare Ethernet Physical + Coding Sublayer (XPCS). + The PCS provides an interface between the Media Access Control (MAC) + and the Physical Medium Attachment (PMA) sublayer through a Media + Independent Interface (GMII). + + The XPCS is accessed over the APB3 bus and internally connected to a + Naneng Combo SerDes PHY. + It supports 1000BASE-X, SGMII and QSGMII modes. + + The block contains four MII ports that can be individually enabled and + routed to one of the Ethernet GMAC controllers via the pcs-handle + property in the MAC device tree node. + +properties: + compatible: + const: rockchip,rk3568-xpcs + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + items: + - description: APB3 bus interface clock (clk_csr_i), required for re= gister access + - description: EEE clock (clk_eee_i), required for Energy Efficient = Ethernet operation + + clock-names: + items: + - const: csr + - const: eee + + phys: + maxItems: 1 + + phy-names: + const: serdes + + power-domains: + maxItems: 1 + +patternProperties: + "^ethernet-pcs-mii@[0-3]$": + type: object + description: + One of the four MII ports of the XPCS. The port is linked to an + Ethernet MAC controller via the pcs-handle property in the MAC's + device tree node. + + properties: + reg: + description: MII port number. + enum: [0, 1, 2, 3] + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - phys + - phy-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + + ethernet-pcs@fda00000 { + compatible =3D "rockchip,rk3568-xpcs"; + reg =3D <0xfda00000 0x200000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; + clock-names =3D "csr", "eee"; + phys =3D <&combphy2 PHY_TYPE_SGMII>; + phy-names =3D "serdes"; + power-domains =3D <&power RK3568_PD_PIPE>; + + ethernet-pcs-mii@0 { + reg =3D <0>; + }; + }; --=20 2.47.3 From nobody Thu Sep 24 22:17:45 2026 Received: from mail-pz2-f8.google.com (mail-pz2-f8.google.com [74.125.228.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CB7A3E1D0E for ; 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Sat, 19 Sep 2026 05:52:24 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877aa0026b2sm991805b3a.44.2026.09.19.05.52.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 05:52:23 -0700 (PDT) From: Coia Prant To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v8 05/11] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes Date: Sat, 19 Sep 2026 20:51:12 +0800 Message-ID: <20260919125119.2107089-6-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RK3568 SoC integrates a Synopsys DesignWare XPCS that provides the Physical Coding Sublayer for 1000BASE-X, SGMII, and QSGMII interfaces via its four MII ports. Add the XPCS device node and its pcs-mii sub-nodes to the SoC device tree. The XPCS device is accessed via the APB3 bus at 0xfda00000 and requires the CSR clock (PCLK_XPCS) for register access and the EEE clock (CLK_XPCS_EEE) for Energy Efficient Ethernet operation. The PD_PIPE power domain must be enabled before any register access. Also add two fixed-clock nodes (clock-xpcs-gmac0 and clock-xpcs-gmac1, labelled clk_gmac0_xpcs_mii and clk_gmac1_xpcs_mii) providing the 125 MHz reference clock for the GMACs when operating with XPCS. Their clock-output-names match the CRU mux parent names in clk-rk3568.c, so boards can reparent SCLK_GMAC0_RX_TX / SCLK_GMAC1_RX_TX through assigned-clock-parents. The XPCS node and its mii sub-nodes are disabled by default and must be enabled at the board level when 1000BASE-X/SGMII/QSGMII is in use. The fixed-clock nodes are always present and do not have a status property, as they are static clock sources. The XPCS node requires a reference to the appropriate Naneng Combo PHY via the phys property. dtbs_check only validates required properties for enabled nodes, so the SoC dtsi does not provide phys/phy-names: boards that enable the XPCS must supply them, since the SerDes link is a board-level design choice (combphy1 on some boards, combphy2 on others). Signed-off-by: Coia Prant --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts= /rockchip/rk3568.dtsi index 3bc653f027f1f..227d03e336043 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -110,6 +110,51 @@ sata0: sata@fc000000 { status =3D "disabled"; }; =20 + xpcs: ethernet-pcs@fda00000 { + compatible =3D "rockchip,rk3568-xpcs"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0xfda00000 0x0 0x200000>; + clocks =3D <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; + clock-names =3D "csr", "eee"; + power-domains =3D <&power RK3568_PD_PIPE>; + status =3D "disabled"; + + xpcs_mii0: ethernet-pcs-mii@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + xpcs_mii1: ethernet-pcs-mii@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + xpcs_mii2: ethernet-pcs-mii@2 { + reg =3D <2>; + status =3D "disabled"; + }; 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Sat, 19 Sep 2026 05:52:32 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877aa0026b2sm991805b3a.44.2026.09.19.05.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 05:52:31 -0700 (PDT) From: Coia Prant To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org, Jiawen Wu Subject: [PATCH net-next v8 06/11] net: pcs: xpcs: add ANRESTART support for SGMII link recovery Date: Sat, 19 Sep 2026 20:51:13 +0800 Message-ID: <20260919125119.2107089-7-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On some hardware using the DesignWare XPCS IP (e.g., RK3568 MAC side SGMII), the PCS does not automatically restart auto-negotiation when the link goes down and comes back up. Without an explicit ANRESTART, the link stays down forever. Add BMCR_ANRESTART in two places: 1. In xpcs_config_aneg_c37_sgmii(), when starting AN, set ANRESTART alongside ANENABLE to initiate a fresh negotiation. 2. In xpcs_get_state_c37_sgmii(), when link is down and AN completion is detected, clear the interrupt and trigger ANRESTART to restart the negotiation process. Propagate the return value of the restart so errors are not silently ignored. The restart cannot go through the .pcs_an_restart op: phylink only calls it for 802.3z interfaces, and SGMII is not one. Changing hardware state from pcs_get_state() is already done elsewhere in this driver (xpcs_get_state_c73() calls xpcs_soft_reset() and xpcs_do_config()), so the same pattern is used here. The latch is cleared before issuing the restart, not after: clearing it afterwards would discard a freshly latched ANCMPLT from the new negotiation. If an MDIO access fails at this point, it indicates an unrecoverable hardware condition until reset. Also clear DW_VR_MII_AN_INTR_STS in xpcs_config_aneg_c37_sgmii() before starting AN, matching what xpcs_config_aneg_c37_1000basex() already does. On the non-inband path the function now returns the result of that write instead of the DIG_CTRL1 modify. Update the comment in xpcs_config_aneg_c37_sgmii() to note that although the DesignWare databook says AN restart is not needed for MAC side SGMII, some implementations (e.g. Rockchip RK3568) require it to recover the link after a disconnect. This is not a fix for an existing mainline platform: the affected platform (RK3568 XPCS) is introduced later in the same series. Tested-by: Jiawen Wu Tested-by: Maxime Chevallier Signed-off-by: Coia Prant --- drivers/net/pcs/pcs-xpcs.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 0337e2bcc0125..8c3875b6985b9 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -761,7 +761,9 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *x= pcs, * DW xPCS used with DW EQoS MAC is always MAC side SGMII. * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] =3D 1b (Automatic * speed/duplex mode change by HW after SGMII AN complete) - * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] =3D 1b (Enable SGMII AN) + * 5) VR_MII_AN_INTR_STS =3D 0x0 (Clear CL37 AN complete status) + * 6) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] =3D 1b (Enable SGMII AN) + * VR_MII_MMD_CTRL Bit(9) [AN_RESTART] =3D 1b (Restart SGMII AN) * * Note that VR_MII_MMD_CTRL is MII_BMCR. * @@ -769,7 +771,14 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *= xpcs, * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from * PHY about the link state change after C28 AN is completed * between PHY and Link Partner. There is also no need to - * trigger AN restart for MAC-side SGMII. + * trigger AN restart for MAC-side SGMII on most devices. + * + * Note: While the DesignWare databook states that AN restart is + * not needed for MAC side SGMII, some implementations (e.g. + * Rockchip RK3568) exhibit a timing quirk when integrated with + * phylink and do not restart AN automatically when the link + * comes back up. An explicit AN restart is required on those + * parts to recover the link after a disconnect. */ mdio_ctrl =3D xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); if (mdio_ctrl < 0) @@ -816,9 +825,14 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *= xpcs, if (ret < 0) return ret; =20 + /* Clear CL37 AN complete status */ + ret =3D xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); + if (ret < 0) + return ret; + if (neg_mode =3D=3D PHYLINK_PCS_NEG_INBAND_ENABLED) ret =3D xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, - mdio_ctrl | BMCR_ANENABLE); + mdio_ctrl | BMCR_ANENABLE | BMCR_ANRESTART); =20 return ret; } @@ -1093,9 +1107,18 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *= xpcs, return 0; } =20 - /* Clear AN complete status or interrupt */ - if (state->an_complete) - xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); + if (state->an_complete) { + /* Clear AN complete status or interrupt */ + ret =3D xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); + if (ret < 0) + return ret; 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Sat, 19 Sep 2026 05:52:40 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877aa0026b2sm991805b3a.44.2026.09.19.05.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 05:52:39 -0700 (PDT) From: Coia Prant To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v8 07/11] net: pcs: xpcs: add Rockchip RK3568 platform glue driver Date: Sat, 19 Sep 2026 20:51:14 +0800 Message-ID: <20260919125119.2107089-8-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RK3568 SoC integrates a Synopsys DesignWare XPCS that is accessed via APB3 memory-mapped registers. This driver provides the glue logic to make the XPCS accessible to the generic pcs-xpcs core. The XPCS block contains four MII ports (0..3), each of which can be routed to GMAC0 or GMAC1 via the pcs-handle property in the MAC node. The hardware maps these ports to different MMDs: - port 0: MMD 7 (ROCKCHIP_MMD_MII) - port 1: MMD 2 (ROCKCHIP_MMD_MII1) - port 2: MMD 3 (ROCKCHIP_MMD_MII2) - port 3: MMD 4 (ROCKCHIP_MMD_MII3) This driver creates a virtual MDIO bus that translates MDIO operations to APB3 register accesses, with proper address remapping for each port. The generic xpcs driver then creates a phylink_pcs instance on top of this bus, allowing the MAC to use the PCS via the standard phylink API. The generic XPCS platform glue (pcs-xpcs-plat.o) is split out of the pcs_xpcs composite object into its own module, gated behind the new PCS_XPCS_PLATFORM symbol. The symbol defaults to PCS_XPCS, so existing configurations keep the snps,dw-xpcs platform glue enabled without any change. PCS_XPCS_ROCKCHIP selects GENERIC_PHY and PM_GENERIC_DOMAINS. ARCH_ROCKCHIP already selects PM, so the dependency of PM_GENERIC_DOMAINS on PM is satisfied on the target platform. The EEE multiplier is derived at runtime from the EEE clock rate instead of being hardcoded, because the clock is muxed between gpll200 (200 MHz) and cpll125 (125 MHz) and can be changed by the board or firmware. A 64-bit intermediate avoids overflow on 32-bit builds, and the result is clamped to the 4-bit DW_VR_MII_EEE_MULT_FACT_100NS field. Link: https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%= 20Part1%20V1.1-20210301.pdf (Page 59, CRU_CLKSEL_CON29) Link: https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%= 20Part2%20V1.1-20210301.pdf (Page 2078) Signed-off-by: Coia Prant --- drivers/net/pcs/Kconfig | 25 ++ drivers/net/pcs/Makefile | 5 +- drivers/net/pcs/pcs-xpcs-rk.c | 599 ++++++++++++++++++++++++++++++++ include/linux/pcs/pcs-xpcs-rk.h | 11 + 4 files changed, 638 insertions(+), 2 deletions(-) create mode 100644 drivers/net/pcs/pcs-xpcs-rk.c create mode 100644 include/linux/pcs/pcs-xpcs-rk.h diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig index e417fd66f660a..5382afcf95748 100644 --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig @@ -12,6 +12,31 @@ config PCS_XPCS This module provides a driver and helper functions for Synopsys DesignWare XPCS controllers. =20 +if PCS_XPCS + +config PCS_XPCS_PLATFORM + tristate "Generic XPCS controller support" + default PCS_XPCS + help + Generic DWXPCS driver for platforms that don't require any + platform specific code to function or is using platform + data for setup. + + If you have a controller with this interface, say Y or M here. + +config PCS_XPCS_ROCKCHIP + tristate "Rockchip XPCS controller support" + default ARCH_ROCKCHIP + depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) + select GENERIC_PHY + select PM_GENERIC_DOMAINS if PM + help + Support for XPCS controller on Rockchip RK356x SoC. + + If you have a Rockchip SoC with this interface, say Y or M here. + +endif # PCS_XPCS + config PCS_LYNX tristate help diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile index 4f7920618b900..f9f6cf2578d72 100644 --- a/drivers/net/pcs/Makefile +++ b/drivers/net/pcs/Makefile @@ -1,10 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 # Makefile for Linux PCS drivers =20 -pcs_xpcs-$(CONFIG_PCS_XPCS) :=3D pcs-xpcs.o pcs-xpcs-plat.o \ - pcs-xpcs-nxp.o pcs-xpcs-wx.o +pcs_xpcs-$(CONFIG_PCS_XPCS) :=3D pcs-xpcs.o pcs-xpcs-nxp.o pcs-xpcs-wx.o =20 obj-$(CONFIG_PCS_XPCS) +=3D pcs_xpcs.o +obj-$(CONFIG_PCS_XPCS_PLATFORM) +=3D pcs-xpcs-plat.o +obj-$(CONFIG_PCS_XPCS_ROCKCHIP) +=3D pcs-xpcs-rk.o obj-$(CONFIG_PCS_LYNX) +=3D pcs-lynx.o obj-$(CONFIG_PCS_MTK_LYNXI) +=3D pcs-mtk-lynxi.o obj-$(CONFIG_PCS_RZN1_MIIC) +=3D pcs-rzn1-miic.o diff --git a/drivers/net/pcs/pcs-xpcs-rk.c b/drivers/net/pcs/pcs-xpcs-rk.c new file mode 100644 index 0000000000000..84f8ea7fa57e8 --- /dev/null +++ b/drivers/net/pcs/pcs-xpcs-rk.c @@ -0,0 +1,599 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip XPCS platform device driver + * + * Based on the Synopsys DesignWare XPCS platform driver. + * Copyright (C) 2024 Serge Semin + * + * Adapted for Rockchip SoCs, with reference to the Rockchip OEM driver. + * Copyright (C) 2026 Coia Prant + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcs-xpcs.h" + +struct dw_xpcs_rk { + struct platform_device *pdev; + struct mii_bus *bus; + void __iomem *reg_base; + struct phy *serdes_phy; + struct clk *csr_clk; + struct clk *eee_clk; + u8 eee_mult_fact; +}; + +static ptrdiff_t xpcs_rk_addr_format(int dev, int reg) +{ + return FIELD_PREP(0x70000, dev) | FIELD_PREP(0xffff, reg); +} + +static int xpcs_rk_read_reg(struct dw_xpcs_rk *pxpcs, int dev, int reg) +{ + ptrdiff_t csr; + int ret; + + csr =3D xpcs_rk_addr_format(dev, reg); + + ret =3D pm_runtime_resume_and_get(&pxpcs->pdev->dev); + if (ret) + return ret; + + ret =3D readl(pxpcs->reg_base + (csr << 2)) & 0xffff; + + pm_runtime_put(&pxpcs->pdev->dev); + return ret; +} + +static int xpcs_rk_write_reg(struct dw_xpcs_rk *pxpcs, int dev, int reg, u= 16 val) +{ + ptrdiff_t csr; + int ret; + + csr =3D xpcs_rk_addr_format(dev, reg); + + ret =3D pm_runtime_resume_and_get(&pxpcs->pdev->dev); + if (ret) + return ret; + + writel(val, pxpcs->reg_base + (csr << 2)); + + pm_runtime_put(&pxpcs->pdev->dev); + return 0; +} + +#define ROCKCHIP_MMD_MII1 2 +#define ROCKCHIP_MMD_MII2 3 +#define ROCKCHIP_MMD_MII3 4 +#define ROCKCHIP_MMD_PMAPMD 6 +#define ROCKCHIP_MMD_MII 7 + +static bool xpcs_rk_mdio_addr_validate(int addr) +{ + return !(addr < 0 || addr > 3); +} + +static int xpcs_rk_mdio_read_remapping(int addr, int dev, int reg) +{ + switch (dev) { + case MDIO_MMD_PMAPMD: + return ROCKCHIP_MMD_PMAPMD; + case MDIO_MMD_VEND2: + break; + default: + return -ENXIO; + } + + /* + * Reads are redirected by hardware to the port's read-only mirror; + * only writes have to be targeted at MII (see the write path). + */ + switch (addr) { + case 0: + return ROCKCHIP_MMD_MII; + case 1: + return ROCKCHIP_MMD_MII1; + case 2: + return ROCKCHIP_MMD_MII2; + case 3: + return ROCKCHIP_MMD_MII3; + default: + return -ENODEV; + } +} + +static int xpcs_rk_mdio_write_remapping(int addr, int dev, int reg) +{ + switch (dev) { + case MDIO_MMD_PMAPMD: + return ROCKCHIP_MMD_PMAPMD; + case MDIO_MMD_VEND2: + break; + default: + return -ENXIO; + } + + /* + * These registers physically live only in MII (the management port). + * Ports 1-3 expose read-only mirrors of these bits, so writes must + * always target MII; the read path remaps per address and the + * hardware redirects to the port's mirror. + */ + switch (reg) { + case DW_VR_MII_AN_CTRL: + case DW_VR_MII_AN_INTR_STS: + case DW_VR_MII_EEE_MCTRL0: + case DW_VR_MII_EEE_MCTRL1: + case DW_VR_MII_DIG_CTRL2: + return ROCKCHIP_MMD_MII; + default: + break; + } + + switch (addr) { + case 0: + return ROCKCHIP_MMD_MII; + case 1: + return ROCKCHIP_MMD_MII1; + case 2: + return ROCKCHIP_MMD_MII2; + case 3: + return ROCKCHIP_MMD_MII3; + default: + return -ENODEV; + } +} + +static int xpcs_rk_read_c22(struct mii_bus *bus, int addr, int reg) +{ + struct dw_xpcs_rk *pxpcs =3D bus->priv; + int dev; + + if (!xpcs_rk_mdio_addr_validate(addr)) + return -ENODEV; + + dev =3D xpcs_rk_mdio_read_remapping(addr, MDIO_MMD_VEND2, reg); + if (dev < 0) + return 0xffff; + + return xpcs_rk_read_reg(pxpcs, dev, reg); +} + +static int xpcs_rk_write_c22(struct mii_bus *bus, int addr, int reg, u16 v= al) +{ + struct dw_xpcs_rk *pxpcs =3D bus->priv; + int dev; + + if (!xpcs_rk_mdio_addr_validate(addr)) + return -ENODEV; + + dev =3D xpcs_rk_mdio_write_remapping(addr, MDIO_MMD_VEND2, reg); + if (dev < 0) + return 0; + + return xpcs_rk_write_reg(pxpcs, dev, reg, val); +} + +static int xpcs_rk_read_c45(struct mii_bus *bus, int addr, int dev, int re= g) +{ + struct dw_xpcs_rk *pxpcs =3D bus->priv; + + if (!xpcs_rk_mdio_addr_validate(addr)) + return -ENODEV; + + dev =3D xpcs_rk_mdio_read_remapping(addr, dev, reg); + if (dev < 0) + return 0xffff; + + return xpcs_rk_read_reg(pxpcs, dev, reg); +} + +static int xpcs_rk_write_c45(struct mii_bus *bus, int addr, int dev, int r= eg, u16 val) +{ + struct dw_xpcs_rk *pxpcs =3D bus->priv; + + if (!xpcs_rk_mdio_addr_validate(addr)) + return -ENODEV; + + dev =3D xpcs_rk_mdio_write_remapping(addr, dev, reg); + if (dev < 0) + return 0; + + return xpcs_rk_write_reg(pxpcs, dev, reg, val); +} + +static struct dw_xpcs_rk *xpcs_rk_create_data(struct platform_device *pdev) +{ + struct dw_xpcs_rk *pxpcs; + + pxpcs =3D devm_kzalloc(&pdev->dev, sizeof(*pxpcs), GFP_KERNEL); + if (!pxpcs) + return ERR_PTR(-ENOMEM); + + pxpcs->pdev =3D pdev; + + dev_set_drvdata(&pdev->dev, pxpcs); + + return pxpcs; +} + +static int xpcs_rk_serdes_phy_init(struct dw_xpcs_rk *pxpcs) +{ + struct device *dev =3D &pxpcs->pdev->dev; + + pxpcs->serdes_phy =3D devm_phy_get(dev, "serdes"); + if (IS_ERR(pxpcs->serdes_phy)) + return dev_err_probe(dev, PTR_ERR(pxpcs->serdes_phy), + "Failed to get SerDes PHY\n"); + + return 0; +} + +static void xpcs_rk_serdes_phy_poweroff(void *data) +{ + struct dw_xpcs_rk *pxpcs =3D data; + struct device *dev =3D &pxpcs->pdev->dev; + + phy_power_off(pxpcs->serdes_phy); + phy_exit(pxpcs->serdes_phy); + + dev_pm_genpd_rpm_always_on(dev, false); +} + +static int xpcs_rk_serdes_phy_poweron(struct dw_xpcs_rk *pxpcs) +{ + struct device *dev =3D &pxpcs->pdev->dev; + int ret; + + /* + * The power domain is required and must be enabled, which allows us to + * dynamically turn the CSR clock on/off using PM while keeping the PCS + * powered on. + */ + ret =3D dev_pm_genpd_rpm_always_on(dev, true); + if (ret) { + dev_err(dev, "Failed to power on power-domains\n"); + return ret; + } + + ret =3D phy_init(pxpcs->serdes_phy); + if (ret) { + dev_err(dev, "Failed to init SerDes PHY\n"); + goto pm_domain; + } + + ret =3D phy_power_on(pxpcs->serdes_phy); + if (ret) { + dev_err(dev, "Failed to power on SerDes PHY\n"); + goto serdes_phy; + } + + ret =3D devm_add_action_or_reset(dev, xpcs_rk_serdes_phy_poweroff, pxpcs); + if (ret) { + dev_err(dev, "Failed to register devm for SerDes PHY: %d\n", ret); + return ret; + } + + return 0; + +serdes_phy: + phy_exit(pxpcs->serdes_phy); +pm_domain: + dev_pm_genpd_rpm_always_on(dev, false); + return ret; +} + +static int xpcs_rk_init_res(struct dw_xpcs_rk *pxpcs) +{ + struct platform_device *pdev =3D pxpcs->pdev; + struct device *dev =3D &pdev->dev; + struct resource *res; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "No reg-space found\n"); + return -EINVAL; + } + + if (resource_size(res) < SZ_2M) { + dev_err(dev, "Invalid reg-space size\n"); + return -EINVAL; + } + + pxpcs->reg_base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(pxpcs->reg_base)) { + dev_err(dev, "Failed to map reg-space\n"); + return PTR_ERR(pxpcs->reg_base); + } + + return 0; +} + +static void xpcs_rk_exit_clk(void *data) +{ + struct dw_xpcs_rk *pxpcs =3D data; + struct device *dev =3D &pxpcs->pdev->dev; + + pm_runtime_force_suspend(dev); + clk_disable_unprepare(pxpcs->eee_clk); +} + +static int xpcs_rk_init_clk(struct dw_xpcs_rk *pxpcs) +{ + struct device *dev =3D &pxpcs->pdev->dev; + unsigned long rate; + u64 mult; + int ret; + + pxpcs->csr_clk =3D devm_clk_get(dev, "csr"); + if (IS_ERR(pxpcs->csr_clk)) + return dev_err_probe(dev, PTR_ERR(pxpcs->csr_clk), + "Failed to get CSR clock\n"); + + pxpcs->eee_clk =3D devm_clk_get(dev, "eee"); + if (IS_ERR(pxpcs->eee_clk)) + return dev_err_probe(dev, PTR_ERR(pxpcs->eee_clk), + "Failed to get EEE clock\n"); + + ret =3D clk_prepare_enable(pxpcs->eee_clk); + if (ret) { + dev_err(dev, "Failed to enable EEE clock\n"); + return ret; + } + + pm_runtime_set_suspended(dev); + pm_runtime_enable(dev); + + ret =3D devm_add_action_or_reset(dev, xpcs_rk_exit_clk, pxpcs); + if (ret) { + dev_err(dev, "Failed to register devm for EEE clock: %d\n", ret); + return ret; + } + + /* + * Compute the multiplier for the EEE clock so that + * clk_eee_period * (mult_fact + 1) falls within 80..120 ns. + * + * On RK3568, clk_xpcs_eee is muxed between gpll200 (200 MHz, 5 ns) + * and cpll125 (125 MHz, 8 ns), selected by CRU_CLKSEL_CON29 bit 13. + * The reset value is 0 (200 MHz), but derive the value at runtime to + * stay correct if the mux is changed by a board. + * + * Use a 64-bit intermediate: on 32-bit builds, 100 * 200000000 + * does not fit in unsigned long. Clamp to the 4-bit + * DW_VR_MII_EEE_MULT_FACT_100NS field. The mux only provides + * 125 MHz or 200 MHz, so the rate cannot drop below the 5 MHz + * threshold where DIV_ROUND_CLOSEST_ULL() would return 0 and the + * subtraction below would underflow. + */ + rate =3D clk_get_rate(pxpcs->eee_clk); + if (!rate) + return dev_err_probe(dev, -EINVAL, "Invalid EEE clock rate\n"); + + mult =3D DIV_ROUND_CLOSEST_ULL(100ULL * rate, NSEC_PER_SEC) - 1; + pxpcs->eee_mult_fact =3D min_t(u64, mult, 15); + return 0; +} + +static int xpcs_rk_init_bus(struct dw_xpcs_rk *pxpcs) +{ + struct device *dev =3D &pxpcs->pdev->dev; + static atomic_t id =3D ATOMIC_INIT(-1); + struct mii_bus *bus; + int ret; + + bus =3D devm_mdiobus_alloc_size(dev, 0); + if (!bus) + return -ENOMEM; + + bus->name =3D "Rockchip DW XPCS MCI/APB3"; + bus->read =3D xpcs_rk_read_c22; + bus->write =3D xpcs_rk_write_c22; + bus->read_c45 =3D xpcs_rk_read_c45; + bus->write_c45 =3D xpcs_rk_write_c45; + bus->phy_mask =3D ~0; + bus->parent =3D dev; + bus->priv =3D pxpcs; + + snprintf(bus->id, MII_BUS_ID_SIZE, + "rockchip_dwxpcs-%x", atomic_inc_return(&id)); + + /* + * MDIO-bus here serves as just a back-end engine abstracting out + * the MDIO and MCI/APB3 IO interfaces utilized for the Rockchip DWXPCS C= SRs + * access. + */ + ret =3D devm_mdiobus_register(dev, bus); + if (ret) { + dev_err(dev, "Failed to create MDIO bus\n"); + return ret; + } + + pxpcs->bus =3D bus; + return 0; +} + +static int xpcs_rk_probe(struct platform_device *pdev) +{ + struct dw_xpcs_rk *pxpcs; + int ret; + + pxpcs =3D xpcs_rk_create_data(pdev); + if (IS_ERR(pxpcs)) + return PTR_ERR(pxpcs); + + /* + * The XPCS may be attached to a power domain (e.g. PD_PIPE). The domain + * must be powered on before any register access, otherwise the SoC will + * trigger a synchronous external abort (SError). + * + * Accessing the XPCS registers also requires a TX clock from the SerDes, + * which is needed for the soft reset. + */ + ret =3D xpcs_rk_serdes_phy_init(pxpcs); + if (ret) + return ret; + + ret =3D xpcs_rk_serdes_phy_poweron(pxpcs); + if (ret) + return ret; + + ret =3D xpcs_rk_init_res(pxpcs); + if (ret) + return ret; + + ret =3D xpcs_rk_init_clk(pxpcs); + if (ret) + return ret; + + ret =3D xpcs_rk_init_bus(pxpcs); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id xpcs_rk_of_ids[] =3D { + { .compatible =3D "rockchip,rk3568-xpcs" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, xpcs_rk_of_ids); + +struct dw_xpcs *xpcs_rk_create(struct device *dev, struct device_node *np) +{ + struct platform_device *pdev; + struct device_node *pcs_np; + struct dw_xpcs_rk *pxpcs; + struct dw_xpcs *xpcs; + u32 port; + + if (!of_device_is_available(np)) + return ERR_PTR(-ENODEV); + + if (of_property_read_u32(np, "reg", &port)) + return ERR_PTR(-EINVAL); + + if (!xpcs_rk_mdio_addr_validate((int)port)) + return ERR_PTR(-EINVAL); + + /* The XPCS pdev is attached to the parent node */ + pcs_np =3D of_get_parent(np); + if (!pcs_np) + return ERR_PTR(-ENODEV); + + if (!of_device_is_available(pcs_np)) { + of_node_put(pcs_np); + return ERR_PTR(-ENODEV); + } + + if (!of_match_node(xpcs_rk_of_ids, pcs_np)) { + of_node_put(pcs_np); + return ERR_PTR(-EINVAL); + } + + pdev =3D of_find_device_by_node(pcs_np); + of_node_put(pcs_np); + if (!pdev) + return ERR_PTR(-EPROBE_DEFER); + + /* + * Establish the device link before touching the supplier's drvdata. + * device_link_add() does not fail on a supplier that is unbinding; + * it creates the link in DL_STATE_SUPPLIER_UNBIND. What keeps the + * drvdata valid afterwards is the link itself: once the supplier is + * confirmed bound below, the link is in DL_STATE_CONSUMER_PROBE, + * which makes device_links_unbind_consumers() wait for this probe + * to finish before the supplier can be unbound. + * + * device_lock() plus device_is_bound() are used only to make the + * "supplier is bound" check atomic with reading the drvdata; they + * do not carry the protection past the unlock. + * + * The link is released automatically when the consumer device is + * destroyed (DL_FLAG_AUTOREMOVE_CONSUMER), so no explicit + * device_link_remove() is needed on the failure paths. + */ + if (!device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_CONSUMER)) { + put_device(&pdev->dev); + return ERR_PTR(-EPROBE_DEFER); + } + + device_lock(&pdev->dev); + if (!device_is_bound(&pdev->dev)) { + device_unlock(&pdev->dev); + put_device(&pdev->dev); + return ERR_PTR(-EPROBE_DEFER); + } + device_unlock(&pdev->dev); + + pxpcs =3D platform_get_drvdata(pdev); + if (!pxpcs || !pxpcs->bus) { + put_device(&pdev->dev); + return ERR_PTR(-EPROBE_DEFER); + } + + xpcs =3D xpcs_create_mdiodev(pxpcs->bus, (int)port); + if (IS_ERR(xpcs)) { + put_device(&pdev->dev); + return xpcs; + } + + xpcs_config_eee_mult_fact(xpcs, pxpcs->eee_mult_fact); + put_device(&pdev->dev); + return xpcs; +} +EXPORT_SYMBOL_GPL(xpcs_rk_create); + +static int xpcs_rk_pm_runtime_suspend(struct device *dev) +{ + struct dw_xpcs_rk *pxpcs =3D dev_get_drvdata(dev); + + clk_disable_unprepare(pxpcs->csr_clk); + + return 0; +} + +static int xpcs_rk_pm_runtime_resume(struct device *dev) +{ + struct dw_xpcs_rk *pxpcs =3D dev_get_drvdata(dev); + + return clk_prepare_enable(pxpcs->csr_clk); +} + +static DEFINE_RUNTIME_DEV_PM_OPS(xpcs_rk_pm_ops, + xpcs_rk_pm_runtime_suspend, + xpcs_rk_pm_runtime_resume, + NULL); + +static struct platform_driver xpcs_rk_driver =3D { + .probe =3D xpcs_rk_probe, + .driver =3D { + .name =3D "rk_xpcs-dwxpcs", + .pm =3D pm_ptr(&xpcs_rk_pm_ops), + .of_match_table =3D xpcs_rk_of_ids, + }, +}; +module_platform_driver(xpcs_rk_driver); + +MODULE_DESCRIPTION("Rockchip XPCS platform device driver"); +MODULE_AUTHOR("Coia Prant "); +MODULE_LICENSE("GPL"); diff --git a/include/linux/pcs/pcs-xpcs-rk.h b/include/linux/pcs/pcs-xpcs-r= k.h new file mode 100644 index 0000000000000..28723d5bd75cc --- /dev/null +++ b/include/linux/pcs/pcs-xpcs-rk.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_PCS_XPCS_ROCKCHIP_H +#define __LINUX_PCS_XPCS_ROCKCHIP_H + +#include +#include +#include + +struct dw_xpcs *xpcs_rk_create(struct device *dev, struct device_node *np); + +#endif /* __LINUX_PCS_XPCS_ROCKCHIP_H */ --=20 2.47.3 From nobody Thu Sep 24 22:17:45 2026 Received: from mail-pz2-f9.google.com (mail-pz2-f9.google.com [74.125.228.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEAB13EFFDB for ; Sat, 19 Sep 2026 12:52:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sat, 19 Sep 2026 05:52:48 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877aa0026b2sm991805b3a.44.2026.09.19.05.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 05:52:48 -0700 (PDT) From: Coia Prant To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v8 08/11] dt-bindings: net: rockchip-dwmac: document pcs-handle Date: Sat, 19 Sep 2026 20:51:15 +0800 Message-ID: <20260919125119.2107089-9-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Rockchip GMAC binding needs to describe the PCS reference used by the SGMII support added later in this series. The property will be parsed by rk_pcs_init(), and a missing phandle fails the probe. Add it and require it when phy-mode is "sgmii" on rockchip,rk3568-gmac, the only SoC in this binding that has SGMII support. Signed-off-by: Coia Prant --- .../bindings/net/rockchip-dwmac.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Do= cumentation/devicetree/bindings/net/rockchip-dwmac.yaml index 80c252845349c..bb7540e838033 100644 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml @@ -120,6 +120,12 @@ properties: maximum: 0x7F default: 0x10 =20 + pcs-handle: + description: + Specifies a reference to a node representing the PCS device + connected to this GMAC. Required when phy-mode is "sgmii". + maxItems: 1 + phy-supply: description: PHY regulator =20 @@ -159,6 +165,18 @@ allOf: clocks: minItems: 5 =20 + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-gmac + phy-mode: + contains: + const: sgmii + then: + required: + - pcs-handle + unevaluatedProperties: false =20 examples: --=20 2.47.3 From nobody Thu Sep 24 22:17:45 2026 Received: from mail-pz2-f7.google.com (mail-pz2-f7.google.com [74.125.228.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE7873E0097 for ; Sat, 19 Sep 2026 12:52:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.228.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789822379; cv=none; b=Dc5LfbaDpM+IDAhyB8BRchYwMvPNjtjbMQ0tYhVOaDJEu/c8FujB0sE9R99V5i6WRrqn3R9BUeBXqmMlbHW3nsf6sHu4UrKZ7MB8ANqV47Qqn4cm03Aq8+oBm3Zhph8Qw6BQIgmeVcQzGzmGt42mqsAF4Yjn5fZBsH1yH+cbEgE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789822379; c=relaxed/simple; bh=MXFdS/dUvSiAcRqIm0RyA3KPYXkr++PgYrKK8uH6q7A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JRfdoaiVHqa7pMTvDMkW+GiuLIqYN7M2S7gVSRQ+AdHRvP31gy3wRBro6CH+SQFOO4sNyPkn67/evy4kgWiTm+nDeXFUHBFH2NxMPyRv/O2DRqPE5FkrDcN6d6clrwbVVa0lhJk2CDAdVFxDOu0mpgplnnHA8AleKEc1VH0sPKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=rTkVu8HX; arc=none smtp.client-ip=74.125.228.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rTkVu8HX" Received: by mail-pz2-f7.google.com with SMTP id 41be03b00d2f7-cc53988d9f3so807679a12.0 for ; Sat, 19 Sep 2026 05:52:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1789822376; x=1790427176; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=iC03NBdaNc6vhu1NpYTcJvmpgqe0vchbrXQWmVX8P1s=; b=rTkVu8HX5hcMZ8hU3JxDltUhF1XnpB82wfoquf92V6tsESjjkUKvrFfMQjZ4MvIHTY boqPlc5AbolA4m65VoUx2gmcWaT87uu6iAZtHChDrst96hB257veXj0IjNTP34Zm2V15 64FlPuBPStmEQ+VvH+Dl2TPsqhVa8yN9AxfZvEq13j8v+DT/RjIOWSdHSo6vjqDN+A14 VfYrwXpvPj945CjZzRX3yUGG36OHaO1TXymvEKRjG5F++hL3pzpPEBjVOTlMa4lkHT5f yXOnZCksJu7tXJOyeS/0FAYqPi0eknGf3qiuk24Rx5Tor1nsoaz/ENVSQzwFe6Ias+UZ Q43g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1789822376; x=1790427176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=iC03NBdaNc6vhu1NpYTcJvmpgqe0vchbrXQWmVX8P1s=; b=UC1y1qJgk4tTcYHrQSB7PdLXY7H0xMwgVWscpdLueQGmXMxe9D7M3wpUZPk5qZkybd 05T/wcOaevbVE3EbaSFMyg1VmPAKoCN9EvoFCGYgivhSPJArLxRvMTR6j22XAUPhJKV1 mcda7AymNa/J1dCZTcopfyatxHogikXLOJlH1Mtv4Pj0zAIMACET9ECmplVZO7f0Qllf 9YUZxY9BR1yVoKmWHhcv9lNZrhClWLdi9wlu9q0SfPplyDVvuC4RnBeWJSapubn+2eRs feenwihJBqTcqR5ei+iw8+f0Kj3V59yTyml59Y8Z7o0yhibyQk3tlONdf9UuXdK2sO44 kc0Q== X-Forwarded-Encrypted: i=1; AKwUvByopxBDtWhgbFIl7j6jvxAJT0lDsxjqgPhEWJawjQEbzZ/cEyqokwG3kK/72TLbA5nPwfj3No8ezNt+gIM=@vger.kernel.org X-Gm-Message-State: AFuF++lWjorX6GHGA6Ri6SIzlvxa9ltcefopEp1hTPfFOkKj+2PtoYI2 lugvF4EHLDQtW0b3dR7hbh+9NoIt2+1skY1xIBvpa5s20bM4olGOFAuO X-Gm-Gg: AYBFou3apRe2fGBLrrZ3pvJBSlBhHkZ5uUraEbPQ7O1PF8uqxj0aMCzVqz+IE8hjXzY qMQDP/FU6TcXsTlko69orDZBktBXULHRQMxCwAoRg1ICpCB27lO1VaZvl87okV9u3GndgD8awVM +uUert9bdnx7qvWn3TyftPV82Pm3LZpqzu3KJeBOGTbGNXQL05bciYNpNdSWAiAnlV+rGm6Q7hX u+bmjRg5qLX35RS2DioT5kveIWSOFnsoxiDSALPUDt2Sq4bb7dQjHgimMIzgyLbH8hK+ZK2BCba 5vJz1/ZEs/pw/TYiRr3hrn6GxCI/rvjj8lUcSkc17Df74Qz6tfqK+qYScuqErOBiVTdwktwRoze 63BMwnhFLW+DjALSx3QmwYPR6NRRGbSbkmdHONXeUS7Wnlp2SjUie7ZTNHxUt9PiXjc3nWapvel +/EYg/L3pwAO20FKav3LRYnk0tXK/bODN44HpqHyj3S9Q6GRB3b0dtr/IHfNS9T/qAzHl9wZeNZ aWvda5T X-Received: by 2002:a05:6a00:1a1a:b0:876:194e:b8fe with SMTP id d2e1a72fcca58-876195e014dmr6720606b3a.26.1789822376156; Sat, 19 Sep 2026 05:52:56 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877aa0026b2sm991805b3a.44.2026.09.19.05.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 05:52:55 -0700 (PDT) From: Coia Prant To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v8 09/11] net: stmmac: dwmac-rk: add SGMII support for RK3568 Date: Sat, 19 Sep 2026 20:51:16 +0800 Message-ID: <20260919125119.2107089-10-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RK3568 SoC integrates a Synopsys DesignWare XPCS that can be connected to GMAC0 or GMAC1 in SGMII mode. Add the necessary glue logic to support this configuration. The current dwmac-rk driver does not support SGMII mode. SGMII requires a PCS to handle auto-negotiation and link state reporting, but the existing driver only supports RGMII and RMII. Add a set_to_sgmii() callback to configure the GMAC GRF register for SGMII mode (bit 7 set, interface selection bits 4:6 ignored when set). Also add a set_to_rmii() callback for rk3568 to explicitly clear bit 7, since the new SGMII path leaves it set and the RMII branch previously relied on the SoC reset value. Provide pcs_init/pcs_exit callbacks to create/destroy the XPCS via xpcs_rk_create() from the Rockchip XPCS platform driver, and a select_pcs callback to return the XPCS to phylink. SGMII is not added to rk_get_interfaces(): it comes from the XPCS's own supported_interfaces, merged by stmmac_phylink_setup(). The SerDes PHY and the PD_PIPE power domain are owned by the XPCS driver rather than managed through the stmmac serdes_poweron/serdes_poweroff callbacks, which are legacy and meant for single-MAC platforms. On RK3568 the XPCS is the natural owner of the shared SerDes. DWMAC_ROCKCHIP selects PCS_XPCS_ROCKCHIP. PCS_XPCS itself is already selected by STMMAC_ETH, and PM is selected by ARCH_ROCKCHIP, so no further selects are needed. Reorder rk_gmac_powerup() so that gmac_clk_enable() is called before the SGMII check. The SGMII path skips rk_get_phy_intf_sel(), so the clock must be enabled earlier to cover all register accesses in that path. While at it, unify the error unwinding into a single clk_disable label and add error handling for the default (unhandled interface) case. SGMII In-band vs Out-of-band =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D On RK3568, the MAC clock is fixed at 125 MHz and cannot be dynamically changed by the stmmac core's set_clk_tx_rate callback. In-band mode works because the PCS handles rate adaptation internally. Out-of-band mode does not work because the MAC would need to change the clock rate to 125/12.5/1.25 MHz for 1000/100/10 Mbps respectively, and the clock is fixed. Enable default_an_inband for SGMII and disable the generic stmmac set_clk_tx_rate callback. This forces phylink to use in-band mode, where the PCS is responsible for speed/duplex negotiation. Note that default_an_inband can be overridden by a fixed-link node, and phylink may also fall back to out-of-band if the PHY does not support in-band signalling. Out-of-band SGMII is not supported by this driver: the MAC clock would stay at 125 MHz for 10/100 Mbps, giving working TX but failing RX. Boards must use in-band mode (managed =3D "in-band-status" or an in-band capable PHY). Link: https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%= 20Part1%20V1.1-20210301.pdf (Page 386) Signed-off-by: Coia Prant Reviewed-by: Maxime Chevallier #include #include +#include #include =20 #include "stmmac_platform.h" @@ -47,6 +48,7 @@ struct rk_gmac_ops { void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay); void (*set_to_rmii)(struct rk_priv_data *bsp_priv); + void (*set_to_sgmii)(struct rk_priv_data *bsp_priv); int (*set_speed)(struct rk_priv_data *bsp_priv, phy_interface_t interface, int speed); void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); @@ -63,6 +65,7 @@ struct rk_gmac_ops { bool clock_grf_reg_in_php; bool supports_rgmii; bool supports_rmii; + bool supports_sgmii; bool php_grf_required; bool regs_valid; u32 regs[]; @@ -98,6 +101,7 @@ struct rk_priv_data { bool integrated_phy; bool supports_rgmii; bool supports_rmii; + bool supports_sgmii; =20 struct clk_bulk_data *clks; int num_clks; @@ -809,6 +813,8 @@ static const struct rk_gmac_ops rk3528_ops =3D { #define RK3568_GRF_GMAC1_CON1 0x038c =20 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ +#define RK3568_GMAC_MODE_RMII_RGMII GRF_CLR_BIT(7) +#define RK3568_GMAC_MODE_SGMII_QSGMII GRF_BIT(7) #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) @@ -836,6 +842,16 @@ static int rk3568_init(struct rk_priv_data *bsp_priv) } } =20 +static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) +{ + u32 con1; + + con1 =3D (bsp_priv->id =3D=3D 1) ? RK3568_GRF_GMAC1_CON1 : + RK3568_GRF_GMAC0_CON1; + + regmap_write(bsp_priv->grf, con1, RK3568_GMAC_MODE_RMII_RGMII); +} + static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { @@ -851,19 +867,31 @@ static void rk3568_set_to_rgmii(struct rk_priv_data *= bsp_priv, RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); =20 regmap_write(bsp_priv->grf, con1, + RK3568_GMAC_MODE_RMII_RGMII | RK3568_GMAC_RXCLK_DLY_ENABLE | RK3568_GMAC_TXCLK_DLY_ENABLE); } =20 +static void rk3568_set_to_sgmii(struct rk_priv_data *bsp_priv) +{ + u32 con1; + + con1 =3D (bsp_priv->id =3D=3D 1) ? RK3568_GRF_GMAC1_CON1 : + RK3568_GRF_GMAC0_CON1; + + regmap_write(bsp_priv->grf, con1, RK3568_GMAC_MODE_SGMII_QSGMII); +} + static const struct rk_gmac_ops rk3568_ops =3D { .init =3D rk3568_init, + .set_to_rmii =3D rk3568_set_to_rmii, .set_to_rgmii =3D rk3568_set_to_rgmii, + .set_to_sgmii =3D rk3568_set_to_sgmii, + .set_speed =3D rk_set_clk_mac_speed, =20 .gmac_phy_intf_sel_mask =3D GENMASK_U16(6, 4), =20 - .supports_rmii =3D true, - .regs_valid =3D true, .regs =3D { 0xfe2a0000, /* gmac0 */ @@ -1208,6 +1236,43 @@ static void rk_phy_powerdown(struct rk_priv_data *bs= p_priv) dev_err(bsp_priv->dev, "fail to disable phy-supply\n"); } =20 +static int rk_pcs_init(struct stmmac_priv *priv) +{ + struct device_node *np =3D priv->device->of_node; + struct device_node *pcs_node; + struct dw_xpcs *xpcs; + + pcs_node =3D of_parse_phandle(np, "pcs-handle", 0); + if (!pcs_node) + return -ENODEV; + + xpcs =3D xpcs_rk_create(priv->device, pcs_node); + of_node_put(pcs_node); + if (IS_ERR(xpcs)) + return PTR_ERR(xpcs); + + priv->hw->xpcs =3D xpcs; + return 0; +} + +static void rk_pcs_exit(struct stmmac_priv *priv) +{ + if (!priv->hw->xpcs) + return; + + xpcs_destroy(priv->hw->xpcs); + priv->hw->xpcs =3D NULL; +} + +static struct phylink_pcs *rk_select_pcs(struct stmmac_priv *priv, + phy_interface_t interface) +{ + if (!priv->hw->xpcs) + return NULL; + + return xpcs_to_phylink_pcs(priv->hw->xpcs); +} + static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, struct plat_stmmacenet_data *plat, const struct rk_gmac_ops *ops) @@ -1330,6 +1395,7 @@ static struct rk_priv_data *rk_gmac_setup(struct plat= form_device *pdev, =20 bsp_priv->supports_rgmii =3D ops->supports_rgmii || !!ops->set_to_rgmii; bsp_priv->supports_rmii =3D ops->supports_rmii || !!ops->set_to_rmii; + bsp_priv->supports_sgmii =3D ops->supports_sgmii || !!ops->set_to_sgmii; =20 if (ops->init) { ret =3D ops->init(bsp_priv); @@ -1361,6 +1427,10 @@ static int rk_gmac_check_ops(struct rk_priv_data *bs= p_priv) if (!bsp_priv->supports_rmii) return -EINVAL; break; + case PHY_INTERFACE_MODE_SGMII: + if (!bsp_priv->supports_sgmii) + return -EINVAL; + break; default: dev_err(bsp_priv->dev, "unsupported interface %d", bsp_priv->phy_iface); @@ -1379,16 +1449,19 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp= _priv) if (ret) return ret; =20 + ret =3D gmac_clk_enable(bsp_priv, true); + if (ret) + return ret; + + if (bsp_priv->phy_iface =3D=3D PHY_INTERFACE_MODE_SGMII) + goto set_mode; + ret =3D rk_get_phy_intf_sel(bsp_priv->phy_iface); if (ret < 0) - return ret; + goto clk_disable; =20 intf =3D ret; =20 - ret =3D gmac_clk_enable(bsp_priv, true); - if (ret) - return ret; - if (bsp_priv->gmac_phy_intf_sel_mask || bsp_priv->gmac_rmii_mode_mask) { /* If defined, encode the phy_intf_sel value */ @@ -1399,10 +1472,8 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_= priv) bsp_priv->gmac_rmii_mode_mask); =20 ret =3D rk_write_gmac_grf_reg(bsp_priv, val); - if (ret < 0) { - gmac_clk_enable(bsp_priv, false); - return ret; - } + if (ret < 0) + goto clk_disable; } =20 if (bsp_priv->clock.rmii_mode_mask) { @@ -1410,13 +1481,12 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp= _priv) bsp_priv->clock.rmii_mode_mask); =20 ret =3D rk_write_clock_grf_reg(bsp_priv, val); - if (ret < 0) { - gmac_clk_enable(bsp_priv, false); - return ret; - } + if (ret < 0) + goto clk_disable; } =20 - /*rmii or rgmii*/ +set_mode: + /* rmii, rgmii, sgmii */ switch (bsp_priv->phy_iface) { case PHY_INTERFACE_MODE_RGMII: dev_info(dev, "init for RGMII\n"); @@ -1447,15 +1517,20 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp= _priv) if (bsp_priv->ops->set_to_rmii) bsp_priv->ops->set_to_rmii(bsp_priv); break; + case PHY_INTERFACE_MODE_SGMII: + dev_info(dev, "init for SGMII\n"); + if (bsp_priv->ops->set_to_sgmii) + bsp_priv->ops->set_to_sgmii(bsp_priv); + break; default: dev_err(dev, "NO interface defined!\n"); + ret =3D -EINVAL; + goto clk_disable; } =20 ret =3D rk_phy_powerup(bsp_priv); - if (ret) { - gmac_clk_enable(bsp_priv, false); - return ret; - } + if (ret) + goto clk_disable; =20 pm_runtime_get_sync(dev); =20 @@ -1463,6 +1538,10 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_= priv) bsp_priv->ops->integrated_phy_powerup(bsp_priv); =20 return 0; + +clk_disable: + gmac_clk_enable(bsp_priv, false); + return ret; } =20 static void rk_gmac_powerdown(struct rk_priv_data *gmac) @@ -1602,6 +1681,17 @@ static int rk_gmac_probe(struct platform_device *pde= v) plat_dat->suspend =3D rk_gmac_suspend; plat_dat->resume =3D rk_gmac_resume; =20 + if (plat_dat->phy_interface =3D=3D PHY_INTERFACE_MODE_SGMII) { + /* SGMII clock always runs at 125 MHz */ + plat_dat->set_clk_tx_rate =3D NULL; + + /* SGMII requires a PCS */ + plat_dat->default_an_inband =3D true; + plat_dat->pcs_init =3D rk_pcs_init; + plat_dat->pcs_exit =3D rk_pcs_exit; + plat_dat->select_pcs =3D rk_select_pcs; + } + plat_dat->bsp_priv =3D rk_gmac_setup(pdev, plat_dat, data); if (IS_ERR(plat_dat->bsp_priv)) return PTR_ERR(plat_dat->bsp_priv); --=20 2.47.3 From nobody Thu Sep 24 22:17:45 2026 Received: from mail-pz2-f9.google.com (mail-pz2-f9.google.com [74.125.228.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A03C93F54D8 for ; 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Sat, 19 Sep 2026 05:53:04 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877aa0026b2sm991805b3a.44.2026.09.19.05.52.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 05:53:03 -0700 (PDT) From: Coia Prant To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v8 10/11] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port Date: Sat, 19 Sep 2026 20:51:17 +0800 Message-ID: <20260919125119.2107089-11-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Ariaboard Photonicat has a Motorcomm YT8521SC Gigabit Ethernet PHY connected to GMAC0 via XPCS SGMII. Enable the necessary nodes to make this port functional. Add rockchip,sgmii-mac-sel =3D <0> to the already enabled combphy2, to route the SGMII interface to GMAC0. RK3568 has three Combo PHYs that can carry SGMII; which one is wired to the XPCS is a board-level choice, and Photonicat uses combphy2. Enable the xpcs node and its port 0 sub-node, referencing combphy2 as the SerDes PHY. Add the mdio0 node with the YT8521SC PHY at address 3, including its reset GPIO and LED configuration. Also add LED configuration for the existing RGMII PHY on mdio1 for consistency. Signed-off-by: Coia Prant --- .../boot/dts/rockchip/rk3568-photonicat.dts | 74 ++++++++++++++++++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm6= 4/boot/dts/rockchip/rk3568-photonicat.dts index 58c1052ba8ef3..fdaa4a2a4328b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts @@ -3,6 +3,7 @@ /dts-v1/; =20 #include +#include #include #include #include "rk3568.dtsi" @@ -241,6 +242,7 @@ &combphy1 { }; =20 &combphy2 { + rockchip,sgmii-mac-sel =3D <0>; status =3D "okay"; }; =20 @@ -260,9 +262,18 @@ &cpu3 { cpu-supply =3D <&vdd_cpu>; }; =20 -/* Motorcomm YT8521SC LAN port (require SGMII) */ +/* Motorcomm YT8521SC LAN port */ &gmac0 { - status =3D "disabled"; + assigned-clocks =3D <&cru SCLK_GMAC0_RX_TX>; + assigned-clock-parents =3D <&clk_gmac0_xpcs_mii>; + managed =3D "in-band-status"; + pcs-handle =3D <&xpcs_mii0>; + phy-handle =3D <&sgmii_phy>; + phy-mode =3D "sgmii"; + phy-supply =3D <&vcc_3v3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_miim>; + status =3D "okay"; }; =20 /* Motorcomm YT8521SC WAN port */ @@ -341,6 +352,36 @@ &i2s0_8ch { status =3D "okay"; }; =20 +&mdio0 { + sgmii_phy: ethernet-phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x3>; + max-speed =3D <1000>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + default-state =3D "keep"; + }; + + led@2 { + reg =3D <2>; + color =3D ; + function =3D LED_FUNCTION_LAN; + default-state =3D "keep"; + }; + }; + }; +}; + &mdio1 { rgmii_phy: ethernet-phy@3 { compatible =3D "ethernet-phy-ieee802.3-c22"; @@ -350,6 +391,25 @@ rgmii_phy: ethernet-phy@3 { reset-gpios =3D <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; rx-internal-delay-ps =3D <1500>; tx-internal-delay-ps =3D <1500>; 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Sat, 19 Sep 2026 05:53:12 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877aa0026b2sm991805b3a.44.2026.09.19.05.53.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 05:53:11 -0700 (PDT) From: Coia Prant To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v8 11/11] MAINTAINERS: add entry for Rockchip XPCS driver Date: Sat, 19 Sep 2026 20:51:18 +0800 Message-ID: <20260919125119.2107089-12-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260919125119.2107089-1-coiaprant@gmail.com> References: <20260919125119.2107089-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a MAINTAINERS entry for the Rockchip RK3568 XPCS platform driver and its device tree binding. Include the relevant mailing lists (netdev and linux-rockchip) so that future patches are properly distributed. Signed-off-by: Coia Prant --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3b2eb2a7a89a8..f53a519da6298 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23739,6 +23739,15 @@ S: Maintained F: Documentation/devicetree/bindings/sound/rockchip,rk3576-sai.yaml F: sound/soc/rockchip/rockchip_sai.* =20 +ROCKCHIP XPCS DRIVER +M: Coia Prant +L: netdev@vger.kernel.org +L: linux-rockchip@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml +F: drivers/net/pcs/pcs-xpcs-rk.c +F: include/linux/pcs/pcs-xpcs-rk.h + ROCKER DRIVER M: Jiri Pirko L: netdev@vger.kernel.org --=20 2.47.3