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charset="utf-8" Add USB3 PHY support for the Google Tensor G5 USB PHY driver. This patch adds functionality for the usb3_tca register, usb3 clock, and usb3 reset as defined in google,lga-usb-phy.yaml. Kconfig now lists USB SuperSpeed support. Refactor the probe sequence to initialize the USB2 and USB3 PHYs, and then initialize clocks and resets for both PHYs afterwards. Refactor set_vbus_valid to reduce duplicated code. Implement USB3 phy_ops for phy_init, phy_exit, and phy_power_on. combo_phy_state enum is added to track PHY bringup state across PHY API calls. google_usb_set_orientation can reprogram the TCA when the PHY is ready. google_usb_set_orientation now calls pm_runtime_get_if_active to guarantee register access. Setting orientation and pm_runtime management are now handled within phy_mutex. Signed-off-by: RD Babiera --- Changes since v1: * Removed mix of goto-based and scope-based cleanup from usb3 phy_init * Removed unused usb3_core resource from probe * Added combo_phy_state enum to interally track ComboPHY bringup state to allow google_usb_set_orientation() to change TCA orientation. * Modify Kconfig documentation to reflect SuperSpeed support Changes since v2: * google_usb3_phy_init now sets USBDP_TOP_CFG_REG_PMGT_REF_CLK_REQ_N to false if phy_init fails elsewhere. * google_usb3_phy_init errors are now handled via DEFINE_FREE structures. This affects set_pmgt_ref_clk_req_n, clk_bulk_prepare_enable, and reset_control_bulk_deassert. * google_usb2_phy_init also handles undoing clk_bulk_prepare_enable via DEFINE_FREE structure. * google_usb3_phy_power_on allows program_tca_locked in the COMBO_PHY_TCA_READY state. Waiting for PoR=3D>NC is only performed once. * Note: there are checkpatch errors for the DEFINE_FREE macros resulting in "ERROR: trailing statements should be on next line". Other cases of DEFINE_FREE where the line limit would otherwise exceed 100 columns have the indentation done the same way. Changes since v3: * set_pmgt_ref_clk_req_n(false) in google_usb3_phy_exit() comes after reset assertion and clock disable to match phy_init() sequence. * program_tca_locked in usb3 power_on() now requires a valid orientation to match google_usb_set_orientation requirements. Changes since v4: * google_usb_set_orientation sets gphy->orientation while holding phy_mutex. * google_usb_set_orientation now holds a pm_runtime reference before checking for suspend, and calls put_autosuspend prior to normal exit. Changes since v5: * google_usb_set_orientation replaces pm_runtime_suspended check with pm_runtime_get_if_active call. Changes since v6: * google_usb_set_orientation uses pm_runtime_put() instead of pm_runtime_put_autosuspend(). * Added newline to all dev_* logs * xa_ack sw poll changed to 100ms, and xa_timeout_val is programmed to match during usb3 phy init * google_usb3_phy_power_on returns -EINVAL when PHY is idle and only performs PoR->NC wait in COMBO_PHY_INIT_DONE --- drivers/phy/Kconfig | 2 +- drivers/phy/phy-google-usb.c | 434 +++++++++++++++++++++++++++++++---- 2 files changed, 393 insertions(+), 43 deletions(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 19f3b7d12b7d..d2d401129af7 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -100,7 +100,7 @@ config PHY_GOOGLE_USB the G5 generation (Laguna). This driver provides the PHY interfaces to interact with the SNPS eUSB2 and USB 3.2/DisplayPort Combo PHY, both of which are integrated with the DWC3 USB DRD controller. - This driver currently supports USB high-speed. + This driver currently supports USB high-speed and SuperSpeed. =20 config USB_LGM_PHY tristate "INTEL Lightning Mountain USB PHY Driver" diff --git a/drivers/phy/phy-google-usb.c b/drivers/phy/phy-google-usb.c index ab20bc20f19e..f2716125ae92 100644 --- a/drivers/phy/phy-google-usb.c +++ b/drivers/phy/phy-google-usb.c @@ -20,6 +20,7 @@ #include #include =20 +/* USB_CFG_CSR */ #define USBCS_USB2PHY_CFG19_OFFSET 0x0 #define USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV GENMASK(19, 8) =20 @@ -28,11 +29,44 @@ #define USBCS_USB2PHY_CFG21_REF_FREQ_SEL GENMASK(15, 13) #define USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL BIT(19) =20 +/* USBDP_TOP */ #define USBCS_PHY_CFG1_OFFSET 0x28 +#define USBCS_PHY_CFG1_PHY0_MPLLA_SSC_EN BIT(1) +#define USBCS_PHY_CFG1_PHY0_SRAM_BYPASS_MODE GENMASK(11, 10) +#define SRAM_BYPASS_MODE_BYPASS_FIRMWARE BIT(0) +#define SRAM_BYPASS_MODE_BYPASS_CONTEXT BIT(1) #define USBCS_PHY_CFG1_SYS_VBUSVALID BIT(17) =20 +#define USBDP_TOP_CFG_REG_OFFSET 0x44 +#define USBDP_TOP_CFG_REG_PMGT_REF_CLK_REQ_N BIT(0) + +#define PHY_POWER_CONFIG_REG1_OFFSET 0x48 +#define PHY_POWER_CONFIG_REG1_PG_MODE_EN BIT(1) +#define PHY_POWER_CONFIG_REG1_UPCS_PIPE_CONFIG GENMASK(31, 14) +#define UPCS_PIPE_CONFIG_ISO_CPM BIT(5) +#define UPCS_PIPE_CONFIG_PG_MODE_STATIC BIT(6) +#define UPCS_PIPE_CONFIG_LANE_RESET_NO_PG_EXIT BIT(9) + +/* USB3_TCA */ +#define TCA_INTR_STS_OFFSET 0x8 +#define TCA_INTR_STS_XA_ACT_EVT BIT(0) +#define TCA_TCPC_OFFSET 0x14 +#define TCA_TCPC_MUX_CONTROL GENMASK(2, 0) +#define TCA_TCPC_MUX_CONTROL_USB_ONLY 0x1 +#define TCA_TCPC_CONNECTOR_ORIENTATION BIT(3) +#define TCA_TCPC_VALID BIT(4) +#define TCA_CTRLSYNCMODE_CFG1_OFFSET 0x24 +#define TCA_CTRLSYNCMODE_CFG1_XA_TIMEOUT_VAL GENMASK(19, 0) +#define TCA_CTRLSYNCMODE_CFG1_XA_TIMEOUT_VAL_100MS 0x1e85 +#define TCA_PSTATE_0_OFFSET 0x50 +#define TCA_PSTATE_0_UPCS_LANE0_PHYSTATUS BIT(8) + +#define GPHY_TCA_DELAY_US 10 +#define GPHY_TCA_TIMEOUT_US 100000 + enum google_usb_phy_id { GOOGLE_USB2_PHY, + GOOGLE_USB3_PHY, GOOGLE_USB_PHY_NUM, }; =20 @@ -46,53 +80,199 @@ struct google_usb_phy_instance { struct reset_control_bulk_data *rsts; }; =20 +struct google_usb_phy_config { + const char * const *clk_names; + unsigned int num_clks; + const char * const *rst_names; + unsigned int num_rsts; +}; + +static const char * const u2phy_clk_names[] =3D { + "usb2", + "usb2_apb", +}; +static const char * const u3phy_clk_names[] =3D { + "usb3" +}; +static const char * const u2phy_rst_names[] =3D { + "usb2", + "usb2_apb", +}; +static const char * const u3phy_rst_names[] =3D { + "usb3" +}; + +static const struct google_usb_phy_config phy_configs[GOOGLE_USB_PHY_NUM] = =3D { + [GOOGLE_USB2_PHY] =3D { + .clk_names =3D u2phy_clk_names, + .num_clks =3D ARRAY_SIZE(u2phy_clk_names), + .rst_names =3D u2phy_rst_names, + .num_rsts =3D ARRAY_SIZE(u2phy_rst_names), + }, + [GOOGLE_USB3_PHY] =3D { + .clk_names =3D u3phy_clk_names, + .num_clks =3D ARRAY_SIZE(u3phy_clk_names), + .rst_names =3D u3phy_rst_names, + .num_rsts =3D ARRAY_SIZE(u3phy_rst_names), + }, +}; + +static inline void google_usb_phy_clk_disable(struct google_usb_phy_instan= ce *inst) +{ + clk_bulk_disable_unprepare(inst->num_clks, inst->clks); +} +DEFINE_FREE(inst_clk_disable, struct google_usb_phy_instance *, + if (_T) google_usb_phy_clk_disable(_T)) + +static inline void google_usb_phy_rst_disable(struct google_usb_phy_instan= ce *inst) +{ + reset_control_bulk_assert(inst->num_rsts, inst->rsts); +} +DEFINE_FREE(inst_rst_disable, struct google_usb_phy_instance *, + if (_T) google_usb_phy_rst_disable(_T)) + +/* + * combo_phy_state + * COMBO_PHY_IDLE: The ComboPHY has been torn down and USB3 has not comple= ted + * bringup + * COMBO_PHY_INIT_DONE: The ComboPHY bringup sequence is complete. + * COMBO_PHY_TCA_READY: The PoR =3D> NC transition is complete, and the TC= A can be + * moved into USB. + */ +enum combo_phy_state { + COMBO_PHY_IDLE, + COMBO_PHY_INIT_DONE, + COMBO_PHY_TCA_READY, +}; + struct google_usb_phy { struct device *dev; struct regmap *usb_cfg_regmap; unsigned int usb2_cfg_offset; void __iomem *usbdp_top_base; + void __iomem *usb3_tca_base; struct google_usb_phy_instance *insts; /* * Protect phy registers from concurrent access, specifically via - * google_usb_set_orientation callback. + * google_usb_set_orientation callback. phy_mutex also protects + * concurrent access to phy_state. */ struct mutex phy_mutex; struct typec_switch_dev *sw; enum typec_orientation orientation; + enum combo_phy_state phy_state; }; =20 static void set_vbus_valid(struct google_usb_phy *gphy) { u32 reg; =20 - if (gphy->orientation =3D=3D TYPEC_ORIENTATION_NONE) { - reg =3D readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + reg =3D readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + if (gphy->orientation =3D=3D TYPEC_ORIENTATION_NONE) reg &=3D ~USBCS_PHY_CFG1_SYS_VBUSVALID; - writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); - } else { - reg =3D readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + else reg |=3D USBCS_PHY_CFG1_SYS_VBUSVALID; - writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); - } + writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); +} + +static void set_sram_bypass(struct google_usb_phy *gphy, u32 bypass) +{ + u32 reg; + + reg =3D readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + reg &=3D ~USBCS_PHY_CFG1_PHY0_SRAM_BYPASS_MODE; + reg |=3D FIELD_PREP(USBCS_PHY_CFG1_PHY0_SRAM_BYPASS_MODE, bypass); + writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); +} + +static void set_pmgt_ref_clk_req_n(struct google_usb_phy *gphy, bool resum= e) +{ + u32 reg; + + reg =3D readl(gphy->usbdp_top_base + USBDP_TOP_CFG_REG_OFFSET); + if (resume) + reg |=3D USBDP_TOP_CFG_REG_PMGT_REF_CLK_REQ_N; + else + reg &=3D ~USBDP_TOP_CFG_REG_PMGT_REF_CLK_REQ_N; + writel(reg, gphy->usbdp_top_base + USBDP_TOP_CFG_REG_OFFSET); +} + +static inline void disable_pmgt_ref_clk_req_n(struct google_usb_phy *gphy) +{ + set_pmgt_ref_clk_req_n(gphy, false); +} +DEFINE_FREE(pmgt_ref_clk_req_n, struct google_usb_phy *, if (_T) disable_p= mgt_ref_clk_req_n(_T)) + +static int wait_tca_xa_ack(struct google_usb_phy *gphy) +{ + int ret; + u32 reg; + + ret =3D readl_poll_timeout(gphy->usb3_tca_base + TCA_INTR_STS_OFFSET, + reg, !!(reg & TCA_INTR_STS_XA_ACT_EVT), + GPHY_TCA_DELAY_US, GPHY_TCA_TIMEOUT_US); + if (ret) + dev_err(gphy->dev, "tca xa_ack timeout, ret=3D%d\n", ret); + + return ret; +} + +static int program_tca_locked(struct google_usb_phy *gphy) + __must_hold(&gphy->phy_mutex) +{ + int ret; + u32 reg; + + reg =3D readl(gphy->usb3_tca_base + TCA_INTR_STS_OFFSET); + writel(reg, gphy->usb3_tca_base + TCA_INTR_STS_OFFSET); + + reg =3D readl(gphy->usb3_tca_base + TCA_TCPC_OFFSET); + reg &=3D ~TCA_TCPC_MUX_CONTROL; + reg |=3D FIELD_PREP(TCA_TCPC_MUX_CONTROL, TCA_TCPC_MUX_CONTROL_USB_ONLY); + if (gphy->orientation =3D=3D TYPEC_ORIENTATION_REVERSE) + reg |=3D TCA_TCPC_CONNECTOR_ORIENTATION; + else + reg &=3D ~TCA_TCPC_CONNECTOR_ORIENTATION; + reg |=3D TCA_TCPC_VALID; + writel(reg, gphy->usb3_tca_base + TCA_TCPC_OFFSET); + + ret =3D wait_tca_xa_ack(gphy); + dev_dbg(gphy->dev, "TCA switch %s, mux %lu, orientation %s\n", + ret ? "failed" : "success", + FIELD_GET(TCA_TCPC_MUX_CONTROL, reg), + FIELD_GET(TCA_TCPC_CONNECTOR_ORIENTATION, reg) ? "reverse" : "normal"); + + reg =3D readl(gphy->usb3_tca_base + TCA_INTR_STS_OFFSET); + writel(reg, gphy->usb3_tca_base + TCA_INTR_STS_OFFSET); + + return ret; } =20 static int google_usb_set_orientation(struct typec_switch_dev *sw, enum typec_orientation orientation) { struct google_usb_phy *gphy =3D typec_switch_get_drvdata(sw); + int ret =3D 0; =20 dev_dbg(gphy->dev, "set orientation %d\n", orientation); =20 - gphy->orientation =3D orientation; + guard(mutex)(&gphy->phy_mutex); =20 - if (pm_runtime_suspended(gphy->dev)) - return 0; + gphy->orientation =3D orientation; =20 - guard(mutex)(&gphy->phy_mutex); + if (IS_ENABLED(CONFIG_PM)) { + if (pm_runtime_get_if_active(gphy->dev) <=3D 0) + return 0; + } =20 set_vbus_valid(gphy); =20 - return 0; + if (gphy->phy_state =3D=3D COMBO_PHY_TCA_READY && orientation !=3D TYPEC_= ORIENTATION_NONE) + ret =3D program_tca_locked(gphy); + + pm_runtime_put(gphy->dev); + + return ret; } =20 static int google_usb2_phy_init(struct phy *_phy) @@ -122,17 +302,18 @@ static int google_usb2_phy_init(struct phy *_phy) ret =3D clk_bulk_prepare_enable(inst->num_clks, inst->clks); if (ret) return ret; + struct google_usb_phy_instance *clk_dev __free(inst_clk_disable) =3D inst; =20 ret =3D reset_control_bulk_deassert(inst->num_rsts, inst->rsts); - if (ret) { - clk_bulk_disable_unprepare(inst->num_clks, inst->clks); + if (ret) return ret; - } =20 regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_C= FG21_OFFSET, ®); reg |=3D USBCS_USB2PHY_CFG21_PHY_ENABLE; regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_= CFG21_OFFSET, reg); =20 + retain_and_null_ptr(clk_dev); + return 0; } =20 @@ -161,6 +342,128 @@ static const struct phy_ops google_usb2_phy_ops =3D { .exit =3D google_usb2_phy_exit, }; =20 +static int google_usb3_phy_init(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D inst->parent; + int ret =3D 0; + u32 reg; + + dev_dbg(gphy->dev, "initializing usb3 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + if (gphy->phy_state !=3D COMBO_PHY_IDLE) { + dev_warn(gphy->dev, "usb3 phy init called when combo phy state is not id= le\n"); + return 0; + } + + reg =3D readl(gphy->usb3_tca_base + TCA_CTRLSYNCMODE_CFG1_OFFSET); + reg &=3D ~TCA_CTRLSYNCMODE_CFG1_XA_TIMEOUT_VAL; + reg |=3D FIELD_PREP(TCA_CTRLSYNCMODE_CFG1_XA_TIMEOUT_VAL, + TCA_CTRLSYNCMODE_CFG1_XA_TIMEOUT_VAL_100MS); + writel(reg, gphy->usb3_tca_base + TCA_CTRLSYNCMODE_CFG1_OFFSET); + + reg =3D readl(gphy->usbdp_top_base + PHY_POWER_CONFIG_REG1_OFFSET); + reg |=3D PHY_POWER_CONFIG_REG1_PG_MODE_EN; + reg &=3D ~PHY_POWER_CONFIG_REG1_UPCS_PIPE_CONFIG; + reg |=3D FIELD_PREP(PHY_POWER_CONFIG_REG1_UPCS_PIPE_CONFIG, + (UPCS_PIPE_CONFIG_ISO_CPM | + UPCS_PIPE_CONFIG_PG_MODE_STATIC | + UPCS_PIPE_CONFIG_LANE_RESET_NO_PG_EXIT)); + writel(reg, gphy->usbdp_top_base + PHY_POWER_CONFIG_REG1_OFFSET); + + set_vbus_valid(gphy); + + reg =3D readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + reg |=3D USBCS_PHY_CFG1_PHY0_MPLLA_SSC_EN; + writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + + set_sram_bypass(gphy, SRAM_BYPASS_MODE_BYPASS_FIRMWARE | + SRAM_BYPASS_MODE_BYPASS_CONTEXT); + set_pmgt_ref_clk_req_n(gphy, true); + struct google_usb_phy *pmgt_ref_clk_req_dev __free(pmgt_ref_clk_req_n) = =3D gphy; + + ret =3D clk_bulk_prepare_enable(inst->num_clks, inst->clks); + if (ret) + return ret; + struct google_usb_phy_instance *clk_dev __free(inst_clk_disable) =3D inst; + + ret =3D reset_control_bulk_deassert(inst->num_rsts, inst->rsts); + if (ret) + return ret; + struct google_usb_phy_instance *rst_dev __free(inst_rst_disable) =3D inst; + + ret =3D readl_poll_timeout(gphy->usb3_tca_base + TCA_PSTATE_0_OFFSET, + reg, !(reg & TCA_PSTATE_0_UPCS_LANE0_PHYSTATUS), + GPHY_TCA_DELAY_US, GPHY_TCA_TIMEOUT_US); + if (ret) { + dev_err(gphy->dev, "wait for lane0 phystatus timed out\n"); + return ret; + } + + gphy->phy_state =3D COMBO_PHY_INIT_DONE; + + retain_and_null_ptr(rst_dev); + retain_and_null_ptr(clk_dev); + retain_and_null_ptr(pmgt_ref_clk_req_dev); + + return 0; +} + +static int google_usb3_phy_exit(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D inst->parent; + + dev_dbg(gphy->dev, "exiting usb3 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + reset_control_bulk_assert(inst->num_rsts, inst->rsts); + clk_bulk_disable_unprepare(inst->num_clks, inst->clks); + set_pmgt_ref_clk_req_n(gphy, false); + + gphy->phy_state =3D COMBO_PHY_IDLE; + + return 0; +} + +static int google_usb3_phy_power_on(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D inst->parent; + int ret; + + dev_dbg(gphy->dev, "power on usb3 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + if (gphy->phy_state =3D=3D COMBO_PHY_IDLE) + return -EINVAL; + + if (gphy->phy_state =3D=3D COMBO_PHY_INIT_DONE) { + /* Wait for PoR -> NC transitions*/ + ret =3D wait_tca_xa_ack(gphy); + if (ret) { + dev_err(gphy->dev, "PoR->NC transition timeout\n"); + return ret; + } + gphy->phy_state =3D COMBO_PHY_TCA_READY; + } + + if (gphy->orientation !=3D TYPEC_ORIENTATION_NONE) + return program_tca_locked(gphy); + + return 0; +} + +static const struct phy_ops google_usb3_phy_ops =3D { + .init =3D google_usb3_phy_init, + .exit =3D google_usb3_phy_exit, + .power_on =3D google_usb3_phy_power_on, +}; + static struct phy *google_usb_phy_xlate(struct device *dev, const struct of_phandle_args *args) { @@ -173,14 +476,61 @@ static struct phy *google_usb_phy_xlate(struct device= *dev, return gphy->insts[args->args[0]].phy; } =20 +static int google_usb_phy_parse_clocks(struct google_usb_phy *gphy) +{ + struct device *dev =3D gphy->dev; + int id, i, ret; + + for (id =3D 0; id < GOOGLE_USB_PHY_NUM; id++) { + const struct google_usb_phy_config *cfg =3D &phy_configs[id]; + struct google_usb_phy_instance *inst =3D &gphy->insts[id]; + + inst->num_clks =3D cfg->num_clks; + inst->clks =3D devm_kcalloc(dev, inst->num_clks, sizeof(*inst->clks), GF= P_KERNEL); + if (!inst->clks) + return -ENOMEM; + + for (i =3D 0; i < inst->num_clks; i++) + inst->clks[i].id =3D cfg->clk_names[i]; + + ret =3D devm_clk_bulk_get(dev, inst->num_clks, inst->clks); + if (ret) + return dev_err_probe(dev, ret, "failed to get phy%d clks\n", id); + } + + return 0; +} + +static int google_usb_phy_parse_resets(struct google_usb_phy *gphy) +{ + struct device *dev =3D gphy->dev; + int id, i, ret; + + for (id =3D 0; id < GOOGLE_USB_PHY_NUM; id++) { + const struct google_usb_phy_config *cfg =3D &phy_configs[id]; + struct google_usb_phy_instance *inst =3D &gphy->insts[id]; + + inst->num_rsts =3D cfg->num_rsts; + inst->rsts =3D devm_kcalloc(dev, inst->num_rsts, sizeof(*inst->rsts), GF= P_KERNEL); + if (!inst->rsts) + return -ENOMEM; + + for (i =3D 0; i < inst->num_rsts; i++) + inst->rsts[i].id =3D cfg->rst_names[i]; + ret =3D devm_reset_control_bulk_get_exclusive(dev, inst->num_rsts, inst-= >rsts); + if (ret) + return dev_err_probe(dev, ret, "failed to get phy%d resets\n", id); + } + + return 0; +} + static int google_usb_phy_probe(struct platform_device *pdev) { struct typec_switch_desc sw_desc =3D { }; - struct google_usb_phy_instance *inst; struct phy_provider *phy_provider; struct device *dev =3D &pdev->dev; struct google_usb_phy *gphy; - struct phy *phy; u32 args[1]; int ret; =20 @@ -212,39 +562,39 @@ static int google_usb_phy_probe(struct platform_devic= e *pdev) return dev_err_probe(dev, PTR_ERR(gphy->usbdp_top_base), "invalid usbdp top\n"); =20 + gphy->usb3_tca_base =3D devm_platform_ioremap_resource_byname(pdev, + "usb3_tca"); + if (IS_ERR(gphy->usb3_tca_base)) + return dev_err_probe(dev, PTR_ERR(gphy->usb3_tca_base), + "invalid usb3 tca\n"); + gphy->insts =3D devm_kcalloc(dev, GOOGLE_USB_PHY_NUM, sizeof(*gphy->insts= ), GFP_KERNEL); if (!gphy->insts) return -ENOMEM; =20 - inst =3D &gphy->insts[GOOGLE_USB2_PHY]; - inst->parent =3D gphy; - inst->index =3D GOOGLE_USB2_PHY; - phy =3D devm_phy_create(dev, NULL, &google_usb2_phy_ops); - if (IS_ERR(phy)) - return dev_err_probe(dev, PTR_ERR(phy), + gphy->insts[GOOGLE_USB2_PHY].phy =3D devm_phy_create(dev, NULL, &google_u= sb2_phy_ops); + gphy->insts[GOOGLE_USB2_PHY].index =3D GOOGLE_USB2_PHY; + gphy->insts[GOOGLE_USB2_PHY].parent =3D gphy; + if (IS_ERR(gphy->insts[GOOGLE_USB2_PHY].phy)) + return dev_err_probe(dev, PTR_ERR(gphy->insts[GOOGLE_USB2_PHY].phy), "failed to create usb2 phy instance\n"); - inst->phy =3D phy; - phy_set_drvdata(phy, inst); + phy_set_drvdata(gphy->insts[GOOGLE_USB2_PHY].phy, &gphy->insts[GOOGLE_USB= 2_PHY]); =20 - inst->num_clks =3D 2; - inst->clks =3D devm_kcalloc(dev, inst->num_clks, sizeof(*inst->clks), GFP= _KERNEL); - if (!inst->clks) - return -ENOMEM; - inst->clks[0].id =3D "usb2"; - inst->clks[1].id =3D "usb2_apb"; - ret =3D devm_clk_bulk_get(dev, inst->num_clks, inst->clks); + gphy->insts[GOOGLE_USB3_PHY].phy =3D devm_phy_create(dev, NULL, &google_u= sb3_phy_ops); + gphy->insts[GOOGLE_USB3_PHY].index =3D GOOGLE_USB3_PHY; + gphy->insts[GOOGLE_USB3_PHY].parent =3D gphy; + if (IS_ERR(gphy->insts[GOOGLE_USB3_PHY].phy)) + return dev_err_probe(dev, PTR_ERR(gphy->insts[GOOGLE_USB3_PHY].phy), + "failed to create usb3 phy instance\n"); + phy_set_drvdata(gphy->insts[GOOGLE_USB3_PHY].phy, &gphy->insts[GOOGLE_USB= 3_PHY]); + + ret =3D google_usb_phy_parse_clocks(gphy); if (ret) - return dev_err_probe(dev, ret, "failed to get u2 phy clks\n"); + return ret; =20 - inst->num_rsts =3D 2; - inst->rsts =3D devm_kcalloc(dev, inst->num_rsts, sizeof(*inst->rsts), GFP= _KERNEL); - if (!inst->rsts) - return -ENOMEM; - inst->rsts[0].id =3D "usb2"; - inst->rsts[1].id =3D "usb2_apb"; - ret =3D devm_reset_control_bulk_get_exclusive(dev, inst->num_rsts, inst->= rsts); + ret =3D google_usb_phy_parse_resets(gphy); if (ret) - return dev_err_probe(dev, ret, "failed to get u2 phy resets\n"); + return ret; =20 phy_provider =3D devm_of_phy_provider_register(dev, google_usb_phy_xlate); if (IS_ERR(phy_provider)) base-commit: cee9395acd8043be0644b25c34bfa86623f2b935 --=20 2.55.0.1082.g2b9226bbc0-goog