From nobody Thu Sep 24 22:57:19 2026 Received: from trabant.uid0.hu (trabant.uid0.hu [81.0.124.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA6B225C818; Fri, 18 Sep 2026 20:44:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=81.0.124.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789764274; cv=none; b=nkATTDIDxvW1cuEHHbVdBj6t07PboI57fgaQBe7qjsqwiT+y+18HTJtvDRLPS625TLRbZ8sGgsD4dtDyCMqQsq8fAHPi/sH79t2Oe+tE5R48bNtnttTvsNLfGtn3MuzIv1XVR65QIzaHowE4SDeHxnCR9CBTQsUQztoibXBy7Ks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789764274; c=relaxed/simple; bh=IzXynBoBnQHRbZIM7KYj+WteAOsX9MEUwb/3J/Ax4hM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mXNAnY2V6qNYibbJC6Rq6tGwmciwPpkecePA24mmGV2uFfF9U563ZlPsJPh7UzgD4uQW626jKYy8paJCwNdjfU3okNPSgQHfSzHW8huaqVQaXwmMhSHHlKxD6KnCZsM2RbhEU6N6xcpUEBcKSBNxAqSl1wwrDrRA54dym5IQ9zA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=uid0.hu; spf=none smtp.mailfrom=trabant.uid0.hu; arc=none smtp.client-ip=81.0.124.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=uid0.hu Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=trabant.uid0.hu Received: from wigyori by trabant.uid0.hu with local (Exim 4.94.2 #2 (Debian)) id 1x7ehW-0000ER-K4 from ; Fri, 18 Sep 2026 21:56:50 +0200 From: Zoltan HERPAI To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Frank.Li@nxp.com, s.hauer@pengutronix.de, festevam@gmail.com, kernel@pengutronix.de Cc: wigyori@uid0.hu, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: arm64: fsl: add Olimex i.MX8MP boards Date: Fri, 18 Sep 2026 21:55:58 +0200 Message-Id: <20260918195559.130443-2-wigyori@uid0.hu> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20260918195559.130443-1-wigyori@uid0.hu> References: <20260918195559.130443-1-wigyori@uid0.hu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Zoltan HERPAI Content-Type: text/plain; charset="utf-8" Document board compatible bindings for the Olimex i.MX8MP-SOM and -EVB boards. Signed-off-by: Zoltan HERPAI --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 656f2596e..aef153222 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1146,6 +1146,8 @@ properties: - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board + - olimex,imx8mp-som # Olimex i.MX8MP-SOM + - olimex,imx8mp-som-evb # Olimex i.MX8MP-SOM-EVB - prt,prt8ml # Protonic PRT8ML - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without fr= ontplate - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control = without panel @@ -1225,6 +1227,11 @@ properties: - const: kontron,imx8mp-osm-s # Kontron i.MX8MP OS= M-S SoM - const: fsl,imx8mp =20 + - description: Olimex i.MX8MP boards + items: + - const: olimex,imx8mp-som # Olimex i.MX8MP-SOM + - const: olimex,imx8mp-som-evb # Olimex i.MX8MP-SOM-EVB + - description: PHYTEC phyCORE-i.MX8MP FPSC based boards items: - enum: --=20 2.39.5 From nobody Thu Sep 24 22:57:19 2026 Received: from trabant.uid0.hu (trabant.uid0.hu [81.0.124.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CD7829E116; Fri, 18 Sep 2026 20:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=81.0.124.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789763963; cv=none; b=c41FpLnuAqmfjdqVpOEhwwswj1BCbwxyFGKx8I1W+1KprzIuFzb52Nm5Gx8NFj1/DGreyzB4FNhvMbUpnVxDYhBDgI1mjrBd7mLOU2mZ5ShB0Vj8WXcicJxprFdMyeqbtnxOWiTNeaKX/FkMrd9zmdLQT0y+IOKcl6GjJ0A8oEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789763963; c=relaxed/simple; bh=kSEzhII1Uv6CoDSYotk7wewXURai/zaHhs5CPre3kcU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UhDrSLj47ZXraPieP+St00zrr7HTSmyz4gPfYhdFCxhe96ZYt0mwnpYlOYhbakeBfBK0YJAbUhLKPE1xwOrVnmFzyB0mjap6eUa3vYcN/00pN/8YmSkUHyKQMPE3r0VcoooTMp7ondbKsA2u+cADgJ/6VmZV/kTGfv3gkXx8v9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=uid0.hu; spf=none smtp.mailfrom=trabant.uid0.hu; arc=none smtp.client-ip=81.0.124.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=uid0.hu Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=trabant.uid0.hu Received: from wigyori by trabant.uid0.hu with local (Exim 4.94.2 #2 (Debian)) id 1x7ehX-0000Ek-0w from ; Fri, 18 Sep 2026 21:56:51 +0200 From: Zoltan HERPAI To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Frank.Li@nxp.com, s.hauer@pengutronix.de, festevam@gmail.com, kernel@pengutronix.de Cc: wigyori@uid0.hu, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit Date: Fri, 18 Sep 2026 21:55:59 +0200 Message-Id: <20260918195559.130443-3-wigyori@uid0.hu> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20260918195559.130443-1-wigyori@uid0.hu> References: <20260918195559.130443-1-wigyori@uid0.hu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Zoltan HERPAI Content-Type: text/plain; charset="utf-8" This adds support for an i.MX8-based system-on-module + EVB board. The product pages are here [1] and here [2] respectively. There are two new files, one dts for the EVB and one dtsi for the SoM. EVB features: - microSD slot, eMMC headers - 2x Ethernet 1Gb - 2x USB 3.0 - 1x m.2 PCIe slot - 2x CAN interface - audio (2x jacks via ES8328) - at24 eeprom - separate UARTs for the A53 and the M7 cores - HDMI - UEXT and GPIO connectors with I2C available SoM features: - NXP i.MX8MP @ 1600MHz - 4GByte memory - LVDS interface - 2x MIPI_CSI, 1x MIPI_DSI - status LED [1] https://www.olimex.com/Products/SOM/NXP-iMX8/iMX8MP-SOM-4GB-IND [2] https://www.olimex.com/Products/SOM/NXP-iMX8/iMX8MP-SOM-EVB-IND Signed-off-by: Zoltan HERPAI --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-olimex-som-evb.dts | 137 +++++ .../boot/dts/freescale/imx8mp-olimex-som.dtsi | 571 ++++++++++++++++++ 3 files changed, 709 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 95ae85ab4..3657e3464 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -447,6 +447,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-nitrogen-enc-carrier-board.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-nitrogen-smarc-universal-board.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-olimex-som-evb.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-etml1010g3dra-dtbs +=3D imx8mp-phyboard-pollux-rdk.= dtb \ imx8mp-phyboard-pollux-etml1010g3dra.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts b/arch= /arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts new file mode 100644 index 000000000..26fee72d5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2026 Zoltan HERPAI + */ + +/dts-v1/; + +#include "imx8mp-olimex-som.dtsi" + +/ { + compatible =3D "olimex,imx8mp-som-evb", "fsl,imx8mp"; + model =3D "Olimex i.MX8MP-SOM-EVB"; + + chosen { + stdout-path =3D &uart2; + }; +}; + +&ecspi2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + + status =3D "okay"; + + spidev1: spi@0 { + reg =3D <0>; + compatible =3D "rohm,dh2228fv"; + spi-max-frequency =3D <500000>; + }; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + + status =3D "okay"; +}; + +&i2c1 { + eeprom: eeprom@50 { + compatible =3D "atmel,24c16"; + reg =3D <0x50>; + pagesize =3D <16>; + }; +}; + +&snvs_pwrkey { + status =3D "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-preemp-amp-tune-microamp =3D <1800>; + fsl,phy-tx-vref-tune-percent =3D <122>; + + status =3D "okay"; +}; + +&usb3_0 { + status =3D "okay"; +}; + +&usb_dwc3_0 { + dr_mode =3D "host"; + + status =3D "okay"; +}; + +&usb3_phy1 { + vbus-supply =3D <®_usb1_host_vbus>; + fsl,phy-tx-preemp-amp-tune-microamp =3D <1800>; + fsl,phy-tx-vref-tune-percent =3D <116>; + + status =3D "okay"; +}; + +&usb3_1 { + status =3D "okay"; +}; + +&usb_dwc3_1 { + dr_mode =3D "host"; + + status =3D "okay"; +}; + +&iomuxc { + pinctrl_ecspi2: ecspi2grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi b/arch/ar= m64/boot/dts/freescale/imx8mp-olimex-som.dtsi new file mode 100644 index 000000000..9876d3e7b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2026 Zoltan HERPAI + */ + +/dts-v1/; + +#include +#include +#include +#include "imx8mp.dtsi" + +/ { + compatible =3D "olimex,imx8mp-som", "fsl,imx8mp"; + + chosen { + stdout-path =3D &uart2; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_led>; + + led_status: status { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + }; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0x40000000>; + }; + + pcie0_refclk: clock-pcie0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + }; + + reg_pcie0: regulator-pcie { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcie0_reg>; + regulator-name =3D "MPCIE_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio2 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb1_host_vbus"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb1_vbus>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply =3D <&buck2>; +}; + +&A53_1 { + cpu-supply =3D <&buck2>; +}; + +&A53_2 { + cpu-supply =3D <&buck2>; +}; + +&A53_3 { + cpu-supply =3D <&buck2>; +}; + +&eqos { + phy-handle =3D <ðphy0>; + phy-mode =3D "rgmii-id"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + eee-broken-100tx; + eee-broken-1000t; + reset-gpios =3D <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <150000>; + reset-deassert-us =3D <10000>; + + reg =3D <3>; + }; + }; +}; + +&fec { + fsl,magic-packet; + phy-handle =3D <ðphy1>; + phy-mode =3D "rgmii-id"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reset-gpios =3D <&gpio4 2 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <150000>; + reset-deassert-us =3D <10000>; + + reg =3D <7>; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + + status =3D "okay"; + + pmic: pmic@25 { + reg =3D <0x25>; + compatible =3D "nxp,pca9450c"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 GPIO_ACTIVE_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name =3D "BUCK1"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck2: BUCK2 { + regulator-name =3D "BUCK2"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <950000>; + nxp,dvs-standby-voltage =3D <850000>; + }; + + buck4: BUCK4 { + regulator-name =3D "BUCK4"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name =3D "BUCK5"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name =3D "BUCK6"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1600000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name =3D "LDO3"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name =3D "LDO5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + + status =3D "okay"; +}; + +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + + status =3D "okay"; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcie0>; + reset-gpio =3D <&gpio2 7 GPIO_ACTIVE_LOW>; + vpcie-supply =3D <®_pcie0>; + + status =3D "okay"; +}; + +&pcie_phy { + clocks =3D <&pcie0_refclk>; + clock-names =3D "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode =3D ; + + status =3D "okay"; +}; + +&sdma2 { + status =3D "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + + status =3D "okay"; +}; + +&uart3 { + assigned-clocks =3D <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart3>; + + status =3D "okay"; +}; + +&usdhc2 { + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <4>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply =3D <®_usdhc2_vmmc>; + + status =3D "okay"; +}; + +&usdhc3 { + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <8>; + non-removable; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + + status =3D "okay"; +}; + +&wdog1 { + fsl,ext-reset-output; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 /* PCIE_RESET */ + >; + }; + + pinctrl_pcie0_reg: pcie0reggrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usb1_vbus: usb1grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_usb1_vbus: usb1grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; --=20 2.39.5