From nobody Thu Sep 24 23:04:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF93E5226BD; Fri, 18 Sep 2026 19:49:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789761002; cv=none; b=FDv5S35ZE/943Ccuq9PCMFf6ueMqoYBYl5T7cr9WlGb9v76aUy/MqMs89v4es+WbY31OtLPvDvvH3YK0L6jp2GWu0gtqpg+wHpkMk7JpfQKTWob2SEYTbXa5edj49z2PvZh8WDDw2dPb7a2czTQDzPbMGnQcN3xHaTD0yLMMdu4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789761002; c=relaxed/simple; bh=3iMYST5X29l3027pQ/XLTAVky5fTbewHB42aIY95FOM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cF97JDyXvMz1qBDYnKS1csiqjxeBCE9eIoSNlEyq57Ni+myzA/agfGE5VdIK2vK2RmYa5ybVFClHfmP+kb4mq9dQ0Mw8BVoSb7i9sRgVdu76dP/sLY6PBq2mG6LDtD2OCKQmXtsx71jHRTbnLj999nFYvAdcp3O95zWtUGAflhQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XWIgZg6O; arc=none smtp.client-ip=192.198.163.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XWIgZg6O" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789761000; x=1821297000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3iMYST5X29l3027pQ/XLTAVky5fTbewHB42aIY95FOM=; b=XWIgZg6O/tkd2jzIboRetmk6YxwfTi4xTlbfjqOex9xtnifsUfhAOqkL +iOhg7Y61JbHFL4tnBoOb75TqKaoXBWwiU2oRHMegrHMPommVZMjLQZz2 qHLekwa36Zl8ax8nRfQmE5Bxmn0mMctS5SNk75lIerYUlASIgjHDsPO2t iWY1GVJXJjUCpN9AHk0OrAgm289wEERkk4J9RzezQd8uw5x6wP9VsEdKb w5KwoiEXyctM1ZSmh9FOPYyuRx9x0PghPrp9f43/wmUsA7UpoAMcYUDKB Gl7RqtLuLXy+cYIaU7ADOBm04P5UMQRaKcUCQMqbmq/fZPNwK89lgrBf6 g==; X-CSE-ConnectionGUID: a4tjooTzT+aYtVxzLFhxZQ== X-CSE-MsgGUID: tog2zncTQ/+azimDHsoPAA== X-IronPort-AV: E=McAfee;i="6800,10657,11909"; a="790316" X-IronPort-AV: E=Sophos;i="6.27,109,1787036400"; d="scan'208";a="790316" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa115.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 12:49:59 -0700 X-CSE-ConnectionGUID: MJk4jq/zRainXTqPj7fVnQ== X-CSE-MsgGUID: hbR/DltSSfa2CYXim4yLYQ== X-ExtLoop1: 1 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 12:49:58 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v9 01/12] KVM: x86/pmu: Do not map fixed counters >= 3 to generic perf events Date: Fri, 18 Sep 2026 12:39:26 -0700 Message-ID: <20260918193937.569414-2-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260918193937.569414-1-zide.chen@intel.com> References: <20260918193937.569414-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Only fixed counters 0..2 have matching generic cross-platform hardware perf events (INSTRUCTIONS, CPU_CYCLES, REF_CPU_CYCLES). Therefore, perf_get_hw_event_config() is only applicable to these counters. KVM does not intend to emulate fixed counters >=3D 3 on legacy (non-mediated) vPMU, while for mediated vPMU, KVM does not care what the fixed counter event mappings are. Therefore, return 0 for their eventsel. The two BUILD_BUG_ON() checks are no longer needed, so drop them along with __always_inline. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi Reviewed-by: Jim Mattson --- v6: - Re-arrange the code for early return. Clearer. --- arch/x86/kvm/vmx/pmu_intel.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 70a8c4816135..11ad64d43e35 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -468,11 +468,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, st= ruct msr_data *msr_info) * different perf_event is already utilizing the requested counter, but th= e end * result is the same (ignoring the fact that using a general purpose coun= ter * will likely exacerbate counter contention). - * - * Forcibly inlined to allow asserting on @index at build time, and there = should - * never be more than one user. */ -static __always_inline u64 intel_get_fixed_pmc_eventsel(unsigned int index) +static u64 intel_get_fixed_pmc_eventsel(unsigned int index) { const enum perf_hw_id fixed_pmc_perf_ids[] =3D { [0] =3D PERF_COUNT_HW_INSTRUCTIONS, @@ -481,8 +478,13 @@ static __always_inline u64 intel_get_fixed_pmc_eventse= l(unsigned int index) }; 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18 Sep 2026 12:49:58 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v9 02/12] KVM: x86/pmu: Support Intel fixed counter 3 on mediated vPMU Date: Fri, 18 Sep 2026 12:39:27 -0700 Message-ID: <20260918193937.569414-3-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260918193937.569414-1-zide.chen@intel.com> References: <20260918193937.569414-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Starting with Ice Lake, Intel introduced fixed counter 3, which counts TOPDOWN.SLOTS - the number of available slots for an unhalted logical processor. It serves as the denominator for top-level metrics in the Top-down Microarchitecture Analysis method. Emulating this counter on legacy vPMU would require introducing a new generic perf encoding for the Intel-specific TOPDOWN.SLOTS event in order to call perf_get_hw_event_config(). This is undesirable as it would pollute the generic perf event encoding. Moreover, KVM does not intend to emulate IA32_PERF_METRICS in the legacy vPMU model, and without IA32_PERF_METRICS, emulating this counter has little practical value. Therefore, expose fixed counter 3 to guests only when mediated vPMU is enabled. Signed-off-by: Dapeng Mi Co-developed-by: Zide Chen Signed-off-by: Zide Chen Reviewed-by: Jim Mattson --- v6: - Update comments to replace 2 with KVM_MAX_NR_INTEL_FIXED_COUNTERS - 1. --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/msrs.c | 4 ++-- arch/x86/kvm/pmu.c | 19 ++++++++++++++++++- 3 files changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 30ffaa65f589..00584fcffa33 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -563,7 +563,7 @@ struct kvm_pmc { #define KVM_MAX_NR_GP_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_GP_COUNTERS, \ KVM_MAX_NR_AMD_GP_COUNTERS) =20 -#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 3 +#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 4 #define KVM_MAX_NR_AMD_FIXED_COUNTERS 0 #define KVM_MAX_NR_FIXED_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_FIXED_COUNTERS,= \ KVM_MAX_NR_AMD_FIXED_COUNTERS) diff --git a/arch/x86/kvm/msrs.c b/arch/x86/kvm/msrs.c index 37d5bed3529f..45e4c8a32436 100644 --- a/arch/x86/kvm/msrs.c +++ b/arch/x86/kvm/msrs.c @@ -217,7 +217,7 @@ static const u32 msrs_to_save_base[] =3D { =20 static const u32 msrs_to_save_pmu[] =3D { MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, - MSR_ARCH_PERFMON_FIXED_CTR0 + 2, + MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, MSR_CORE_PERF_GLOBAL_CTRL, MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, @@ -2672,7 +2672,7 @@ void kvm_init_msr_lists(void) { unsigned i; =20 - BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS !=3D 3, + BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS !=3D 4, "Please update the fixed PMCs in msrs_to_save_pmu[]"); =20 num_msrs_to_save =3D 0; diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index d2fd47ee5ec8..448044a2b121 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "x86.h" #include "cpuid.h" #include "lapic.h" @@ -99,7 +100,8 @@ static const struct x86_cpu_id vmx_pebs_pdist_cpu[] =3D { * all perf counters (both gp and fixed). The mapping relationship * between pmc and perf counters is as the following: * * Intel: [0 .. KVM_MAX_NR_INTEL_GP_COUNTERS-1] <=3D> gp counters - * [KVM_FIXED_PMC_BASE_IDX .. KVM_FIXED_PMC_BASE_IDX + 2] = <=3D> fixed + * KVM_MAX_NR_INTEL_FIXED_COUNTERS counters starting at + * KVM_FIXED_PMC_BASE_IDX <=3D> fixed * * AMD: [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H * and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=3D> gp counters */ @@ -134,6 +136,8 @@ void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_op= s) { bool is_intel =3D boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL; int min_nr_gp_ctrs =3D pmu_ops->MIN_NR_GP_COUNTERS; + union cpuid10_edx edx; + u32 eax, ebx, ecx; =20 /* * Hybrid PMUs don't play nice with virtualization without careful @@ -181,6 +185,19 @@ void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_o= ps) kvm_pmu_cap.num_counters_fixed =3D min(kvm_pmu_cap.num_counters_fixed, KVM_MAX_NR_FIXED_COUNTERS); =20 + /* + * Currently, KVM doesn't support non-contiguous fixed counters; make + * sure only contiguous ones are retained in kvm_pmu_cap. + */ + if (kvm_host_pmu.version >=3D 5) { + cpuid(0xa, &eax, &ebx, &ecx, &edx.full); + if (kvm_pmu_cap.num_counters_fixed > edx.split.num_counters_fixed) + kvm_pmu_cap.num_counters_fixed =3D edx.split.num_counters_fixed; + } + + if (!enable_mediated_pmu && kvm_pmu_cap.num_counters_fixed > 3) + kvm_pmu_cap.num_counters_fixed =3D 3; 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charset="utf-8" This is in preparation for it to be called from common x86 code, for example kvm_need_rdpmc_intercept(), to check the guest's PERF_METRICS capability. Rename it to kvm_vcpu_get_perf_caps() to indicate that it's part of the common API, and shorten _capabilities to _caps. No functional change intended. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi Reviewed-by: Jim Mattson --- v8: - remove include "cpuid.h" from pmu_intel.h. --- arch/x86/kvm/pmu.h | 8 ++++++++ arch/x86/kvm/vmx/pmu_intel.c | 6 +++--- arch/x86/kvm/vmx/pmu_intel.h | 12 +----------- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 090c9bbb74f4..82f955e5a450 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -271,6 +271,14 @@ static inline bool kvm_pmu_is_fastpath_emulation_allow= ed(struct kvm_vcpu *vcpu) X86_PMC_IDX_MAX); } =20 +static inline u64 kvm_vcpu_get_perf_caps(struct kvm_vcpu *vcpu) +{ + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM)) + return 0; + + return vcpu->arch.perf_capabilities; +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); int kvm_pmu_check_rdpmc_early(struct kvm_vcpu *vcpu, unsigned int idx); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 11ad64d43e35..28c1542e5ba5 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -193,13 +193,13 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu,= u32 msr) case MSR_CORE_PERF_FIXED_CTR_CTRL: return kvm_pmu_has_perf_global_ctrl(pmu); case MSR_IA32_PEBS_ENABLE: - ret =3D vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; + ret =3D kvm_vcpu_get_perf_caps(vcpu) & PERF_CAP_PEBS_FORMAT; break; case MSR_IA32_DS_AREA: ret =3D guest_cpu_cap_has(vcpu, X86_FEATURE_DS); break; case MSR_PEBS_DATA_CFG: - perf_capabilities =3D vcpu_get_perf_capabilities(vcpu); + perf_capabilities =3D kvm_vcpu_get_perf_caps(vcpu); ret =3D (perf_capabilities & PERF_CAP_PEBS_BASELINE) && ((perf_capabilities & PERF_CAP_PEBS_FORMAT) > 3); break; @@ -554,7 +554,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->raw_event_mask |=3D (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); } =20 - perf_capabilities =3D vcpu_get_perf_capabilities(vcpu); + perf_capabilities =3D kvm_vcpu_get_perf_caps(vcpu); if (intel_pmu_lbr_is_compatible(vcpu) && (perf_capabilities & PERF_CAP_LBR_FMT)) memcpy(&lbr_desc->records, &vmx_lbr_caps, sizeof(vmx_lbr_caps)); diff --git a/arch/x86/kvm/vmx/pmu_intel.h b/arch/x86/kvm/vmx/pmu_intel.h index 5d9357640aa1..dd447d8b6fdd 100644 --- a/arch/x86/kvm/vmx/pmu_intel.h +++ b/arch/x86/kvm/vmx/pmu_intel.h @@ -4,19 +4,9 @@ =20 #include =20 -#include "cpuid.h" - -static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu) -{ - if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM)) - return 0; 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18 Sep 2026 12:49:59 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v9 04/12] KVM: x86/pmu: Snapshot host IA32_PERF_CAPABILITIES in kvm_host Date: Fri, 18 Sep 2026 12:39:29 -0700 Message-ID: <20260918193937.569414-5-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260918193937.569414-1-zide.chen@intel.com> References: <20260918193937.569414-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mingwei Zhang Cache the unadulterated snapshot of perf_capabilities so that KVM can compare guest vPMU capabilities against raw hardware capabilities. For example, if the host supports PERF_METRICS but it is not configured for the guest, KVM can use it to determine that RDPMC accesses must be intercepted. Signed-off-by: Mingwei Zhang Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi Reviewed-by: Jim Mattson --- v5: new patch. --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/vmx/vmx.c | 8 ++------ arch/x86/kvm/x86.c | 4 ++++ 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 00584fcffa33..d00c7cbcfa14 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -295,6 +295,7 @@ struct kvm_host_values { u64 xss; u64 s_cet; u64 arch_capabilities; + u64 perf_capabilities; }; extern struct kvm_host_values kvm_host; =20 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 56b44e032395..715e44489e22 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7949,14 +7949,10 @@ void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) static __init u64 vmx_get_perf_capabilities(void) { u64 perf_cap =3D PERF_CAP_FW_WRITES; - u64 host_perf_cap =3D 0; =20 if (!enable_pmu) return 0; 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18 Sep 2026 12:49:59 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v9 05/12] KVM: x86/pmu: Support PERF_METRICS MSR in mediated vPMU Date: Fri, 18 Sep 2026 12:39:30 -0700 Message-ID: <20260918193937.569414-6-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260918193937.569414-1-zide.chen@intel.com> References: <20260918193937.569414-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Bit 15 in IA32_PERF_CAPABILITIES indicates that the CPU provides built-in support for Topdown Microarchitecture Analysis (TMA) L1 metrics via the IA32_PERF_METRICS MSR. Expose this capability only when mediated vPMU is enabled, as emulating IA32_PERF_METRICS in the legacy vPMU model is impractical. Pass IA32_PERF_METRICS through to the guest only when mediated vPMU is enabled and bit 15 is set in guest IA32_PERF_CAPABILITIES. Allow kvm_pmu_{get,set}_msr() to handle this MSR for host accesses. Save and restore this MSR on host/guest PMU context switches so that host PMU activity does not clobber the guest value, and guest state is not leaked into the host. If the host supports PERF_METRICS but it is not exposed to the guest, MSR_CORE_PERF_GLOBAL_CTRL must be intercepted so the guest cannot enable PERF_METRICS via GLOBAL_CTRL[48]. Signed-off-by: Dapeng Mi Co-developed-by: Zide Chen Signed-off-by: Zide Chen --- v9: - Remove the incorrect comment about writing to MSR_PERF_METRICS. v8: - Intercept global ctrl MSR if host supports PerfMetrics but not enabled in the guest. --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 1 + arch/x86/kvm/msrs.c | 6 +++++- arch/x86/kvm/pmu.c | 7 +++++++ arch/x86/kvm/pmu.h | 5 +++++ arch/x86/kvm/vmx/nested.c | 2 ++ arch/x86/kvm/vmx/pmu_intel.c | 29 +++++++++++++++++++++++++++++ arch/x86/kvm/vmx/vmx.c | 7 +++++++ 8 files changed, 57 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index d00c7cbcfa14..052bf377dedb 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -584,6 +584,7 @@ struct kvm_pmu { u64 global_status_rsvd; u64 reserved_bits; u64 raw_event_mask; + u64 perf_metrics; struct kvm_pmc gp_counters[KVM_MAX_NR_GP_COUNTERS]; struct kvm_pmc fixed_counters[KVM_MAX_NR_FIXED_COUNTERS]; =20 diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 3a8e51a0c9e8..8fad944197fb 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -331,6 +331,7 @@ #define PERF_CAP_PEBS_FORMAT 0xf00 #define PERF_CAP_FW_WRITES BIT_ULL(13) #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) +#define PERF_CAP_PERF_METRICS BIT_ULL(15) #define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ diff --git a/arch/x86/kvm/msrs.c b/arch/x86/kvm/msrs.c index 45e4c8a32436..7b7b5db00f54 100644 --- a/arch/x86/kvm/msrs.c +++ b/arch/x86/kvm/msrs.c @@ -219,7 +219,7 @@ static const u32 msrs_to_save_pmu[] =3D { MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, - MSR_CORE_PERF_GLOBAL_CTRL, + MSR_CORE_PERF_GLOBAL_CTRL, MSR_PERF_METRICS, MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, =20 /* This part of MSRs should match KVM_MAX_NR_INTEL_GP_COUNTERS. */ @@ -2609,6 +2609,10 @@ static void kvm_probe_msr_to_save(u32 msr_index) intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)) return; break; + case MSR_PERF_METRICS: + if (!(kvm_caps.supported_perf_cap & PERF_CAP_PERF_METRICS)) + return; + break; case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + KVM_MAX_NR_GP_COUNTERS - 1: if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=3D diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 448044a2b121..f4d3801b97bc 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -806,9 +806,16 @@ static bool kvm_need_any_pmc_intercept(struct kvm_vcpu= *vcpu) pmu->nr_arch_fixed_counters !=3D kvm_host_pmu.num_counters_fixed; } =20 +static bool kvm_need_perf_metrics_intercept(struct kvm_vcpu *vcpu) +{ + return (kvm_host.perf_capabilities & PERF_CAP_PERF_METRICS) && + !kvm_vcpu_has_perf_metrics(vcpu); +} + bool kvm_need_perf_global_ctrl_intercept(struct kvm_vcpu *vcpu) { return kvm_need_any_pmc_intercept(vcpu) || + kvm_need_perf_metrics_intercept(vcpu) || !kvm_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu)); } EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_need_perf_global_ctrl_intercept); diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 82f955e5a450..be578013ed83 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -279,6 +279,11 @@ static inline u64 kvm_vcpu_get_perf_caps(struct kvm_vc= pu *vcpu) return vcpu->arch.perf_capabilities; } =20 +static inline bool kvm_vcpu_has_perf_metrics(struct kvm_vcpu *vcpu) +{ + return kvm_vcpu_get_perf_caps(vcpu) & PERF_CAP_PERF_METRICS; +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); int kvm_pmu_check_rdpmc_early(struct kvm_vcpu *vcpu, unsigned int idx); diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 0e5f4d7ce9eb..a1cf57c6bea1 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -724,6 +724,8 @@ static void nested_vmx_merge_pmu_msr_bitmaps(struct kvm= _vcpu *vcpu, nested_vmx_merge_msr_bitmaps_rw(MSR_CORE_PERF_GLOBAL_CTRL); nested_vmx_merge_msr_bitmaps_read(MSR_CORE_PERF_GLOBAL_STATUS); nested_vmx_merge_msr_bitmaps_write(MSR_CORE_PERF_GLOBAL_OVF_CTRL); + + nested_vmx_merge_msr_bitmaps_rw(MSR_PERF_METRICS); } =20 /* diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 28c1542e5ba5..fe66f03b006b 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -192,6 +192,8 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u= 32 msr) case MSR_CORE_PERF_GLOBAL_OVF_CTRL: case MSR_CORE_PERF_FIXED_CTR_CTRL: return kvm_pmu_has_perf_global_ctrl(pmu); + case MSR_PERF_METRICS: + return kvm_vcpu_has_perf_metrics(vcpu); case MSR_IA32_PEBS_ENABLE: ret =3D kvm_vcpu_get_perf_caps(vcpu) & PERF_CAP_PEBS_FORMAT; break; @@ -349,6 +351,9 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) case MSR_CORE_PERF_FIXED_CTR_CTRL: msr_info->data =3D pmu->fixed_ctr_ctrl; break; + case MSR_PERF_METRICS: + msr_info->data =3D pmu->perf_metrics; + break; case MSR_IA32_PEBS_ENABLE: msr_info->data =3D pmu->pebs_enable; break; @@ -398,6 +403,9 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) if (pmu->fixed_ctr_ctrl !=3D data) reprogram_fixed_counters(pmu, data); break; + case MSR_PERF_METRICS: + pmu->perf_metrics =3D data; + break; case MSR_IA32_PEBS_ENABLE: if (data & pmu->pebs_enable_rsvd) return 1; @@ -580,6 +588,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) counter_rsvd =3D ~((BIT_ULL(pmu->nr_arch_gp_counters) - 1) | ((BIT_ULL(pmu->nr_arch_fixed_counters) - 1) << KVM_FIXED_PMC_BASE_IDX)= ); pmu->global_ctrl_rsvd =3D counter_rsvd; + if (perf_capabilities & PERF_CAP_PERF_METRICS) + pmu->global_ctrl_rsvd &=3D ~GLOBAL_CTRL_EN_PERF_METRICS; =20 /* * GLOBAL_STATUS and GLOBAL_OVF_CONTROL (a.k.a. GLOBAL_STATUS_RESET) @@ -636,6 +646,9 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) =20 static void intel_pmu_reset(struct kvm_vcpu *vcpu) { + struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); + + pmu->perf_metrics =3D 0; intel_pmu_release_guest_lbr_event(vcpu); } =20 @@ -806,6 +819,9 @@ static void intel_mediated_pmu_load(struct kvm_vcpu *vc= pu) struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); u64 global_status, toggle; =20 + if (kvm_vcpu_has_perf_metrics(vcpu)) + wrmsrq(MSR_PERF_METRICS, pmu->perf_metrics); + rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, global_status); toggle =3D pmu->global_status ^ global_status; if (global_status & toggle) @@ -834,6 +850,19 @@ static void intel_mediated_pmu_put(struct kvm_vcpu *vc= pu) */ if (pmu->fixed_ctr_ctrl_hw) wrmsrq(MSR_CORE_PERF_FIXED_CTR_CTRL, 0); + + if (kvm_vcpu_has_perf_metrics(vcpu)) { + pmu->perf_metrics =3D rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); + /* + * The SDM requires restoring fixed counter 3 before + * PERF_METRICS. However, this path writes 0 to PERF_METRICS + * before fixed counter 3. For this all-zero case, the + * resulting hardware state is therefore the same regardless + * of write order. + */ + if (pmu->perf_metrics) + wrmsrq(MSR_PERF_METRICS, 0); + } } =20 struct kvm_pmu_ops intel_pmu_ops __initdata =3D { diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 715e44489e22..372de66365ab 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4289,6 +4289,10 @@ static void vmx_recalc_pmu_msr_intercepts(struct kvm= _vcpu *vcpu) MSR_TYPE_RW, intercept); vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, MSR_TYPE_RW, intercept); + + intercept =3D !has_mediated_pmu || !kvm_vcpu_has_perf_metrics(vcpu); + vmx_set_intercept_for_msr(vcpu, MSR_PERF_METRICS, + MSR_TYPE_RW, intercept); } =20 static void vmx_recalc_msr_intercepts(struct kvm_vcpu *vcpu) @@ -7994,6 +7998,9 @@ static __init u64 vmx_get_perf_capabilities(void) perf_cap &=3D ~PERF_CAP_PEBS_BASELINE; } =20 + if (enable_mediated_pmu) + perf_cap |=3D kvm_host.perf_capabilities & PERF_CAP_PERF_METRICS; + return perf_cap; } =20 --=20 2.55.0 From nobody Thu Sep 24 23:04:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B39E35237A1; Fri, 18 Sep 2026 19:50:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789761016; cv=none; b=i1yzX5sJ7s2aik/5ob/AgP2ksH4E6Q+U34SrmuvsJX6vpSixlkOHk1Pj4LKx59MdbD/y0baK5GQZAhcFIAyHo9jd4VzHuUlxTSmutc8oNAG9OsAiy+6kA3pK0E5FxwkvRE26iYjNMH/Rnw4MuN+9aBjvqUoYsplGr32XUryffVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789761016; c=relaxed/simple; bh=YeQrnXm/MpIrm1eB//WMGKQys/HDtcFhaBFrGisfMgs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HBddIOWo9Tx/91KQkUkahsjfdIq8tB3a4Ez2pD6nKzUhWLSuIa9PPLQMBeXw8B3xiuMnZ9AgNdwULmNxycqn+7qSLaUVE2xk/I6mbzBbjbj+M3QtWOAP0RZT5WOQK84HleGtkg9sAZbXom9xclmsC3G3Eem+Y0hPpzIcV6AAEBY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=S332o+C7; arc=none smtp.client-ip=192.198.163.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="S332o+C7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789761005; x=1821297005; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YeQrnXm/MpIrm1eB//WMGKQys/HDtcFhaBFrGisfMgs=; b=S332o+C7IeItsj0T8aSS+O1XjPF/iNPbfwKlIHDDyfDPTPERzpF/99ZA 4ohCSh6POw5+5cBhSlfcoVBsvcP6DuSPK19QTW4kvUgRyWITaar543+sL Hxts+y5ZvgRKiQRbHmOIzbfNHKzMgJ4nCe1eauzCxgADJQGE/aBlAJvpx ilgm/rusiPJ8DsVBt8539K1bMKp0QVLp7BT/0rMflss6GmC95teKdj0IJ jhvjAUpZW5bgae3Gt6XmBGuIYBmlKSV6vIf1gFEhC8avIevdT3qhil5Bo xngTmg8HR3JbTHnYgYN4bFJkBWjiWjLrWvA2WD0kOY/5scS189RpDrTV9 Q==; X-CSE-ConnectionGUID: zYBOJH0sSDCGqTxpCtNhbg== X-CSE-MsgGUID: 9gtHUyMqSDO0WoUfFGgXsg== X-IronPort-AV: E=McAfee;i="6800,10657,11909"; a="790323" X-IronPort-AV: E=Sophos;i="6.27,109,1787036400"; d="scan'208";a="790323" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa115.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 12:50:00 -0700 X-CSE-ConnectionGUID: YaIpM4s5QYKEPpg2rV7GEg== X-CSE-MsgGUID: 68etZKu0TVmakTEdLgXDrA== X-ExtLoop1: 1 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 12:50:00 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v9 06/12] KVM: x86/pmu: Move RDPMC emulation into per-vendor callbacks Date: Fri, 18 Sep 2026 12:39:31 -0700 Message-ID: <20260918193937.569414-7-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260918193937.569414-1-zide.chen@intel.com> References: <20260918193937.569414-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current RDPMC emulation splits responsibility: rdpmc_ecx_to_pmc() in each vendor returns a kvm_pmc, then common code calls pmc_read_counter(). This design cannot support RDPMC reads that don't map to a counter, such as PERF_METRICS on Intel platforms. Replace rdpmc_ecx_to_pmc() with emulate_rdpmc(), which takes full ownership of the emulation and writes the result directly into @data. Opportunistically drop the redundant bitmask in intel_emulate_rdpmc() since pmc_read_counter() already applies the counter's bit-width mask. No functional change intended. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi Reviewed-by: Jim Mattson Reviewed-by: Sandipan Das --- v6: new patch. --- arch/x86/include/asm/kvm-x86-pmu-ops.h | 2 +- arch/x86/kvm/pmu.c | 9 +-------- arch/x86/kvm/pmu.h | 4 ++-- arch/x86/kvm/svm/pmu.c | 13 +++++++++---- arch/x86/kvm/vmx/pmu_intel.c | 25 ++++++++++++------------- 5 files changed, 25 insertions(+), 28 deletions(-) diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/= kvm-x86-pmu-ops.h index 4a223c2793e3..4b50ed058aed 100644 --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h @@ -13,7 +13,7 @@ * KVM_X86_PMU_OP_OPTIONAL() can be used for those functions that can have * a NULL definition. */ -KVM_X86_PMU_OP(rdpmc_ecx_to_pmc) +KVM_X86_PMU_OP(emulate_rdpmc) KVM_X86_PMU_OP(msr_idx_to_pmc) KVM_X86_PMU_OP_OPTIONAL(check_rdpmc_early) KVM_X86_PMU_OP(is_valid_msr) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index f4d3801b97bc..897c1428b650 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -768,8 +768,6 @@ static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu, = unsigned idx, u64 *data) int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data) { struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); - struct kvm_pmc *pmc; - u64 mask =3D ~0ull; =20 if (!pmu->version) return 1; @@ -777,17 +775,12 @@ int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx= , u64 *data) if (is_vmware_backdoor_pmc(idx)) return kvm_pmu_rdpmc_vmware(vcpu, idx, data); =20 - pmc =3D kvm_pmu_call(rdpmc_ecx_to_pmc)(vcpu, idx, &mask); - if (!pmc) - return 1; - if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCE) && (kvm_x86_call(get_cpl)(vcpu) !=3D 0) && kvm_is_cr0_bit_set(vcpu, X86_CR0_PE)) return 1; =20 - *data =3D pmc_read_counter(pmc) & mask; - return 0; + return kvm_pmu_call(emulate_rdpmc)(vcpu, idx, data); } =20 static bool kvm_need_any_pmc_intercept(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index be578013ed83..eb6bbc658f5b 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -24,8 +24,8 @@ #define KVM_FIXED_PMC_BASE_IDX INTEL_PMC_IDX_FIXED =20 struct kvm_pmu_ops { - struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, - unsigned int idx, u64 *mask); + int (*emulate_rdpmc)(struct kvm_vcpu *vcpu, unsigned int idx, + u64 *data); struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr); int (*check_rdpmc_early)(struct kvm_vcpu *vcpu, unsigned int idx); bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr); diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index c18286545a7a..0517fd4bbcd7 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -84,10 +84,15 @@ static int amd_check_rdpmc_early(struct kvm_vcpu *vcpu,= unsigned int idx) } =20 /* idx is the ECX register of RDPMC instruction */ -static struct kvm_pmc *amd_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, - unsigned int idx, u64 *mask) +static int amd_emulate_rdpmc(struct kvm_vcpu *vcpu, unsigned int idx, u64 = *data) { - return amd_pmu_get_pmc(vcpu_to_pmu(vcpu), idx); + struct kvm_pmc *pmc =3D amd_pmu_get_pmc(vcpu_to_pmu(vcpu), idx); + + if (!pmc) + return 1; + + *data =3D pmc_read_counter(pmc); + return 0; } =20 static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) @@ -302,7 +307,7 @@ static bool amd_pmc_is_disabled_in_current_mode(struct = kvm_pmc *pmc) } =20 struct kvm_pmu_ops amd_pmu_ops __initdata =3D { - .rdpmc_ecx_to_pmc =3D amd_rdpmc_ecx_to_pmc, + .emulate_rdpmc =3D amd_emulate_rdpmc, .msr_idx_to_pmc =3D amd_msr_idx_to_pmc, .check_rdpmc_early =3D amd_check_rdpmc_early, .is_valid_msr =3D amd_is_valid_msr, diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index fe66f03b006b..2eb1bff75e60 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -85,14 +85,13 @@ static void reprogram_fixed_counters(struct kvm_pmu *pm= u, u64 data) } } =20 -static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, - unsigned int idx, u64 *mask) +static int intel_emulate_rdpmc(struct kvm_vcpu *vcpu, unsigned int idx, + u64 *data) { unsigned int type =3D idx & INTEL_RDPMC_TYPE_MASK; struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); - struct kvm_pmc *counters; + struct kvm_pmc *counters, *pmc; unsigned int num_counters; - u64 bitmask; =20 /* * The encoding of ECX for RDPMC is different for architectural versus @@ -105,7 +104,9 @@ static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct kv= m_vcpu *vcpu, * as KVM doesn't support such PMUs. */ if (WARN_ON_ONCE(!pmu->version)) - return NULL; + return 1; + + idx &=3D INTEL_RDPMC_INDEX_MASK; =20 /* * General Purpose (GP) PMCs are supported on all PMUs, and fixed PMCs @@ -119,23 +120,21 @@ static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct = kvm_vcpu *vcpu, case INTEL_RDPMC_FIXED: counters =3D pmu->fixed_counters; num_counters =3D pmu->nr_arch_fixed_counters; - bitmask =3D pmu->counter_bitmask[KVM_PMC_FIXED]; break; case INTEL_RDPMC_GP: counters =3D pmu->gp_counters; num_counters =3D pmu->nr_arch_gp_counters; - bitmask =3D pmu->counter_bitmask[KVM_PMC_GP]; break; default: - return NULL; + return 1; } =20 - idx &=3D INTEL_RDPMC_INDEX_MASK; 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charset="utf-8" If the host has the PERF_METRICS capability but it's not present on the guest, RDPMC interception must be enabled and KVM should inject an #GP when the guest attempts a PERF_METRICS RDPMC. If the guest has PERF_METRICS but RDPMC interception is enabled for other reasons, KVM needs to emulate RDPMC with type 0x2000. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- v9: - Remove references to Metrics Clear from the changelog. v8: - Move kvm_need_perf_metrics_intercept() to patch 5/9. --- arch/x86/kvm/pmu.c | 1 + arch/x86/kvm/vmx/pmu_intel.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 897c1428b650..0df283a169b6 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -825,6 +825,7 @@ bool kvm_need_rdpmc_intercept(struct kvm_vcpu *vcpu) return true; =20 return kvm_need_any_pmc_intercept(vcpu) || + kvm_need_perf_metrics_intercept(vcpu) || pmu->counter_bitmask[KVM_PMC_GP] !=3D (BIT_ULL(kvm_host_pmu.bit_wi= dth_gp) - 1) || pmu->counter_bitmask[KVM_PMC_FIXED] !=3D (BIT_ULL(kvm_host_pmu.bit= _width_fixed) - 1); } diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 2eb1bff75e60..fab0891ad46a 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -31,6 +31,7 @@ */ #define INTEL_RDPMC_GP 0 #define INTEL_RDPMC_FIXED INTEL_PMC_FIXED_RDPMC_BASE +#define INTEL_RDPMC_METRICS INTEL_PMC_FIXED_RDPMC_METRICS =20 #define INTEL_RDPMC_TYPE_MASK GENMASK(31, 16) #define INTEL_RDPMC_INDEX_MASK GENMASK(15, 0) @@ -125,6 +126,19 @@ static int intel_emulate_rdpmc(struct kvm_vcpu *vcpu, = unsigned int idx, counters =3D pmu->gp_counters; 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18 Sep 2026 12:50:00 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v9 08/12] KVM: selftests: Add PERF_METRICS and fixed counter 3 tests Date: Fri, 18 Sep 2026 12:39:33 -0700 Message-ID: <20260918193937.569414-9-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260918193937.569414-1-zide.chen@intel.com> References: <20260918193937.569414-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a test case to exercise IA32_PERF_METRICS, i.e. architectural support for Topdown (TMA) Level 1 metrics, enumerated by IA32_PERF_CAPABILITIES[15]. Only check for non-zero metrics, as they are derived and depend on the workload, CPU model, and host scheduling, making precise expectations fragile. Extend the PMU selftest to cover Intel fixed counter 3 by bumping MAX_NR_FIXED_COUNTERS to 4 and validating basic functionality. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- v7: - Use RDPMC instead of RDMSR in PERF_METRICS sanity test. --- tools/arch/x86/include/asm/msr-index.h | 1 + tools/testing/selftests/kvm/include/x86/pmu.h | 3 + .../selftests/kvm/x86/pmu_counters_test.c | 97 ++++++++++++++++++- 3 files changed, 96 insertions(+), 5 deletions(-) diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/includ= e/asm/msr-index.h index 18c4be75e927..fdcaeb6c8352 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -331,6 +331,7 @@ #define PERF_CAP_PEBS_FORMAT 0xf00 #define PERF_CAP_FW_WRITES BIT_ULL(13) #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) +#define PERF_CAP_PERF_METRICS BIT_ULL(15) #define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ diff --git a/tools/testing/selftests/kvm/include/x86/pmu.h b/tools/testing/= selftests/kvm/include/x86/pmu.h index 608ed83d7c6a..6c19503e0bb7 100644 --- a/tools/testing/selftests/kvm/include/x86/pmu.h +++ b/tools/testing/selftests/kvm/include/x86/pmu.h @@ -52,6 +52,9 @@ /* Fixed PMC controls, Intel only. */ #define FIXED_PMC_GLOBAL_CTRL_ENABLE(_idx) BIT_ULL((32 + (_idx))) =20 +/* PERF_METRICS enable, Intel only. */ +#define PERF_METRICS_GLOBAL_CTRL_ENABLE BIT_ULL(48) + #define FIXED_PMC_KERNEL BIT_ULL(0) #define FIXED_PMC_USER BIT_ULL(1) #define FIXED_PMC_ANYTHREAD BIT_ULL(2) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index c3e784e16348..cf09b587a4ac 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -3,6 +3,7 @@ * Copyright (C) 2023, Tencent, Inc. */ #include +#include =20 #include "pmu.h" #include "processor.h" @@ -254,17 +255,20 @@ do { \ ); \ } while (0) =20 -#define GUEST_TEST_EVENT(_idx, _pmc, _pmc_msr, _ctrl_msr, _value, FEP) \ +#define GUEST_RUN_PAYLOAD(_ctrl_msr, _value, FEP) \ do { \ - wrmsr(_pmc_msr, 0); \ - \ if (this_cpu_has(X86_FEATURE_CLFLUSHOPT)) \ GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflushopt %[m]", FEP); \ else if (this_cpu_has(X86_FEATURE_CLFLUSH)) \ GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflush %[m]", FEP); \ else \ GUEST_MEASURE_EVENT(_ctrl_msr, _value, "nop", FEP); \ - \ +} while (0) + +#define GUEST_TEST_EVENT(_idx, _pmc, _pmc_msr, _ctrl_msr, _value, FEP) \ +do { \ + wrmsr(_pmc_msr, 0); \ + GUEST_RUN_PAYLOAD(_ctrl_msr, _value, FEP); \ guest_assert_event_count(_idx, _pmc, _pmc_msr); \ } while (0) =20 @@ -412,7 +416,7 @@ static void test_arch_events(u8 pmu_version, u64 perf_c= apabilities) * other than PMCs in the future. */ #define MAX_NR_GP_COUNTERS 8 -#define MAX_NR_FIXED_COUNTERS 3 +#define MAX_NR_FIXED_COUNTERS 4 =20 #define GUEST_ASSERT_PMC_MSR_ACCESS(insn, msr, expect_gp, vector) \ __GUEST_ASSERT(expect_gp ? vector =3D=3D GP_VECTOR : !vector, \ @@ -653,8 +657,85 @@ static void test_fixed_counters(u8 pmu_version, u64 pe= rf_capabilities) pmu_vm_free(vm, vcpus); } =20 +static void __guest_test_perf_metrics(void) +{ + int retiring, bad_spec, fe_bound, be_bound, sum; + u64 global_ctrl, metrics; + + if ((guest_get_pmu_version() < 2) || /* Does guest have GLOBAL_CTRL? */ + !this_cpu_has(X86_FEATURE_PDCM) || + !(rdmsr(MSR_IA32_PERF_CAPABILITIES) & PERF_CAP_PERF_METRICS)) + return; + + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + wrmsr(MSR_CORE_PERF_FIXED_CTR3, 0); + wrmsr(MSR_PERF_METRICS, 0); + + /* Enable fixed ctr3 (TOPDOWN.SLOTS) and PERF_METRICS. */ + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(3, FIXED_PMC_KERNEL)); + global_ctrl =3D FIXED_PMC_GLOBAL_CTRL_ENABLE(3) | + PERF_METRICS_GLOBAL_CTRL_ENABLE; + + GUEST_RUN_PAYLOAD(MSR_CORE_PERF_GLOBAL_CTRL, global_ctrl, ""); + + /* Check test results. */ + metrics =3D rdmsr(MSR_PERF_METRICS); + retiring =3D FIELD_GET(GENMASK_ULL(7, 0), metrics); + bad_spec =3D FIELD_GET(GENMASK_ULL(15, 8), metrics); + fe_bound =3D FIELD_GET(GENMASK_ULL(23, 16), metrics); + be_bound =3D FIELD_GET(GENMASK_ULL(31, 24), metrics); + + /* + * Be conservative: the measured payload definitely retires work, so + * Retiring should be non-zero. + */ + GUEST_ASSERT_NE(metrics, 0); + GUEST_ASSERT_NE(retiring, 0); + + /* + * Each level-1 Topdown metric is an integer fraction of 0xff. + * A +/-3 error margin is chosen for a loose sanity check. + */ + sum =3D retiring + bad_spec + fe_bound + be_bound; + GUEST_ASSERT(sum >=3D 0xfc && sum <=3D 0x102); + + /* + * Burn some cycles; MSR_CORE_PERF_GLOBAL_CTRL is left zeroed after + * GUEST_RUN_PAYLOAD() returns, so PERF_METRICS is not counting. + */ + __asm__ __volatile__("loop ." : "+c"((int){NUM_LOOPS})); + /* Confirm PERF_METRICS did not advance while counting was disabled. */ + GUEST_ASSERT_EQ(rdmsr(MSR_PERF_METRICS), metrics); + wrmsr(MSR_PERF_METRICS, 0xdeaddead); + + guest_test_rdpmc(INTEL_RDPMC_METRICS, true, 0xdeaddead); +} + +static void guest_test_perf_metrics(void) +{ + __guest_test_perf_metrics(); + GUEST_DONE(); +} + +static void test_perf_metrics(u8 pmu_version, u64 perf_capabilities) +{ + struct kvm_vcpu **vcpus; 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charset="utf-8" Replace the hard coded field width (8) and the equivalent 0xff mask used for PERF_METRICS MSR field access with named constants INTEL_TD_METRIC_FIELD_{BITS,MASK}. INTEL_TD_METRIC_FIELD_BITS will be used by a subsequent KVM patch to validat reserved bits in the PERF_METRICS MSR. No functional change intended. Signed-off-by: Zide Chen Cc: Peter Zijlstra --- v9: new patch. --- arch/x86/events/intel/core.c | 8 +++++--- arch/x86/include/asm/perf_event.h | 4 ++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index cc13164d948f..cbc9a179f2e5 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3159,6 +3159,7 @@ DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period= , x86_perf_event_set_period =20 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int i= dx) { + int shift =3D (idx - INTEL_PMC_IDX_METRIC_BASE) * INTEL_TD_METRIC_FIELD_B= ITS; u32 val; =20 /* @@ -3166,8 +3167,8 @@ static inline u64 icl_get_metrics_event_value(u64 met= ric, u64 slots, int idx) * summing up to 0xff. * slots-in-metric =3D (Metric / 0xff) * slots */ - val =3D (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; - return mul_u64_u32_div(slots, val, 0xff); + val =3D (metric >> shift) & INTEL_TD_METRIC_FIELD_MASK; + return mul_u64_u32_div(slots, val, INTEL_TD_METRIC_FIELD_MASK); } =20 static u64 icl_get_topdown_value(struct perf_event *event, @@ -4742,7 +4743,8 @@ static int core_pmu_hw_config(struct perf_event *even= t) } =20 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ - ((x86_pmu.num_topdown_events - 1) << 8)) + ((x86_pmu.num_topdown_events - 1) << \ + INTEL_TD_METRIC_FIELD_BITS)) =20 static bool is_available_metric_event(struct perf_event *event) { diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 1eb13673e889..ceb6188e5217 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -418,6 +418,10 @@ static inline bool use_fixed_pseudo_encoding(u64 code) #define INTEL_TD_METRIC_MAX INTEL_TD_METRIC_MEM_BOUND #define INTEL_TD_METRIC_NUM 8 =20 +/* Width, in bits, of each metric's field within the PERF_METRICS MSR. */ +#define INTEL_TD_METRIC_FIELD_BITS 8 +#define INTEL_TD_METRIC_FIELD_MASK GENMASK_ULL(INTEL_TD_METRIC_FIELD_BITS= - 1, 0) + #define INTEL_TD_CFG_METRIC_CLEAR_BIT 0 #define INTEL_TD_CFG_METRIC_CLEAR BIT_ULL(INTEL_TD_CFG_METRIC_CLEAR_BIT) =20 --=20 2.55.0 From nobody Thu Sep 24 23:04:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99E6C522EEA; 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a="790330" X-IronPort-AV: E=Sophos;i="6.27,109,1787036400"; d="scan'208";a="790330" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa115.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 12:50:01 -0700 X-CSE-ConnectionGUID: i9h21FlWQ0CzKb85vVMmLQ== X-CSE-MsgGUID: y1zCjMv8QnOiwnBRUNZjIw== X-ExtLoop1: 1 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 12:50:01 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v9 10/12] perf/x86: Expose number of Topdown metric events to KVM Date: Fri, 18 Sep 2026 12:39:35 -0700 Message-ID: <20260918193937.569414-11-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260918193937.569414-1-zide.chen@intel.com> References: <20260918193937.569414-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The number of Topdown metric events varies by CPU: ICL/TGL/RKL support 4, while SPR/GNR/DMR and some hybrid CPUs support 8. Add num_topdown_events to struct x86_pmu_capability and populate it in perf_get_x86_pmu_capability() so that KVM can determine how many PERF_METRICS fields are valid on the host CPU and correctly identify the reserved bits in IA32_PERF_METRICS. Signed-off-by: Zide Chen Cc: Peter Zijlstra --- v9: new patch --- arch/x86/events/core.c | 1 + arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 8b3ea0adb965..01c1c9447f30 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -3164,6 +3164,7 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capab= ility *cap) cap->events_mask_len =3D x86_pmu.events_mask_len; cap->pebs_ept =3D x86_pmu.pebs_ept; cap->mediated =3D !!(pmu.capabilities & PERF_PMU_CAP_MEDIATED_VPMU); + cap->num_topdown_events =3D x86_pmu.num_topdown_events; } EXPORT_SYMBOL_FOR_KVM(perf_get_x86_pmu_capability); =20 diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index ceb6188e5217..3c02389b2ea6 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -306,6 +306,7 @@ struct x86_pmu_capability { int bit_width_fixed; unsigned int events_mask; int events_mask_len; + int num_topdown_events; unsigned int pebs_ept :1; unsigned int mediated :1; }; --=20 2.55.0 From nobody Thu Sep 24 23:04:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73C25522F18; Fri, 18 Sep 2026 19:50:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789761020; cv=none; b=gDR7yjqkKd1X/UgtMGyagM2O17FroXlQOfnzKJ90uN0uTXZ6pU6lvsl3cquJZc3ElP7v5e/xtqPVBKcMnAY4Pug5x1UErdQU0ghl/USGILAu+UUmuIGBNmtwMOeni+gm0un8StWmDr8oFnbwn0HEecdq2eNCai5fqQCVJUzH/Q4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789761020; c=relaxed/simple; bh=ysWbtPoovnUUuEs7ePCxtRTEHCH8yywg1iONeXDgVNA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UyIcMdy3IepokHGvB3qVUtZIh8LkIKDXkM8N8U7v940kP6JWULG8oIeVTSqvLQODPfOyX+88LsG5T7lZ0IgBfHUJTejo8YOJS+z0PyPnDa1ySSdGEYO/vOHRQ/bqKRKPc0tve1zjcHiA8Z2arwOBmp+pwZ6Vv/HbStqsFfbwhTw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XlRnwkUp; arc=none smtp.client-ip=192.198.163.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XlRnwkUp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789761019; x=1821297019; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ysWbtPoovnUUuEs7ePCxtRTEHCH8yywg1iONeXDgVNA=; b=XlRnwkUpxD6ZVBT+UgO3p/g01e27hMCKLl2yfu+YwbbXhYrgL2ziS7hr pTUcqdT1c1H124zhWE9G+vMpMoADnLTjrwiJnCFbFQziQ6ZOL2TKYo4E0 LQMmeowFAFw1gJiyDl1CK4KHx50fN1Cgs8ZM6/RGS5qHmHBUsW/T8zXan /Ou9WPbh9xIauFW8oXA1CyU7vRYONDOpbSiShPVm6VZwHZgSxRQD4WuzA yoDj5KtaHTCQqi8bZuvQghbeWZX2jsF77+xZjjUBRPrI2T70oeHhLGHEI voh0q9fIEE7lhPJRQbDSZtb2DNZczoJrUXIxDJBHyEZiX+KPFCIOiXsa5 w==; X-CSE-ConnectionGUID: gLNTKs+gQoCxlYCEiBjGTg== X-CSE-MsgGUID: Wqzjnuh9Tl60enPuogfjEQ== X-IronPort-AV: E=McAfee;i="6800,10657,11909"; a="790332" X-IronPort-AV: E=Sophos;i="6.27,109,1787036400"; d="scan'208";a="790332" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa115.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 12:50:01 -0700 X-CSE-ConnectionGUID: JZhBiKOVSQKIavqHcxGkPQ== X-CSE-MsgGUID: O2LyjqwqRgyb4l78uQH86g== X-ExtLoop1: 1 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 12:50:01 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v9 11/12] KVM: x86/pmu: Reject writes to reserved MSR_PERF_METRICS bits Date: Fri, 18 Sep 2026 12:39:36 -0700 Message-ID: <20260918193937.569414-12-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260918193937.569414-1-zide.chen@intel.com> References: <20260918193937.569414-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the host CPU supports only 4 Topdown metrics, bits [63:32] of MSR_PERF_METRICS are reserved. Derive pmu->perf_metrics_rsvd from the number of supported Topdown metrics and use it to validate writes. Reject any attempts to set reserved bits in MSR_PERF_METRICS. Signed-off-by: Zide Chen --- v9: new patch. --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/pmu.c | 1 + arch/x86/kvm/vmx/pmu_intel.c | 18 +++++++++++++++++- 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 052bf377dedb..31454ecee371 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -585,6 +585,7 @@ struct kvm_pmu { u64 reserved_bits; u64 raw_event_mask; u64 perf_metrics; + u64 perf_metrics_rsvd; struct kvm_pmc gp_counters[KVM_MAX_NR_GP_COUNTERS]; struct kvm_pmc fixed_counters[KVM_MAX_NR_FIXED_COUNTERS]; =20 diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 0df283a169b6..41f2d31c495f 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -1006,6 +1006,7 @@ void kvm_pmu_refresh(struct kvm_vcpu *vcpu) pmu->fixed_ctr_ctrl_rsvd =3D ~0ull; pmu->pebs_enable_rsvd =3D ~0ull; pmu->pebs_data_cfg_rsvd =3D ~0ull; + pmu->perf_metrics_rsvd =3D ~0ull; bitmap_zero(pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX); =20 if (!vcpu->kvm->arch.enable_pmu) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index fab0891ad46a..98e2fb80347a 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -417,6 +417,9 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) reprogram_fixed_counters(pmu, data); break; case MSR_PERF_METRICS: + if (data & pmu->perf_metrics_rsvd) + return 1; + pmu->perf_metrics =3D data; break; case MSR_IA32_PEBS_ENABLE: @@ -601,9 +604,22 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) counter_rsvd =3D ~((BIT_ULL(pmu->nr_arch_gp_counters) - 1) | ((BIT_ULL(pmu->nr_arch_fixed_counters) - 1) << KVM_FIXED_PMC_BASE_IDX)= ); pmu->global_ctrl_rsvd =3D counter_rsvd; - if (perf_capabilities & PERF_CAP_PERF_METRICS) + if (perf_capabilities & PERF_CAP_PERF_METRICS) { pmu->global_ctrl_rsvd &=3D ~GLOBAL_CTRL_EN_PERF_METRICS; =20 + /* + * PERF_METRICS has one 8-bit field per metric. At 8 metrics, + * skip computing the mask and set perf_metrics_rsvd to 0 + * directly, since BIT_ULL(64) is undefined. + */ + if (kvm_pmu_cap.num_topdown_events < INTEL_TD_METRIC_NUM) + pmu->perf_metrics_rsvd =3D + ~(BIT_ULL(kvm_pmu_cap.num_topdown_events * + INTEL_TD_METRIC_FIELD_BITS) - 1); + else + pmu->perf_metrics_rsvd =3D 0; + } + /* * GLOBAL_STATUS and GLOBAL_OVF_CONTROL (a.k.a. GLOBAL_STATUS_RESET) * share reserved bit definitions. The kernel just happens to use --=20 2.55.0 From nobody Thu Sep 24 23:04:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B852E522EF7; Fri, 18 Sep 2026 19:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789761022; cv=none; b=PsCLkURBIX7G6R6e8jww4FYdxx4DmeVUsxH/CeRrNDIwsqv9k6KG0rxB/tTA2jwMqNbojW+63WGZMXsG7o8AdC/7f+MZNWHtqSQwm3WG0G2O65kHJhzYse7SrEekxxkYEWQoXvlJO4f6ArzXw+27EHeNn9Pc+PUPvYvVl8lhBak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789761022; c=relaxed/simple; bh=q/Ylq4VOuCweW7soP1rWHUekmtQBs+CbvU+5Fa4f/2Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KJjEb59fkNZWnFexHln41K5tvp20ZzQmm9l3u07YPT7U01vWjSUnxRcz5vBYUDwdE3ClULXJOw5xnto13unNKbnOldTO159FPGvCPYIY9S758BSxYLB1W3pUi3BQ3jTCJcbl4TyObDSQjyHOMEPUxr5nVYZYAbhLMJzBHkYl2Ig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L+IzvDP+; arc=none smtp.client-ip=192.198.163.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L+IzvDP+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789761019; x=1821297019; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=q/Ylq4VOuCweW7soP1rWHUekmtQBs+CbvU+5Fa4f/2Y=; b=L+IzvDP+64xqBDcFDcaIgbBYaAb7GE3txDt+rvbz2Fw8jQjCGXOTLO11 bE6cUYqy7RRT/TO8NEfjbj3+TUinCQ378JgACwokkL30fZPYvX/8NE+Sx gZDU0Dqzbg2mFj2hWVJVWlgspYEfYAmFD95TAynOlY66qeQC3zkm0h9SM d46eKBZBXuhHu6vlTp10WrHLf/23tKtL2b5Qv/NYDCbd9HHnVQiFXe0ZX Tz8bsawlbHa7khqBxFoVzYy+T3ytz8QLviuEIYmXMqf9VjrFfniBS97Qm x7Dbc4uzbPU9FC6jM7XnGxdw6tj05IcTpTwQUIZUH38bRNgWtnMpFzfGF Q==; X-CSE-ConnectionGUID: EFOJSXWuR8GBAKsK6Vi81w== X-CSE-MsgGUID: 19Rlvo+jQEOO00cLw/UswQ== X-IronPort-AV: E=McAfee;i="6800,10657,11909"; a="790333" X-IronPort-AV: E=Sophos;i="6.27,109,1787036400"; d="scan'208";a="790333" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa115.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 12:50:01 -0700 X-CSE-ConnectionGUID: NknVs8TMQL6MCSMaaEWtog== X-CSE-MsgGUID: p02D6JC6TaiFIJ18DxJ8+A== X-ExtLoop1: 1 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 12:50:01 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v9 12/12] KVM: x86/pmu: Support RDPMC Metrics Clear Mode Date: Fri, 18 Sep 2026 12:39:37 -0700 Message-ID: <20260918193937.569414-13-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260918193937.569414-1-zide.chen@intel.com> References: <20260918193937.569414-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PERF_CAP_RDPMC_METRICS_CLEAR (IA32_PERF_CAPABILITIES bit 19) support. When set, and IA32_FIXED_CTR_CTRL.METRICS_CLEAR_EN (bit 14) is also set, RDPMC of PERF_METRICS clears both PERF_METRICS and fixed counter 3 (SLOTS) after the read. Advertise the capability to guests only when the mediated PMU is enabled and the host reports it. Unmask FIXED_CTR_CTRL bit 14 in intel_pmu_refresh(), scoped to fixed counter 3 only via intel_fixed_bits_by_idx(). For the mediated PMU, METRICS_CLEAR_EN takes effect natively via passthrough. But kvm_need_rdpmc_intercept() can still force interception for unrelated reasons, so intel_emulate_rdpmc() also replicates the clear-on-read behavior for consistency. Signed-off-by: Zide Chen --- v9: new patch. --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kvm/vmx/pmu_intel.c | 28 ++++++++++++++++++++++++++++ arch/x86/kvm/vmx/vmx.c | 6 +++++- 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 8fad944197fb..5851edcdda05 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -333,6 +333,7 @@ #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) #define PERF_CAP_PERF_METRICS BIT_ULL(15) #define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) +#define PERF_CAP_RDPMC_METRICS_CLEAR BIT_ULL(19) #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ PERF_CAP_PEBS_TIMING_INFO) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 98e2fb80347a..3e5e8bae67ab 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -36,6 +36,9 @@ #define INTEL_RDPMC_TYPE_MASK GENMASK(31, 16) #define INTEL_RDPMC_INDEX_MASK GENMASK(15, 0) =20 +/* Index of the SLOTS fixed counter relative to the first fixed counter. */ +#define INTEL_FIXED_SLOTS_IDX (INTEL_PMC_IDX_FIXED_SLOTS - INTEL_PMC_IDX_F= IXED) + #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0) =20 static struct lbr_desc *vcpu_to_lbr_desc(struct kvm_vcpu *vcpu) @@ -86,6 +89,14 @@ static void reprogram_fixed_counters(struct kvm_pmu *pmu= , u64 data) } } =20 +static bool intel_pmu_metrics_clear_enabled(struct kvm_pmu *pmu) +{ + u8 fixed_ctr_ctrl =3D fixed_ctrl_field(pmu->fixed_ctr_ctrl, + INTEL_FIXED_SLOTS_IDX); + + return fixed_ctr_ctrl & INTEL_FIXED_3_METRICS_CLEAR; +} + static int intel_emulate_rdpmc(struct kvm_vcpu *vcpu, unsigned int idx, u64 *data) { @@ -138,6 +149,18 @@ static int intel_emulate_rdpmc(struct kvm_vcpu *vcpu, = unsigned int idx, return 1; =20 *data =3D pmu->perf_metrics; + + /* + * Per the SDM, RDPMC of PERF_METRICS clears both PERF_METRICS + * and the SLOTS fixed counter when Metrics Clear Mode is + * enabled via INTEL_FIXED_3_METRICS_CLEAR in FIXED_CTR_CTRL. + */ + pmc =3D kvm_pmc_idx_to_pmc(pmu, INTEL_PMC_IDX_FIXED_SLOTS); + if (pmc && intel_pmu_metrics_clear_enabled(pmu)) { + pmu->perf_metrics =3D 0; + pmc_write_counter(pmc, 0); + } + return 0; default: return 1; @@ -601,6 +624,11 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) INTEL_FIXED_0_USER | INTEL_FIXED_0_ENABLE_PMI); =20 + if (perf_capabilities & PERF_CAP_RDPMC_METRICS_CLEAR) + pmu->fixed_ctr_ctrl_rsvd &=3D + ~intel_fixed_bits_by_idx(INTEL_FIXED_SLOTS_IDX, + INTEL_FIXED_3_METRICS_CLEAR); + counter_rsvd =3D ~((BIT_ULL(pmu->nr_arch_gp_counters) - 1) | ((BIT_ULL(pmu->nr_arch_fixed_counters) - 1) << KVM_FIXED_PMC_BASE_IDX)= ); pmu->global_ctrl_rsvd =3D counter_rsvd; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 372de66365ab..df02372c70e3 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2616,6 +2616,9 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_dat= a *msr_info) if (!cpuid_model_is_consistent(vcpu)) return 1; } + if ((data & PERF_CAP_RDPMC_METRICS_CLEAR) && + !(data & PERF_CAP_PERF_METRICS)) + return 1; ret =3D kvm_set_msr_common(vcpu, msr_info); break; =20 @@ -7999,7 +8002,8 @@ static __init u64 vmx_get_perf_capabilities(void) } =20 if (enable_mediated_pmu) - perf_cap |=3D kvm_host.perf_capabilities & PERF_CAP_PERF_METRICS; + perf_cap |=3D kvm_host.perf_capabilities & + (PERF_CAP_PERF_METRICS | PERF_CAP_RDPMC_METRICS_CLEAR); =20 return perf_cap; } --=20 2.55.0