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Fri, 18 Sep 2026 10:57:47 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Jitao shi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/4] dt-bindings: display: mediatek: dpi: Add compatible for mt8167 Date: Fri, 18 Sep 2026 19:55:25 +0200 Message-ID: <20260918175736.355305-2-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918175736.355305-1-l.scorcia@gmail.com> References: <20260918175736.355305-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MediaTek mt8167 SoC has two Digital Parallel Interface (DPI) blocks, one can be routed to a DPI display while the other is wired to the HDMI block. They are not compatible with any other device, so add a new compatible to describe them in the device tree. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.ya= ml index eb4f276e8dc4..6cd96a5cd4ae 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -21,6 +21,7 @@ properties: - enum: - mediatek,mt2701-dpi - mediatek,mt7623-dpi + - mediatek,mt8167-dpi - mediatek,mt8173-dpi - mediatek,mt8183-dpi - mediatek,mt8186-dpi --=20 2.43.0 From nobody Fri Sep 25 00:01:58 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E7E647C0F1 for ; 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Fri, 18 Sep 2026 10:57:49 -0700 (PDT) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48724562aebsm268461f8f.14.2026.09.18.10.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 10:57:49 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Jitao shi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/4] drm/mediatek: Add support for mt8167 Digital Parallel Interface Date: Fri, 18 Sep 2026 19:55:26 +0200 Message-ID: <20260918175736.355305-3-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918175736.355305-1-l.scorcia@gmail.com> References: <20260918175736.355305-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the two DPI blocks found in the mt8167 SoCs. One of them can be routed to a DPI connector and another is directly connected to the HDMI IP. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 0e4f430de983..9012adeb63d0 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -1114,6 +1114,10 @@ static const struct mtk_dpi_factor dpi_factor_mt2701= [] =3D { { 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 } }; =20 +static const struct mtk_dpi_factor dpi_factor_mt8167[] =3D { + { 64000, 16 }, { 74250, 8 }, { 160000, 4 }, { U32_MAX, 2 } +}; + static const struct mtk_dpi_factor dpi_factor_mt8173[] =3D { { 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 } }; @@ -1163,6 +1167,24 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .csc_enable_bit =3D CSC_ENABLE, }; =20 +static const struct mtk_dpi_conf mt8167_conf =3D { + .dpi_factor =3D dpi_factor_mt8167, + .num_dpi_factor =3D ARRAY_SIZE(dpi_factor_mt8167), + .reg_h_fre_con =3D 0xe0, + .max_clock_khz =3D 150000, + .output_fmts =3D mt8173_output_fmts, + .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .pixels_per_iter =3D 1, + .is_ck_de_pol =3D true, + .swap_input_support =3D true, + .support_direct_pin =3D true, + .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, +}; + static const struct mtk_dpi_conf mt8183_conf =3D { .dpi_factor =3D dpi_factor_mt8183, .num_dpi_factor =3D ARRAY_SIZE(dpi_factor_mt8183), @@ -1342,6 +1364,7 @@ static void mtk_dpi_remove(struct platform_device *pd= ev) =20 static const struct of_device_id mtk_dpi_of_ids[] =3D { { .compatible =3D "mediatek,mt2701-dpi", .data =3D &mt2701_conf }, + { .compatible =3D "mediatek,mt8167-dpi", .data =3D &mt8167_conf }, { .compatible =3D "mediatek,mt8173-dpi", .data =3D &mt8173_conf }, { .compatible =3D "mediatek,mt8183-dpi", .data =3D &mt8183_conf }, { .compatible =3D "mediatek,mt8186-dpi", .data =3D &mt8186_conf }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index c86a3f54f35b..64c87221d931 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -802,6 +802,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8167-dsi", .data =3D (void *)MTK_DSI }, + { .compatible =3D "mediatek,mt8167-dpi", + .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8173-dpi", .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8183-dpi", --=20 2.43.0 From nobody Fri Sep 25 00:01:58 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D204D47534C for ; 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Fri, 18 Sep 2026 10:57:51 -0700 (PDT) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48724562aebsm268461f8f.14.2026.09.18.10.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 10:57:50 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Jitao shi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/4] soc: mediatek: mt8167-mmsys: add routes for all display paths Date: Fri, 18 Sep 2026 19:55:27 +0200 Message-ID: <20260918175736.355305-4-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918175736.355305-1-l.scorcia@gmail.com> References: <20260918175736.355305-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mt8167 display output pipeline can be configured in many different ways. Add support for additional routes according to the SoC data sheet and Android sources. There's a few inconsistencies between those two, but assume the Android sources are correct since they are required to drive HDMI output via DPI1. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt8167-mmsys.h | 183 ++++++++++++++++++++++++++-- 1 file changed, 174 insertions(+), 9 deletions(-) diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8= 167-mmsys.h index 001379373507..aab1774152c5 100644 --- a/drivers/soc/mediatek/mt8167-mmsys.h +++ b/drivers/soc/mediatek/mt8167-mmsys.h @@ -5,35 +5,200 @@ =20 #define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x030 #define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN 0x038 +#define MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x03c #define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x058 +#define MT8167_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN 0x05c +#define MT8167_DISP_REG_CONFIG_DISP_UFOE_SEL_IN 0x060 #define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0x064 +#define MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0x068 #define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x06c +#define MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN 0x070 +#define MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN 0x074 + +#define MT8167_OVL0_MOUT_EN_COLOR0 0x1 +#define MT8167_OVL0_MOUT_EN_WDMA0 0x2 +#define MT8167_OVL0_MOUT_EN_MASK 0x3 =20 #define MT8167_DITHER_MOUT_EN_RDMA0 0x1 +#define MT8167_DITHER_MOUT_EN_UFOE 0x2 +#define MT8167_DITHER_MOUT_EN_WDMA0 0x4 #define MT8167_DITHER_MOUT_EN_MASK 0x7 =20 -#define MT8167_RDMA0_SOUT_DSI0 0x2 -#define MT8167_RDMA0_SOUT_MASK 0x3 +#define MT8167_UFOE_MOUT_EN_DSI0 0x1 +#define MT8167_UFOE_MOUT_EN_DPI0 0x2 +/* + * For some reason Android sources and the data sheet don't agree here, + * the data sheet has UFOE_MOUT_EN_WDMA0 as 0x4 and does not mention DPI1. + */ +#define MT8167_UFOE_MOUT_EN_DPI1 0x4 +#define MT8167_UFOE_MOUT_EN_WDMA0 0x8 +#define MT8167_UFOE_MOUT_EN_MASK 0xF + +#define MT8167_COLOR0_SEL_IN_RDMA0 0x0 +#define MT8167_COLOR0_SEL_IN_OVL0 0x1 +#define MT8167_COLOR0_SEL_IN_MASK 0x1 + +#define MT8167_WDMA0_SEL_IN_OVL0 0x0 +#define MT8167_WDMA0_SEL_IN_DITHER 0x1 +#define MT8167_WDMA0_SEL_IN_UFOE 0x2 +#define MT8167_WDMA0_SEL_IN_MASK 0x3 + +#define MT8167_UFOE_SEL_IN_RDMA0 0x0 +#define MT8167_UFOE_SEL_IN_DITHER 0x1 +#define MT8167_UFOE_SEL_IN_MASK 0x1 =20 +#define MT8167_DSI0_SEL_IN_UFOE 0x0 #define MT8167_DSI0_SEL_IN_RDMA0 0x1 +#define MT8167_DSI0_SEL_IN_RDMA1 0x2 #define MT8167_DSI0_SEL_IN_MASK 0x3 =20 +#define MT8167_DPI0_SEL_IN_UFOE 0x0 +#define MT8167_DPI0_SEL_IN_RDMA0 0x1 +#define MT8167_DPI0_SEL_IN_RDMA1 0x2 +#define MT8167_DPI0_SEL_IN_MASK 0x3 + +#define MT8167_DPI1_SEL_IN_UFOE 0x0 +#define MT8167_DPI1_SEL_IN_RDMA0 0x1 +#define MT8167_DPI1_SEL_IN_RDMA1 0x2 +#define MT8167_DPI1_SEL_IN_MASK 0x3 + +#define MT8167_RDMA0_SOUT_UFOE 0x0 +#define MT8167_RDMA0_SOUT_COLOR0 0x1 +#define MT8167_RDMA0_SOUT_DSI0 0x2 +#define MT8167_RDMA0_SOUT_DPI0 0x3 +/* DPI1 is only defined in Android sources, not in the data sheet */ +#define MT8167_RDMA0_SOUT_DPI1 0x4 +#define MT8167_RDMA0_SOUT_MASK 0x7 + +#define MT8167_RDMA1_SOUT_DSI0 0x0 +#define MT8167_RDMA1_SOUT_DPI0 0x1 +/* DPI1 is only defined in Android sources, not in the data sheet */ +#define MT8167_RDMA1_SOUT_DPI1 0x2 +#define MT8167_RDMA1_SOUT_MASK 0x3 + static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] =3D { + /* OVL0<->COLOR0 */ MMSYS_ROUTE(OVL, 0, COLOR, 0, - MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, - OVL0_MOUT_EN_COLOR0), + MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8167_OVL0_MOUT_EN_MASK, + MT8167_OVL0_MOUT_EN_COLOR0), + MMSYS_ROUTE(OVL, 0, COLOR, 0, + MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK, + MT8167_COLOR0_SEL_IN_OVL0), + + /* OVL0<->WDMA0 */ + MMSYS_ROUTE(OVL, 0, WDMA, 0, + MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8167_OVL0_MOUT_EN_MASK, + MT8167_OVL0_MOUT_EN_WDMA0), + MMSYS_ROUTE(OVL, 0, WDMA, 0, + MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK, + MT8167_WDMA0_SEL_IN_OVL0), + + /* DITHER0 outputs */ MMSYS_ROUTE(DITHER, 0, RDMA, 0, MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MA= SK, MT8167_DITHER_MOUT_EN_RDMA0), - MMSYS_ROUTE(OVL, 0, COLOR, 0, - MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0, - COLOR0_SEL_IN_OVL0), - MMSYS_ROUTE(RDMA, 0, DSI, 0, + MMSYS_ROUTE(DITHER, 0, UFOE, 0, + MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MA= SK, + MT8167_DITHER_MOUT_EN_UFOE), + MMSYS_ROUTE(DITHER, 0, WDMA, 0, + MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MA= SK, + MT8167_DITHER_MOUT_EN_WDMA0), + + /* UFOE<->DSI0 */ + MMSYS_ROUTE(UFOE, 0, DSI, 0, + MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK, + MT8167_UFOE_MOUT_EN_DSI0), + MMSYS_ROUTE(UFOE, 0, DSI, 0, MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK, - MT8167_DSI0_SEL_IN_RDMA0), + MT8167_DSI0_SEL_IN_UFOE), + + /* UFOE<->DPI0 */ + MMSYS_ROUTE(UFOE, 0, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK, + MT8167_UFOE_MOUT_EN_DPI0), + MMSYS_ROUTE(UFOE, 0, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK, + MT8167_DPI0_SEL_IN_UFOE), + + /* UFOE<->DPI1 */ + MMSYS_ROUTE(UFOE, 0, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK, + MT8167_UFOE_MOUT_EN_DPI1), + MMSYS_ROUTE(UFOE, 0, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK, + MT8167_DPI1_SEL_IN_UFOE), + + /* UFOE<->WDMA0 */ + MMSYS_ROUTE(UFOE, 0, WDMA, 0, + MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK, + MT8167_UFOE_MOUT_EN_WDMA0), + MMSYS_ROUTE(UFOE, 0, WDMA, 0, + MT8167_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN, MT8167_WDMA0_SEL_IN_MASK, + MT8167_WDMA0_SEL_IN_UFOE), + + /* RDMA0<->UFOE */ + MMSYS_ROUTE(RDMA, 0, UFOE, 0, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MAS= K, + MT8167_RDMA0_SOUT_UFOE), + MMSYS_ROUTE(RDMA, 0, UFOE, 0, + MT8167_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8167_UFOE_SEL_IN_MASK, + MT8167_UFOE_SEL_IN_RDMA0), + + /* RDMA0->COLOR0 */ + MMSYS_ROUTE(RDMA, 0, COLOR, 0, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MAS= K, + MT8167_RDMA0_SOUT_COLOR0), + MMSYS_ROUTE(RDMA, 0, COLOR, 0, + MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK, + MT8167_COLOR0_SEL_IN_RDMA0), + + /* RDMA0<->DSI0 */ MMSYS_ROUTE(RDMA, 0, DSI, 0, MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MAS= K, MT8167_RDMA0_SOUT_DSI0), + MMSYS_ROUTE(RDMA, 0, DSI, 0, + MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK, + MT8167_DSI0_SEL_IN_RDMA0), + + /* RDMA0<->DPI0 */ + MMSYS_ROUTE(RDMA, 0, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MAS= K, + MT8167_RDMA0_SOUT_DPI0), + MMSYS_ROUTE(RDMA, 0, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK, + MT8167_DPI0_SEL_IN_RDMA0), + + /* RDMA0<->DPI1 */ + MMSYS_ROUTE(RDMA, 0, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MAS= K, + MT8167_RDMA0_SOUT_DPI1), + MMSYS_ROUTE(RDMA, 0, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK, + MT8167_DPI1_SEL_IN_RDMA0), + + /* RDMA1<->DSI0 */ + MMSYS_ROUTE(RDMA, 1, DSI, 0, + MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MAS= K, + MT8167_RDMA1_SOUT_DSI0), + MMSYS_ROUTE(RDMA, 1, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK, + MT8167_DPI0_SEL_IN_RDMA1), + + /* RDMA1<->DPI0 */ + MMSYS_ROUTE(RDMA, 1, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MAS= K, + MT8167_RDMA1_SOUT_DPI0), + MMSYS_ROUTE(RDMA, 1, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK, + MT8167_DPI0_SEL_IN_RDMA1), + + /* RDMA1<->DPI1 */ + MMSYS_ROUTE(RDMA, 1, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MAS= K, + MT8167_RDMA1_SOUT_DPI1), + MMSYS_ROUTE(RDMA, 1, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK, + MT8167_DPI1_SEL_IN_RDMA1), }; =20 #endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */ 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devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/4] arm64: dts: mediatek: mt8167: Add DRM nodes Date: Fri, 18 Sep 2026 19:55:28 +0200 Message-ID: <20260918175736.355305-5-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918175736.355305-1-l.scorcia@gmail.com> References: <20260918175736.355305-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add all the DRM nodes required to get DSI and DPI to work on MT8167 SoC. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 369 +++++++++++++++++++++++ 1 file changed, 369 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts= /mediatek/mt8167.dtsi index 27cf32d7ae35..a50bae4307c1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -16,6 +16,22 @@ / { compatible =3D "mediatek,mt8167"; =20 + aliases { + aal0 =3D &aal; + ccorr0 =3D &ccorr; + color0 =3D &color; + dither0 =3D &dither; + dpi0 =3D &dpi0; + dpi1 =3D &dpi1; + dsi0 =3D &dsi; + gamma0 =3D γ + ovl0 =3D &ovl0; + pwm0 =3D &disp_pwm; + rdma0 =3D &rdma0; + rdma1 =3D &rdma1; + wdma0 =3D &wdma; + }; + soc { topckgen: topckgen@10000000 { compatible =3D "mediatek,mt8167-topckgen", "syscon"; @@ -120,10 +136,325 @@ iommu: m4u@10203000 { #iommu-cells =3D <1>; }; =20 + disp_pwm: pwm@1100f000 { + compatible =3D "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm"; + reg =3D <0 0x1100f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_PWM_26M>, <&mmsys CLK_MM_DISP_PWM_MM>; + clock-names =3D "main", "mm"; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + mmsys: syscon@14000000 { compatible =3D "mediatek,mt8167-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; #clock-cells =3D <1>; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mmsys_main: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_in>; + }; + + mmsys_ext: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&rdma1_in>; + }; + }; + }; + + ovl0: ovl0@14007000 { + compatible =3D "mediatek,mt8167-disp-ovl"; + reg =3D <0 0x14007000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_OVL0>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + ovl0_in: endpoint { + remote-endpoint =3D <&mmsys_main>; + }; + }; + + port@1 { + reg =3D <1>; + ovl0_out: endpoint { + remote-endpoint =3D <&color_in>; + }; + }; + }; + }; + + rdma0: rdma0@14009000 { + compatible =3D "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma"; + reg =3D <0 0x14009000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + rdma0_in: endpoint { + remote-endpoint =3D <&dither_out>; + }; + }; + + port@1 { + reg =3D <1>; + rdma0_out: endpoint { }; + }; + }; + }; + + rdma1: rdma1@1400a000 { + compatible =3D "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma"; + reg =3D <0 0x1400a000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + rdma1_in: endpoint { + remote-endpoint =3D <&mmsys_ext>; + }; + }; + + port@1 { + reg =3D <1>; + rdma1_out: endpoint { }; + }; + }; + }; + + wdma: wdma0@1400b000 { + compatible =3D "mediatek,mt8167-disp-wdma", "mediatek,mt8173-disp-wdma"; + reg =3D <0 0x1400b000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_WDMA>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_WDMA0>; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + }; + + color: color@1400c000 { + compatible =3D "mediatek,mt8167-disp-color"; + reg =3D <0 0x1400c000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_COLOR>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + color_in: endpoint { + remote-endpoint =3D <&ovl0_out>; + }; + }; + + port@1 { + reg =3D <1>; + color_out: endpoint { + remote-endpoint =3D <&ccorr_in>; + }; + }; + }; + }; + + ccorr: ccorr@1400d000 { + compatible =3D "mediatek,mt8167-disp-ccorr", "mediatek,mt8183-disp-ccor= r"; + reg =3D <0 0x1400d000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_CCORR>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + ccorr_in: endpoint { + remote-endpoint =3D <&color_out>; + }; + }; + + port@1 { + reg =3D <1>; + ccorr_out: endpoint { + remote-endpoint =3D <&aal_in>; + }; + }; + }; + }; + + aal: aal@1400e000 { + compatible =3D "mediatek,mt8167-disp-aal", "mediatek,mt8173-disp-aal"; + reg =3D <0 0x1400e000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_AAL>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + aal_in: endpoint { + remote-endpoint =3D <&ccorr_out>; + }; + }; + + port@1 { + reg =3D <1>; + aal_out: endpoint { + remote-endpoint =3D <&gamma_in>; + }; + }; + }; + }; + + gamma: gamma@1400f000 { + compatible =3D "mediatek,mt8167-disp-gamma", "mediatek,mt8173-disp-gamm= a"; + reg =3D <0 0x1400f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_GAMMA>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + gamma_in: endpoint { + remote-endpoint =3D <&aal_out>; + }; + }; + + port@1 { + reg =3D <1>; + gamma_out: endpoint { + remote-endpoint =3D <&dither_in>; + }; + }; + }; + }; + + dither: dither@14010000 { + compatible =3D "mediatek,mt8167-disp-dither", "mediatek,mt8183-disp-dit= her"; + reg =3D <0 0x14010000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_DITHER>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dither_in: endpoint { + remote-endpoint =3D <&gamma_out>; + }; + }; + + port@1 { + reg =3D <1>; + dither_out: endpoint { + remote-endpoint =3D <&rdma0_in>; + }; + }; + }; + }; + + dsi: dsi@14012000 { + compatible =3D "mediatek,mt8167-dsi"; + reg =3D <0 0x14012000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIGITAL>, + <&mipi_tx>; + clock-names =3D "engine", "digital", "hs"; + interrupts =3D ; + phys =3D <&mipi_tx>; + phy-names =3D "dphy"; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi_in: endpoint { }; + }; + + port@1 { + reg =3D <1>; + dsi_out: endpoint { }; + }; + }; + }; + + dpi0: dpi@14013000 { + compatible =3D "mediatek,mt8167-dpi"; + reg =3D <0 0x14013000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DPI0_PXL>, <&mmsys CLK_MM_DPI0_ENGINE>, + <&apmixedsys CLK_APMIXED_LVDSPLL>; + clock-names =3D "pixel", "engine", "pll"; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpi0_in: endpoint { }; + }; + + port@1 { + reg =3D <1>; + dpi0_out: endpoint { }; + }; + }; + }; + + mutex: mutex@14015000 { + compatible =3D "mediatek,mt8167-disp-mutex"; + reg =3D <0 0x14015000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; }; =20 larb0: larb@14016000 { @@ -145,6 +476,44 @@ smi_common: smi@14017000 { power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; }; =20 + mipi_tx: dsi-phy@14018000 { + compatible =3D "mediatek,mt8167-mipi-tx", "mediatek,mt2701-mipi-tx"; + reg =3D <0 0x14018000 0 0x90>; + clocks =3D <&topckgen CLK_TOP_MIPI_26M_DBG>; + clock-output-names =3D "mipi_tx0_pll"; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + dpi1: dpi1@14019000 { + compatible =3D "mediatek,mt8167-dpi"; + reg =3D <0 0x14019000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DPI1_PXL>, <&mmsys CLK_MM_DPI1_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names =3D "pixel", "engine", "pll"; + interrupts =3D ; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpi1_in: endpoint { }; + }; + + port@1 { + reg =3D <1>; + + dpi1_out: endpoint { }; + }; + }; + }; + imgsys: syscon@15000000 { compatible =3D "mediatek,mt8167-imgsys", "syscon"; reg =3D <0 0x15000000 0 0x1000>; --=20 2.43.0