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Fri, 18 Sep 2026 09:52:39 -0700 (PDT) From: Alex Elder To: sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, kees@kernel.org, gustavoars@kernel.org, p.zabel@pengutronix.de Cc: daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mfd@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: mfd: introduce the TC9564 config syscon Date: Fri, 18 Sep 2026 11:52:30 -0500 Message-ID: <20260918165234.687224-2-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260918165234.687224-1-elder@riscstar.com> References: <20260918165234.687224-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define the binding for a system controller used in the Toshiba TC9564 SoC. Co-developed-by: Daniel Thompson Signed-off-by: Daniel Thompson Signed-off-by: Alex Elder --- .../bindings/mfd/toshiba,tc9564.yaml | 56 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/toshiba,tc9564.ya= ml diff --git a/Documentation/devicetree/bindings/mfd/toshiba,tc9564.yaml b/Do= cumentation/devicetree/bindings/mfd/toshiba,tc9564.yaml new file mode 100644 index 0000000000000..32e73a727c82a --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/toshiba,tc9564.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/toshiba,tc9564.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC9564 System Controller + +maintainers: + - Alex Elder + - Daniel Thompson + +description: | + The Toshiba TC9564 is an SoC accessed by a host system through the + upstream PCIe port on the PCIe switch it implements. The switch includes + an embedded PCIe endpoint on one of its downstream ports that provides + access to various SoC peripherals (including a clock and reset controlle= r) + via one of its BARs. A system controller provides managed access to the + first two pages of this memory region to ensure accesses made by these + peripherals produce well-defined results. + +properties: + compatible: + items: + - const: toshiba,tc9564-config + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + syscon@0 { + compatible =3D "toshiba,tc9564-config", + "syscon", + "simple-mfd"; + reg =3D <0x0 0x2000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + }; diff --git a/MAINTAINERS b/MAINTAINERS index cf846853fdc79..b2d3257b8f892 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27674,6 +27674,7 @@ TOSHIBA TC9564 PCI DRIVER M: Alex Elder M: Daniel Thompson S: Maintained +F: Documentation/devicetree/bindings/mfd/toshiba,tc9564.yaml F: Documentation/devicetree/bindings/misc/pci1179,0220.yaml F: drivers/misc/tc9564-pci.c =20 --=20 2.53.0 From nobody Fri Sep 25 00:01:47 2026 Received: from mail-qv2-f12.google.com (mail-qv2-f12.google.com [74.125.230.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 431FC51A743 for ; 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Fri, 18 Sep 2026 09:52:41 -0700 (PDT) Received: from zippy.localdomain ([73.62.185.64]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93be0f0762dsm183582785a.39.2026.09.18.09.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 09:52:40 -0700 (PDT) From: Alex Elder To: sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, kees@kernel.org, gustavoars@kernel.org, p.zabel@pengutronix.de Cc: daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mfd@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml Date: Fri, 18 Sep 2026 11:52:31 -0500 Message-ID: <20260918165234.687224-3-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260918165234.687224-1-elder@riscstar.com> References: <20260918165234.687224-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define the binding for the clock controller functionality present in the Toshiba TC9564 SoC. Co-developed-by: Daniel Thompson Signed-off-by: Daniel Thompson Signed-off-by: Alex Elder --- .../bindings/clock/toshiba,tc9564-clock.yaml | 64 +++++++++++++++++++ MAINTAINERS | 7 ++ include/dt-bindings/clock/toshiba,tc9564.h | 54 ++++++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tc9564-= clock.yaml create mode 100644 include/dt-bindings/clock/toshiba,tc9564.h diff --git a/Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.y= aml b/Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml new file mode 100644 index 0000000000000..cc7019bd240e4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tc9564-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC9564 Clock and Reset Controller + +maintainers: + - Alex Elder + - Daniel Thompson + +description: | + The Toshiba TC9564 is an SoC accessed by a host system through the + upstream PCIe port on the PCIe switch it implements. The switch + includes an embedded PCIe endpoint that provides access to various + SoC peripherals (including a clock/reset controller) via its BARs. + + The SoC is represented using a devicetree PCI endpoint bus, so the + clock controller is bound to its driver using a platform driver + compatible string. All of the clocks are simple gate clocks. + + A total of 21 clocks are implemented, though two of these are not + controllable. Access to the clock controller relies on PCIe being + functional, so the PCIe clock is assumed to be always on. Similarly, + the PCIe controller relies on I2C, so the I2C clock is also assumed + to be always on. + + In addition, 13 resets are implemented. Similar to clocks, the PCIe + and I2C resets are assumed to be deasserted and cannot be controlled. + + Clock and reset ids are defined in . + +properties: + compatible: + const: toshiba,tc9564-clock + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +unevaluatedProperties: false + +examples: + - | + #include + + clock@1004 { + compatible =3D "toshiba,tc9564-clock"; + reg =3D <0x1004 0x20>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index b2d3257b8f892..66d0e7e65adcb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27670,6 +27670,13 @@ F: Documentation/devicetree/bindings/media/i2c/tos= hiba,tc358743.txt F: drivers/media/i2c/tc358743* F: include/media/i2c/tc358743.h =20 +TOSHIBA TC9564 CLOCK DRIVER +M: Alex Elder +M: Daniel Thompson +S: Maintained +F: Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml +F: include/dt-bindings/clock/toshiba,tc9564.h + TOSHIBA TC9564 PCI DRIVER M: Alex Elder M: Daniel Thompson diff --git a/include/dt-bindings/clock/toshiba,tc9564.h b/include/dt-bindin= gs/clock/toshiba,tc9564.h new file mode 100644 index 0000000000000..75732fddd3025 --- /dev/null +++ b/include/dt-bindings/clock/toshiba,tc9564.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +/* + * Copyright (C) 2026 by RISCstar Solutions Corporation. All rights reser= ved. + */ + +#ifndef __ClOCK_TOSHIBA_TC9564_H__ +#define __ClOCK_TOSHIBA_TC9564_H__ + +/* Clock IDs */ + +#define CLOCK_MCU 0 +#define CLOCK_INTC 1 +/* #define CLOCK_PCIE 2 */ +/* #define CLOCK_I2C 3 */ +#define CLOCK_SRAM 4 +#define CLOCK_UART 5 +#define CLOCK_MSIGEN 6 +#define CLOCK_PLL 7 +#define CLOCK_SGMII 8 +#define CLOCK_REFCLKO 9 + +#define CLOCK_MAC0_TX 10 +#define CLOCK_MAC0_RX 11 +#define CLOCK_MAC0_125M 12 +#define CLOCK_MAC0_312_5M 13 +#define CLOCK_MAC0_ALL 14 + +#define CLOCK_MAC1_TX 15 +#define CLOCK_MAC1_RX 16 +#define CLOCK_MAC1_RMII 17 +#define CLOCK_MAC1_125M 18 +#define CLOCK_MAC1_312_5M 19 +#define CLOCK_MAC1_ALL 20 + +/* Reset IDs */ + +#define RESET_MCU 0 +#define RESET_MCU1 1 +#define RESET_MSIGEN 2 +#define RESET_INTC 3 +#define RESET_UART 4 +/* #define RESET_I2C 5 */ +/* #define RESET_PCIE 6 */ + +#define RESET_MAC0_MAC 7 +#define RESET_MAC0_PMA 8 +#define RESET_MAC0_XPCS 9 + +#define RESET_MAC1_MAC 10 +#define RESET_MAC1_PMA 11 +#define RESET_MAC1_XPCS 12 + +#endif /* __ClOCK_TOSHIBA_TC9564_H__*/ --=20 2.53.0 From nobody Fri Sep 25 00:01:47 2026 Received: from mail-qk2-f13.google.com (mail-qk2-f13.google.com [74.125.230.205]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69A2751A73C for ; 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Fri, 18 Sep 2026 09:52:42 -0700 (PDT) Received: from zippy.localdomain ([73.62.185.64]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93be0f0762dsm183582785a.39.2026.09.18.09.52.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 09:52:42 -0700 (PDT) From: Alex Elder To: sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, kees@kernel.org, gustavoars@kernel.org, p.zabel@pengutronix.de Cc: daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mfd@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] clk: toshiba: introduce a TC9564 SoC clock and reset driver Date: Fri, 18 Sep 2026 11:52:32 -0500 Message-ID: <20260918165234.687224-4-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260918165234.687224-1-elder@riscstar.com> References: <20260918165234.687224-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define a new platform driver that manages clock and reset signals within the TC9564 SoC. There are 21 clocks, which can only be enabled and disabled, as well as 13 reset signals. Two registers manage the state of the clocks and two others manage the state of the resets. The registers are accessed via a regmap supplied by a system controller, which coordinates access to a region of memory that will be shared with another driver. Access to the memory region is provided via a BAR on a PCIe endpoint function embedded in the TC9564 SoC. For that reason, neither the PCIe clock nor PCIe reset can be manipulated by this driver (they are assumed always on and deasserted, respectively). Similarly, control is not available for the I2C clock and reset, because the PCIe subsystem on the TC9564 relies on I2C Co-developed-by: Daniel Thompson Signed-off-by: Daniel Thompson Signed-off-by: Alex Elder --- MAINTAINERS | 1 + drivers/clk/Kconfig | 11 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-tc9564.c | 366 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 379 insertions(+) create mode 100644 drivers/clk/clk-tc9564.c diff --git a/MAINTAINERS b/MAINTAINERS index 66d0e7e65adcb..39346a5cd9a7f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27675,6 +27675,7 @@ M: Alex Elder M: Daniel Thompson S: Maintained F: Documentation/devicetree/bindings/clock/toshiba,tc9564-clock.yaml +F: drivers/clk/clk-tc9564.c F: include/dt-bindings/clock/toshiba,tc9564.h =20 TOSHIBA TC9564 PCI DRIVER diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index f9592fd9ec2bb..50efa10d48450 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -292,6 +292,17 @@ config COMMON_CLK_S2MPS11 clock. These multi-function devices have two (S2MPS14) or three (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each. =20 +config COMMON_CLK_TC9564 + tristate "Toshiba TC9564 clock support" + depends on TC9564_PCI + default m + help + This enables support for the clock and reset controller embedded + in the Toshiba TC9564 (and Qualcomm QPS615) SoC. The state of + clock and reset lines is controlled by MMIO to a region managed + by a system controller; this ensures access to the region is + coordinated between this and other drivers. + config CLK_TWL tristate "Clock driver for the TWL PMIC family" depends on TWL4030_CORE diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index b18af485d7f03..a98ea8ff92066 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -110,6 +110,7 @@ obj-$(CONFIG_COMMON_CLK_SI570) +=3D clk-si570.o obj-$(CONFIG_COMMON_CLK_SP7021) +=3D clk-sp7021.o obj-$(CONFIG_COMMON_CLK_STM32F) +=3D clk-stm32f4.o obj-$(CONFIG_COMMON_CLK_STM32H7) +=3D clk-stm32h7.o +obj-$(CONFIG_COMMON_CLK_TC9564) +=3D clk-tc9564.o obj-$(CONFIG_COMMON_CLK_TPS68470) +=3D clk-tps68470.o obj-$(CONFIG_CLK_TWL6040) +=3D clk-twl6040.o obj-$(CONFIG_CLK_TWL) +=3D clk-twl.o diff --git a/drivers/clk/clk-tc9564.c b/drivers/clk/clk-tc9564.c new file mode 100644 index 0000000000000..4f900bc8994a7 --- /dev/null +++ b/drivers/clk/clk-tc9564.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* + * Copyright (C) 2026 by RISCstar Solutions Corporation. All rights reser= ved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define CLK_CTRL0_OFFSET 0x1004 +#define RST_CTRL0_OFFSET 0x1008 +#define CLK_CTRL1_OFFSET 0x100c +#define RST_CTRL1_OFFSET 0x1010 + +struct tc9564_clock_init { + const char *name; /* NULL means unused entry */ + u32 offset; + u32 mask; +}; + +struct tc9564_clock { + struct clk_hw hw; + u32 which; + u32 offset; /* CLK_CTRL0_OFFSET or CLK_CTRL1_OFFSET */ + u32 mask; /* Zero means undefined clock */ +}; + +struct tc9564_reset { + u32 offset; /* RST_CTRL0_OFFSET or RST_CTRL1_OFFSET */ + u32 mask; /* Zero means undefined reset */ +}; + +struct tc9564_clocks { + struct device *dev; + struct regmap *regmap; + struct reset_controller_dev rcdev; + size_t clock_count; + struct tc9564_clock clocks[] __counted_by(clock_count); +}; + +#define TC9564_CLOCK_INIT0(_name, _bit) __TC9564_CLOCK_INIT(_name, 0, _bit) +#define TC9564_CLOCK_INIT1(_name, _bit) __TC9564_CLOCK_INIT(_name, 1, _bit) + +#define __TC9564_CLOCK_INIT(_name, _reg, _bit) \ + [CLOCK_##_name] =3D { \ + .name =3D #_name, \ + .offset =3D CLK_CTRL ## _reg ## _OFFSET, \ + .mask =3D BIT(_bit), \ + } + +#define TC9564_RESET_INIT0(_name, _bit) __TC9564_RESET_INIT(_name, 0, _bit) +#define TC9564_RESET_INIT1(_name, _bit) __TC9564_RESET_INIT(_name, 1, _bit) + +#define __TC9564_RESET_INIT(_name, _reg, _bit) \ + [RESET_##_name] =3D { \ + .offset =3D RST_CTRL ## _reg ## _OFFSET, \ + .mask =3D BIT(_bit), \ + } + +static const struct tc9564_clock_init tc9564_clock_init[] =3D { + TC9564_CLOCK_INIT0(MCU, 0), + TC9564_CLOCK_INIT0(INTC, 4), + /* TC9564_CLOCK_INIT0(PCIE, 9), */ + /* TC9564_CLOCK_INIT0(I2C, 12), */ + TC9564_CLOCK_INIT0(SRAM, 13), + TC9564_CLOCK_INIT0(UART, 16), + TC9564_CLOCK_INIT0(MSIGEN, 18), + TC9564_CLOCK_INIT0(PLL, 24), + TC9564_CLOCK_INIT0(SGMII, 25), + TC9564_CLOCK_INIT0(REFCLKO, 26), + + TC9564_CLOCK_INIT0(MAC0_TX, 7), + TC9564_CLOCK_INIT0(MAC0_RX, 14), + TC9564_CLOCK_INIT0(MAC0_125M, 29), + TC9564_CLOCK_INIT0(MAC0_312_5M, 30), + TC9564_CLOCK_INIT0(MAC0_ALL, 31), + + TC9564_CLOCK_INIT1(MAC1_TX, 7), + TC9564_CLOCK_INIT1(MAC1_RX, 14), + TC9564_CLOCK_INIT1(MAC1_RMII, 15), + TC9564_CLOCK_INIT1(MAC1_125M, 29), + TC9564_CLOCK_INIT1(MAC1_312_5M, 30), + TC9564_CLOCK_INIT1(MAC1_ALL, 31), +}; +#define TC9564_CLOCK_COUNT ARRAY_SIZE(tc9564_clock_init) + +static const struct tc9564_reset tc9564_reset[] =3D { + TC9564_RESET_INIT0(MCU, 0), + TC9564_RESET_INIT0(MCU1, 1), + TC9564_RESET_INIT0(INTC, 4), + /* TC9564_RESET_INIT0(PCIE, 9), */ + /* TC9564_RESET_INIT0(I2C, 12), */ + TC9564_RESET_INIT0(UART, 16), + TC9564_RESET_INIT0(MSIGEN, 18), + + TC9564_RESET_INIT0(MAC0_MAC, 7), + TC9564_RESET_INIT0(MAC0_PMA, 30), + TC9564_RESET_INIT0(MAC0_XPCS, 31), + + TC9564_RESET_INIT1(MAC1_MAC, 7), + TC9564_RESET_INIT1(MAC1_PMA, 30), + TC9564_RESET_INIT1(MAC1_XPCS, 31), +}; +#define TC9564_RESET_COUNT ARRAY_SIZE(tc9564_reset) + +static const struct tc9564_clock *hw_to_tc9564_clock(struct clk_hw *hw) +{ + return container_of_const(hw, struct tc9564_clock, hw); +} + +static const struct tc9564_clocks * +tc9564_clock_to_clocks(const struct tc9564_clock *clock) +{ + u32 which =3D clock->which; + + if (which >=3D TC9564_CLOCK_COUNT) + return ERR_PTR(-ENXIO); + + return container_of_const(clock, struct tc9564_clocks, clocks[which]); +} + +static int tc9564_clk_manage(struct clk_hw *hw, bool enable) +{ + const struct tc9564_clock *clock =3D hw_to_tc9564_clock(hw); + const struct tc9564_clocks *clocks; + u32 offset =3D clock->offset; + u32 mask =3D clock->mask; + + clocks =3D tc9564_clock_to_clocks(clock); + if (IS_ERR(clocks) || !mask) { + dev_err(clk_hw_get_dev(hw), "invalid clock (%s id %u)\n", + enable ? "enable" : "disable", clock->which); + return -ENXIO; + } + + return regmap_update_bits(clocks->regmap, offset, mask, + enable ? mask : 0); +} + +static int tc9564_clk_enable(struct clk_hw *hw) +{ + return tc9564_clk_manage(hw, true); +} + +static void tc9564_clk_disable(struct clk_hw *hw) +{ + (void)tc9564_clk_manage(hw, false); +} + +static const struct clk_ops tc9564_clk_ops =3D { + .enable =3D tc9564_clk_enable, + .disable =3D tc9564_clk_disable, +}; + +static void tc9564_clock_disable_all(struct tc9564_clocks *clocks) +{ + for (int i =3D 0; i < clocks->clock_count; i++) { + const struct tc9564_clock *clock =3D &clocks->clocks[i]; + + if (clock->mask) + regmap_update_bits(clocks->regmap, clock->offset, + clock->mask, 0); + } +} + +static struct clk_hw *tc9564_clk_hw_get(struct of_phandle_args *clkspec, + void *data) +{ + struct tc9564_clocks *clocks =3D data; + unsigned int i =3D clkspec->args[0]; + + if (i < clocks->clock_count) + return &clocks->clocks[i].hw; + + dev_err(clocks->dev, "invalid index %u\n", i); + + return ERR_PTR(-EINVAL); +} + +static struct tc9564_clocks *tc9564_clk_init(struct device *dev) +{ + struct tc9564_clocks *clocks; + size_t clocks_size; + int ret; + + clocks_size =3D struct_size(clocks, clocks, TC9564_CLOCK_COUNT); + clocks =3D devm_kzalloc(dev, clocks_size, GFP_KERNEL); + if (!clocks) + return ERR_PTR(-ENOMEM); + + clocks->dev =3D dev; + clocks->clock_count =3D TC9564_CLOCK_COUNT; + + clocks->regmap =3D syscon_node_to_regmap(dev_of_node(dev->parent)); + if (IS_ERR(clocks->regmap)) { + dev_err(dev, "failed to get config regmap\n"); + return ERR_CAST(clocks->regmap); + } + + for (u32 i =3D 0; i < TC9564_CLOCK_COUNT; i++) { + const struct tc9564_clock_init *clock_init; + struct clk_init_data init =3D { }; + struct tc9564_clock *clock; + + clock_init =3D &tc9564_clock_init[i]; + if (!clock_init->name) + continue; + + init.name =3D clock_init->name; + init.ops =3D &tc9564_clk_ops; + + clock =3D &clocks->clocks[i]; + clock->hw.init =3D &init; + + ret =3D devm_clk_hw_register(dev, &clock->hw); + if (ret) { + dev_err(dev, "failed to register clock \"%s\"\n", + init.name); + return ERR_PTR(ret); + } + + clock->which =3D i; + clock->offset =3D clock_init->offset; + clock->mask =3D clock_init->mask; + } + + ret =3D devm_of_clk_add_hw_provider(dev, tc9564_clk_hw_get, clocks); + if (ret) { + dev_err(dev, "failed to add clock hardware provider\n"); + return ERR_PTR(ret); + } + + return clocks; +} + +static const struct tc9564_clocks * +rcdev_to_tc9564_clocks(struct reset_controller_dev *rcdev) +{ + return container_of_const(rcdev, struct tc9564_clocks, rcdev); +} + +static int tc9564_reset_manage(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + const struct tc9564_clocks *clocks =3D rcdev_to_tc9564_clocks(rcdev); + + if (id < rcdev->nr_resets) { + const struct tc9564_reset *reset =3D &tc9564_reset[id]; + u32 mask =3D reset->mask; + + if (mask) + return regmap_update_bits(clocks->regmap, + reset->offset, mask, + assert ? mask : 0); + } + + dev_err(clocks->dev, "invalid reset (%sassert id %lu)\n", + assert ? "" : "de", id); + + return -ENXIO; +} + +static int tc9564_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return tc9564_reset_manage(rcdev, id, true); +} + +static int tc9564_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return tc9564_reset_manage(rcdev, id, false); +} + +static const struct reset_control_ops tc9564_reset_control_ops =3D { + .assert =3D tc9564_reset_assert, + .deassert =3D tc9564_reset_deassert, +}; + +static void tc9564_reset_assert_all(struct tc9564_clocks *clocks) +{ + for (u32 id =3D 0; id < TC9564_RESET_COUNT; id++) + if (tc9564_reset[id].mask) + tc9564_reset_manage(&clocks->rcdev, id, true); +} + +static int tc9564_reset_init(struct tc9564_clocks *clocks) +{ + struct reset_controller_dev *rcdev =3D &clocks->rcdev; + + rcdev->ops =3D &tc9564_reset_control_ops; + rcdev->owner =3D THIS_MODULE; + rcdev->dev =3D clocks->dev; + rcdev->of_node =3D dev_of_node(clocks->dev); + rcdev->nr_resets =3D TC9564_RESET_COUNT; + + return devm_reset_controller_register(clocks->dev, rcdev); +} + +static int tc9564_clk_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct tc9564_clocks *clocks; + int ret; + + if (!dev_of_node(dev)) + return dev_err_probe(dev, -EINVAL, "no devicetree node\n"); + + clocks =3D tc9564_clk_init(dev); + if (IS_ERR(clocks)) + return dev_err_probe(dev, PTR_ERR(clocks), + "failed to initialize clocks\n"); + + ret =3D tc9564_reset_init(clocks); + if (ret) + return dev_err_probe(dev, ret, "failed to initialize resets\n"); + + /* Force all resets to be initially asserted */ + tc9564_reset_assert_all(clocks); + + /* Force all clocks to be initially disabled */ + tc9564_clock_disable_all(clocks); + + platform_set_drvdata(pdev, clocks); + + return 0; +} + +static void tc9564_clk_remove(struct platform_device *pdev) +{ + struct tc9564_clocks *clocks =3D platform_get_drvdata(pdev); + + /* Leave all resets to be deasserted when done */ + tc9564_reset_assert_all(clocks); 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Fri, 18 Sep 2026 09:52:44 -0700 (PDT) Received: from zippy.localdomain ([73.62.185.64]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93be0f0762dsm183582785a.39.2026.09.18.09.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 09:52:44 -0700 (PDT) From: Alex Elder To: sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, kees@kernel.org, gustavoars@kernel.org, p.zabel@pengutronix.de Cc: daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mfd@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: qcom: qcs6490-rb3gen2: add the clock controller Date: Fri, 18 Sep 2026 11:52:33 -0500 Message-ID: <20260918165234.687224-5-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260918165234.687224-1-elder@riscstar.com> References: <20260918165234.687224-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The clock (and reset) controller within the TC9564 SoC is accessed via a PCI endpoint bus through BAR 4 of the first embedded PCIe function. A syscon node is created to provide access to a range of memory that is used by the clock/reset controller and shared by other devices. Co-developed-by: Daniel Thompson Signed-off-by: Daniel Thompson Signed-off-by: Alex Elder --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 22 +++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot= /dts/qcom/qcs6490-rb3gen2.dts index 5b7f5292a8864..a99ee153e2473 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -9,6 +9,7 @@ #define PM7250B_SID 8 #define PM7250B_SID1 9 =20 +#include #include #include #include @@ -983,7 +984,7 @@ dev@0,1 { <0x2 0x0 0x0 0x83050100 0x0 0x4000 0x0 0x80000>, <0x4 0x0 0x0 0x83050100 0x0 0x84000 0x0 0x200000>; =20 - pci-ep-bus@4 { + pcie_s1b5d0f0_bar4_bus: pci-ep-bus@4 { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; @@ -995,6 +996,25 @@ pci-ep-bus@4 { }; }; =20 +&pcie_s1b5d0f0_bar4_bus { + syscon@0 { + compatible =3D "toshiba,tc9564-config", + "syscon", + "simple-mfd"; + reg =3D <0x0 0x2000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + tc9564_clock0: clock@1004 { + compatible =3D "toshiba,tc9564-clock"; + reg =3D <0x1004 0x10>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + }; +}; + &pm7325_gpios { kypd_vol_up_n: kypd-vol-up-n-state { pins =3D "gpio6"; --=20 2.53.0