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The SMMU CSR block acts as a vendor-specific interrupt controller in front of the ARM SMMUv3, providing registers to enable and clear standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ. Interrupts must be acknowledged in this block before being forwarded to the parent interrupt controller (e.g. GIC). Signed-off-by: Anirudha Sarangi Co-developed-by: Tushar Nimkar Signed-off-by: Tushar Nimkar --- .../xlnx,versal-net-smmu-csr.yaml | 75 ++++++++++++++++++= ++++ 1 file changed, 75 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/xlnx,ve= rsal-net-smmu-csr.yaml b/Documentation/devicetree/bindings/interrupt-contro= ller/xlnx,versal-net-smmu-csr.yaml new file mode 100644 index 000000000000..38b63e51b732 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-ne= t-smmu-csr.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/xlnx,versal-net-sm= mu-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal NET SMMU CSR Interrupt Controller + +maintainers: + - Anirudha Sarangi + - Tushar Nimkar + +description: | + The Versal NET platform includes a Xilinx-specific SMMU CSR (Control and + Status Register) block that acts as an intermediate interrupt controller + for ARM SMMUv3. + + The block provides registers to enable, disable and clear the + standard SMMUv3 interrupt sources (EVENTQ, CMDQ_SYNC, GERROR and PRIQ) + before forwarding them to the parent interrupt controller, + typically a GIC. + + The controller receives one parent interrupt and demultiplexes CSR + status bits into the following child interrupt identifiers + 0 - EVENTQ + 1 - CMDQ_SYNC + 2 - GERROR (GLOBAL) + 3 - PRIQ + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: xlnx,versal-net-smmu-csr + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + description: | + Single cell containing the child interrupt identifier + 0 - EVENTQ + 1 - CMDQ_SYNC + 2 - GERROR (GLOBAL) + 3 - PRIQ + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + interrupt-controller@eca10000 { + compatible =3D "xlnx,versal-net-smmu-csr"; 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Fri, 18 Sep 2026 01:40:18 -0500 From: Tushar Nimkar Date: Fri, 18 Sep 2026 12:09:34 +0530 Subject: [PATCH v2 2/2] irqchip: Add Xilinx Versal NET SMMU CSR interrupt controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-smmu-changes-v2-v2-2-adda681ab983@amd.com> References: <20260918-smmu-changes-v2-v2-0-adda681ab983@amd.com> In-Reply-To: <20260918-smmu-changes-v2-v2-0-adda681ab983@amd.com> To: Anirudha Sarangi , Thomas Gleixner , Radu Rendec , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek CC: , , , , Tushar Nimkar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789713611; l=9690; i=tushar.nimkar@amd.com; s=20260917; h=from:subject:message-id; bh=aN5LkxJWjSxzVVL/Ex/rhtXwc0Gk49BcrM/v+OqPWSA=; b=Aknz2eOmBa85QODsjY9WynZwMTzBGx3Wv+18fGC4zv3EwV3Q8kmL3VcDvGSBbGFWdiAdLupv2 /lhYLp21+aaDs2BoxnvGyb8KLn67ooFvgMmGl7ClDRTbaBDQyQFygtn X-Developer-Key: i=tushar.nimkar@amd.com; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Yn9cy8P9gLkMLvHKjfdVzHpZry+tgLpKUnwnGlXmeemeCFNR34PyNaTAMIhbePx/xbT2yjdHyjOpevuimJIV/ym/+Fvk0FNB45LwBg3vzMPnvKZjMs+y9tRDF5ac2zmDoP9RGWSYwvDkhsJ+8HguOhxf52MZYiuKNAKYG7OtSzPy/W3eANPObQlttOirYQ/78rQHBrytvunN+16PTpeWjKhy8YjvzHw8p9groW4mhwUz+bbiUuzqntBUB1Tw+YloJTKkATg91aiAwAxSOPVRcSyzjvfFRM3o6LpUE45LWNaD9jajkOdQewwbeND9l/83lw8VyuKw+wIDvqZSBGdO1FCC93qlsFdXOhZnvQ8m66Uo7hsZSe/rlPyv0gMqRD9Q2Grx85gYeHW/qosIa4TYjtgi4naXDDSzE1FQ2ndzDZc0BaRoLCiV5eZZpeuezDJp X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2026 06:40:25.6459 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14dc7b6b-2212-4073-1ffc-08df154fb8d5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002313.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: FT1PR12MB679827 From: Anirudha Sarangi The Xilinx Versal NET SoC implements a Control and Status Register (CSR) block in front of the ARM SMMUv3 to manage EVENTQ, PRIQ and GLOBAL interrupts. Interrupts are enabled, cleared, and acknowledged through this block by writing to the relevant registers. Once an interrupt is acknowledged, it is forwarded to the parent interrupt controller for further processing. Add an irqchip driver for the CSR block. The driver registers as an interrupt controller and chains to the upstream SMMUv3 driver, so that the standard SMMUv3 driver does not require modification while still supporting Xilinx SoCs. The CSR block can also gate the SMMUv3 CMDQ_SYNC completion interrupt (bit 1), but it is intentionally left unsupported. The Linux arm-smmu-v3 driver signals CMDQ_SYNC completion via polling or MSI and never requests a wired CMD_SYNC interrupt, so there is no in-kernel consumer for it. Exposing it as a child line would only risk spurious, never-acked interrupts, and it is omitted from the DT binding for the same reason. This driver is intended to operate in conjunction with the ARM SMMUv3 driver and the kernel's IOMMU DMA infrastructure. These dependencies are not selected directly in Kconfig to avoid introducing dependency recursion. Signed-off-by: Anirudha Sarangi Co-developed-by: Tushar Nimkar Signed-off-by: Tushar Nimkar --- MAINTAINERS | 10 ++ drivers/irqchip/Kconfig | 10 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-xilinx-smmu-csr.c | 216 ++++++++++++++++++++++++++++++= ++++ 4 files changed, 237 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6e50747a621c..40ef350285a6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -30141,6 +30141,16 @@ F: Documentation/misc-devices/xilinx_sdfec.rst F: drivers/misc/xilinx_sdfec.c F: include/uapi/misc/xilinx_sdfec.h =20 +XILINX SMMU CSR IRQ DRIVER +M: Anirudha Sarangi +M: Tushar Nimkar +L: git@amd.com +L: linux-arm-kernel@lists.infradead.org +L: linux-kernel@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-= smmu-csr.yaml +F: drivers/irqchip/irq-xilinx-smmu-csr.c + XILINX TRNG DRIVER M: Mounika Botcha M: Harsh Jain diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index a8f8c423b795..81a2c9107601 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -842,4 +842,14 @@ config SUNPLUS_SP7021_INTC chained controller, routing all interrupt source in P-Chip to the primary controller on C-Chip. =20 +config IRQCHIP_XILINX_SMMU_CSR + bool "Xilinx SMMU CSR Interrupt Driver" + depends on ARCH_ZYNQMP + select IRQ_DOMAIN + help + This driver does the initial handling of SMMU interrupts before + forwarding them to the ARM SMMU v3 driver. It is intended for + ZynqMP-class platforms where a vendor CSR block mediates SMMU + interrupts. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index ab33cccd8471..16a5fd126c9a 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -135,3 +135,4 @@ obj-$(CONFIG_APPLE_AIC) +=3D irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) +=3D irq-mchp-eic.o obj-$(CONFIG_SOPHGO_SG2042_MSI) +=3D irq-sg2042-msi.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) +=3D irq-sp7021-intc.o +obj-$(CONFIG_IRQCHIP_XILINX_SMMU_CSR) +=3D irq-xilinx-smmu-csr.o diff --git a/drivers/irqchip/irq-xilinx-smmu-csr.c b/drivers/irqchip/irq-xi= linx-smmu-csr.c new file mode 100644 index 000000000000..d9b575c6c58b --- /dev/null +++ b/drivers/irqchip/irq-xilinx-smmu-csr.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal Net SMMU CSR interrupt controller driver + * + * Copyright (C) 2026 Advanced Micro Devices, Inc. + * + * Vendor CSR block that gates the ARM SMMUv3 wired interrupts. Chains + * off the single GIC parent line and demultiplexes the CSR status into + * three children (eventq, gerror, priq), each enabled/acked + * via SMMU_CSR_IER/IDR/ISR that the ARM SMMUv3 driver requests individual= ly. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Interrupt types */ +#define SMMU_INTR_EVENT BIT(0) +#define SMMU_INTR_GLOBAL BIT(2) +#define SMMU_INTR_PRI BIT(3) + +/* Mask for all SMMU interrupts */ +#define SMMU_INTR_ALL (SMMU_INTR_EVENT | \ + SMMU_INTR_GLOBAL | SMMU_INTR_PRI) + +#define SMMU_CSR_ISR 0x24 /* Interrupt Status */ +#define SMMU_CSR_IER 0x2c /* Interrupt Enable */ +#define SMMU_CSR_IDR 0x30 /* Interrupt Disable */ + +/** + * struct xilinx_smmu_csr - SMMU CSR interrupt controller context + * @base: MMIO base address of the CSR registers + * @domain: Interrupt domain for the child interrupts + * @parent_irq: parent (GIC) interrupt this block is chained to + * @lock: protects the SMMU_CSR_IER/IDR/ISR read and writes + */ +struct xilinx_smmu_csr { + void __iomem *base; + struct irq_domain *domain; + int parent_irq; + raw_spinlock_t lock; +}; + +enum xilinx_smmu_csr_irq { + SMMU_CSR_IRQ_EVENTQ =3D 0, + SMMU_CSR_IRQ_GERROR =3D 2, + SMMU_CSR_IRQ_PRIQ =3D 3, + SMMU_CSR_IRQ_NR, +}; + +static u32 xilinx_smmu_csr_hwirq_mask(irq_hw_number_t hwirq) +{ + if (hwirq >=3D SMMU_CSR_IRQ_NR) + return 0; + + return BIT(hwirq) & SMMU_INTR_ALL; +} + +static void xilinx_smmu_csr_irq_mask(struct irq_data *d) +{ + struct xilinx_smmu_csr *csr =3D irq_data_get_irq_chip_data(d); + u32 mask =3D xilinx_smmu_csr_hwirq_mask(d->hwirq); + + if (!mask) + return; + + guard(raw_spinlock)(&csr->lock); + writel(mask, csr->base + SMMU_CSR_IDR); +} + +static void xilinx_smmu_csr_irq_unmask(struct irq_data *d) +{ + struct xilinx_smmu_csr *csr =3D irq_data_get_irq_chip_data(d); + u32 mask =3D xilinx_smmu_csr_hwirq_mask(d->hwirq); + + if (!mask) + return; + + guard(raw_spinlock)(&csr->lock); + writel(mask, csr->base + SMMU_CSR_IER); +} + +static void xilinx_smmu_csr_irq_ack(struct irq_data *d) +{ + struct xilinx_smmu_csr *csr =3D irq_data_get_irq_chip_data(d); + u32 mask =3D xilinx_smmu_csr_hwirq_mask(d->hwirq); + + if (!mask) + return; + + guard(raw_spinlock)(&csr->lock); + writel(mask, csr->base + SMMU_CSR_ISR); +} + +static struct irq_chip xilinx_smmu_csr_chip =3D { + .name =3D "xlnx-smmu-csr", + .irq_mask =3D xilinx_smmu_csr_irq_mask, + .irq_unmask =3D xilinx_smmu_csr_irq_unmask, + .irq_ack =3D xilinx_smmu_csr_irq_ack, +}; + +static void xilinx_smmu_csr_irq_handler(struct irq_desc *desc) +{ + struct xilinx_smmu_csr *csr =3D irq_desc_get_handler_data(desc); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + u32 status, pending; + + chained_irq_enter(chip, desc); + + status =3D readl(csr->base + SMMU_CSR_ISR); + + /* Only service sources we support; SMMU_CSR_ISR latches raw status */ + pending =3D status & SMMU_INTR_ALL; + + while (pending) { + irq_hw_number_t hwirq =3D __ffs(pending); + int ret; + + ret =3D generic_handle_domain_irq(csr->domain, hwirq); + if (ret) + pr_err_ratelimited("xilinx-smmu-csr: Failed to handle domain IRQ %lu: %= d\n", + hwirq, ret); + + pending &=3D ~BIT(hwirq); + } + + chained_irq_exit(chip, desc); +} + +static int xilinx_smmu_csr_domain_map(struct irq_domain *d, unsigned int v= irq, + irq_hw_number_t hwirq) +{ + struct xilinx_smmu_csr *csr =3D d->host_data; + + if (!xilinx_smmu_csr_hwirq_mask(hwirq)) + return -EINVAL; + + irq_set_chip_and_handler(virq, &xilinx_smmu_csr_chip, handle_level_irq); + irq_set_chip_data(virq, csr); + irq_set_status_flags(virq, IRQ_LEVEL); + + return 0; +} + +static const struct irq_domain_ops xilinx_smmu_csr_domain_ops =3D { + .map =3D xilinx_smmu_csr_domain_map, + .xlate =3D irq_domain_xlate_onecell, +}; + +static int __init xilinx_smmu_csr_init(struct device_node *node, struct de= vice_node *parent) +{ + struct xilinx_smmu_csr *csr; + int ret; + + if (WARN_ON_ONCE(!parent)) + return -EINVAL; + + if (irq_find_matching_fwnode(of_fwnode_handle(node), + DOMAIN_BUS_ANY)) + return -ENODEV; + + csr =3D kzalloc(sizeof(*csr), GFP_KERNEL); + if (!csr) + return -ENOMEM; + + raw_spin_lock_init(&csr->lock); + + csr->base =3D of_iomap(node, 0); + if (!csr->base) { + ret =3D -ENOMEM; + goto free; + } + + /* Start from a known state: all sources disabled, latches cleared. */ + writel(SMMU_INTR_ALL, csr->base + SMMU_CSR_IDR); + writel(SMMU_INTR_ALL, csr->base + SMMU_CSR_ISR); + + csr->domain =3D irq_domain_create_linear(of_fwnode_handle(node), SMMU_CSR= _IRQ_NR, + &xilinx_smmu_csr_domain_ops, + csr); + if (!csr->domain) { + pr_err("%pOF: failed to create irq domain\n", node); + ret =3D -ENOMEM; + goto unmap; + } + + csr->parent_irq =3D irq_of_parse_and_map(node, 0); + if (!csr->parent_irq) { + pr_err("%pOF: failed to map parent irq\n", node); + ret =3D -EINVAL; + goto remove_domain; + } + + irq_set_chained_handler_and_data(csr->parent_irq, + xilinx_smmu_csr_irq_handler, csr); + + pr_debug("%pOF: Xilinx SMMU CSR interrupt controller registered\n", node); + + return 0; + +remove_domain: + irq_domain_remove(csr->domain); +unmap: + iounmap(csr->base); +free: + kfree(csr); + return ret; +} + +IRQCHIP_DECLARE(xilinx_smmu_csr, "xlnx,versal-net-smmu-csr", + xilinx_smmu_csr_init); --=20 2.34.1