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[84.3.243.148]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-487244608a3sm1010447f8f.8.2026.09.18.12.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 12:53:14 -0700 (PDT) From: Gabor Juhos Date: Fri, 18 Sep 2026 21:53:08 +0200 Subject: [PATCH] spi: spi-qpic-snand: add qcom_spi_config_page_read() helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-qpic-snand-config_page_read-v1-1-a686c4657857@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/y3NQQrCMBCF4auUWTuQFDXUq4iUOJnG2UzTSRWh9 O4Gdfm9xf82qGzCFS7dBsYvqTJrgz90QI+omVFSM/SuP7vBB1yKEFaNmpBmnSSPJWYejWNCdwq UjsF5Gu7QCsV4kve3fr39bLw828n6H/f9A0Nr4g2CAAAA X-Change-ID: 20260917-qpic-snand-config_page_read-057cd4701c9b To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan , Sricharan Ramabadhran , Md Sadre Alam , linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.14.3 Move the register write sequence needed for configuring a page read into a separate function to reduce code duplication. No functional changes. Signed-off-by: Gabor Juhos --- drivers/spi/spi-qpic-snand.c | 45 +++++++++++++++-------------------------= ---- 1 file changed, 15 insertions(+), 30 deletions(-) diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c index 9e626ffbe63a..aaa40753d274 100644 --- a/drivers/spi/spi-qpic-snand.c +++ b/drivers/spi/spi-qpic-snand.c @@ -501,6 +501,17 @@ static void qcom_spi_set_read_loc(struct qcom_nand_con= troller *snandc, int cw, i read_size, is_last_read_loc); } =20 +static void qcom_spi_config_page_read(struct qcom_nand_controller *snandc) +{ + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, + NAND_ERASED_CW_DETECT_CFG, 1, 0); + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, + NAND_ERASED_CW_DETECT_CFG, 1, + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); +} + static void qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc,= int cw) { @@ -564,13 +575,7 @@ static void qcom_spi_config_single_cw_page_read(struct= qcom_nand_controller *sna __le32 *reg =3D &snandc->regs->read_location0; int num_cw =3D snandc->qspi->num_cw; =20 - qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); - qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); - qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, - NAND_ERASED_CW_DETECT_CFG, 1, 0); - qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, - NAND_ERASED_CW_DETECT_CFG, 1, - NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); + qcom_spi_config_page_read(snandc); =20 if (cw =3D=3D (num_cw - 1)) { reg =3D &snandc->regs->read_location_last0; @@ -763,14 +768,7 @@ static int qcom_spi_read_cw_raw(struct qcom_nand_contr= oller *snandc, u8 *data_bu snandc->regs->exec =3D cpu_to_le32(1); =20 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1); - - qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); - qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); - qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, - NAND_ERASED_CW_DETECT_CFG, 1, 0); - qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, - NAND_ERASED_CW_DETECT_CFG, 1, - NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); + qcom_spi_config_page_read(snandc); =20 data_size1 =3D mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); oob_size1 =3D ecc_cfg->bbm_size; @@ -875,14 +873,7 @@ static int qcom_spi_read_page_ecc(struct qcom_nand_con= troller *snandc, snandc->regs->exec =3D cpu_to_le32(1); =20 qcom_clear_bam_transaction(snandc); - - qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); - qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); - qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, - NAND_ERASED_CW_DETECT_CFG, 1, 0); - qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, - NAND_ERASED_CW_DETECT_CFG, 1, - NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); + qcom_spi_config_page_read(snandc); =20 for (i =3D 0; i < num_cw; i++) { int data_size, oob_size; @@ -963,13 +954,7 @@ static int qcom_spi_read_page_oob(struct qcom_nand_con= troller *snandc, snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); snandc->regs->exec =3D cpu_to_le32(1); =20 - qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); - qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); - qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, - NAND_ERASED_CW_DETECT_CFG, 1, 0); - qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, - NAND_ERASED_CW_DETECT_CFG, 1, - NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); + qcom_spi_config_page_read(snandc); =20 for (i =3D 0; i < num_cw; i++) { int data_size, oob_size; --- base-commit: ca01ebd9e2ed0ea7ed4a068bcd666b0f394581ac change-id: 20260917-qpic-snand-config_page_read-057cd4701c9b Best regards, --=20 Gabor Juhos