From nobody Fri Sep 25 00:40:52 2026 Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1E7A415B92; Fri, 18 Sep 2026 10:41:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789728114; cv=none; b=iEb//lcDKx3qtZ3r4Cme5jy5QMwpku+CvAkwQpTL2TSaUCv5UcIILvf4kfrFj/QE9raJKWP3EsVLGQHuA0EcM4p4jhq5MzhwqUDDaArc+Ae8efWMIX2RYf3BvPds+vdHAWbzaAN756lWOyBMj87utz1OG6MXk6XMkuMfNJnXTlE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789728114; c=relaxed/simple; bh=rl84C4ONuIM6uvedwccwpsIKbrFWDQorasJcY+NMHR0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=oA3zPzAme1ghLdSl5apphau3ACs4/WGcFptt97PmWxE3aOF/QEnYvP215qygFsiNoWvm+TaNEF1kKoDPxxxnS4QE7eWLVpq2Px9I4gGF5g6BpXodEgX1H2hSvfiyEz2j+QgQovcvDKwsy5tSk54sJqtIP9jpp+z8BUhdU4tBryI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=OUzBpx/f; arc=none smtp.client-ip=91.207.212.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="OUzBpx/f" Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68I9ddEN2867218; Fri, 18 Sep 2026 11:41:32 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=W FZDtpGn0hp1sx5qqrvhGry+sbXQlcx/KuBrsyBaufo=; b=OUzBpx/fVqzctSxa2 vkWOPd7A72A2cHNOSNgFucNavOdjDDweQJiT9YnVpotPPP5wRFS0/jODSIeN+3U+ JbIdGIxJ97t4Kn0xmKoD3i5NaPj3bBOhoiO/anpAsiut1NTovePU8om3tImU79tC poNE9mvUz3bx37ccJnxe4eD0t4+k7QTSz9GgSgKREjEa/gcm+GfgwXsRg9Tq9tCf W3sw5EyFr6U8TUTyHduB805ldMJrdBwmueMftIkBR5xLPHOrhvS0fyL0uhTerXBa YyzBsH9KjA+eKsNmIUF1WVwwMiiWzPN2rQzffE+GQ5c9gL4t7BNMFk2Vrq2yIgjU hvNTw== Received: from hhmail01.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 4gmw0q4ysn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Sep 2026 11:41:32 +0100 (BST) Received: from [127.0.1.1] (172.25.128.225) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Fri, 18 Sep 2026 11:41:28 +0100 From: Brajesh Gupta Date: Fri, 18 Sep 2026 16:11:13 +0530 Subject: [PATCH v3 1/2] drm/imagination: Propagate map failures correctly from pvr_mmu_map_sgl() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-mmu_fix-v3-1-7b3d73aef041@imgtec.com> References: <20260918-mmu_fix-v3-0-7b3d73aef041@imgtec.com> In-Reply-To: <20260918-mmu_fix-v3-0-7b3d73aef041@imgtec.com> To: Alessio Belle , Luigi Santivetti , Frank Binns , Alexandru Dadu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , , , Brajesh Gupta X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4877; i=brajesh.gupta@imgtec.com; h=from:subject:message-id; bh=rl84C4ONuIM6uvedwccwpsIKbrFWDQorasJcY+NMHR0=; b=owEBbQKS/ZANAwAKAdAmd1l+AvFwAcsmYgBqrRVT0lTuMbmKXiXhUkzoG/Lz59pJFnv6aLx/H LaXw3iG+NGJAjMEAAEKAB0WIQSQIkZAwD1cxcAsz3LQJndZfgLxcAUCaq0VUwAKCRDQJndZfgLx cHxgEADNxkalTc2ecg5QLb7rfw56qeTKxOuZzPEZDvEwOBMFZmkuUkREranotllF2ZJ2fNzTCr0 Gpx+2hgkDHMGSmmIzKo35SP84cKONPY/ELF8qNlGbnBMNllw3RkN6pSOV96+b5j9JJPUy+t8CN8 BTRUzO4lfY+U+QQzj6AQWPTRpAUWIUIg9WP0ogrbKJP2lGx6pELTLR2YjA6sj5BNq5ZhBeDUigL SaolUVlkrOTsh8pB/2O856a9cPMWz5GS+io6Vxc6WaspqoT+28F267CvwkH4nnoUSOZPpfTmwGL pspHCvSnCYBpsZS/OpupPwwMZb8Y475N1qdr1VOIA7QkrV2hvK30Tvlfbcr2Gmy7l3p1GrGzH6D VNnnWR11+t8ssGtl2hc0Ed7LvWx6xq6HG16MimsDiGdb4VU8sEqhdHtx8XUVuXBy4fGYmJMTZrX bvxgrs/8fFf3hxRXNQMu/DVzGLs+gFIyCXK7PiijMVVdROv5R/4trmLBQGZgVwh38FFm7MIhFl6 qNM0EHQHvqy+MjpwwYJ/Z3GOdhIR4WTwg57Rgzjmq5tKXM5Q1L6O+CuWimctIK5CBVelAHamVMw LY315a2llc8VOzGQFFHCvpitZOInJAfmUoFb64OYXKc58j2z7xxsY+dx7/va2hVY76SJTJYAvul zNBJqXiN1SHl4qg== X-Developer-Key: i=brajesh.gupta@imgtec.com; a=openpgp; fpr=05BAA300FD5C580EFD3F8D2F073292BAD0D39671 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE4MDE0OSBTYWx0ZWRfX7PJwjtISwIsT BzJEvIs4TdMyMiwGm3QxR3j8+UxiurHJUNLcjOVNF/Un443hSL2ebkY5ZoPVOxgmNLZX41yGw8A lWsCitJrD048nCeUQoRvMHA7J3fqvPWE9vp3//cBa9GeX0b9g/KjxCiUW9ud/NKJdfMv2ZNeyV3 T5Bi9oOffwoEpqu11goy5MVchA79hzikdSDDrzfjs9Wxh7S3jpgkeMae2lDZd15rrFUE3NrUs6n gTOwZbZ5P7DWgb0vNoUW+MJccMOhikEoS3uu0yKfdsxxXTU70Fs7I4uAr+xfRRuzPuSwGWhc1Pa y41y7BrnFyPwLFMj/HOHKPQuYrHW9nyf6SzFJ83Ci+qK/ssNByaiP0wMyVDO2a7cJJ3Fc1f+WEo yQoa8Juukiu0UC8X2xiZ7byU0tYv+cc1hE4jzsAE1IHNCsv7IPPxYUVOBxs4prVEJtECWAjBqD/ 7CS3PWBG9uPaNI0Hfkg== X-Authority-Analysis: v=2.4 cv=c8M+0h9l c=1 sm=1 tr=0 ts=6aad155c cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=HYrZrZQ_E1YA:10 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=kQ-hrUj2-E3RCbRHssb7:22 a=qZQ2PDNLMSdLoqI-hfl9:22 a=r_1tXGB3AAAA:8 a=MA1SxRKIldkD5NN-sdEA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-ORIG-GUID: djoCe916n0ZA6tM_RbmTyOx_0skWeDoO X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE4MDE0OSBTYWx0ZWRfX9FTaaUHmF9Zp g45JOzMOOVnGM2hcrngS3Wo36jo7YyQpOTeE7Q6+XKvauGsl0y9HAn7sMxxKnZ1Gwm87YzqwzUL VQhZFGLP4i+DBTYQlzP1Neh4Y0AFJo8= X-Proofpoint-GUID: djoCe916n0ZA6tM_RbmTyOx_0skWeDoO Map failure from pvr_mmu_map_sgl() interface was not returned correctly to pvr_mmu_map() interface. This resulted in pvr_mmu_map() interface to continue instead of returning an error to caller. Fix it by returning a proper error code from pvr_mmu_map_sgl() interface. Call stack for crash: [ 1179.286237] Unable to handle kernel NULL pointer dereference at virtual = address 0000000000000008 [ 1179.295067] Mem abort info: [ 1179.297877] ESR =3D 0x0000000096000004 [ 1179.301656] EC =3D 0x25: DABT (current EL), IL =3D 32 bits [ 1179.306987] SET =3D 0, FnV =3D 0 [ 1179.310048] EA =3D 0, S1PTW =3D 0 [ 1179.313198] FSC =3D 0x04: level 0 translation fault [ 1179.318096] Data abort info: [ 1179.320993] ISV =3D 0, ISS =3D 0x00000004, ISS2 =3D 0x00000000 [ 1179.326483] CM =3D 0, WnR =3D 0, TnD =3D 0, TagAccess =3D 0 [ 1179.331546] GCS =3D 0, Overlay =3D 0, DirtyBit =3D 0, Xs =3D 0 [ 1179.336895] user pgtable: 4k pages, 48-bit VAs, pgdp=3D000000009822a000 [ 1179.343402] [0000000000000008] pgd=3D0000000000000000, p4d=3D00000000000= 00000 [ 1179.350243] Internal error: Oops: 0000000096000004 [#2] SMP [ 1179.355908] Modules linked in: powervr gpu_sched drm_shmem_helper drm_gp= uvm drm_exec xhci_plat_hcd xhci_hcd dwc3 usbcore usb_common snd_soc_simple_= card snd_soc_simple_card_utils dwc3_am62 at24 sa2ul sha512 libsha512 sha256= authenc sch_fq_codel fuse dm_mod ipv6 [ 1179.378992] CPU: 1 UID: 1000 PID: 680 Comm: deqp-vk Tainted: G D = 6.17.0 #1 PREEMPT [ 1179.388120] Tainted: [D]=3DDIE [ 1179.390994] Hardware name: Texas Instruments AM625 SK (DT) [ 1179.396467] pstate: 00000005 (nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE= =3D--) [ 1179.403415] pc : pvr_mmu_op_context_unmap_curr_page+0x6c/0x134 [powervr] [ 1179.410140] lr : pvr_mmu_op_context_unmap_curr_page+0x58/0x134 [powervr] [ 1179.416848] sp : ffff8000839ab8c0 [ 1179.420153] x29: ffff8000839ab8c0 x28: 0000000000000001 x27: 000000008f3= 86000 [ 1179.427283] x26: ffff000016d1df98 x25: 0000000000247000 x24: 00000000000= 001e6 [ 1179.434413] x23: 0000000000000002 x22: 000000000000ffff x21: 00000000000= 00247 [ 1179.441540] x20: 0000000000000245 x19: ffff000016d1df60 x18: 00000000000= 00002 [ 1179.448668] x17: 0000000000000000 x16: 0000000000000000 x15: 00000000000= 00001 [ 1179.455793] x14: 0000000000060810 x13: ffff80007fffffff x12: ffff0000041= 90480 [ 1179.462921] x11: ffff8000853f7000 x10: ffff8000811ae000 x9 : ffff0000041= 900b8 [ 1179.470051] x8 : 0000000000000000 x7 : 00000000990c4001 x6 : 00000000000= 00007 [ 1179.477177] x5 : ffff000016d1df60 x4 : 0000000000000000 x3 : ffff00000a7= d8000 [ 1179.484306] x2 : 00000000000001ff x1 : 0000000000000000 x0 : 00000000000= 00000 [ 1179.491433] Call trace: [ 1179.493872] pvr_mmu_op_context_unmap_curr_page+0x6c/0x134 [powervr] (P) [ 1179.500582] pvr_mmu_map+0x31c/0x388 [powervr] [ 1179.505027] pvr_vm_gpuva_map+0x40/0x88 [powervr] [ 1179.509732] __drm_gpuvm_sm_map+0x250/0x44c [drm_gpuvm] [ 1179.514952] drm_gpuvm_sm_map+0x48/0x5c [drm_gpuvm] [ 1179.519822] pvr_vm_bind_op_exec+0x64/0x70 [powervr] [ 1179.524785] pvr_vm_map+0x1f8/0x2a8 [powervr] [ 1179.529142] pvr_ioctl_vm_map+0x12c/0x188 [powervr] [ 1179.534018] drm_ioctl_kernel+0xb8/0x128 [ 1179.537941] drm_ioctl+0x21c/0x4ec [ 1179.541337] __arm64_sys_ioctl+0xac/0x108 [ 1179.545344] invoke_syscall+0x44/0x100 [ 1179.549091] el0_svc_common.constprop.0+0x40/0xe0 [ 1179.553790] do_el0_svc+0x1c/0x28 [ 1179.557106] el0_svc+0x34/0xf0 [ 1179.560159] el0t_64_sync_handler+0xd0/0xe4 [ 1179.564334] el0t_64_sync+0x198/0x19c [ 1179.567996] Code: 54000300 35000360 f9402261 79409a62 (f9400421) [ 1179.574081] ---[ end trace 0000000000000000 ]--- Fixes: ff5f643de0bf ("drm/imagination: Add GEM and VM related code") Signed-off-by: Brajesh Gupta Reviewed-by: Alexandru Dadu Reviewed-by: Alessio Belle --- drivers/gpu/drm/imagination/pvr_mmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/pvr_mmu.c b/drivers/gpu/drm/imagin= ation/pvr_mmu.c index 3cac482e1034..23261d9ad3fd 100644 --- a/drivers/gpu/drm/imagination/pvr_mmu.c +++ b/drivers/gpu/drm/imagination/pvr_mmu.c @@ -12,6 +12,7 @@ #include "pvr_rogue_mmu_defs.h" =20 #include +#include #include #include #include @@ -2553,7 +2554,9 @@ pvr_mmu_map_sgl(struct pvr_mmu_op_context *op_ctx, st= ruct scatterlist *sgl, =20 err_destroy_pages: memcpy(&op_ctx->curr_page, &ptr_copy, sizeof(op_ctx->curr_page)); - err =3D pvr_mmu_op_context_unmap_curr_page(op_ctx, page); + if (pvr_mmu_op_context_unmap_curr_page(op_ctx, page)) + drm_err(from_pvr_device(op_ctx->mmu_ctx->pvr_dev), + "%s : Failure in unmapping pages\n", __func__); =20 return err; } --=20 2.43.0 From nobody Fri Sep 25 00:40:52 2026 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69FC34B7A4F; Fri, 18 Sep 2026 10:41:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.180.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789728117; cv=none; b=Mf5GFnC4/4oaM/zXIP5f57zCzTJ0O/S6INpklZKxuKOk+jlAYAxQ+JUx/1BYx7H4m+ub4poOb79Hy0dJLeM+9OFfZw6egf7Mc5LxxTWzcdTZVMHObjKVILLy2DdkFxIhVbYRT/+XCMiIU3XkBVMmmk4DQNIYdIqSogvIYBHrOdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789728117; c=relaxed/simple; bh=hr31MLDk78Vm4gpqDFRdeOtP0lsOlahxqI2LUyBNWOo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=UZWbmn00CV/l2CaUm8wlf9Lgxl/G/1Ls+dsFrG9pi8kBJdrqEvjK6l1XRTQ+22b7iHCZV1lSDVxuI01Zij9BTymQnojNSJZA4WVxorsbtaFVQHocnAefrXqwK5wBTPtJjzl7OZM5bLGMV2eUBRUGbvEeGMc9L/Ik39djJC7bLss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=Z0JnkJZ9; arc=none smtp.client-ip=185.132.180.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="Z0JnkJZ9" Received: from pps.filterd (m0168889.ppops.net [127.0.0.1]) by mx07-00376f01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68I9deIo1687771; Fri, 18 Sep 2026 11:41:36 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=P 9s+38RWbu/7v34wRavJ3rNdn0EYpfrcE4CennW2IuY=; b=Z0JnkJZ9QIYXU9lZM ML4RBHnJtXQhTfZf6WgV74mcPpJAfc6CLPWh7u5Um5HGpjSTLtq92BdmoLex5Ydk WtzKfDJxqt5YjLOimuTQlPePLY4QyQbnYglTMKPkXqhOMhcWneH8g65nSNNgP6fn hkCrInR+jfvpUaWBiXJktS0ksusdaTYJuEFbQg5TQgrg+dLJ3SZ/KcO2v9gYjoC2 CJ9vXZ3hbYtQ7X8bOcLeTIrHdnqOOdFbJ3bRBsFEa3Phu1xMXrJbQupmge3Rwm6h NA6tG/Box4LHQn/SU7r58WX/15vuMvHjX8K332VTOFe4PJauLlcwr60iOlhKscmv xLu0Q== Received: from hhmail01.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx07-00376f01.pphosted.com (PPS) with ESMTPS id 4gmxtungv1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Sep 2026 11:41:35 +0100 (BST) Received: from [127.0.1.1] (172.25.128.225) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Fri, 18 Sep 2026 11:41:31 +0100 From: Brajesh Gupta Date: Fri, 18 Sep 2026 16:11:14 +0530 Subject: [PATCH v3 2/2] drm/imagination: Fix page count for page table for map() interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-mmu_fix-v3-2-7b3d73aef041@imgtec.com> References: <20260918-mmu_fix-v3-0-7b3d73aef041@imgtec.com> In-Reply-To: <20260918-mmu_fix-v3-0-7b3d73aef041@imgtec.com> To: Alessio Belle , Luigi Santivetti , Frank Binns , Alexandru Dadu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , , , Brajesh Gupta X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5065; i=brajesh.gupta@imgtec.com; h=from:subject:message-id; bh=hr31MLDk78Vm4gpqDFRdeOtP0lsOlahxqI2LUyBNWOo=; b=owEBbQKS/ZANAwAKAdAmd1l+AvFwAcsmYgBqrRVUf3/1+de4tw5zWt8UgEQZ7axbPC84XGfvu b8Vid2BQHaJAjMEAAEKAB0WIQSQIkZAwD1cxcAsz3LQJndZfgLxcAUCaq0VVAAKCRDQJndZfgLx cMS3EACTgs3HSvyLNgy6GU5Mkxw7asew/eUWvdqiptRxAgcEySOKPQMpg73VIoESe1dy177DS6T mQ8mqL+IfcgdxqWBHw/x3STv6nRzDPraz77btOQzXuzFJhcL/lFRIMutK2ie4FDBr6xSVGhw18m oY8qqE+s9qryVQ10AWbSJzyV5tYptcCTY3aSZPgiUDWuzvGNqvgb7xEfSNgrN7G5Zw19SmXtJ5R yeqxg6xFmnLfhIQl3vMfCi4xA25mSKGUyp9dh7hRkJXSnZrPyUtHWuwfMJBjBxNHIHbEn4MyU68 D35HPIik8LBZo2Wznr7QhVaks8u909xkSVChupVLACgJSiDEdLJFme+wbRKgfUqE1exvQBn81es l53XZ2fD2o70qkhQUmzR3AOgCNMiBWFcYE1b2eU/UlQLPvB8rIh0893MZmO/o/PlxNRM0KMDV/Q z2FWPeOABnF8t3JyzRGGBYzaHOIecv3x/5L+CayMjCVCciQJy8AsQ/wgMCX3dFo8II4pQLBOf9c 7c57nR0aBDjPUmfGbELoatW/d5rfNw+1Mu+9J+d38QtEWUJDimmBg1s2Aa6fNvyrJLDQsY66gy3 QBGPh66+YC54oWC8Ovkk9wnYL3WQxcvszn0iyL16K7SOe71wqU272EWsAT+0yY85NJ0g8SQWQd5 ao8yEvyUv7aUXKA== X-Developer-Key: i=brajesh.gupta@imgtec.com; a=openpgp; fpr=05BAA300FD5C580EFD3F8D2F073292BAD0D39671 X-Authority-Analysis: v=2.4 cv=Se9i5fRu c=1 sm=1 tr=0 ts=6aad155f cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=HYrZrZQ_E1YA:10 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=kQ-hrUj2-E3RCbRHssb7:22 a=7RYWX5rxfSByPNLylY2M:22 a=r_1tXGB3AAAA:8 a=lyzDSBJAejP7XBH9i10A:9 a=0bXxn9q0MV6snEgNplNhOjQmxlI=:19 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-ORIG-GUID: OQOzjgKRMxNdoEJ1mV7ZhaTMNV2sC-o7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE4MDE0OSBTYWx0ZWRfX8qTX/7yW+Jor C0qWQp766iQMU5zxusMTGNiDkXgEWzC/jBxh+9O8d+LpWHyrCyCkvyNWWzHMk4X/jE6UcG3baL5 gQaWWpGYf03ggd+q71ekoMzH8VAVx1aqm87eCewn3aQcjKZYVNTo10YOAy5nnvhHSwv8m1PldJv iDoU2ANg5U1ETnoVHW2bmJBnVraxxrusheOmQuVtBa3vg9PkC+E/OP7OH1eL/eNRH8PBDgs6Df7 nac/jGZ4qPhWNViaHEt4SaoJEaoZ2T9Aq6nCcME/ucT+0tY734I/hv1iipwR2NqtW23b4wYAf8Y r3ZcFiXc1QoPWo6G3QQYpn/Nh87eqsITCibWJXqWzPacXsGVqo8ECQL5DI0o6E19oRFmRfUtnJc XIQ8hoyvWsc7h5fOCNu5n0IYmtF3s/6A/NSPhMh48OQoXt4WDnlIC1UvlMj9x4QeXvkOEEBjqg3 BMSdlsFV9g26Hff7N+g== X-Proofpoint-GUID: OQOzjgKRMxNdoEJ1mV7ZhaTMNV2sC-o7 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE4MDE0OSBTYWx0ZWRfX/uPzFBQg9+YR /HT6FMAODuQ1pZC6wEcQajQX7IzVvuuZ/AQzBvMiNkvwcmZzfGOQkdkA/iCIn1BzBKEew9hbHuH 2+fIukwXwxjMdhoRIQ0+RWLA5BEc2Ig= The GPU virtual start address wasn't included in the calculation for the amount of page tables required for mapping a BO object in map() interface. It resulted in map failure later due to not enough pages at L0/L1 level. Update pvr_mmu_op_context_create() interface to pass device address as well to allow correct calculation for page table memory. Miscalculation of page table pages for mapping a BO starting at a device address 0x8001b45000 of size 0x8ca000: old new L0 count 5 6 L1 count 1 1 Fixes: ff5f643de0bf ("drm/imagination: Add GEM and VM related code") Signed-off-by: Brajesh Gupta Reviewed-by: Alexandru Dadu Reviewed-by: Alessio Belle --- drivers/gpu/drm/imagination/pvr_mmu.c | 14 ++++++++------ drivers/gpu/drm/imagination/pvr_mmu.h | 2 +- drivers/gpu/drm/imagination/pvr_vm.c | 4 ++-- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_mmu.c b/drivers/gpu/drm/imagin= ation/pvr_mmu.c index 23261d9ad3fd..62eae7fcd5a2 100644 --- a/drivers/gpu/drm/imagination/pvr_mmu.c +++ b/drivers/gpu/drm/imagination/pvr_mmu.c @@ -2336,6 +2336,7 @@ void pvr_mmu_op_context_destroy(struct pvr_mmu_op_con= text *op_ctx) * pvr_mmu_op_context_create() - Create an MMU op context. * @ctx: MMU context associated with owning VM context. * @sgt: Scatter gather table containing pages pinned for use by this cont= ext. + * @device_addr: Virtual device address at the start of the requested mapp= ing. * @sgt_offset: Start offset of the requested device-virtual memory mappin= g. * @size: Size in bytes of the requested device-virtual memory mapping. Fo= r an * unmapping, this should be zero so that no page tables are allocated. @@ -2347,8 +2348,9 @@ void pvr_mmu_op_context_destroy(struct pvr_mmu_op_con= text *op_ctx) */ struct pvr_mmu_op_context * pvr_mmu_op_context_create(struct pvr_mmu_context *ctx, struct sg_table *sg= t, - u64 sgt_offset, u64 size) + u64 device_addr, u64 sgt_offset, u64 size) { + u64 start_addr =3D device_addr + sgt_offset; int err; =20 struct pvr_mmu_op_context *op_ctx =3D kzalloc_obj(*op_ctx); @@ -2364,16 +2366,16 @@ pvr_mmu_op_context_create(struct pvr_mmu_context *c= tx, struct sg_table *sgt, if (size) { /* * The number of page table objects we need to prealloc is - * indicated by the mapping size, start offset and the sizes + * indicated by the mapping size, start address and the sizes * of the areas mapped per PT or PD. The range calculation is * identical to that for the index into a table for a device * address, so we reuse those functions here. */ - const u32 l1_start_idx =3D pvr_page_table_l2_idx(sgt_offset); - const u32 l1_end_idx =3D pvr_page_table_l2_idx(sgt_offset + size); + const u32 l1_start_idx =3D pvr_page_table_l2_idx(start_addr); + const u32 l1_end_idx =3D pvr_page_table_l2_idx(start_addr + size); const u32 l1_count =3D l1_end_idx - l1_start_idx + 1; - const u32 l0_start_idx =3D pvr_page_table_l1_idx(sgt_offset); - const u32 l0_end_idx =3D pvr_page_table_l1_idx(sgt_offset + size); + const u32 l0_start_idx =3D pvr_page_table_l1_idx(start_addr); + const u32 l0_end_idx =3D pvr_page_table_l1_idx(start_addr + size); const u32 l0_count =3D l0_end_idx - l0_start_idx + 1; =20 /* diff --git a/drivers/gpu/drm/imagination/pvr_mmu.h b/drivers/gpu/drm/imagin= ation/pvr_mmu.h index a8ecd460168d..2c02d61ba0a2 100644 --- a/drivers/gpu/drm/imagination/pvr_mmu.h +++ b/drivers/gpu/drm/imagination/pvr_mmu.h @@ -99,7 +99,7 @@ dma_addr_t pvr_mmu_get_root_table_dma_addr(struct pvr_mmu= _context *ctx); void pvr_mmu_op_context_destroy(struct pvr_mmu_op_context *op_ctx); struct pvr_mmu_op_context * pvr_mmu_op_context_create(struct pvr_mmu_context *ctx, - struct sg_table *sgt, u64 sgt_offset, u64 size); + struct sg_table *sgt, u64 device_addr, u64 sgt_offset, u64 size); =20 int pvr_mmu_map(struct pvr_mmu_op_context *op_ctx, u64 size, u64 flags, u64 device_addr); diff --git a/drivers/gpu/drm/imagination/pvr_vm.c b/drivers/gpu/drm/imagina= tion/pvr_vm.c index 396d349fb6ce..867a4a44958a 100644 --- a/drivers/gpu/drm/imagination/pvr_vm.c +++ b/drivers/gpu/drm/imagination/pvr_vm.c @@ -276,7 +276,7 @@ pvr_vm_bind_op_map_init(struct pvr_vm_bind_op *bind_op, goto err_bind_op_fini; =20 bind_op->mmu_op_ctx =3D - pvr_mmu_op_context_create(vm_ctx->mmu_ctx, sgt, offset, size); + pvr_mmu_op_context_create(vm_ctx->mmu_ctx, sgt, device_addr, offset, siz= e); err =3D PTR_ERR_OR_ZERO(bind_op->mmu_op_ctx); if (err) { bind_op->mmu_op_ctx =3D NULL; @@ -318,7 +318,7 @@ pvr_vm_bind_op_unmap_init(struct pvr_vm_bind_op *bind_o= p, } =20 bind_op->mmu_op_ctx =3D - pvr_mmu_op_context_create(vm_ctx->mmu_ctx, NULL, 0, 0); + pvr_mmu_op_context_create(vm_ctx->mmu_ctx, NULL, device_addr, 0, 0); err =3D PTR_ERR_OR_ZERO(bind_op->mmu_op_ctx); if (err) { bind_op->mmu_op_ctx =3D NULL; --=20 2.43.0