From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28CD34B66D2; Fri, 18 Sep 2026 11:34:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731260; cv=none; b=dF4w6kMTpeh0tXw8hi9O5aXyVYOMPthYj/j6lD7igjHuOsqre4uSefIOKpC+EDxvDfRVQIHfx5s3d9eRp1renNI9eR87yCfY4XDpiSqNyrd5uUTPGZadMavniOKxbD05Q5XRcdZe+senTM7HbBWrlQOW4Y1Yjyp/CH7BNs22IrQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731260; c=relaxed/simple; bh=LhixG2fCAUNCT+8en6PrRgF6aAtHhOutp8kzJk8cL28=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=W3lR23P+e+LjbGjuMEPD00rEgOcEQMnbU9vaZlEhYJIwodIJUQESUXh/nZ98SgwAuCLNMkmbyWlELDasVHUR2Z5Tv7SCJTRwlomLZL1lsu7tKe5pvGhQshGhGwyvMQvS2rk5ejApIVEIFbFBzm0xvS0AVt+TCGCaET+fz6tBi+w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=X94jQLDs; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="X94jQLDs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1789731257; x=1821267257; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=LhixG2fCAUNCT+8en6PrRgF6aAtHhOutp8kzJk8cL28=; b=X94jQLDsqjVcjXfMi619Lgnw7LrT9XPnBjJD1PBshqWy5JKT4r0qhGyT hTleeeDPXHVkWN10CikBtO0GFsz3I6uYZyvV9PhYYNG2FJnoBTVPuk5Ig s7SLHfbiQwe617z16/duKJwxvjf1jyQqNNsLtSXNInpG24QRzcv5dmneH yWJ0l2eOYvSwc0uciKtR+q11h2VDkq2VziqBB8yZnuJKkcO3J2zRR2KZ8 i2qXORtGsvBKokB3R1QpLonuEo9decVUJgatO2qLCnpRZiloWyyfhzhOh 4Ayrw2yY1LMuFKbw6pDk8ixpg7eLmBacjq3NLQjcoq1Buoeui05rqQgxy A==; X-CSE-ConnectionGUID: dg8cqeJqSmOc+EtBdo31DA== X-CSE-MsgGUID: KN83PZ+MQK2vb0B5phUZeg== X-IronPort-AV: E=Sophos;i="6.27,108,1787036400"; d="scan'208";a="62877995" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 04:34:16 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Fri, 18 Sep 2026 04:34:15 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:12 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:33:53 +0200 Subject: [PATCH net-next v7 01/14] MAINTAINERS: add FDMA library to Sparx5 SoC entry Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-1-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 The FDMA library under drivers/net/ethernet/microchip/fdma/ is shared by the lan966x, sparx5 and lan969x drivers, but is not covered by an entry in the MAINTAINERS file. A subsequent patch will add new files to the FDMA library, so let's make sure it's covered. Add drivers/net/ethernet/microchip/fdma/ to the Sparx5 SoC entry, since I am already listed there. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index b23fb6f2f4ef..e41d4337136d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3214,6 +3214,7 @@ M: UNGLinuxDriver@microchip.com L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported F: arch/arm64/boot/dts/microchip/sparx* +F: drivers/net/ethernet/microchip/fdma/ F: drivers/net/ethernet/microchip/vcap/ F: drivers/pinctrl/pinctrl-microchip-sgpio.c N: sparx5 --=20 2.34.1 From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C40B4973BE; Fri, 18 Sep 2026 11:34:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731264; cv=none; b=Ia4ZvXknE3Z+r8p/GgcNnYenjJAdWE7PCfOz+OtskzKmAqoFbkF5/r9smoY1RfW0PNVozlcaHeoJ8mwGom/JWQ+wBpqfjh5tXAo7X1QI4DCOeqt8tDSxNqh0A37a9zY2ykRV5uIVBtffQaVaNx8rg3uHMLbiwqLbwGNkRMY94fE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731264; c=relaxed/simple; bh=Iy12tCl7T6s6ZRBeoiQcoNoKALMADqPH0I/xSE+s2mQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=XUmSxnpkMpeWRQS21yPyokBgo3ImgTy42ahi0O334y0dLRDYkPLL1sn8YPAa6XAra9uIeE0PonUoA/cAJ4dCBITASfRh3nJlOsrbtMYVybSqlcE1G5rpkts2HOo+IPfmNdDrnb10uLE+b0VYYCzmttSIaX65cEfQWIuVeUS5eKI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Mj9HHY68; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Mj9HHY68" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1789731262; x=1821267262; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=Iy12tCl7T6s6ZRBeoiQcoNoKALMADqPH0I/xSE+s2mQ=; b=Mj9HHY68JmH2JnG7+RdMJ4PRbGptO3itmtRYztQS6v2iPAOc5/oA4cT7 9OF3DmYd71aVyby15lJci/XwqrJE3dVnTcRskjO/NWofP+he+lZc71aSH XM5yJfaTu8Bio1qlB1iOwkyO4c7qd2GZ3GY7MXbl1DtlqFbKf9rYbsoQw XGefZu1FIcb/OKgBnw0DdruWt68AFIIuyryu5xhHICphcZsWq1xdybcgR 9Al/Yka6Y+MetCC7lg9OfAXb0sRsjntqoMrdl1JlkNSEYTqOJDBmlM9Ry rTD+RRka7nxRe4YoUaDHv7J6+iC1O6mX70y4D+0zJhhzSOwEJvmpQ/q94 Q==; X-CSE-ConnectionGUID: 8cdT/sOBSWm5lsOZnY2FOQ== X-CSE-MsgGUID: K7aEDpCZQ8iyJ3x6J6gLDw== X-IronPort-AV: E=Sophos;i="6.27,108,1787036400"; d="scan'208";a="64120987" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 Sep 2026 04:34:20 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 18 Sep 2026 04:34:19 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:16 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:33:54 +0200 Subject: [PATCH net-next v7 02/14] net: microchip: fdma: rename contiguous dataptr helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-2-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 When the FDMA library was introduced [1], two helpers to get the DMA and virtual address of a data buffer, in contiguous memory, were added. These helpers have had no callers until this series. I found the naming I initially used confusing and inconsistent. Rename fdma_dataptr_get_contiguous() and fdma_dataptr_virt_get_contiguous() to fdma_dataptr_dma_addr_contiguous() and fdma_dataptr_virt_addr_contiguous(). This makes the pair symmetric and clarifies what type of address each returns. [1]: commit 30e48a75df9c ("net: microchip: add FDMA library") Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- drivers/net/ethernet/microchip/fdma/fdma_api.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.h b/drivers/net/e= thernet/microchip/fdma/fdma_api.h index d91affe8bd98..dea8e3cc155a 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.h +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.h @@ -197,8 +197,8 @@ static inline int fdma_nextptr_cb(struct fdma *fdma, in= t dcb_idx, u64 *nextptr) * if the dataptr addresses and DCB's are in contiguous memory and the dri= ver * supports XDP. */ -static inline u64 fdma_dataptr_get_contiguous(struct fdma *fdma, int dcb_i= dx, - int db_idx) +static inline u64 fdma_dataptr_dma_addr_contiguous(struct fdma *fdma, + int dcb_idx, int db_idx) { return fdma->dma + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + (dcb_idx * fdma->n_dbs + db_idx) * fdma->db_size + @@ -209,8 +209,8 @@ static inline u64 fdma_dataptr_get_contiguous(struct fd= ma *fdma, int dcb_idx, * applicable if the dataptr addresses and DCB's are in contiguous memory = and * the driver supports XDP. */ -static inline void *fdma_dataptr_virt_get_contiguous(struct fdma *fdma, - int dcb_idx, int db_idx) +static inline void *fdma_dataptr_virt_addr_contiguous(struct fdma *fdma, + int dcb_idx, int db_idx) { return (u8 *)fdma->dcbs + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + (dcb_idx * fdma->n_dbs + db_idx) * fdma->db_size + --=20 2.34.1 From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C7394CDDD2; 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X-CSE-ConnectionGUID: bZTt7TbaTeWTq0SiTYnUig== X-CSE-MsgGUID: m9vowb6tRNm+yAZq9LLpSQ== X-IronPort-AV: E=Sophos;i="6.27,108,1787036400"; d="scan'208";a="64120988" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 04:34:24 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Fri, 18 Sep 2026 04:34:23 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:20 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:33:55 +0200 Subject: [PATCH net-next v7 03/14] net: microchip: fdma: add PCIe ATU support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-3-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 When lan966x or lan969x operates as a PCIe endpoint, the internal FDMA engine cannot directly access host memory. Instead, DMA addresses must be translated through the PCIe Address Translation Unit (ATU). The ATU provides outbound windows that map internal addresses to PCIe bus addresses. The ATU outbound address space (0x10000000-0x1fffffff) is divided into six equally-sized regions (~42MB each). When FDMA buffers are allocated, a free ATU region is claimed and programmed with the DMA target address. The FDMA engine then uses the region's base address in its descriptors, and the ATU translates these to the actual DMA addresses on the PCIe bus. Add the required functions and helpers that combine the DMA allocation with the ATU region mapping. These are used by the lan966x PCIe FDMA path. The ATU cannot express a limit finer than its 64KB region granularity, so pad the mapped allocation to that boundary; otherwise the outbound window would extend past the memory the host allocated for DMA. This implementation will also be used by the lan969x, when PCIe FDMA is added for that platform in the future. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- drivers/net/ethernet/microchip/fdma/Makefile | 4 + drivers/net/ethernet/microchip/fdma/fdma_api.c | 44 ++++++ drivers/net/ethernet/microchip/fdma/fdma_api.h | 14 ++ drivers/net/ethernet/microchip/fdma/fdma_pci.c | 208 +++++++++++++++++++++= ++++ drivers/net/ethernet/microchip/fdma/fdma_pci.h | 57 +++++++ 5 files changed, 327 insertions(+) diff --git a/drivers/net/ethernet/microchip/fdma/Makefile b/drivers/net/eth= ernet/microchip/fdma/Makefile index cc9a736be357..910a10b33fb9 100644 --- a/drivers/net/ethernet/microchip/fdma/Makefile +++ b/drivers/net/ethernet/microchip/fdma/Makefile @@ -5,3 +5,7 @@ =20 obj-$(CONFIG_FDMA) +=3D fdma.o fdma-y +=3D fdma_api.o + +ifneq ($(CONFIG_MCHP_LAN966X_PCI),) +fdma-y +=3D fdma_pci.o +endif diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.c b/drivers/net/e= thernet/microchip/fdma/fdma_api.c index e78c3590da9e..a3c9e3097c5c 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.c +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.c @@ -127,6 +127,50 @@ void fdma_free_phys(struct fdma *fdma) } EXPORT_SYMBOL_GPL(fdma_free_phys); =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +/* Allocate coherent DMA memory and map it in the ATU. */ +int fdma_alloc_coherent_and_map(struct device *dev, struct fdma *fdma, + struct fdma_pci_atu *atu) +{ + struct fdma_pci_atu_region *region; + int err; + + if (WARN_ON(fdma->atu_region)) + return -EBUSY; + + /* The ATU cannot express a limit finer than the region granularity, so + * the hardware widens the programmed limit to that boundary. Pad the + * allocation to match, or the outbound window would extend past the + * memory we own. + */ + fdma->size =3D ALIGN(fdma->size, FDMA_PCI_ATU_REGION_ALIGN); + + err =3D fdma_alloc_coherent(dev, fdma); + if (err) + return err; + + region =3D fdma_pci_atu_region_map(atu, fdma->dma, fdma->size); + if (IS_ERR(region)) { + fdma_free_coherent(dev, fdma); + return PTR_ERR(region); + } + + fdma->atu_region =3D region; + + return 0; +} +EXPORT_SYMBOL_GPL(fdma_alloc_coherent_and_map); + +/* Free coherent DMA memory and unmap the memory in the ATU. */ +void fdma_free_coherent_and_unmap(struct device *dev, struct fdma *fdma) +{ + fdma_pci_atu_region_unmap(fdma->atu_region); + fdma->atu_region =3D NULL; + fdma_free_coherent(dev, fdma); +} +EXPORT_SYMBOL_GPL(fdma_free_coherent_and_unmap); +#endif + /* Get the size of the FDMA memory */ u32 fdma_get_size(struct fdma *fdma) { diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.h b/drivers/net/e= thernet/microchip/fdma/fdma_api.h index dea8e3cc155a..ccc30d506e89 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.h +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.h @@ -7,6 +7,8 @@ #include #include =20 +#include "fdma_pci.h" + /* This provides a common set of functions and data structures for interac= ting * with the Frame DMA engine on multiple Microchip switchcores. * @@ -109,6 +111,11 @@ struct fdma { u32 channel_id; =20 struct fdma_ops ops; + +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + /* PCI ATU region for this FDMA instance. */ + struct fdma_pci_atu_region *atu_region; +#endif }; =20 /* Advance the DCB index and wrap if required. */ @@ -233,9 +240,16 @@ int __fdma_dcb_add(struct fdma *fdma, int dcb_idx, u64= info, u64 status, =20 int fdma_alloc_coherent(struct device *dev, struct fdma *fdma); int fdma_alloc_phys(struct fdma *fdma); +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +int fdma_alloc_coherent_and_map(struct device *dev, struct fdma *fdma, + struct fdma_pci_atu *atu); +#endif =20 void fdma_free_coherent(struct device *dev, struct fdma *fdma); void fdma_free_phys(struct fdma *fdma); +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +void fdma_free_coherent_and_unmap(struct device *dev, struct fdma *fdma); +#endif =20 u32 fdma_get_size(struct fdma *fdma); u32 fdma_get_size_contiguous(struct fdma *fdma); diff --git a/drivers/net/ethernet/microchip/fdma/fdma_pci.c b/drivers/net/e= thernet/microchip/fdma/fdma_pci.c new file mode 100644 index 000000000000..dd1dc46cbc9d --- /dev/null +++ b/drivers/net/ethernet/microchip/fdma/fdma_pci.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include + +#include "fdma_pci.h" + +/* When the switch operates as a PCIe endpoint, the FDMA engine needs to + * DMA to/from host memory. The FDMA writes to addresses within the endpoi= nt's + * internal Outbound (OB) address space, and the PCIe ATU translates these= to + * DMA addresses on the PCIe bus, targeting host memory. + * + * The ATU supports up to six outbound regions. This implementation divides + * the OB address space into six equally sized chunks. + * + * +-------------+------------+------------+-----+------------+ + * | Index | Region 0 | Region 1 | ... | Region 5 | + * +-------------+------------+------------+-----+------------+ + * | Base addr | 0x10000000 | 0x12aa0000 | ... | 0x1d520000 | + * | Limit addr | 0x12a9ffff | 0x1553ffff | ... | 0x1ffbffff | + * | Target addr | host dma | host dma | ... | host dma | + * +-------------+------------+------------+-----+------------+ + * + * Base addr is the start address of the region within the OB address spac= e. + * Limit addr is each region's own upper bound. The value actually + * programmed is set per-mapping as base_addr + mapped size - 1, and is + * usually smaller than this. + * Target addr is the host DMA address that the base addr translates to. + */ + +#define FDMA_PCI_ATU_OB_START 0x10000000 +#define FDMA_PCI_ATU_OB_END 0x1fffffff + +#define FDMA_PCI_ATU_ADDR 0x300000 +#define FDMA_PCI_ATU_IDX_SIZE 0x200 +#define FDMA_PCI_ATU_ENA_REG 0x4 +#define FDMA_PCI_ATU_ENA_BIT BIT(31) +#define FDMA_PCI_ATU_LWR_BASE_ADDR 0x8 +#define FDMA_PCI_ATU_UPP_BASE_ADDR 0xc +#define FDMA_PCI_ATU_LIMIT_ADDR 0x10 +#define FDMA_PCI_ATU_LWR_TARGET_ADDR 0x14 +#define FDMA_PCI_ATU_UPP_TARGET_ADDR 0x18 + +static u32 fdma_pci_atu_region_size(void) +{ + return round_down((FDMA_PCI_ATU_OB_END - FDMA_PCI_ATU_OB_START) / + FDMA_PCI_ATU_REGION_MAX, FDMA_PCI_ATU_REGION_ALIGN); +} + +static void __iomem *fdma_pci_atu_addr_get(void __iomem *addr, int offset, + int idx) +{ + return addr + FDMA_PCI_ATU_ADDR + FDMA_PCI_ATU_IDX_SIZE * idx + offset; +} + +static void fdma_pci_atu_region_enable(struct fdma_pci_atu_region *region) +{ + writel(FDMA_PCI_ATU_ENA_BIT, + fdma_pci_atu_addr_get(region->atu->addr, FDMA_PCI_ATU_ENA_REG, + region->idx)); +} + +static void fdma_pci_atu_region_disable(struct fdma_pci_atu_region *region) +{ + writel(0, fdma_pci_atu_addr_get(region->atu->addr, FDMA_PCI_ATU_ENA_REG, + region->idx)); +} + +/* Configure the address translation in the ATU. */ +static void +fdma_pci_atu_configure_translation(struct fdma_pci_atu_region *region) +{ + struct fdma_pci_atu *atu =3D region->atu; + int idx =3D region->idx; + + writel(lower_32_bits(region->base_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_LWR_BASE_ADDR, idx)); + + writel(upper_32_bits(region->base_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_UPP_BASE_ADDR, idx)); + + /* The OB address space lies entirely below 4GB, so the limit always + * fits the lower limit register and the upper one is left alone. + */ + writel(region->limit_addr, + fdma_pci_atu_addr_get(atu->addr, FDMA_PCI_ATU_LIMIT_ADDR, idx)); + + writel(lower_32_bits(region->target_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_LWR_TARGET_ADDR, idx)); + + writel(upper_32_bits(region->target_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_UPP_TARGET_ADDR, idx)); +} + +/* Find an unused ATU region. */ +static struct fdma_pci_atu_region * +fdma_pci_atu_region_get_free(struct fdma_pci_atu *atu) +{ + struct fdma_pci_atu_region *regions =3D atu->regions; + + for (int i =3D 0; i < FDMA_PCI_ATU_REGION_MAX; i++) { + if (regions[i].in_use) + continue; + + return ®ions[i]; + } + + return ERR_PTR(-ENOSPC); +} + +/* Unmap an ATU region, clearing its translation and disabling it. */ +void fdma_pci_atu_region_unmap(struct fdma_pci_atu_region *region) +{ + if (IS_ERR_OR_NULL(region)) + return; + + mutex_lock(®ion->atu->lock); + + region->target_addr =3D 0; + region->in_use =3D false; + + fdma_pci_atu_region_disable(region); + fdma_pci_atu_configure_translation(region); + + mutex_unlock(®ion->atu->lock); +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_region_unmap); + +/* Map a host DMA address into a free outbound region. */ +struct fdma_pci_atu_region * +fdma_pci_atu_region_map(struct fdma_pci_atu *atu, u64 target_addr, int siz= e) +{ + struct fdma_pci_atu_region *region; + + if (!atu) + return ERR_PTR(-EINVAL); + + if (size <=3D 0) + return ERR_PTR(-EINVAL); + + if (size > fdma_pci_atu_region_size()) + return ERR_PTR(-ERANGE); + + /* The ATU region base is only ever aligned to FDMA_PCI_ATU_REGION_ALIGN; + * require the same alignment of the host target address, since the ATU + * translates addr - target_addr + base_addr and any misalignment here + * would shift every translated address by the same amount. + */ + if (!IS_ALIGNED(target_addr, FDMA_PCI_ATU_REGION_ALIGN)) + return ERR_PTR(-EINVAL); + + mutex_lock(&atu->lock); + + region =3D fdma_pci_atu_region_get_free(atu); + if (IS_ERR(region)) { + mutex_unlock(&atu->lock); + return region; + } + + region->target_addr =3D target_addr; + region->limit_addr =3D region->base_addr + size - 1; + region->in_use =3D true; + + fdma_pci_atu_configure_translation(region); + fdma_pci_atu_region_enable(region); + + mutex_unlock(&atu->lock); + + return region; +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_region_map); + +/* Translate a host DMA address to the corresponding OB address. */ +u64 fdma_pci_atu_translate_addr(struct fdma_pci_atu_region *region, u64 ad= dr) +{ + return region->base_addr + (addr - region->target_addr); +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_translate_addr); + +/* Initialize ATU, dividing the OB space into equally sized regions. */ +void fdma_pci_atu_init(struct fdma_pci_atu *atu, void __iomem *addr) +{ + struct fdma_pci_atu_region *regions =3D atu->regions; + u32 region_size =3D fdma_pci_atu_region_size(); + + atu->addr =3D addr; + mutex_init(&atu->lock); + + for (int i =3D 0; i < FDMA_PCI_ATU_REGION_MAX; i++) { + regions[i].base_addr =3D + FDMA_PCI_ATU_OB_START + (i * region_size); + regions[i].limit_addr =3D 0; + regions[i].target_addr =3D 0; + regions[i].idx =3D i; + regions[i].atu =3D atu; + regions[i].in_use =3D false; + + fdma_pci_atu_region_disable(®ions[i]); + } +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_init); diff --git a/drivers/net/ethernet/microchip/fdma/fdma_pci.h b/drivers/net/e= thernet/microchip/fdma/fdma_pci.h new file mode 100644 index 000000000000..010bdb4d50b0 --- /dev/null +++ b/drivers/net/ethernet/microchip/fdma/fdma_pci.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _FDMA_PCI_H_ +#define _FDMA_PCI_H_ + +#include +#include +#include +#include + +#define FDMA_PCI_ATU_REGION_MAX 6 + +/* Outbound regions are 64KB granular (datasheet section 3.24.7.4.1), so b= oth + * the region base and the mapped size must be aligned to this. + */ +#define FDMA_PCI_ATU_REGION_ALIGN BIT(16) + +#define FDMA_PCI_DB_ALIGN 128 +#define FDMA_PCI_DB_SIZE(mtu) ALIGN(mtu, FDMA_PCI_DB_ALIGN) + +struct fdma_pci_atu; + +struct fdma_pci_atu_region { + struct fdma_pci_atu *atu; + u64 base_addr; /* Base addr of the OB window */ + u64 limit_addr; /* End addr of the active mapping (base_addr + size - 1) = */ + u64 target_addr; /* Host DMA address this region maps to */ + int idx; + bool in_use; +}; + +struct fdma_pci_atu { + void __iomem *addr; + struct mutex lock; /* Protects region alloc/free and ATU register access = */ + struct fdma_pci_atu_region regions[FDMA_PCI_ATU_REGION_MAX]; +}; + +/* Initialize ATU, dividing OB space into regions. */ +void fdma_pci_atu_init(struct fdma_pci_atu *atu, void __iomem *addr); + +/* Unmap an ATU region, clearing its translation and disabling it. */ +void fdma_pci_atu_region_unmap(struct fdma_pci_atu_region *region); + +/* Map a host DMA address into a free ATU region. target_addr and size mus= t be + * FDMA_PCI_ATU_REGION_ALIGN aligned; a misaligned target_addr returns -EI= NVAL. + */ +struct fdma_pci_atu_region *fdma_pci_atu_region_map(struct fdma_pci_atu *a= tu, + u64 target_addr, + int size); + +/* Translate a host DMA address to the OB address space. Reads the region + * unlocked, so the caller must quiesce DMA and the descriptor paths before + * unmapping the region. + */ +u64 fdma_pci_atu_translate_addr(struct fdma_pci_atu_region *region, u64 ad= dr); + +#endif --=20 2.34.1 From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 442454E4C4C; Fri, 18 Sep 2026 11:34:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731271; cv=none; b=dwmZFehFlfFFDp/CwkcI4ho/xcExmsHIiuEn8nWBqCvthlzSTjzIdW6IN04oGMZV++7QgAyxWAcjoRzQ0u3JqiMC4ykjBOAMNB0amU3fWUtGyfbDHpNiutzwgmlz/VYe/OZuwEWEynz9p6J7Il4DfKiovJuAa6Fj0RQvKJvZGDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731271; c=relaxed/simple; bh=QYGrFqOkLMGg0egcUveRB4ur4cCoutEpPPiq+t5aHao=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=szYzskqYrN6yb8kL0C6zniumKs8ruxU4OA6KCcEFmhRNC22cYeKnKcstszGlq8PR28BeDF6yCS1Pv/cv7HAD9mGohkfZ6J5xUlWlOU37TbLST30gxQvVr434ecs6emOpDsz/9cvNzxMXwTXjLgPA9IkFK0j/GqXlIWlqvJyLnNk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=0t6ZDKS2; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="0t6ZDKS2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1789731270; x=1821267270; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=QYGrFqOkLMGg0egcUveRB4ur4cCoutEpPPiq+t5aHao=; b=0t6ZDKS2d3tsohExScV77p0HrEJvsBRQQXHID7kewpnnlt0oTwanS8Hz wwfEocH7312Sgo2I5PX30ihFdKX/296fbWrvcKESYxBVQjPEt8V3dMYyO CUtjxnlmWvMQGXWOQaCSDdF9QFZTTcbnXYP44ShaxFVPD9v6jJuiTYWew dSHRq/+SRhfs+YWVaQisL23RMFxgRl72uzPvG3/ZlsAMT4fdnzEdCayX8 w2I+E8JnTKw6wAcqCCQ5ktrddoEMhAJUuFnv4zXOlBtsJUk+wGYtkcVXo 34jAgZjRJM/SU/Q1EySCfoEb68M8Frv+ovWORE41G2q8gLny0Z5+rLfxL Q==; X-CSE-ConnectionGUID: uo6KZvGdTLa58gFarbPKYA== X-CSE-MsgGUID: U1RNkHnpQXi54m3bcOSe6Q== X-IronPort-AV: E=Sophos;i="6.27,108,1787036400"; d="scan'208";a="295223728" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 04:34:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Fri, 18 Sep 2026 04:34:27 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:23 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:33:56 +0200 Subject: [PATCH net-next v7 04/14] net: lan966x: add FDMA LLP register write helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-4-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 The FDMA Link List Pointer (LLP) register points to the first DCB in the chain and must be written before the channel is activated. This tells the FDMA engine where to begin DMA transfers. Move the LLP register writes from the channel start/activate functions into the allocation functions and introduce a shared lan966x_fdma_llp_configure() helper. This is needed because the upcoming PCIe FDMA path writes ATU-translated addresses to the LLP registers instead of DMA addresses. Keeping the writes in the shared start/activate path would overwrite these translated addresses. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 30 ++++++++++--------= ---- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 41d4ec7f2f57..b8344fd5e5ad 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -109,6 +109,13 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan9= 66x_rx *rx) return 0; } =20 +static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) +{ + lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); + lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); +} + static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; @@ -128,6 +135,8 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), FDMA_DCB_STATUS_INTR); =20 + lan966x_fdma_llp_configure(lan966x, fdma->dma, fdma->channel_id); + return 0; } =20 @@ -137,14 +146,6 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *r= x) struct fdma *fdma =3D &rx->fdma; u32 mask; =20 - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -215,6 +216,8 @@ static int lan966x_fdma_tx_alloc(struct lan966x_tx *tx) =20 fdma_dcbs_init(fdma, 0, 0); =20 + lan966x_fdma_llp_configure(lan966x, fdma->dma, fdma->channel_id); + return 0; =20 out: @@ -236,14 +239,6 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx= *tx) struct fdma *fdma =3D &tx->fdma; u32 mask; =20 - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); 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18 Sep 2026 04:34:32 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 18 Sep 2026 04:34:31 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:27 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:33:57 +0200 Subject: [PATCH net-next v7 05/14] net: lan966x: export FDMA helpers for reuse Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-5-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Make shared FDMA helpers non-static, so they can be reused by the PCIe FDMA implementation. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 22 +++++++++++-------= ---- .../net/ethernet/microchip/lan966x/lan966x_main.h | 11 +++++++++++ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index b8344fd5e5ad..1311b79bd11f 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -109,8 +109,8 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan96= 6x_rx *rx) return 0; } =20 -static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, - u8 channel_id) +void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) { lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); @@ -140,7 +140,7 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) return 0; } =20 -static void lan966x_fdma_rx_start(struct lan966x_rx *rx) +void lan966x_fdma_rx_start(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -171,7 +171,7 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *rx) lan966x, FDMA_CH_ACTIVATE); } =20 -static void lan966x_fdma_rx_disable(struct lan966x_rx *rx) +void lan966x_fdma_rx_disable(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -191,7 +191,7 @@ static void lan966x_fdma_rx_disable(struct lan966x_rx *= rx) lan966x, FDMA_CH_DB_DISCARD); } =20 -static void lan966x_fdma_rx_reload(struct lan966x_rx *rx) +void lan966x_fdma_rx_reload(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; =20 @@ -264,7 +264,7 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx = *tx) lan966x, FDMA_CH_ACTIVATE); } =20 -static void lan966x_fdma_tx_disable(struct lan966x_tx *tx) +void lan966x_fdma_tx_disable(struct lan966x_tx *tx) { struct lan966x *lan966x =3D tx->lan966x; struct fdma *fdma =3D &tx->fdma; @@ -296,7 +296,7 @@ static void lan966x_fdma_tx_reload(struct lan966x_tx *t= x) lan966x, FDMA_CH_RELOAD); } =20 -static void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x) +void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x) { struct lan966x_port *port; int i; @@ -470,7 +470,7 @@ static struct sk_buff *lan966x_fdma_rx_get_frame(struct= lan966x_rx *rx, return NULL; } =20 -static int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight) +int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight) { struct lan966x *lan966x =3D container_of(napi, struct lan966x, napi); struct lan966x_rx *rx =3D &lan966x->rx; @@ -583,7 +583,7 @@ static int lan966x_fdma_get_next_dcb(struct lan966x_tx = *tx) return -1; } =20 -static void lan966x_fdma_tx_start(struct lan966x_tx *tx) +void lan966x_fdma_tx_start(struct lan966x_tx *tx) { struct lan966x *lan966x =3D tx->lan966x; =20 @@ -801,7 +801,7 @@ static int lan966x_fdma_get_max_mtu(struct lan966x *lan= 966x) return max_mtu; } =20 -static int lan966x_qsys_sw_status(struct lan966x *lan966x) +int lan966x_qsys_sw_status(struct lan966x *lan966x) { return lan_rd(lan966x, QSYS_SW_STATUS(CPU_PORT)); } @@ -883,7 +883,7 @@ static int lan966x_fdma_reload(struct lan966x *lan966x,= int new_mtu) return err; } =20 -static int lan966x_fdma_get_max_frame(struct lan966x *lan966x) +int lan966x_fdma_get_max_frame(struct lan966x *lan966x) { return lan966x_fdma_get_max_mtu(lan966x) + IFH_LEN_BYTES + diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index eea286c29474..83c361abb789 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -561,6 +561,17 @@ int lan966x_fdma_init(struct lan966x *lan966x); void lan966x_fdma_deinit(struct lan966x *lan966x); irqreturn_t lan966x_fdma_irq_handler(int irq, void *args); int lan966x_fdma_reload_page_pool(struct lan966x *lan966x); +int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight); 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d="scan'208";a="62877999" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 Sep 2026 04:34:35 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 18 Sep 2026 04:34:35 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:31 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:33:58 +0200 Subject: [PATCH net-next v7 06/14] net: lan966x: use a dedicated device for DMA operations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-6-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 In preparation for the PCIe FDMA implementation, add lan966x->dma_dev, resolved once at probe time, and use it for every DMA operation the FDMA path performs: coherent allocations, streaming mappings and the RX page pool. Natively, dma_dev is lan966x->dev, so there is no functional change. Since dma_dev differs from dev only on the PCIe path, add lan966x_is_pci() on top of it, for the later PCIe patches to key off. Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 30 +++++++++++-------= ---- .../net/ethernet/microchip/lan966x/lan966x_main.c | 16 ++++++++++++ .../net/ethernet/microchip/lan966x/lan966x_main.h | 10 ++++++++ 3 files changed, 41 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 1311b79bd11f..15fc59cb4ad7 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -80,7 +80,7 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan966x= _rx *rx) .flags =3D PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, .pool_size =3D rx->fdma.n_dcbs, .nid =3D NUMA_NO_NODE, - .dev =3D lan966x->dev, + .dev =3D lan966x->dma_dev, .dma_dir =3D DMA_FROM_DEVICE, .offset =3D XDP_PACKET_HEADROOM, .max_len =3D rx->max_mtu - @@ -126,7 +126,7 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) if (err) return err; =20 - err =3D fdma_alloc_coherent(lan966x->dev, fdma); + err =3D fdma_alloc_coherent(lan966x->dma_dev, fdma); if (err) { page_pool_destroy(rx->page_pool); return err; @@ -210,7 +210,7 @@ static int lan966x_fdma_tx_alloc(struct lan966x_tx *tx) if (!tx->dcbs_buf) return -ENOMEM; =20 - err =3D fdma_alloc_coherent(lan966x->dev, fdma); + err =3D fdma_alloc_coherent(lan966x->dma_dev, fdma); if (err) goto out; =20 @@ -230,7 +230,7 @@ static void lan966x_fdma_tx_free(struct lan966x_tx *tx) struct lan966x *lan966x =3D tx->lan966x; =20 kfree(tx->dcbs_buf); - fdma_free_coherent(lan966x->dev, &tx->fdma); + fdma_free_coherent(lan966x->dma_dev, &tx->fdma); } =20 static void lan966x_fdma_tx_activate(struct lan966x_tx *tx) @@ -355,7 +355,7 @@ static void lan966x_fdma_tx_clear_buf(struct lan966x *l= an966x, int weight) =20 dcb_buf->used =3D false; if (dcb_buf->use_skb) { - dma_unmap_single(lan966x->dev, + dma_unmap_single(lan966x->dma_dev, dcb_buf->dma_addr, dcb_buf->len, DMA_TO_DEVICE); @@ -364,7 +364,7 @@ static void lan966x_fdma_tx_clear_buf(struct lan966x *l= an966x, int weight) napi_consume_skb(dcb_buf->data.skb, weight); } else { if (dcb_buf->xdp_ndo) - dma_unmap_single(lan966x->dev, + dma_unmap_single(lan966x->dma_dev, dcb_buf->dma_addr, dcb_buf->len, DMA_TO_DEVICE); @@ -400,7 +400,7 @@ static int lan966x_fdma_rx_check_frame(struct lan966x_r= x *rx, u64 *src_port) if (unlikely(!page)) return FDMA_ERROR; =20 - dma_sync_single_for_cpu(lan966x->dev, + dma_sync_single_for_cpu(lan966x->dma_dev, (dma_addr_t)db->dataptr + XDP_PACKET_HEADROOM, FDMA_DCB_STATUS_BLOCKL(db->status), DMA_FROM_DEVICE); @@ -635,11 +635,11 @@ int lan966x_fdma_xmit_xdpf(struct lan966x_port *port,= void *ptr, u32 len) lan966x_ifh_set_bypass(ifh, 1); lan966x_ifh_set_port(ifh, BIT_ULL(port->chip_port)); =20 - dma_addr =3D dma_map_single(lan966x->dev, + dma_addr =3D dma_map_single(lan966x->dma_dev, xdpf->data - IFH_LEN_BYTES, xdpf->len + IFH_LEN_BYTES, DMA_TO_DEVICE); - if (dma_mapping_error(lan966x->dev, dma_addr)) { + if (dma_mapping_error(lan966x->dma_dev, dma_addr)) { ret =3D NETDEV_TX_OK; goto out; } @@ -655,7 +655,7 @@ int lan966x_fdma_xmit_xdpf(struct lan966x_port *port, v= oid *ptr, u32 len) lan966x_ifh_set_port(ifh, BIT_ULL(port->chip_port)); =20 dma_addr =3D page_pool_get_dma_addr(page); - dma_sync_single_for_device(lan966x->dev, + dma_sync_single_for_device(lan966x->dma_dev, dma_addr + XDP_PACKET_HEADROOM, len + IFH_LEN_BYTES, DMA_TO_DEVICE); @@ -734,9 +734,9 @@ int lan966x_fdma_xmit(struct sk_buff *skb, __be32 *ifh,= struct net_device *dev) memcpy(skb->data, ifh, IFH_LEN_BYTES); skb_put(skb, 4); =20 - dma_addr =3D dma_map_single(lan966x->dev, skb->data, skb->len, + dma_addr =3D dma_map_single(lan966x->dma_dev, skb->data, skb->len, DMA_TO_DEVICE); - if (dma_mapping_error(lan966x->dev, dma_addr)) { + if (dma_mapping_error(lan966x->dma_dev, dma_addr)) { dev->stats.tx_dropped++; err =3D NETDEV_TX_OK; goto release; @@ -842,7 +842,7 @@ static int lan966x_fdma_reload(struct lan966x *lan966x,= int new_mtu) page_pool_put_full_page(page_pool, old_pages[i][j], false); =20 - fdma_free_coherent(lan966x->dev, &fdma_rx_old); + fdma_free_coherent(lan966x->dma_dev, &fdma_rx_old); =20 page_pool_destroy(page_pool); =20 @@ -992,7 +992,7 @@ int lan966x_fdma_init(struct lan966x *lan966x) =20 err =3D lan966x_fdma_tx_alloc(&lan966x->tx); if (err) { - fdma_free_coherent(lan966x->dev, &lan966x->rx.fdma); + fdma_free_coherent(lan966x->dma_dev, &lan966x->rx.fdma); page_pool_destroy(lan966x->rx.page_pool); return err; } @@ -1014,7 +1014,7 @@ void lan966x_fdma_deinit(struct lan966x *lan966x) napi_disable(&lan966x->napi); =20 lan966x_fdma_rx_free_pages(&lan966x->rx); - fdma_free_coherent(lan966x->dev, &lan966x->rx.fdma); + fdma_free_coherent(lan966x->dma_dev, &lan966x->rx.fdma); page_pool_destroy(lan966x->rx.page_pool); lan966x_fdma_tx_free(&lan966x->tx); } diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 1179a6e127c5..2741f7c9fa4c 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1081,6 +1082,20 @@ static int lan966x_reset_switch(struct lan966x *lan9= 66x) return 0; } =20 +/* When enumerated over PCIe, dev is a platform device with no + * iommus/dma-ranges of its own, so DMA must target the PCIe endpoint inst= ead. + * The result differs from dev only in that case; lan966x_is_pci() relies = on it. + */ +static struct device *lan966x_get_dma_dev(struct device *dev) +{ + for (struct device *p =3D dev->parent; p; p =3D p->parent) { + if (dev_is_pci(p)) + return p; + } + + return dev; +} + static int lan966x_probe(struct platform_device *pdev) { struct fwnode_handle *ports, *portnp; @@ -1094,6 +1109,7 @@ static int lan966x_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, lan966x); lan966x->dev =3D &pdev->dev; + lan966x->dma_dev =3D lan966x_get_dma_dev(lan966x->dev); =20 if (!device_get_mac_address(&pdev->dev, mac_addr)) { ether_addr_copy(lan966x->base_mac, mac_addr); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index 83c361abb789..3f09f8ddf620 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -270,6 +270,9 @@ struct lan966x_skb_cb { struct lan966x { struct device *dev; =20 + /* Device used for DMA; the PCIe endpoint when enumerated over PCIe. */ + struct device *dma_dev; + u8 num_phys_ports; struct lan966x_port **ports; =20 @@ -573,6 +576,13 @@ void lan966x_fdma_wakeup_netdev(struct lan966x *lan966= x); int lan966x_fdma_get_max_frame(struct lan966x *lan966x); int lan966x_qsys_sw_status(struct lan966x *lan966x); =20 +/* dma_dev differs from dev only on the PCIe path. */ +static inline bool lan966x_is_pci(struct lan966x *lan966x) +{ + return IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) && + lan966x->dma_dev !=3D lan966x->dev; +} + int lan966x_lag_port_join(struct lan966x_port *port, struct net_device *brport_dev, struct net_device *bond, --=20 2.34.1 From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68CAB4EB85C; Fri, 18 Sep 2026 11:34:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="62878000" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 04:34:39 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Fri, 18 Sep 2026 04:34:39 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:35 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:33:59 +0200 Subject: [PATCH net-next v7 07/14] net: lan966x: add FDMA ops dispatch for PCIe support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-7-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Introduce lan966x_fdma_ops to support different FDMA implementations for platform and PCIe. Plumb fdma_init, fdma_deinit, fdma_xmit, fdma_poll and fdma_resize through the ops table, and select the implementation at probe time. Only the platform implementation exists at this point; the PCIe implementation is added in a later patch. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 2 +- .../net/ethernet/microchip/lan966x/lan966x_main.c | 20 +++++++++++++++-= ---- .../net/ethernet/microchip/lan966x/lan966x_main.h | 13 +++++++++++++ 3 files changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 15fc59cb4ad7..2695bc41e52a 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -947,7 +947,7 @@ void lan966x_fdma_netdev_init(struct lan966x *lan966x, = struct net_device *dev) return; =20 lan966x->fdma_ndev =3D dev; - netif_napi_add(dev, &lan966x->napi, lan966x_fdma_napi_poll); + netif_napi_add(dev, &lan966x->napi, lan966x->ops->fdma_poll); napi_enable(&lan966x->napi); } =20 diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 2741f7c9fa4c..6e6c08bb8eea 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -27,6 +27,14 @@ =20 #define IO_RANGES 2 =20 +static const struct lan966x_fdma_ops lan966x_fdma_ops =3D { + .fdma_init =3D &lan966x_fdma_init, + .fdma_deinit =3D &lan966x_fdma_deinit, + .fdma_xmit =3D &lan966x_fdma_xmit, + .fdma_poll =3D &lan966x_fdma_napi_poll, + .fdma_resize =3D &lan966x_fdma_change_mtu, +}; + static const struct of_device_id lan966x_match[] =3D { { .compatible =3D "microchip,lan966x-switch" }, { } @@ -392,7 +400,7 @@ static netdev_tx_t lan966x_port_xmit(struct sk_buff *sk= b, =20 spin_lock(&lan966x->tx_lock); if (port->lan966x->fdma) - err =3D lan966x_fdma_xmit(skb, ifh, dev); + err =3D lan966x->ops->fdma_xmit(skb, ifh, dev); else err =3D lan966x_port_ifh_xmit(skb, ifh, dev); spin_unlock(&lan966x->tx_lock); @@ -414,7 +422,7 @@ static int lan966x_port_change_mtu(struct net_device *d= ev, int new_mtu) if (!lan966x->fdma) return 0; =20 - err =3D lan966x_fdma_change_mtu(lan966x); + err =3D lan966x->ops->fdma_resize(lan966x); if (err) { lan_wr(DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(LAN966X_HW_MTU(old_mtu)), lan966x, DEV_MAC_MAXLEN_CFG(port->chip_port)); @@ -1111,6 +1119,8 @@ static int lan966x_probe(struct platform_device *pdev) lan966x->dev =3D &pdev->dev; lan966x->dma_dev =3D lan966x_get_dma_dev(lan966x->dev); =20 + lan966x->ops =3D &lan966x_fdma_ops; + if (!device_get_mac_address(&pdev->dev, mac_addr)) { ether_addr_copy(lan966x->base_mac, mac_addr); } else { @@ -1250,7 +1260,7 @@ static int lan966x_probe(struct platform_device *pdev) if (err) goto cleanup_fdb; =20 - err =3D lan966x_fdma_init(lan966x); + err =3D lan966x->ops->fdma_init(lan966x); if (err) goto cleanup_ptp; =20 @@ -1263,7 +1273,7 @@ static int lan966x_probe(struct platform_device *pdev) return 0; =20 cleanup_fdma: - lan966x_fdma_deinit(lan966x); + lan966x->ops->fdma_deinit(lan966x); =20 cleanup_ptp: lan966x_ptp_deinit(lan966x); @@ -1291,7 +1301,7 @@ static void lan966x_remove(struct platform_device *pd= ev) =20 lan966x_taprio_deinit(lan966x); lan966x_vcap_deinit(lan966x); - lan966x_fdma_deinit(lan966x); + lan966x->ops->fdma_deinit(lan966x); lan966x_cleanup_ports(lan966x); =20 cancel_delayed_work_sync(&lan966x->stats_work); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index 3f09f8ddf620..aab5e53ed059 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -193,6 +193,17 @@ enum vcap_is1_port_sel_rt { VCAP_IS1_PS_RT_FOLLOW_OTHER =3D 7, }; =20 +struct lan966x; + +struct lan966x_fdma_ops { + int (*fdma_init)(struct lan966x *lan966x); + void (*fdma_deinit)(struct lan966x *lan966x); + int (*fdma_xmit)(struct sk_buff *skb, __be32 *ifh, + struct net_device *dev); + int (*fdma_poll)(struct napi_struct *napi, int weight); + int (*fdma_resize)(struct lan966x *lan966x); +}; + struct lan966x_port; =20 struct lan966x_rx { @@ -273,6 +284,8 @@ struct lan966x { /* Device used for DMA; the PCIe endpoint when enumerated over PCIe. */ struct device *dma_dev; =20 + const struct lan966x_fdma_ops *ops; + u8 num_phys_ports; struct lan966x_port **ports; =20 --=20 2.34.1 From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 278264E9C20; Fri, 18 Sep 2026 11:34:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; 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d="scan'208";a="295223735" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 Sep 2026 04:34:44 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 18 Sep 2026 04:34:43 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:39 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:34:00 +0200 Subject: [PATCH net-next v7 08/14] net: lan966x: clear FDMA interrupt stickies after switch reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-8-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 When in PCI mode, the GCB soft reset issued by the reset controller can latch spurious bits in the FDMA error stickies. The latched bits sit in FDMA_INTR_ERR until the FDMA IRQ is requested later in probe, at which point the handler fires immediately and WARNs. Clear FDMA_ERRORS, FDMA_INTR_ERR and FDMA_INTR_DB right after the switch reset so the FDMA comes out clean and the IRQ handler does not see ghost errors on probe. The clear runs on both the PCI and platform paths. On the platform path it has no effect =E2=80=94 there are no spurious stickies to clear =E2= =80=94 but keeping it unconditional avoids a PCI-specific code path here. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- drivers/net/ethernet/microchip/lan966x/lan966x_main.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 6e6c08bb8eea..11094a381ec2 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -1067,6 +1067,15 @@ static int lan966x_reset_switch(struct lan966x *lan9= 66x) =20 reset_control_reset(switch_reset); =20 + /* When in PCI mode, the GCB soft reset issued by the reset + * controller can latch spurious bits in the FDMA error stickies. + * Clear them before request_irq hooks up the FDMA IRQ line, + * otherwise the handler fires immediately on probe. + */ + lan_wr(lan_rd(lan966x, FDMA_ERRORS), lan966x, FDMA_ERRORS); + lan_wr(lan_rd(lan966x, FDMA_INTR_ERR), lan966x, FDMA_INTR_ERR); + lan_wr(lan_rd(lan966x, FDMA_INTR_DB), lan966x, FDMA_INTR_DB); + /* Don't reinitialize the switch core, if it is already initialized. In * case it is initialized twice, some pointers inside the queue system * in HW will get corrupted and then after a while the queue system gets --=20 2.34.1 From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFD9E4E433C; Fri, 18 Sep 2026 11:34:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731291; cv=none; b=icPoUa2wYzJdTlURr5M4rU6ZZXGsPrn3BIP+co0MbJJLMu3OvukwL6MbRfAiME/ZzXqLvWoJEFml9D3qsKz5u9rxOTjPKtKhGfZGK7rtueM/tlw9QlsJYGbf1gBbHShmNTagmbLxBn7EgogBkZU3pcuo82S/m7oddBnDyjks5Ec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731291; c=relaxed/simple; bh=I+RMCp6el7em+a5tIhA0J/RX8bcnUi2aMV6+mV4DCp8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=jCu5uO85W1MnaUbtBgaTlgsTHpIH/AnV/ujD2R3EPXpM8iPRJGg2p4YEpDoFKgHKVGKgwkKW89UNEf79lfEL71odKh6kWmr7K6+c/tYRctthWqLRIysBhedNOJcNgkfBiwU8ByDQ1+p/grW2tfBz5nxRlqM1UWf/EfzTtuhp05A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=o+VErBJV; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="o+VErBJV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1789731288; x=1821267288; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=I+RMCp6el7em+a5tIhA0J/RX8bcnUi2aMV6+mV4DCp8=; b=o+VErBJV3VOrWAEWF44pH/g3TfukGEhoQSrjwRtaUVNIuMR1tDz9jPIg aFx5YWa9ddvD2UBAjSYv3qPn8TM2ezA2ONvKZkvN1bOLoJmlMWSWt69DS Mhw7z060VIXkiJT4B5tRTHkgoxDeZpGMesvvsFMn77VUbMGpM/4t8lvTd QoA+7tqJ8FT+m6AMAksXL8w3bBHvWcn0xjXHxqOCJnbQbV5IESPr9HNv9 vLlFf+aWMBiHaTKO4gtPwJr7SLVPj42VYHbjrX2xxN1k9ZVRTNTAZFD6h g7gxoeQulPlc7gUQgIr8ob0f4he7y0qFl6KaCv0X/3LDLpN25M0x4OpEe Q==; X-CSE-ConnectionGUID: FzjkXaHlTH+SGLvAfS4nvA== X-CSE-MsgGUID: vF2FsFq8SrGdhFAN5i7Xeg== X-IronPort-AV: E=Sophos;i="6.27,108,1787036400"; d="scan'208";a="62878001" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 Sep 2026 04:34:47 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 18 Sep 2026 04:34:47 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:43 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:34:01 +0200 Subject: [PATCH net-next v7 09/14] net: lan966x: add shutdown callback to stop the FDMA on reboot Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-9-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 As a PCIe endpoint, lan966x is not reset by a host reboot: its FDMA channels and interrupt sources stay armed, and the OIC ORs every source into the shared PCIe INTx, asserted before the driver has re-probed. A still-active channel also keeps write access to host memory the next kernel will reuse. Add a shutdown callback that: - frees the ana, xtr and FDMA irqs, masking and unmapping them at the OIC (disable_irq() would leave both set - the OIC has no irq_disable()) - masks the analyzer source, armed unconditionally by lan966x_init() and re-armed by the MAC table's age timer - stops and detaches the netdevs, draining in-flight xmit and clearing netif_device_present() so ndo_open/ndo_change_mtu cannot re-enter the FDMA against a disabled NAPI - disables both FDMA channels and masks their interrupts - unmaps the outbound ATU windows, leaving none armed NAPI is skipped when fdma_ndev is unset (a probed switch with no usable port never adds one), and XDP attach cannot re-enter either, since lan966x_xdp_setup() returns early on PCIe before touching the FDMA. Only the PCIe instantiation needs this - the SoC one resets with the chip - so the callback returns early on a platform device; the check is at runtime since .shutdown belongs to the driver, and a PCIe-enabled kernel binds both. FDMA_INTR_ENA persists across a warm reboot, so also restore the full enable in lan966x_fdma_rx_start(), run after both rings are allocated, re-arming both backends from one site. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 4 ++ .../net/ethernet/microchip/lan966x/lan966x_main.c | 56 ++++++++++++++++++= ++++ .../net/ethernet/microchip/lan966x/lan966x_regs.h | 15 ++++++ 3 files changed, 75 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 2695bc41e52a..6fb2482eeb17 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -146,6 +146,10 @@ void lan966x_fdma_rx_start(struct lan966x_rx *rx) struct fdma *fdma =3D &rx->fdma; u32 mask; =20 + lan_wr(FDMA_INTR_ENA_INTR_PORT_ENA_SET(GENMASK(1, 0)) | + FDMA_INTR_ENA_INTR_CH_ENA_SET(GENMASK(7, 0)), + lan966x, FDMA_INTR_ENA); + lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 11094a381ec2..2c1e2bc12024 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -1324,9 +1324,65 @@ static void lan966x_remove(struct platform_device *p= dev) debugfs_remove_recursive(lan966x->debugfs_root); } =20 +static void lan966x_shutdown(struct platform_device *pdev) +{ + struct lan966x *lan966x =3D platform_get_drvdata(pdev); + + /* As a PCIe endpoint the switch is not reset by the host reboot, so it + * has to be quiesced here: + * + * Free the irqs and mask the sources: no source can assert INTx. + * Disable NAPI: the teardown must not race a poll. + * Stop and detach the netdevs: drains xmit, closes ndo_open and MTU. + * Stop the FDMA channels: waits for the engine to go idle. + * Unmap the ATU windows: revokes the engine's access to host memory. + */ + if (!lan966x_is_pci(lan966x)) + return; + + if (lan966x->xtr_irq > 0) + devm_free_irq(lan966x->dev, lan966x->xtr_irq, lan966x); + if (lan966x->ana_irq > 0) + devm_free_irq(lan966x->dev, lan966x->ana_irq, lan966x); + if (lan966x->fdma_irq > 0) + devm_free_irq(lan966x->dev, lan966x->fdma_irq, lan966x); + + lan_wr(0, lan966x, ANA_ANAINTR); + + if (!lan966x->fdma) + return; + + rtnl_lock(); + + if (lan966x->fdma_ndev) + napi_disable(&lan966x->napi); + + for (int p =3D 0; p < lan966x->num_phys_ports; p++) { + if (!lan966x->ports[p] || !lan966x->ports[p]->dev) + continue; + + netif_tx_disable(lan966x->ports[p]->dev); + netif_device_detach(lan966x->ports[p]->dev); + } + + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + + lan_wr(0, lan966x, FDMA_INTR_ENA); + lan_wr(0, lan966x, FDMA_INTR_DB_ENA); + +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + fdma_pci_atu_region_unmap(lan966x->rx.fdma.atu_region); + fdma_pci_atu_region_unmap(lan966x->tx.fdma.atu_region); +#endif + + rtnl_unlock(); +} + static struct platform_driver lan966x_driver =3D { .probe =3D lan966x_probe, .remove =3D lan966x_remove, + .shutdown =3D lan966x_shutdown, .driver =3D { .name =3D "lan966x-switch", .of_match_table =3D lan966x_match, diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_regs.h index 4b553927d2e0..aba0d36ae6b5 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h @@ -1039,6 +1039,21 @@ enum lan966x_target { /* FDMA:FDMA:FDMA_INTR_ERR */ #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 00, 0, 1, 4) =20 +/* FDMA:FDMA:FDMA_INTR_ENA */ +#define FDMA_INTR_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 04, 0, 1, 4) + +#define FDMA_INTR_ENA_INTR_PORT_ENA GENMASK(9, 8) +#define FDMA_INTR_ENA_INTR_PORT_ENA_SET(x)\ + FIELD_PREP(FDMA_INTR_ENA_INTR_PORT_ENA, x) +#define FDMA_INTR_ENA_INTR_PORT_ENA_GET(x)\ + FIELD_GET(FDMA_INTR_ENA_INTR_PORT_ENA, x) + +#define FDMA_INTR_ENA_INTR_CH_ENA GENMASK(7, 0) +#define FDMA_INTR_ENA_INTR_CH_ENA_SET(x)\ + FIELD_PREP(FDMA_INTR_ENA_INTR_CH_ENA, x) +#define FDMA_INTR_ENA_INTR_CH_ENA_GET(x)\ + FIELD_GET(FDMA_INTR_ENA_INTR_CH_ENA, x) + /* FDMA:FDMA:FDMA_ERRORS */ #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 12, 0, 1, 4) =20 --=20 2.34.1 From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD8043914E9; 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X-CSE-ConnectionGUID: peD+uZCFRx64PW1MGkf/3Q== X-CSE-MsgGUID: /lyk+MOSSOG7HsuKLh/eOg== X-IronPort-AV: E=Sophos;i="6.27,108,1787036400"; d="scan'208";a="63804820" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 04:34:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Fri, 18 Sep 2026 04:34:51 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:47 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:34:02 +0200 Subject: [PATCH net-next v7 10/14] net: lan966x: add PCIe FDMA support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-10-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Add PCIe FDMA support for lan966x. The PCIe FDMA path uses contiguous DMA buffers mapped through the endpoint's ATU, with memcpy-based frame transfer instead of per-page DMA mappings. With PCIe FDMA, throughput increases from ~33 Mbps (register-based I/O) to ~620 Mbps on an Intel x86 host with a lan966x PCIe card. XDP is not supported on this path yet, so do not advertise xdp_features and reject program attach for PCIe instances. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan966x/Makefile | 4 + .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 421 +++++++++++++++++= ++++ .../net/ethernet/microchip/lan966x/lan966x_main.c | 11 +- .../net/ethernet/microchip/lan966x/lan966x_main.h | 7 + .../net/ethernet/microchip/lan966x/lan966x_regs.h | 10 + .../net/ethernet/microchip/lan966x/lan966x_xdp.c | 6 + 6 files changed, 456 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/Makefile b/drivers/net/= ethernet/microchip/lan966x/Makefile index 4cdbe263502c..02db4d4d9826 100644 --- a/drivers/net/ethernet/microchip/lan966x/Makefile +++ b/drivers/net/ethernet/microchip/lan966x/Makefile @@ -18,6 +18,10 @@ lan966x-switch-objs :=3D lan966x_main.o lan966x_phylink= .o lan966x_port.o \ lan966x-switch-$(CONFIG_LAN966X_DCB) +=3D lan966x_dcb.o lan966x-switch-$(CONFIG_DEBUG_FS) +=3D lan966x_vcap_debugfs.o =20 +ifneq ($(CONFIG_MCHP_LAN966X_PCI),) +lan966x-switch-y +=3D lan966x_fdma_pci.o +endif + # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/vcap ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/fdma diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c new file mode 100644 index 000000000000..5d6902459f20 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "fdma_api.h" +#include "lan966x_main.h" + +static int lan966x_fdma_pci_dataptr_cb(struct fdma *fdma, int dcb, int db, + u64 *dataptr) +{ + u64 addr; + + addr =3D fdma_dataptr_dma_addr_contiguous(fdma, dcb, db); + + *dataptr =3D fdma_pci_atu_translate_addr(fdma->atu_region, addr); + + return 0; +} + +static int lan966x_fdma_pci_nextptr_cb(struct fdma *fdma, int dcb, u64 *ne= xtptr) +{ + u64 addr; + + fdma_nextptr_cb(fdma, dcb, &addr); + + *nextptr =3D fdma_pci_atu_translate_addr(fdma->atu_region, addr); + + return 0; +} + +/* Stop the TX queues on every port, so nothing feeds the injection channel + * while it is torn down or resized. + */ +static void lan966x_fdma_tx_disable_netdev(struct lan966x *lan966x) +{ + struct lan966x_port *port; + int i; + + for (i =3D 0; i < lan966x->num_phys_ports; ++i) { + port =3D lan966x->ports[i]; + if (!port) + continue; + + netif_tx_disable(port->dev); + } +} + +static int lan966x_fdma_pci_rx_alloc(struct lan966x_rx *rx) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + int err; + + err =3D fdma_alloc_coherent_and_map(lan966x->dma_dev, fdma, + &lan966x->atu); + if (err) + return err; + + err =3D fdma_dcbs_init(fdma, + FDMA_DCB_INFO_DATAL(fdma->db_size - XDP_PACKET_HEADROOM), + FDMA_DCB_STATUS_INTR); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dma_dev, fdma); + return err; + } + + lan966x_fdma_llp_configure(lan966x, + fdma->atu_region->base_addr, + fdma->channel_id); + + return 0; +} + +static int lan966x_fdma_pci_tx_alloc(struct lan966x_tx *tx) +{ + struct lan966x *lan966x =3D tx->lan966x; + struct fdma *fdma =3D &tx->fdma; + int err; + + err =3D fdma_alloc_coherent_and_map(lan966x->dma_dev, fdma, + &lan966x->atu); + if (err) + return err; + + err =3D fdma_dcbs_init(fdma, + FDMA_DCB_INFO_DATAL(fdma->db_size), + FDMA_DCB_STATUS_DONE); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dma_dev, fdma); + return err; + } + + lan966x_fdma_llp_configure(lan966x, + fdma->atu_region->base_addr, + fdma->channel_id); + + return 0; +} + +static int lan966x_fdma_pci_get_next_dcb(struct fdma *fdma) +{ + struct fdma_db *db; + + for (int i =3D 0; i < fdma->n_dcbs; i++) { + db =3D fdma_db_get(fdma, i, 0); + + if (!fdma_db_is_done(db)) + continue; + if (fdma_is_last(fdma, &fdma->dcbs[i])) + continue; + + return i; + } + + return -ENOSPC; +} + +/* TX slot layout (sizes in bytes): + * + * +---------------------+-----+---------+-----+ + * | XDP_PACKET_HEADROOM | IFH | payload | FCS | + * | 256 | 28 | len | 4 | + * +---------------------+-----+---------+-----+ + * |<---------------- db_size ----------------->| + * + * Return true if the frame plus required overhead fits. + */ +static bool lan966x_fdma_pci_tx_size_fits(struct fdma *fdma, u32 len) +{ + return XDP_PACKET_HEADROOM + IFH_LEN_BYTES + len + ETH_FCS_LEN <=3D + fdma->db_size; +} + +/* Return true if blockl is a valid RX frame size. */ +static bool lan966x_fdma_pci_rx_size_fits(struct fdma *fdma, u32 blockl) +{ + return blockl >=3D IFH_LEN_BYTES + ETH_HLEN + ETH_FCS_LEN && + blockl <=3D fdma->db_size - XDP_PACKET_HEADROOM; +} + +static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + struct lan966x_port *port; + struct fdma_db *db; + void *virt_addr; + u32 blockl; + + /* virt_addr points to the IFH. */ + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, + fdma->dcb_index, + fdma->db_index); + + lan966x_ifh_get_src_port(virt_addr, src_port); + + if (*src_port >=3D lan966x->num_phys_ports) + return FDMA_ERROR; + + port =3D lan966x->ports[*src_port]; + if (!port) + return FDMA_ERROR; + + db =3D fdma_db_next_get(fdma); + + /* BLOCKL is a 16-bit HW-populated field; reject obviously-bad + * values before they feed memcpy/XDP sizes. + */ + blockl =3D FDMA_DCB_STATUS_BLOCKL(db->status); + if (!lan966x_fdma_pci_rx_size_fits(fdma, blockl)) + return FDMA_ERROR; + + return FDMA_PASS; +} + +static struct sk_buff *lan966x_fdma_pci_rx_get_frame(struct lan966x_rx *rx, + u64 src_port) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + struct sk_buff *skb; + struct fdma_db *db; + u32 data_len; + + /* Get the received frame and create an SKB for it. */ + db =3D fdma_db_next_get(fdma); + data_len =3D FDMA_DCB_STATUS_BLOCKL(db->status); + + skb =3D napi_alloc_skb(&lan966x->napi, data_len); + if (unlikely(!skb)) + return NULL; + + memcpy(skb->data, + fdma_dataptr_virt_addr_contiguous(fdma, + fdma->dcb_index, + fdma->db_index), + data_len); + + skb_put(skb, data_len); + + skb->dev =3D lan966x->ports[src_port]->dev; + skb_pull(skb, IFH_LEN_BYTES); + + skb_trim(skb, skb->len - ETH_FCS_LEN); + + skb->protocol =3D eth_type_trans(skb, skb->dev); + + if (lan966x->bridge_mask & BIT(src_port)) { + skb->offload_fwd_mark =3D 1; + + skb_reset_network_header(skb); + if (!lan966x_hw_offload(lan966x, src_port, skb)) + skb->offload_fwd_mark =3D 0; + } + + skb->dev->stats.rx_bytes +=3D skb->len; + skb->dev->stats.rx_packets++; + + return skb; +} + +static int lan966x_fdma_pci_xmit(struct sk_buff *skb, __be32 *ifh, + struct net_device *dev) +{ + struct lan966x_port *port =3D netdev_priv(dev); + struct lan966x *lan966x =3D port->lan966x; + struct lan966x_tx *tx =3D &lan966x->tx; + struct fdma *fdma =3D &tx->fdma; + int next_to_use; + void *virt_addr; + + next_to_use =3D lan966x_fdma_pci_get_next_dcb(fdma); + + if (next_to_use < 0) { + netif_stop_queue(dev); + return NETDEV_TX_BUSY; + } + + if (skb_put_padto(skb, ETH_ZLEN)) { + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + + if (!lan966x_fdma_pci_tx_size_fits(fdma, skb->len)) { + dev_kfree_skb_any(skb); + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + + skb_tx_timestamp(skb); + + /* virt_addr points to the IFH. */ + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, next_to_use, 0); + memcpy(virt_addr, ifh, IFH_LEN_BYTES); + memcpy(virt_addr + IFH_LEN_BYTES, skb->data, skb->len); + + /* Order frame write before DCB status write below. */ + dma_wmb(); + + fdma_dcb_add(fdma, + next_to_use, + 0, + FDMA_DCB_STATUS_INTR | + FDMA_DCB_STATUS_SOF | + FDMA_DCB_STATUS_EOF | + FDMA_DCB_STATUS_BLOCKO(0) | + FDMA_DCB_STATUS_BLOCKL(IFH_LEN_BYTES + skb->len + ETH_FCS_LEN)); + + /* Start the transmission. */ + lan966x_fdma_tx_start(tx); + + dev->stats.tx_bytes +=3D skb->len; + dev->stats.tx_packets++; + + /* Safe to free: PTP is not supported on the PCIe path yet, + * so lan966x->ptp is always 0 here. + */ + dev_consume_skb_any(skb); + + return NETDEV_TX_OK; +} + +static int lan966x_fdma_pci_napi_poll(struct napi_struct *napi, int weight) +{ + struct lan966x *lan966x =3D container_of(napi, struct lan966x, napi); + struct lan966x_rx *rx =3D &lan966x->rx; + struct fdma *fdma =3D &rx->fdma; + int dcb_reload, old_dcb; + struct sk_buff *skb; + int counter =3D 0; + u64 src_port; + + /* Wake any stopped TX queues if a TX DCB is available. */ + spin_lock(&lan966x->tx_lock); + if (lan966x_fdma_pci_get_next_dcb(&lan966x->tx.fdma) >=3D 0) + lan966x_fdma_wakeup_netdev(lan966x); + spin_unlock(&lan966x->tx_lock); + + dcb_reload =3D fdma->dcb_index; + + /* Get all received skbs. */ + while (counter < weight) { + if (!fdma_has_frames(fdma)) + break; + /* Order DONE read before DCB/frame reads below. */ + dma_rmb(); + counter++; + switch (lan966x_fdma_pci_rx_check_frame(rx, &src_port)) { + case FDMA_PASS: + break; + case FDMA_ERROR: + /* No rx_dropped increment here because src_port is + * invalid. + */ + fdma_dcb_advance(fdma); + continue; + } + skb =3D lan966x_fdma_pci_rx_get_frame(rx, src_port); + fdma_dcb_advance(fdma); + if (!skb) { + lan966x->ports[src_port]->dev->stats.rx_dropped++; + continue; + } + + napi_gro_receive(&lan966x->napi, skb); + } + while (dcb_reload !=3D fdma->dcb_index) { + old_dcb =3D dcb_reload; + dcb_reload++; + dcb_reload &=3D fdma->n_dcbs - 1; + + fdma_dcb_add(fdma, + old_dcb, + FDMA_DCB_INFO_DATAL(fdma->db_size - XDP_PACKET_HEADROOM), + FDMA_DCB_STATUS_INTR); + + lan966x_fdma_rx_reload(rx); + } + + if (counter < weight && napi_complete_done(napi, counter)) + lan_wr(0xff, lan966x, FDMA_INTR_DB_ENA); + + return counter; +} + +static int lan966x_fdma_pci_init(struct lan966x *lan966x) +{ + struct fdma *rx_fdma =3D &lan966x->rx.fdma; + struct fdma *tx_fdma =3D &lan966x->tx.fdma; + int err; + + if (!lan966x->fdma) + return 0; + + lan_wr(FDMA_CTRL_NRESET_SET(0), lan966x, FDMA_CTRL); + lan_wr(FDMA_CTRL_NRESET_SET(1), lan966x, FDMA_CTRL); + + fdma_pci_atu_init(&lan966x->atu, lan966x->regs[TARGET_PCIE_DBI]); + + lan966x->rx.lan966x =3D lan966x; + lan966x->rx.max_mtu =3D lan966x_fdma_get_max_frame(lan966x); + rx_fdma->channel_id =3D FDMA_XTR_CHANNEL; + rx_fdma->n_dcbs =3D FDMA_DCB_MAX; + rx_fdma->n_dbs =3D FDMA_RX_DCB_MAX_DBS; + rx_fdma->priv =3D lan966x; + rx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + rx_fdma->size =3D fdma_get_size_contiguous(rx_fdma); + rx_fdma->ops.nextptr_cb =3D &lan966x_fdma_pci_nextptr_cb; + rx_fdma->ops.dataptr_cb =3D &lan966x_fdma_pci_dataptr_cb; + + lan966x->tx.lan966x =3D lan966x; + tx_fdma->channel_id =3D FDMA_INJ_CHANNEL; + tx_fdma->n_dcbs =3D FDMA_DCB_MAX; + tx_fdma->n_dbs =3D FDMA_TX_DCB_MAX_DBS; + tx_fdma->priv =3D lan966x; + tx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + tx_fdma->size =3D fdma_get_size_contiguous(tx_fdma); + tx_fdma->ops.nextptr_cb =3D &lan966x_fdma_pci_nextptr_cb; + tx_fdma->ops.dataptr_cb =3D &lan966x_fdma_pci_dataptr_cb; + + err =3D lan966x_fdma_pci_rx_alloc(&lan966x->rx); + if (err) + return err; + + err =3D lan966x_fdma_pci_tx_alloc(&lan966x->tx); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dma_dev, rx_fdma); + return err; + } + + lan966x_fdma_rx_start(&lan966x->rx); + + return 0; +} + +static int lan966x_fdma_pci_resize(struct lan966x *lan966x) +{ + return -EOPNOTSUPP; +} + +static void lan966x_fdma_pci_deinit(struct lan966x *lan966x) +{ + if (!lan966x->fdma) + return; + + if (lan966x->fdma_ndev) + napi_disable(&lan966x->napi); + + lan966x_fdma_tx_disable_netdev(lan966x); + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + + fdma_free_coherent_and_unmap(lan966x->dma_dev, &lan966x->rx.fdma); + fdma_free_coherent_and_unmap(lan966x->dma_dev, &lan966x->tx.fdma); +} + +const struct lan966x_fdma_ops lan966x_fdma_pci_ops =3D { + .fdma_init =3D &lan966x_fdma_pci_init, + .fdma_deinit =3D &lan966x_fdma_pci_deinit, + .fdma_xmit =3D &lan966x_fdma_pci_xmit, + .fdma_poll =3D &lan966x_fdma_pci_napi_poll, + .fdma_resize =3D &lan966x_fdma_pci_resize, +}; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 2c1e2bc12024..c803619d83e2 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -50,6 +50,7 @@ struct lan966x_main_io_resource { static const struct lan966x_main_io_resource lan966x_main_iomap[] =3D { { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ + { TARGET_PCIE_DBI, 0x400000, 0 }, /* 0xe0400000 */ { TARGET_ORG, 0, 1 }, /* 0xe2000000 */ { TARGET_GCB, 0x4000, 1 }, /* 0xe2004000 */ { TARGET_QS, 0x8000, 1 }, /* 0xe2008000 */ @@ -873,7 +874,8 @@ static int lan966x_probe_port(struct lan966x *lan966x, = u32 p, =20 port->phylink =3D phylink; =20 - if (lan966x->fdma) + /* XDP is not supported on the PCIe FDMA path. */ + if (lan966x->fdma && !lan966x_is_pci(lan966x)) dev->xdp_features =3D NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | NETDEV_XDP_ACT_NDO_XMIT; @@ -1128,7 +1130,8 @@ static int lan966x_probe(struct platform_device *pdev) lan966x->dev =3D &pdev->dev; lan966x->dma_dev =3D lan966x_get_dma_dev(lan966x->dev); =20 - lan966x->ops =3D &lan966x_fdma_ops; + lan966x->ops =3D lan966x_is_pci(lan966x) ? &lan966x_fdma_pci_ops : + &lan966x_fdma_ops; =20 if (!device_get_mac_address(&pdev->dev, mac_addr)) { ether_addr_copy(lan966x->base_mac, mac_addr); @@ -1187,7 +1190,9 @@ static int lan966x_probe(struct platform_device *pdev) if (err) return dev_err_probe(&pdev->dev, err, "Unable to use ptp irq"); =20 - lan966x->ptp =3D 1; + /* PTP is not supported on the PCIe path yet. */ + if (!lan966x_is_pci(lan966x)) + lan966x->ptp =3D 1; } =20 lan966x->fdma_irq =3D platform_get_irq_byname(pdev, "fdma"); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index aab5e53ed059..16bc28c8f11f 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -17,6 +17,7 @@ #include =20 #include +#include #include #include =20 @@ -291,6 +292,10 @@ struct lan966x { =20 void __iomem *regs[NUM_TARGETS]; =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + struct fdma_pci_atu atu; +#endif + int shared_queue_sz; =20 u8 base_mac[ETH_ALEN]; @@ -589,6 +594,8 @@ void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x= ); int lan966x_fdma_get_max_frame(struct lan966x *lan966x); int lan966x_qsys_sw_status(struct lan966x *lan966x); =20 +extern const struct lan966x_fdma_ops lan966x_fdma_pci_ops; + /* dma_dev differs from dev only on the PCIe path. */ static inline bool lan966x_is_pci(struct lan966x *lan966x) { diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_regs.h index aba0d36ae6b5..4778ea217673 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h @@ -20,6 +20,7 @@ enum lan966x_target { TARGET_FDMA =3D 21, TARGET_GCB =3D 27, TARGET_ORG =3D 36, + TARGET_PCIE_DBI =3D 40, TARGET_PTP =3D 41, TARGET_QS =3D 42, TARGET_QSYS =3D 46, @@ -1009,6 +1010,15 @@ enum lan966x_target { #define FDMA_CH_CFG_CH_MEM_GET(x)\ FIELD_GET(FDMA_CH_CFG_CH_MEM, x) =20 +/* FDMA:FDMA:FDMA_CTRL */ +#define FDMA_CTRL __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 24, 0, 1, 4) + +#define FDMA_CTRL_NRESET BIT(0) +#define FDMA_CTRL_NRESET_SET(x)\ + FIELD_PREP(FDMA_CTRL_NRESET, x) +#define FDMA_CTRL_NRESET_GET(x)\ + FIELD_GET(FDMA_CTRL_NRESET, x) + /* FDMA:FDMA:FDMA_PORT_CTRL */ #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 3= 76, r, 2, 4) =20 diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c b/drivers= /net/ethernet/microchip/lan966x/lan966x_xdp.c index 9ee61db8690b..e63634887f64 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c @@ -20,6 +20,12 @@ static int lan966x_xdp_setup(struct net_device *dev, str= uct netdev_bpf *xdp) return -EOPNOTSUPP; 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Fri, 18 Sep 2026 04:34:55 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:51 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:34:03 +0200 Subject: [PATCH net-next v7 11/14] net: lan966x: add PCIe FDMA MTU change support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-11-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Add MTU change support for the PCIe FDMA path: on an MTU change, the contiguous ATU-mapped RX and TX buffers are reallocated at the new size, falling back to the existing buffers on failure. Cap the PCIe DCB ring at 256 (FDMA_PCI_DCB_MAX): 512 DCBs would overflow MAX_PAGE_ORDER at jumbo MTU. The ring must fit one MAX_PAGE_ORDER block after ATU padding, and db_size is handed to the FDMA in the 16-bit DCB DATAL field. Advertise the resulting limit in dev->max_mtu (FDMA_PCI_MAX_MTU) when the FDMA is in use - a switch with no "fdma" interrupt named uses the unconstrained register-based path instead, so the cap is gated on lan966x->fdma, not lan966x_is_pci() alone. On a 4KB-page, MAX_PAGE_ORDER=3D10 build this is MTU 15498; the overhead is shared with lan966x_fdma_get_max_frame() via FDMA_OVERHEAD. Skip the resize until lan966x_fdma_pci_init() has built the rings; it runs after the netdevs register and sizes them from DEV_MAC_MAXLEN_CFG, already programmed by the caller. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 6 +- .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 153 +++++++++++++++++= +++- .../net/ethernet/microchip/lan966x/lan966x_main.c | 3 +- .../net/ethernet/microchip/lan966x/lan966x_main.h | 28 ++++ 4 files changed, 181 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 6fb2482eeb17..81103b94e36f 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -889,11 +889,7 @@ static int lan966x_fdma_reload(struct lan966x *lan966x= , int new_mtu) =20 int lan966x_fdma_get_max_frame(struct lan966x *lan966x) { - return lan966x_fdma_get_max_mtu(lan966x) + - IFH_LEN_BYTES + - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + - VLAN_HLEN * 2 + - XDP_PACKET_HEADROOM; + return lan966x_fdma_get_max_mtu(lan966x) + FDMA_OVERHEAD; } =20 static int __lan966x_fdma_reload(struct lan966x *lan966x, int max_mtu) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c index 5d6902459f20..940425beec2f 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -358,7 +358,7 @@ static int lan966x_fdma_pci_init(struct lan966x *lan966= x) lan966x->rx.lan966x =3D lan966x; lan966x->rx.max_mtu =3D lan966x_fdma_get_max_frame(lan966x); rx_fdma->channel_id =3D FDMA_XTR_CHANNEL; - rx_fdma->n_dcbs =3D FDMA_DCB_MAX; + rx_fdma->n_dcbs =3D FDMA_PCI_DCB_MAX; rx_fdma->n_dbs =3D FDMA_RX_DCB_MAX_DBS; rx_fdma->priv =3D lan966x; rx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); @@ -368,7 +368,7 @@ static int lan966x_fdma_pci_init(struct lan966x *lan966= x) =20 lan966x->tx.lan966x =3D lan966x; tx_fdma->channel_id =3D FDMA_INJ_CHANNEL; - tx_fdma->n_dcbs =3D FDMA_DCB_MAX; + tx_fdma->n_dcbs =3D FDMA_PCI_DCB_MAX; tx_fdma->n_dbs =3D FDMA_TX_DCB_MAX_DBS; tx_fdma->priv =3D lan966x; tx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); @@ -391,9 +391,156 @@ static int lan966x_fdma_pci_init(struct lan966x *lan9= 66x) return 0; } =20 +/* Reset existing rx and tx buffers. */ +static void lan966x_fdma_pci_reset_mem(struct lan966x *lan966x) +{ + struct lan966x_rx *rx =3D &lan966x->rx; + struct lan966x_tx *tx =3D &lan966x->tx; + + memset(rx->fdma.dcbs, 0, rx->fdma.size); + memset(tx->fdma.dcbs, 0, tx->fdma.size); + + fdma_dcbs_init(&rx->fdma, + FDMA_DCB_INFO_DATAL(rx->fdma.db_size - XDP_PACKET_HEADROOM), + FDMA_DCB_STATUS_INTR); + + fdma_dcbs_init(&tx->fdma, + FDMA_DCB_INFO_DATAL(tx->fdma.db_size), + FDMA_DCB_STATUS_DONE); + + lan966x_fdma_llp_configure(lan966x, + tx->fdma.atu_region->base_addr, + tx->fdma.channel_id); + lan966x_fdma_llp_configure(lan966x, + rx->fdma.atu_region->base_addr, + rx->fdma.channel_id); +} + +/* Wake all TX queues on every port (undoes lan966x_fdma_tx_disable_netdev= ). */ +static void lan966x_fdma_pci_wakeup_netdev(struct lan966x *lan966x) +{ + for (int i =3D 0; i < lan966x->num_phys_ports; ++i) { + struct lan966x_port *port =3D lan966x->ports[i]; + + if (port) + netif_tx_wake_all_queues(port->dev); + } +} + +static int lan966x_fdma_pci_reload(struct lan966x *lan966x, int new_mtu) +{ + struct fdma tx_fdma_old =3D lan966x->tx.fdma; + struct fdma rx_fdma_old =3D lan966x->rx.fdma; + u32 old_mtu =3D lan966x->rx.max_mtu; + int err; + + napi_disable(&lan966x->napi); + lan966x_fdma_tx_disable_netdev(lan966x); + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + + lan966x->rx.max_mtu =3D new_mtu; + + /* Must be NULL'ed in order to realloc them. */ + lan966x->rx.fdma.atu_region =3D NULL; + lan966x->tx.fdma.atu_region =3D NULL; + + lan966x->tx.fdma.db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + lan966x->tx.fdma.size =3D fdma_get_size_contiguous(&lan966x->tx.fdma); + lan966x->rx.fdma.db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + lan966x->rx.fdma.size =3D fdma_get_size_contiguous(&lan966x->rx.fdma); + + err =3D lan966x_fdma_pci_rx_alloc(&lan966x->rx); + if (err) + goto restore; + + err =3D lan966x_fdma_pci_tx_alloc(&lan966x->tx); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dma_dev, + &lan966x->rx.fdma); + goto restore; + } + + /* Free and unmap old memory. */ + fdma_free_coherent_and_unmap(lan966x->dma_dev, &rx_fdma_old); + fdma_free_coherent_and_unmap(lan966x->dma_dev, &tx_fdma_old); + + /* Order matters: napi_enable() must precede the wakes, or a TX that + * completes first clears FDMA_INTR_DB_ENA with nothing scheduled to + * restore it, leaving RX dead until the next reload. + */ + napi_enable(&lan966x->napi); + lan966x_fdma_rx_start(&lan966x->rx); + lan966x_fdma_pci_wakeup_netdev(lan966x); + + return err; +restore: + + /* No new buffers are allocated at this point. Use the old buffers, + * but reset them before starting the FDMA again. + */ + + memcpy(&lan966x->tx.fdma, &tx_fdma_old, sizeof(struct fdma)); + memcpy(&lan966x->rx.fdma, &rx_fdma_old, sizeof(struct fdma)); + + lan966x->rx.max_mtu =3D old_mtu; + + lan966x_fdma_pci_reset_mem(lan966x); + + napi_enable(&lan966x->napi); + lan966x_fdma_rx_start(&lan966x->rx); + lan966x_fdma_pci_wakeup_netdev(lan966x); + + return err; +} + +static int __lan966x_fdma_pci_reload(struct lan966x *lan966x, int max_mtu) +{ + int err; + u32 val; + + /* Disable the CPU port. */ + lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(0), + QSYS_SW_PORT_MODE_PORT_ENA, + lan966x, QSYS_SW_PORT_MODE(CPU_PORT)); + + /* Flush the CPU queues. */ + readx_poll_timeout(lan966x_qsys_sw_status, + lan966x, + val, + !(QSYS_SW_STATUS_EQ_AVAIL_GET(val)), + READL_SLEEP_US, READL_TIMEOUT_US); + + /* Add a sleep in case there are frames between the queues and the CPU + * port + */ + usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); + + err =3D lan966x_fdma_pci_reload(lan966x, max_mtu); + + /* Enable back the CPU port. */ + lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(1), + QSYS_SW_PORT_MODE_PORT_ENA, + lan966x, QSYS_SW_PORT_MODE(CPU_PORT)); + + return err; +} + static int lan966x_fdma_pci_resize(struct lan966x *lan966x) { - return -EOPNOTSUPP; + int max_mtu; + + /* Nothing to resize until fdma_pci_init() has built the rings; it + * sizes them from DEV_MAC_MAXLEN_CFG, which the caller already set. + */ + if (!lan966x->rx.lan966x) + return 0; + + max_mtu =3D lan966x_fdma_get_max_frame(lan966x); + if (max_mtu =3D=3D lan966x->rx.max_mtu) + return 0; + + return __lan966x_fdma_pci_reload(lan966x, max_mtu); } =20 static void lan966x_fdma_pci_deinit(struct lan966x *lan966x) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index c803619d83e2..2177e2bbfbd3 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -823,7 +823,8 @@ static int lan966x_probe_port(struct lan966x *lan966x, = u32 p, port->chip_port =3D p; lan966x->ports[p] =3D port; =20 - dev->max_mtu =3D ETH_MAX_MTU; + dev->max_mtu =3D lan966x_is_pci(lan966x) && lan966x->fdma ? + FDMA_PCI_MAX_MTU : ETH_MAX_MTU; =20 dev->netdev_ops =3D &lan966x_port_netdev_ops; dev->ethtool_ops =3D &lan966x_ethtool_ops; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index 16bc28c8f11f..1877f1916d71 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -87,6 +88,33 @@ #define FDMA_INJ_CHANNEL 0 #define FDMA_DCB_MAX 512 =20 +/* Ring must fit in one MAX_PAGE_ORDER DMA block; 512 DCBs overflows + * at jumbo MTU. + */ +#define FDMA_PCI_DCB_MAX 256 + +#define FDMA_OVERHEAD \ + (IFH_LEN_BYTES + \ + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \ + VLAN_HLEN * 2 + \ + XDP_PACKET_HEADROOM) + +/* Largest db_size keeping the ATU-padded ring inside one MAX_PAGE_ORDER + * block and within the 16-bit DCB DATAL field. Inverts ALIGN(x, R) <=3D L + * into x <=3D ALIGN_DOWN(L, R) to bound x directly. + */ +#define FDMA_PCI_DB_SIZE_MAX \ + MIN_T(u32, \ + (ALIGN_DOWN(PAGE_SIZE << MAX_PAGE_ORDER, \ + FDMA_PCI_ATU_REGION_ALIGN) - \ + FDMA_PCI_DCB_MAX * sizeof(struct fdma_dcb)) / \ + (FDMA_PCI_DCB_MAX * FDMA_RX_DCB_MAX_DBS), \ + ALIGN_DOWN(GENMASK(15, 0), FDMA_PCI_DB_ALIGN)) + +#define FDMA_PCI_MAX_MTU \ + (FDMA_PCI_DB_SIZE_MAX - FDMA_OVERHEAD - \ + (ETH_HLEN + ETH_FCS_LEN)) + #define SE_IDX_QUEUE 0 /* 0-79 : Queue scheduler elements */ #define SE_IDX_PORT 80 /* 80-89 : Port schedular elements */ =20 --=20 2.34.1 From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C65C04EE86F; Fri, 18 Sep 2026 11:35:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731303; cv=none; b=oNAMl7/X072IDJDMfL3acd2mYvSq7QHN6rFJnpnHXRWpw2BmRxVjcADH+LFdD+ORoVXN5L8r2i7DNKZSSBnnGrTbO1cP95UwqDiGAVa+Pf+NpqLZy1VeymrMh5b2KDWi0rqI7qX/7iRXnWIEf7v4ROLCM8xKBSFFhCor275srw4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731303; c=relaxed/simple; bh=gjDctCrjO9fidz08IBjObtAdUqa2xLyuwM6VEhU+n/8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Gbuz5565mEvNK+s64mFoFgSdnmiN6E7g65rTx355xDFirG/0gjod8COly2n9RWYlaE8jMawRtlBqdtJ6Ka6+ZfkU8Cyto7rJpRuexHXGwmvbWMfpFPyo6JD+3LL0ZRpOXHf82Sg7FHmDYDSqp1aARufRVr2dr8ElmOR6Ve5G/h8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ei7KFeMQ; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ei7KFeMQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1789731301; x=1821267301; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=gjDctCrjO9fidz08IBjObtAdUqa2xLyuwM6VEhU+n/8=; b=ei7KFeMQWR/t+1MdtK2lXnqm+qo2xzNKv3O8U7yNAft1xtsSfN1oC6yF WwNDW+dgM0catcYjlz0xQ9dZMDDWuRQYli/F/g9J8ZmZ5fwNk9+93lNU9 S15fis0vKh4QF+KZNqb57SLBt++NWRR9QmsQ5FVYAyXxfrsksxh6ZTDS4 XTu13ovEzRcT09EJOqnrBreFaIEKJzqftN+jPkTHiwZ3HphOAa8HhQ6Pp 6/h9iYdhOhL2CjcdnlJmHE/bnfc244XRxx5EDcohufxTFidC859aJyjgL eEvNBzIATn5DzZXlQF2LB5dKi3BmZmqIpaXFwYyQUjXB57Fe23u1sg/SL w==; X-CSE-ConnectionGUID: AsnkTzQTSr6bQnIhn1UHIQ== X-CSE-MsgGUID: hu29enfvRku9PAsyQBSLLQ== X-IronPort-AV: E=Sophos;i="6.27,108,1787036400"; d="scan'208";a="295223745" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 Sep 2026 04:35:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 18 Sep 2026 04:34:59 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:55 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:34:04 +0200 Subject: [PATCH net-next v7 12/14] net: lan966x: add PCIe FDMA XDP support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-12-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Add XDP support for the PCIe FDMA path. The implementation operates on contiguous ATU-mapped buffers with memcpy-based XDP_TX, unlike the platform path which uses page_pool. XDP sees the frame with IFH and FCS stripped. These are removed in lan966x_fdma_pci_rx_check_frame() before the BPF program runs, because after the program returns the driver cannot tell whether the tail region was modified. The skb_pull/skb_trim previously done in lan966x_fdma_pci_rx_get_frame() are removed for the same reason; the frame pointer and length are pre-computed by rx_check_frame() and passed through rx_get_frame() and lan966x_xdp_pci_run() to the caller. lan966x_fdma_pci_xmit_xdpf() handles XDP_TX: it rebuilds a fresh IFH in the TX slot, copies the post-XDP frame after it, and lets HW insert a new FCS. lan966x_xdp_setup() is extended so the PCIe path skips the page_pool reload that the platform path needs. Only XDP_ACT_BASIC is supported. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 167 +++++++++++++++++= +--- .../net/ethernet/microchip/lan966x/lan966x_main.c | 12 +- .../net/ethernet/microchip/lan966x/lan966x_xdp.c | 12 +- 3 files changed, 160 insertions(+), 31 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c index 940425beec2f..e833dbb4fcf0 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ =20 +#include + #include "fdma_api.h" #include "lan966x_main.h" =20 @@ -136,7 +138,123 @@ static bool lan966x_fdma_pci_rx_size_fits(struct fdma= *fdma, u32 blockl) blockl <=3D fdma->db_size - XDP_PACKET_HEADROOM; } =20 -static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port) +static int lan966x_fdma_pci_xmit_xdpf(struct lan966x_port *port, + void *ptr, u32 len) +{ + struct lan966x *lan966x =3D port->lan966x; + struct lan966x_tx *tx =3D &lan966x->tx; + struct fdma *fdma =3D &tx->fdma; + int next_to_use, ret =3D 0; + void *virt_addr; + + spin_lock(&lan966x->tx_lock); + + next_to_use =3D lan966x_fdma_pci_get_next_dcb(fdma); + + if (next_to_use < 0) { + netif_stop_queue(port->dev); + port->dev->stats.tx_dropped++; + ret =3D NETDEV_TX_BUSY; + goto out; + } + + /* Only the upper bound is enforced: XDP owns the frame contents and + * length, so a program that shrinks below ETH_ZLEN gets what it asked + * for. + */ + if (!lan966x_fdma_pci_tx_size_fits(fdma, len)) { + port->dev->stats.tx_dropped++; + ret =3D -EINVAL; + goto out; + } + + /* virt_addr points to the IFH. */ + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, next_to_use, 0); + + /* Construct a fresh IFH. */ + memset(virt_addr, 0, IFH_LEN_BYTES); + lan966x_ifh_set_bypass(virt_addr, 1); + lan966x_ifh_set_port(virt_addr, BIT_ULL(port->chip_port)); + + /* Copy the (post-XDP) frame after the IFH. */ + memcpy(virt_addr + IFH_LEN_BYTES, ptr, len); + + /* Order frame write before DCB status write below. */ + dma_wmb(); + + /* Reserve ETH_FCS_LEN for the HW-inserted FCS (len is FCS-stripped). */ + fdma_dcb_add(fdma, + next_to_use, + 0, + FDMA_DCB_STATUS_INTR | + FDMA_DCB_STATUS_SOF | + FDMA_DCB_STATUS_EOF | + FDMA_DCB_STATUS_BLOCKO(0) | + FDMA_DCB_STATUS_BLOCKL(IFH_LEN_BYTES + len + ETH_FCS_LEN)); + + /* Start the transmission. */ + lan966x_fdma_tx_start(tx); + + port->dev->stats.tx_bytes +=3D len; + port->dev->stats.tx_packets++; + +out: + spin_unlock(&lan966x->tx_lock); + + return ret; +} + +static int lan966x_xdp_pci_run(struct lan966x_port *port, void *data, + u32 data_len, void **xdp_data, u32 *xdp_len) +{ + /* Read once so the NULL check and bpf_prog_run_xdp() see the same + * pointer. + */ + struct bpf_prog *xdp_prog =3D READ_ONCE(port->xdp_prog); + struct lan966x *lan966x =3D port->lan966x; + struct fdma *fdma =3D &lan966x->rx.fdma; + struct xdp_buff xdp; + u32 act; + + if (!xdp_prog) + return FDMA_PASS; + + xdp_init_buff(&xdp, fdma->db_size, &port->xdp_rxq); + + /* hard_start is set to slot start (virt_addr is XDP_PACKET_HEADROOM + * into the slot). Headroom includes the IFH; BPF may grow into it + * via adjust_head. IFH is rebuilt on XDP_TX and unread on XDP_PASS. + */ + xdp_prepare_buff(&xdp, + data - XDP_PACKET_HEADROOM, + XDP_PACKET_HEADROOM + IFH_LEN_BYTES, + data_len, + false); + + act =3D bpf_prog_run_xdp(xdp_prog, &xdp); + + *xdp_data =3D xdp.data; + *xdp_len =3D xdp.data_end - xdp.data; + + switch (act) { + case XDP_PASS: + return FDMA_PASS; + case XDP_TX: + return lan966x_fdma_pci_xmit_xdpf(port, *xdp_data, *xdp_len) ? + FDMA_DROP : FDMA_TX; + default: + bpf_warn_invalid_xdp_action(port->dev, xdp_prog, act); + fallthrough; + case XDP_ABORTED: + trace_xdp_exception(port->dev, xdp_prog, act); + fallthrough; + case XDP_DROP: + return FDMA_DROP; + } +} + +static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port, + void **data, u32 *data_len) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -168,38 +286,33 @@ static int lan966x_fdma_pci_rx_check_frame(struct lan= 966x_rx *rx, u64 *src_port) if (!lan966x_fdma_pci_rx_size_fits(fdma, blockl)) return FDMA_ERROR; =20 - return FDMA_PASS; + /* Present the Ethernet frame (no IFH, no FCS). HW re-inserts the + * FCS on TX; see lan966x_fdma_pci_xmit_xdpf(). May be overridden + * by XDP. The FCS strip is unconditional because NETIF_F_RXFCS + * is not advertised in hw_features. + */ + *data =3D virt_addr + IFH_LEN_BYTES; + *data_len =3D blockl - IFH_LEN_BYTES - ETH_FCS_LEN; + + return lan966x_xdp_pci_run(port, virt_addr, *data_len, data, data_len); } =20 static struct sk_buff *lan966x_fdma_pci_rx_get_frame(struct lan966x_rx *rx, - u64 src_port) + u64 src_port, void *data, + u32 data_len) { struct lan966x *lan966x =3D rx->lan966x; - struct fdma *fdma =3D &rx->fdma; struct sk_buff *skb; - struct fdma_db *db; - u32 data_len; - - /* Get the received frame and create an SKB for it. */ - db =3D fdma_db_next_get(fdma); - data_len =3D FDMA_DCB_STATUS_BLOCKL(db->status); =20 skb =3D napi_alloc_skb(&lan966x->napi, data_len); if (unlikely(!skb)) return NULL; =20 - memcpy(skb->data, - fdma_dataptr_virt_addr_contiguous(fdma, - fdma->dcb_index, - fdma->db_index), - data_len); + memcpy(skb->data, data, data_len); =20 skb_put(skb, data_len); =20 skb->dev =3D lan966x->ports[src_port]->dev; - skb_pull(skb, IFH_LEN_BYTES); - - skb_trim(skb, skb->len - ETH_FCS_LEN); =20 skb->protocol =3D eth_type_trans(skb, skb->dev); =20 @@ -287,6 +400,8 @@ static int lan966x_fdma_pci_napi_poll(struct napi_struc= t *napi, int weight) struct sk_buff *skb; int counter =3D 0; u64 src_port; + u32 data_len; + void *data; =20 /* Wake any stopped TX queues if a TX DCB is available. */ spin_lock(&lan966x->tx_lock); @@ -303,7 +418,10 @@ static int lan966x_fdma_pci_napi_poll(struct napi_stru= ct *napi, int weight) /* Order DONE read before DCB/frame reads below. */ dma_rmb(); counter++; - switch (lan966x_fdma_pci_rx_check_frame(rx, &src_port)) { + switch (lan966x_fdma_pci_rx_check_frame(rx, + &src_port, + &data, + &data_len)) { case FDMA_PASS: break; case FDMA_ERROR: @@ -312,8 +430,17 @@ static int lan966x_fdma_pci_napi_poll(struct napi_stru= ct *napi, int weight) */ fdma_dcb_advance(fdma); continue; + case FDMA_TX: + fdma_dcb_advance(fdma); + continue; + case FDMA_DROP: + fdma_dcb_advance(fdma); + continue; } - skb =3D lan966x_fdma_pci_rx_get_frame(rx, src_port); + skb =3D lan966x_fdma_pci_rx_get_frame(rx, + src_port, + data, + data_len); fdma_dcb_advance(fdma); if (!skb) { lan966x->ports[src_port]->dev->stats.rx_dropped++; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 2177e2bbfbd3..7812d495f753 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -875,11 +875,13 @@ static int lan966x_probe_port(struct lan966x *lan966x= , u32 p, =20 port->phylink =3D phylink; =20 - /* XDP is not supported on the PCIe FDMA path. */ - if (lan966x->fdma && !lan966x_is_pci(lan966x)) - dev->xdp_features =3D NETDEV_XDP_ACT_BASIC | - NETDEV_XDP_ACT_REDIRECT | - NETDEV_XDP_ACT_NDO_XMIT; + if (lan966x->fdma) { + dev->xdp_features =3D NETDEV_XDP_ACT_BASIC; + + if (!lan966x_is_pci(lan966x)) + dev->xdp_features |=3D NETDEV_XDP_ACT_REDIRECT | + NETDEV_XDP_ACT_NDO_XMIT; + } =20 err =3D register_netdev(dev); if (err) { diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c b/drivers= /net/ethernet/microchip/lan966x/lan966x_xdp.c index e63634887f64..b98426afc785 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c @@ -20,16 +20,16 @@ static int lan966x_xdp_setup(struct net_device *dev, st= ruct netdev_bpf *xdp) return -EOPNOTSUPP; } =20 - if (lan966x_is_pci(lan966x)) { - NL_SET_ERR_MSG_MOD(xdp->extack, - "XDP is not supported on the PCIe FDMA path"); - return -EOPNOTSUPP; - } - old_xdp =3D lan966x_xdp_present(lan966x); old_prog =3D xchg(&port->xdp_prog, xdp->prog); new_xdp =3D lan966x_xdp_present(lan966x); =20 + /* PCIe FDMA uses contiguous buffers, so no page_pool reload + * is needed. + */ + if (lan966x_is_pci(lan966x)) + goto out; + if (old_xdp =3D=3D new_xdp) goto out; =20 --=20 2.34.1 From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CB124F30CF; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-13-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 The ATU outbound windows used by the FDMA engine are programmed through registers at offset 0x400000+, which falls outside the current cpu reg mapping. Extend the cpu reg size from 0x100000 (1MB) to 0x800000 (8MB) to cover the full PCIE DBI and iATU register space. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- drivers/misc/lan966x_pci.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7b196b0a0eb6..7bb726550caf 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -135,7 +135,7 @@ lan966x_phy1: ethernet-lan966x_phy@2 { =20 switch: switch@e0000000 { compatible =3D "microchip,lan966x-switch"; - reg =3D <0xe0000000 0x0100000>, + reg =3D <0xe0000000 0x0800000>, <0xe2000000 0x0800000>; reg-names =3D "cpu", "gcb"; =20 --=20 2.34.1 From nobody Fri Sep 25 00:40:34 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 765BC4F392E; Fri, 18 Sep 2026 11:35:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731310; cv=none; b=QVMcCS5yV2G+laaliS90QbmNVnSsTFe0pyf4MZwGoxqgDVq/2nWu/wN1IcGQ6f+eQVxL0Z+QVRTk/bTWb5eiDRKE9T8vLPMxGXb/WIk3dv0L8lXGA32HznnmF0u4CKIwp+fpxdQIujcaiXXTQrbeG7HlHCMNwzAR9EU1N+Qdc8E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731310; c=relaxed/simple; bh=wGxs+F/+5Vrhuyz2y5uEWLeuFrAw1YPbFSMnjR0PIic=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=RGOy6xoFs/2OwyBp6RPe+4GKGmba2HJ5p+SGJc4oDsXTX+wAIk5Kc7lzOPZmYMezeNJ+SZ7xsKAYr3vdlRbqbwa+k2b9KpAoHY+5+p+3UohCKlYqgPQv+78zAKz1grq/nEPPp/nRmOKIj56NR5ipw+zC6LjHeG9onnNWMjaFk1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=UfiHvClL; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="UfiHvClL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1789731308; x=1821267308; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=wGxs+F/+5Vrhuyz2y5uEWLeuFrAw1YPbFSMnjR0PIic=; b=UfiHvClLrqONT81au3QmtN1De0oPKobZOw5buAAToyvnbfqiwAlKcP11 q6kVtYr/rvYG5yM3PhFnfGAgg65dHYRRpjZzLV/547/l9V4BuRtoCWTcz 3In3Nuyq+GN9T5+kjmJap+xih2zBdBI6VuyVQEZE2O0Z/hkEfODOEHAP5 XcLJk6u1OUtHqSA7VVwkt5iwSp08+TmeGi5gSTLkJX4MJasC352k9Ze20 HtqFqnpQN2GDRNGW3BdQTwqLIb/8n4CO44TfiUwfzxKwUvS/CGN4TtoSd 30W7IyGwbqcIXRcehh4sEYlHh1Lt9GEQx1wiwXQcaaj4RTOOvvfKEf64e w==; X-CSE-ConnectionGUID: sCLJV7FZS8mM3CChFuNh7w== X-CSE-MsgGUID: WSOfmcd1RBWFuEl/bh22iA== X-IronPort-AV: E=Sophos;i="6.27,108,1787036400"; d="scan'208";a="73885846" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 04:35:07 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Fri, 18 Sep 2026 04:35:07 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:35:03 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:34:06 +0200 Subject: [PATCH net-next v7 14/14] misc: lan966x-pci: dts: add fdma interrupt to overlay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260918-lan966x-pci-fdma-v7-14-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Add the fdma interrupt (OIC interrupt 14) to the lan966x PCI device tree overlay, enabling FDMA-based frame injection/extraction when the switch is connected over PCIe. Tested-by: Herve Codina Signed-off-by: Daniel Machon Reviewed-by: Simon Horman --- drivers/misc/lan966x_pci.dtso | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7bb726550caf..5bb12dbc0843 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -141,8 +141,9 @@ switch: switch@e0000000 { =20 interrupt-parent =3D <&oic>; interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names =3D "xtr", "ana"; + interrupt-names =3D "xtr", "fdma", "ana"; =20 resets =3D <&reset 0>; reset-names =3D "switch"; --=20 2.34.1