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[34.90.118.116]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2a35701d8bsm902966b.27.2026.09.18.10.26.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 10:26:49 -0700 (PDT) From: Peter Griffin Date: Fri, 18 Sep 2026 17:26:34 +0000 Subject: [PATCH v3 1/4] dt-bindings: arm: google: Add dt bindings for frankel/blazer/mustang Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-contrib-pg-pixel10-initial-dts-v3-1-c94e51140509@linaro.org> References: <20260918-contrib-pg-pixel10-initial-dts-v3-0-c94e51140509@linaro.org> In-Reply-To: <20260918-contrib-pg-pixel10-initial-dts-v3-0-c94e51140509@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Catalin Marinas , Will Deacon , Mark Rutland , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, soc@lists.linux.dev, Douglas Anderson , Juan Yescas , RD Babiera , Brian Norris , William McVicker , kernel-team@android.com, linux-serial@vger.kernel.org, Peter Griffin , Krzysztof Kozlowski , Brian Norris X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3553; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=qo8jkdcJFEHFTzGipPaUfZqW7W+79EGKtSF4WXhEUus=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBqrXRXzv2ubpfgFzjRAOY1RgWBr71XsDwLoS9hx 9EJkqiEJ9SJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCaq10VwAKCRDO6LjWAjRy uoxOEACNW73L3XepiEmszEXR+097pW2CyPuEVZUfEl1WFOxXsh2s9eREfKoQrvGdelmSZRGPO3f Fw3a8grTgAuHA5Ffm1J2bFTpozcO6nolBLfQAQbxkO81z1ho4nXHIRPKjfts5/Ll7vfwo8735tp S120by72b/v10A+hPdPTqSKYaCTfq8xmE7XRjAYB6syuE97GssBdyNv5RaUeCxqYksWWQhLzeSd kCzW2mRtVsMHcVe0Pyytdf1k+LQrWMf9TDqZF8lm5kPe02eEv7ASqxzLDbaAoRblPuQ00Y0fU16 kEXEZFKABxaOFoR6j+FypBuZ787lHgw5mD/a3SNUK6ItYyE6ZaRmqQ+EBsrfmLDgdVoKQDQidE8 QWRUAbY5zT2IQq0irMXNN8yggaBfvOaMnCHrA4IpaT4GvY/SqtM1KAZ8Xbf+Rd3X9xxja6k0Lz7 zcv/99P/DEnP56aFQaWi04uhwMn9P8mjUDBAwxxd8X9EALxvRJRHPlz0F3iPL0Wrbfh9eg9e9Ef UTsZYYLhBP3tWluUYOMMaZ8N9lNEk1mWUVQK/WTQTt6C6uc1W5hGg1NP5KnP4YIR0wEVidgSyg8 MX3/R6blspUuCSfbbFv9F27lXKp18SH1J4zmtN9ZLwuThYmtPNXDm0a/on/Rvp9maHZ3UGsdoHE vSaPuqr1RVm7YMQ== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Add binding documentation for Tensor G5 SoC (Laguna) which is referred to in code as "lga" and three of the boards that use the Laguna SoC Frankel (Pixel 10), Blazer (Pixel 10 Pro) and Mustang (Pixel 10 Pro XL). Additionally update to use a more efficient and scalable way to express the various names a SoC is known by. Co-developed-by: Douglas Anderson Signed-off-by: Douglas Anderson Reviewed-by: Krzysztof Kozlowski Reviewed-by: Brian Norris Signed-off-by: Peter Griffin --- Changes in v2: * Update ect rule as per Krysztof suggestion * Remove all the pre-production variants (EVT, DVT etc) * The equivalent patch in the previous submission is https://lore.kernel.org/lkml/05c833f0-15bc-4a86-9ac4-daf835fe4393@kernel= .org/ but this is now almost entirely different diff. I've added the co-developed-by tag as I've kept the more efficient way to express the names a SoC is known by. --- Documentation/devicetree/bindings/arm/google.yaml | 48 ++++++++++++++-----= ---- 1 file changed, 29 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentat= ion/devicetree/bindings/arm/google.yaml index 99961e5282e56..b5977e20f3937 100644 --- a/Documentation/devicetree/bindings/arm/google.yaml +++ b/Documentation/devicetree/bindings/arm/google.yaml @@ -13,27 +13,16 @@ description: | ARM platforms using SoCs designed by Google branded "Tensor" used in Pix= el devices. =20 - Currently upstream this is devices using "gs101" SoC which is found in P= ixel - 6, Pixel 6 Pro and Pixel 6a. - - Google have a few different names for the SoC: - - Marketing name ("Tensor") - - Codename ("Whitechapel") - - SoC ID ("gs101") - - Die ID ("S5P9845") - - Likewise there are a couple of names for the actual device - - Marketing name ("Pixel 6") - - Codename ("Oriole") - - Devicetrees should use the lowercased SoC ID and lowercased board codena= me, - e.g. gs101 and gs101-oriole. + Currently upstream this is devices using gs101 SoC which is found in Pix= el + 6, Pixel 6 Pro and Pixel 6a and Laguna SoC canonically referred to as lga + found in Pixel 10, Pixel 10 Pro and Pixel 10 Pro XL. =20 properties: $nodename: const: '/' compatible: oneOf: + # Google Tensor G1 AKA gs101 AKA whitechapel AKA Die ID S5P9845 boar= ds - description: Google Pixel 6 or 6 Pro (Oriole or Raven) items: - enum: @@ -41,14 +30,35 @@ properties: - google,gs101-raven - const: google,gs101 =20 - # Bootloader requires empty ect node to be present + # Google Tensor G5 AKA lga (laguna) SoC and boards + - description: + Google Pixel 10, 10 Pro, 10 Pro XL (Frankel, Blazer, + Mustang). + items: + - enum: + - google,lga-blazer + - google,lga-frankel + - google,lga-mustang + - const: google,lga + ect: type: object additionalProperties: false =20 -required: - - ect - additionalProperties: true =20 +allOf: + # Bootloader requires empty ect node to be present + - if: + properties: + compatible: + contains: + const: google,gs101 + then: + required: + - ect + else: + properties: + ect: false + ... --=20 2.55.0.1082.g2b9226bbc0-goog From nobody Fri Sep 25 00:41:18 2026 Received: from mail-ej2-f41.google.com (mail-ej2-f41.google.com [74.125.228.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14A6A20D4FF for ; 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[34.90.118.116]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2a35701d8bsm902966b.27.2026.09.18.10.26.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 10:26:49 -0700 (PDT) From: Peter Griffin Date: Fri, 18 Sep 2026 17:26:35 +0000 Subject: [PATCH v3 2/4] arm64: dts: google: Add dts directory for Google-designed silicon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-contrib-pg-pixel10-initial-dts-v3-2-c94e51140509@linaro.org> References: <20260918-contrib-pg-pixel10-initial-dts-v3-0-c94e51140509@linaro.org> In-Reply-To: <20260918-contrib-pg-pixel10-initial-dts-v3-0-c94e51140509@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Catalin Marinas , Will Deacon , Mark Rutland , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, soc@lists.linux.dev, Douglas Anderson , Juan Yescas , RD Babiera , Brian Norris , William McVicker , kernel-team@android.com, linux-serial@vger.kernel.org, Peter Griffin , Krzysztof Kozlowski , Brian Norris X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2879; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=prHtn5W9Y5dmFFjTBpt1J6sbCTHN8IgoPCiN1ehs4ME=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBqrXRXFTEYAGEsoS7MUfIrg6CjdIOaifPmsSFmo QQ8leTp7q6JAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCaq10VwAKCRDO6LjWAjRy ug/fD/9Urr6DgBP6/xSBuCZzkbqwlAfIRnR0z+L2WO+ksdtXeV/usopNI2AWlnxNecYkTWIZGJa nEg5M1CL0S432JJKZVtOBTqNyd3O3himpBwj8neXDBebwgX61R3vSYad2+Ux1jX1O/Klpi4qnPb oOqdhdPqvqxSOVUE2sk8HR53f0KERaeGyP0yrfXHq+bYR1M/KtSQoUGXuqfDH/0dIHedUIYy/dh X5jFUZvD4fhLsridougvieTgMWG79r/RcfaeeakcMYvEjU2eOgZWA2vxlhQpsHd/T0aBahZhRHr VYTEMfKs2DWxuMakwGN39vpfRy630y/vqTowyXYfAUZqFM8Iw/frDfJTm61WD6dvAB3rVU6ToZt pEcem4gWuKQcuROBYfK3PepyoPV2dWpA+kwsYy3tMGkw5z334AP7kqOxBt5A83YssgBip21tv9+ Fp2Fwgi7hYNtNCTiGOEn9mqSsp6ysDQYA9mf/0b7wIehZUycnJrVRAYijVrhOH2K62bvqeMH7ZA 8Ini+nFiLhcz+uYLVsqNuJfSY8lZ185M79jJY9EzEVarntgmQhWexSBmttBx74LR64QRnudxm1i f5x2MsrmsBrVPnJIml/VkouixLbIM9jrTMEqGSfCLiDTtIrDIP1Bh5z7dE3Icy1rqDk8mVlHF51 btmyUow4Did/arA== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA From: Douglas Anderson The first four Google Tensor SoCs were offshoots of Samsung Exynos SoCs and their device trees were organized under the "exynos/google" directory. Starting with the Google Tensor G5 SoC in Pixel 10 phones, Google Tensor SoCs are now of Google's own design. Add a location in the tree to store these device tree files. Changes by Peter Griffin * update config symbol help with at least 4 lines to avoid checkpatch warning Signed-off-by: Douglas Anderson Reviewed-by: Krzysztof Kozlowski Tested-by: Brian Norris Reviewed-by: Brian Norris Signed-off-by: Peter Griffin --- MAINTAINERS | 1 + arch/arm64/Kconfig.platforms | 8 ++++++++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/google/Makefile | 1 + 4 files changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 06760c45c582c..bee67180e93e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11245,6 +11245,7 @@ F: Documentation/devicetree/bindings/phy/google,lga= -usb-phy.yaml F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.= yaml F: Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml F: arch/arm64/boot/dts/exynos/google/ +F: arch/arm64/boot/dts/google/ F: drivers/clk/samsung/clk-gs101.c F: drivers/phy/phy-google-usb.c F: drivers/soc/samsung/gs101-pmu.c diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 1489bad527d8e..c52dc955df5f0 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -154,6 +154,14 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. =20 +config ARCH_GOOGLE + bool "Google-Designed SoC family" + help + This enables support for Google Tensor SoCs starting at the + Google Tensor G5 (Laguna) found in Pixel 10 and later phones. + Tensor G1 to G4 are offshoots of the Exynos family and are + enabled via ARCH_EXYNOS. + config ARCH_K3 bool "Texas Instruments Inc. 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[34.90.118.116]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2a35701d8bsm902966b.27.2026.09.18.10.26.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 10:26:50 -0700 (PDT) From: Peter Griffin Date: Fri, 18 Sep 2026 17:26:36 +0000 Subject: [PATCH v3 3/4] arm64: dts: google: Add initial dts for frankel/blazer/mustang Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-contrib-pg-pixel10-initial-dts-v3-3-c94e51140509@linaro.org> References: <20260918-contrib-pg-pixel10-initial-dts-v3-0-c94e51140509@linaro.org> In-Reply-To: <20260918-contrib-pg-pixel10-initial-dts-v3-0-c94e51140509@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Catalin Marinas , Will Deacon , Mark Rutland , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, soc@lists.linux.dev, Douglas Anderson , Juan Yescas , RD Babiera , Brian Norris , William McVicker , kernel-team@android.com, linux-serial@vger.kernel.org, Peter Griffin , Brian Norris X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=15306; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=lcFwjQmOWlIcJGB25aCSCMYe86ZTVVkq6y+rYEhX3Yk=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBqrXRXD4ckyAVvu1qjkD9tlbhI2NBhj0u65Qmfi EbqRQB6W/qJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCaq10VwAKCRDO6LjWAjRy ukKtD/4kgjLYzFR53/sN8hBBlLfL+tbCDnUnZOUKh5klYZW8swG4UNP1+qIOfcowj8lPXy0p5Bu 4SGwpoB+Esak+6h/Uh4BDqvTiTT7066WvLt8cBaDNc8MPruXU8W8fHTeoyxC+/SvFhRRi/w+S+0 /Y/CuAgxRMhKjGXiapT6KEsQatJFlVnfLgEtODOhsQS7VEMs9EhOC+O4fDrhLc+cKf3vyCj+44f 1NrIRO7TKxwTldDw+VTL1WRDnF3mVCthqDC/9OXwGiroOAG129b8pqv/usK26h8CnPHqYxxYkkH nB8pyWhG07Z7nFbDYkOKHCVpCuYsTXQqZMrk1Rm6GNov+EWLbZqFsIGgEWv4AuVDtzyYSZav8do Z1taN/wG8rc+0AMQAv9GbMPPXMCKsRcJisiaAFSHpnUPwfMCv0vfvT+OZ1uYrcqgeHY/BYxMlqp 4VzrQ9D/UkRWrjvFnINbeO6BD79t+TPXhZspnWb+vhaehu6z7/qU84ni7UL7HLDL+UOV1bukcSf ihBzR6nBUro6oDScf33WMK0qnq6458AR/A+NDW0jTEMagJurb4yItGGNejv+tTsnkmPkaTMoxUn TRyjch/M3Kyjj7bl25bZks70TYSEl7Qbuf3oZI+nwBJyaIAOQ9A/GTe8PvioVvJcSci6F6JKZS2 VKXmytaT/dxmVug== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA From: Douglas Anderson Add initial device trees for frankel (Pixel 10), blazer (Pixel 10 Pro) and mustang (Pixel 10 Pro XL). These device trees are enough to boot to a serial prompt using an initramfs. Currently only Laguna B0 silicon found in mass production phones is officially supported. Further revisions such as A0 silicon and EVT devices maybe added in the future if they are useful. As of today, these device trees boot fine on EVT devices with A0 silicon. A few things can be noted about these device trees: 1. They purposely choose to use the full 64-bit address and size cells for the root node and the `soc@0` node. Although I haven't tested the need for this, I presume the arguments made in commit bede7d2dc8f3 ("arm64: dts: qcom: sdm845: Increase address and size cells for soc") would apply here. 2. Though it looks as if the UART is never enabled, the bootloader knows to enable the UART when the console is turned on. Baud rate is configurable in the bootloader so is never hardcoded in the device tree. Changes by Peter Griffin: - Remove dtbo overlay approach and add individual board dts - Update to lga-pixel-common naming like gs101-pixel-common - Reorder nodes alpha-numerically by the node name - Add ramoops reserved-memory (tested with console=3Dpstore) - Add reserved-memory for bootloader & gsa logs - Add reserved-memory for Android BootLoader ABL (used on Watchdog reset to extract boolotader logs / parse breadcrumbs / ramdump etc). - Add osc 38.4Mhz fixed-clock Signed-off-by: Douglas Anderson Co-developed-by: Peter Griffin Signed-off-by: Peter Griffin Tested-by: Brian Norris Reviewed-by: Brian Norris --- Changes in v3 * Use 0x0 instead of 0 consistently for new code (Krysztof) * Remove 'ranges' from gic-v3 as no msi child node with unit address (Krys= ztof) * Remove ufs0 alias and ufs placeholder node (Krysztof) * Remove memory node from lga.dtsi (Krysztof) It turns out bootloader adds the node anyway * Use standard '/ {' not overlay style (Krysztof) * Update alias to point at label (Brian) * Drop GIC_CPU_MASK_SIMPLE for GICv3 interrupt controller (Shashiko) * Fix dt-check-style --mode=3Dstrict warnings (Peter) Changes in v2 (by Peter Griffin): * Remove dtbo overlay approach and add individual board dts * Update to lga-pixel-common naming like gs101-pixel-common * Reorder nodes alpha-numerically by the node name * Add ramoops reserved-memory (tested with console=3Dpstore) * Add reserved-memory for bootloader & gsa logs * Add reserved-memory for Android BootLoader ABL (used on Watchdog reset to extract boolotader logs / parse breadcrumbs / ramdump etc). * Add osc 38.4Mhz fixed-clock --- arch/arm64/boot/dts/google/Makefile | 5 + arch/arm64/boot/dts/google/lga-blazer.dts | 15 + arch/arm64/boot/dts/google/lga-frankel.dts | 16 + arch/arm64/boot/dts/google/lga-mustang.dts | 15 + arch/arm64/boot/dts/google/lga-pixel-common.dtsi | 22 ++ arch/arm64/boot/dts/google/lga.dtsi | 413 +++++++++++++++++++= ++++ 6 files changed, 486 insertions(+) diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/goog= le/Makefile index a6b187e2d6318..4e833b2561e08 100644 --- a/arch/arm64/boot/dts/google/Makefile +++ b/arch/arm64/boot/dts/google/Makefile @@ -1 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + +dtb-$(CONFIG_ARCH_GOOGLE) +=3D \ + lga-blazer.dtb \ + lga-frankel.dtb \ + lga-mustang.dtb diff --git a/arch/arm64/boot/dts/google/lga-blazer.dts b/arch/arm64/boot/dt= s/google/lga-blazer.dts new file mode 100644 index 0000000000000..0894606624f8e --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-blazer.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Blazer Device Tree (Pixel 10 Pro) + * + * Copyright 2021-2023 Google LLC + */ + +/dts-v1/; + +#include "lga-pixel-common.dtsi" + +/ { + model =3D "Blazer"; + compatible =3D "google,lga-blazer", "google,lga"; +}; diff --git a/arch/arm64/boot/dts/google/lga-frankel.dts b/arch/arm64/boot/d= ts/google/lga-frankel.dts new file mode 100644 index 0000000000000..57df197a544fa --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-frankel.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Frankel Device Tree (Pixel 10) + * + * Copyright 2021-2023 Google LLC + */ + +/dts-v1/; + +#include "lga-pixel-common.dtsi" + +/ { + model =3D "Frankel"; + compatible =3D "google,lga-frankel", "google,lga"; +}; + diff --git a/arch/arm64/boot/dts/google/lga-mustang.dts b/arch/arm64/boot/d= ts/google/lga-mustang.dts new file mode 100644 index 0000000000000..6ac0b5ef22ff2 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-mustang.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Mustang Device Tree (Pixel 10 Pro XL) + * + * Copyright 2021-2023 Google LLC + */ + +/dts-v1/; + +#include "lga-pixel-common.dtsi" + +/ { + model =3D "Mustang"; + compatible =3D "google,lga-mustang", "google,lga"; +}; diff --git a/arch/arm64/boot/dts/google/lga-pixel-common.dtsi b/arch/arm64/= boot/dts/google/lga-pixel-common.dtsi new file mode 100644 index 0000000000000..218b55a5d00af --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-pixel-common.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Pixel 10 family common dtsi. + * + * Copyright 2024-2025 Google LLC. + */ + +#include "lga.dtsi" + +/ { + chosen { + stdout-path =3D "serial0"; + }; + + aliases { + serial0 =3D &lsion_cli16_uart; + }; +}; + +&osc { + clock-frequency =3D <38400000>; +}; diff --git a/arch/arm64/boot/dts/google/lga.dtsi b/arch/arm64/boot/dts/goog= le/lga.dtsi new file mode 100644 index 0000000000000..26a14b3a1b190 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Tensor G5 (laguna) SoC rev B0 + * + * Copyright 2024-2025 Google LLC. + */ + +/dts-v1/; + +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + osc: clock-38400000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + hayes_0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x000>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <258>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + }; + + hayes_1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x100>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <258>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + }; + + hunter_0: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a725"; + reg =3D <0x200>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + }; + + hunter_1: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a725"; + reg =3D <0x300>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + }; + + hunter_2: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a725"; + reg =3D <0x400>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + }; + + hunter_3: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a725"; + reg =3D <0x500>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + }; + + hunter_4: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a725"; + reg =3D <0x600>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + }; + + hunterelp_0: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-x4"; + reg =3D <0x700>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <1024>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&hayes_0>; + }; + + core1 { + cpu =3D <&hayes_1>; + }; + + core2 { + cpu =3D <&hunter_0>; + }; + + core3 { + cpu =3D <&hunter_1>; + }; + + core4 { + cpu =3D <&hunter_2>; + }; + + core5 { + cpu =3D <&hunter_3>; + }; + + core6 { + cpu =3D <&hunter_4>; + }; + + core7 { + cpu =3D <&hunterelp_0>; + }; + }; + }; + + domain-idle-states { + cluster_1_c3: cluster-1-c3 { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <325>; + exit-latency-us =3D <553>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-1-c3"; + + arm,psci-suspend-param =3D <0x40010033>; + }; + + cluster_2_c3: cluster-2-c3 { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <345>; + exit-latency-us =3D <673>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-2-c3"; + + arm,psci-suspend-param =3D <0x40010033>; + }; + + cluster_c4_deep: cluster-c4-deep { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <510>; + exit-latency-us =3D <1027>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-c4-deep"; + + arm,psci-suspend-param =3D <0x40020333>; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_big_c2: cpu-big-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <110>; + exit-latency-us =3D <413>; + min-residency-us =3D <3950>; + + idle-state-name =3D "cpu-big-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_lit_c2: cpu-lit-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <132>; + exit-latency-us =3D <296>; + min-residency-us =3D <3610>; + + idle-state-name =3D "cpu-lit-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_mid1_c2: cpu-mid1-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <130>; + exit-latency-us =3D <274>; + min-residency-us =3D <2720>; + + idle-state-name =3D "cpu-mid1-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_mid2_c2: cpu-mid2-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <130>; + exit-latency-us =3D <274>; + min-residency-us =3D <2720>; + + idle-state-name =3D "cpu-mid2-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpucl1: power-domain-cluster-1 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_1_c3>; + power-domains =3D <&cpu_top_cl>; + }; + + cpucl2: power-domain-cluster-2 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_2_c3>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_lit_c2>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_lit_c2>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid2_c2>; + power-domains =3D <&cpucl2>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid2_c2>; + power-domains =3D <&cpucl2>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_big_c2>; + power-domains =3D <&cpucl2>; + }; + + cpu_top_cl: power-domain-top-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_c4_deep>; + }; + }; + + reserved_memory: reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + /* + * Store ramoops at a known location in DRAM, for access by the + * ABL following a crash-reset. + */ + ramoops@95200000 { + compatible =3D "ramoops"; + reg =3D <0x0 0x95200000 0x0 0x400000>; + console-size =3D <0x200000>; + pmsg-size =3D <0x200000>; + }; + + /* bootloader logs */ + bldr_log_reserved: bldr-log-reserved@95600000 { + reg =3D <0x0 0x95600000 0x0 0x100000>; + no-map; + }; + + /* gsa logs */ + gsa_reserved_log: gsa-reserved-log@a61b0000 { + reg =3D <0x0 0xa61b0000 0x0 0x00004000>; + no-map; + }; + + /* Android BootLoader (ABL) for ramdump/coredump processing */ + abl@be000000 { + reg =3D <0x0 0xbe000000 0x0 0x1000000>; + no-map; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + + dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; 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[34.90.118.116]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2a35701d8bsm902966b.27.2026.09.18.10.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 10:26:51 -0700 (PDT) From: Peter Griffin Date: Fri, 18 Sep 2026 17:26:37 +0000 Subject: [PATCH v3 4/4] arm64: defconfig: enable Tensor G5 SoC family Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-contrib-pg-pixel10-initial-dts-v3-4-c94e51140509@linaro.org> References: <20260918-contrib-pg-pixel10-initial-dts-v3-0-c94e51140509@linaro.org> In-Reply-To: <20260918-contrib-pg-pixel10-initial-dts-v3-0-c94e51140509@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Catalin Marinas , Will Deacon , Mark Rutland , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, soc@lists.linux.dev, Douglas Anderson , Juan Yescas , RD Babiera , Brian Norris , William McVicker , kernel-team@android.com, linux-serial@vger.kernel.org, Peter Griffin , Brian Norris X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=787; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=BbX8RY98cbW2glkwb44ypYKnRm3un42mGYq+Qy76YHQ=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBqrXRYGuQ5/L4khzKLHRvREUl1l+2lwJGoJSQiY SGyFcbuWBCJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCaq10WAAKCRDO6LjWAjRy utArD/9uj3S4/40eqQyAQNg2mrd8YRRLVD2a+iFnXlDd04AKI6CyH9Aw39xkFrcjJfJ4hkBGr+C bq8pFZNwJu3DH6NN/ZgNqnsiuxemOfw/aUIO1dpSTeW6BvQla9JT3YBduKlaAStNeV9HLWE0cdK FGDB8mVSVVJ0j/jYlX3BOmNAium/Ewfw9PI0ALpuXmOJ60HZabfOMYnun2JV43MuRmmJx+smUde 15IsHXU6GQ15cwQFp56h5tCUisTYD31g39lmK7iD0Qpwd6BC7U3SEFO1LiorExYEECyq9C7h+Mm ATP1VxNycE8kVWDXVD5BlcWBgeQeyqFLUcp0wexvmyoxLICWQGWrCCnipjciOVlKfY4Tc6OyEbG vrlzf1SPtQJMDhH9y26QfsrMaVvnVHHdMrhtrFblU/rHj/mP0MkdHSSktmN0M2Zw/iXgUpfbzBb Sgiz3ymLwkb57NgSqWh4ZEmseH5HGA1gI/D7/tMq3a35ZQZsASN2N8vyisAjaCNPSih+SmS0mfT RnVnZKuvriyPYy0oGMaosjltQVaBzFjx9Ok1WALSvawKVkVkIzo6Du0GkfXaO6QcdiwsAHRhkz8 8q31d2t0PWWn05xdNQ7eM6h+2MYYbGKpYmzkwJcNXA6ObhSV2vGM73rn7RO/wrqM0hT1uhF5d2E A+fovbmpX/pet2g== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Enable the Google Tensor G5 (Laguna) SoC family in the arm64 defconfig. This SoC family is found in Pixel 10 and later phones. Reviewed-by: Douglas Anderson Reviewed-by: Brian Norris Signed-off-by: Peter Griffin --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 982ea1758eb66..75000c12ead03 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -51,6 +51,7 @@ CONFIG_ARCH_BLAIZE=3Dy CONFIG_ARCH_BST=3Dy CONFIG_ARCH_CIX=3Dy CONFIG_ARCH_EXYNOS=3Dy +CONFIG_ARCH_GOOGLE=3Dy CONFIG_ARCH_K3=3Dy CONFIG_ARCH_LG1K=3Dy CONFIG_ARCH_HISI=3Dy --=20 2.55.0.1082.g2b9226bbc0-goog