From nobody Fri Sep 25 01:20:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7359A4A7C83; Thu, 17 Sep 2026 21:42:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789681368; cv=none; b=ZGAwEwoY/DSi/OHJcbV+WPXs9oEf4Tir8c0ca0vfyC2yBjuyRUWEQirpoLWZo6x/aEbx5YIobPnxNk3lAPeO2jsEpxn6PMZlsqoJ73imWXalliIRwIb8D6lQNtdggGt1NLX+rcmVLGVv/+bl6r0/uJgj0g7eN9LbcB7ONLivgko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789681368; c=relaxed/simple; bh=kUZhUVbts+ndC39LiYRFJ2AH2v71NBpBnvqeaYZgEFs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RGhnDKVS5kslF/8t4nPydFMdWwlWjq2R8EGhpIymN2FTtNIWTxVaVx/NdXp+vEcO8BtUZvYj2DLlRXXIVyXQTiJJD4uHC5ymcpx5hrwbnRGJFVCyVABoWQWSh1rCImMoe5jwWajImO0KRPNB/nXbPE4T4XKKviMrhH0/pTG2l5A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=IkH+u8se; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="IkH+u8se" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 01A6C1596; Thu, 17 Sep 2026 14:42:40 -0700 (PDT) Received: from workstation-e142269.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 429C43F7B4; Thu, 17 Sep 2026 14:42:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789681363; bh=kUZhUVbts+ndC39LiYRFJ2AH2v71NBpBnvqeaYZgEFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IkH+u8seP17fq+zdfbRfFgZAD2GQ4dWL+zSuTnoa+he3GN5+gyMfZ9VB1WpbShiC4 VoxLtkoAUg7GXqndsVgmbVOip0wMw3B2cy0EyLUeIs+4p1bOulE8IWZ4jO7zhJVvfZ wRBIzpHB33TB9mYB9XKOThpWiXQPUIopn20KLDhA= From: Wei-Lin Chang To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Cameron , Mark Brown , Sascha Bischoff , James Clark , Lorenzo Pieralisi , Anshuman Khandual , Thomas Huth , Ganapatrao Kulkarni , Wei-Lin Chang , stable@vger.kernel.org Subject: [PATCH v2 1/4] KVM: arm64: nv: Don't advertise FEAT_LPA2 for guest stage-1 Date: Thu, 17 Sep 2026 22:42:11 +0100 Message-ID: <20260917214215.74135-2-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917214215.74135-1-weilin.chang@arm.com> References: <20260917214215.74135-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is no FEAT_LPA2 support for NV guests as of now, but we missed limiting it for the non-stage-2 granule size fields (TGRAN4, TGRAN16) in ID_AA64MMFR0_EL1. Add the sanitisation. Fixes: 9f75b6d447d7 ("KVM: arm64: nv: Filter out unsupported features from = ID regs") Signed-off-by: Wei-Lin Chang Cc: stable@vger.kernel.org Reviewed-by tag, and adds Marc's TCR_EL2 reset patch [1]. Please see --- arch/arm64/kvm/nested.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 3c4fc566eafc..4a860904c1ce 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1731,6 +1731,17 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 va= l) /* Hide CNTPOFF if present */ val =3D ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64MMFR0_EL1, ECV, IMP); =20 + /* NV does not support FEAT_LPA2. */ + if (SYS_FIELD_GET(ID_AA64MMFR0_EL1, TGRAN4, val) =3D=3D ID_AA64MMFR0_EL1= _TGRAN4_52_BIT) { + val &=3D ~ID_AA64MMFR0_EL1_TGRAN4; + val |=3D SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN4, IMP); + } + + if (SYS_FIELD_GET(ID_AA64MMFR0_EL1, TGRAN16, val) =3D=3D ID_AA64MMFR0_EL= 1_TGRAN16_52_BIT) { + val &=3D ~ID_AA64MMFR0_EL1_TGRAN16; + val |=3D SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN16, IMP); + } + /* Disallow unsupported S2 page sizes */ switch (PAGE_SIZE) { case SZ_64K: --=20 2.43.0 From nobody Fri Sep 25 01:20:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CA4502FD696 for ; Thu, 17 Sep 2026 21:42:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789681373; cv=none; b=kRtFfAjp7C6jOo1wTLJg/3jFM47aDSzLy3ooWEKl7Hbffsl7hEQCKPh9ST5cBgo61SoDKS5TxoFOCnZqIDHEvX6XKZCpLQihc6W+d3u+JAtDInuOMk0Rm2RaYyIuyEtpW4kr/8envzrKtOWubHs+ObL35b47WdqCdHVk6f7V6FE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789681373; c=relaxed/simple; bh=JBtsMsEWMNLNADwgEQVSFvPtiXOMRzZv66KQLvRb/3c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u7mjYQDKpFNawhErp52Yi0cl3fPeuhYsBqxrklL+GKBkwQTAIU2SmjH1NgxWz2dattbyiu98ES3TRlyF1+ITYShv2ZzulmWs5oKFqE9kUhqB292sBN8Xe/UKesMyIcs64qiwKko2Tk95RVpFGF+88J4iFNPw6JjkTabsordda2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=RGMe4ec0; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="RGMe4ec0" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7DB451476; Thu, 17 Sep 2026 14:42:43 -0700 (PDT) Received: from workstation-e142269.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DE9D73F7B4; Thu, 17 Sep 2026 14:42:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789681367; bh=JBtsMsEWMNLNADwgEQVSFvPtiXOMRzZv66KQLvRb/3c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RGMe4ec0GnMldFTCsRadt9jQTsoquZh1dSTBA5mHUebCdNDTIgVjxhP95G7609gFW NVunWx1akWr5N7Qv+HgMo02/WBKEsoI9/yR/1lHW9IQG/FIBhl93qNp3hbUfElbku4 kgW+8sGXgFxTHOad2HE1iuYY2LuZ8EwHl2zrLCZw= From: Wei-Lin Chang To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Cameron , Mark Brown , Sascha Bischoff , James Clark , Lorenzo Pieralisi , Anshuman Khandual , Thomas Huth , Ganapatrao Kulkarni , Wei-Lin Chang Subject: [PATCH v2 2/4] arm64: sysreg: Add TCR_EL2 to sysreg infrastructure Date: Thu, 17 Sep 2026 22:42:12 +0100 Message-ID: <20260917214215.74135-3-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917214215.74135-1-weilin.chang@arm.com> References: <20260917214215.74135-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert TCR_EL2 to the sysreg infrastructure with data extracted from Registers.json of the BSD licenced AARCHMRS (AARCHMRS_OPENSOURCE_A_profile_FAT-2026-06). There are two formats of TCR_EL2 based on whether the effective value of HCR_EL2.E2H is 0 or 1. For the E2H =3D=3D 1 case, prefix the macros with "VHE_". For the E2H =3D=3D 0 case, the macros are left unprefixed. Reviewed-by: Mark Brown Signed-off-by: Wei-Lin Chang Reviewed-by tag, and adds Marc's TCR_EL2 reset patch [1]. Please see --- arch/arm64/include/asm/kvm_arm.h | 13 ---- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 125 +++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 4bfbd827c5aa..690c13d0b068 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -108,19 +108,6 @@ #define MPAMHCR_HOST_FLAGS 0 =20 /* TCR_EL2 Registers bits */ -#define TCR_EL2_DS (1UL << 32) -#define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) -#define TCR_EL2_HPD (1 << 24) -#define TCR_EL2_HA (1 << 21) -#define TCR_EL2_TBI (1 << 20) -#define TCR_EL2_PS_SHIFT 16 -#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) -#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT) -#define TCR_EL2_TG0_MASK TCR_TG0_MASK -#define TCR_EL2_SH0_MASK TCR_SH0_MASK -#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK -#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK -#define TCR_EL2_T0SZ_MASK 0x3f #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \ TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK) =20 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 7aa08d59d494..3499e5fab39e 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -514,7 +514,6 @@ =20 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0) #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1) -#define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2) #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) =20 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index e2d37ee221b8..5093598ac5f7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -5561,6 +5561,131 @@ Res0 6 Field 5:0 T0SZ EndSysreg =20 +Sysreg TCR_EL2 3 4 2 0 2 +Prefix VHE +Res0 63:62 +Field 61 MTX1 +Field 60 MTX0 +Field 59 DS +Field 58 TCMA1 +Field 57 TCMA0 +Field 56 E0PD1 +Field 55 E0PD0 +Field 54 NFD1 +Field 53 NFD0 +Field 52 TBID1 +Field 51 TBID0 +Field 50 HWU162 +Field 49 HWU161 +Field 48 HWU160 +Field 47 HWU159 +Field 46 HWU062 +Field 45 HWU061 +Field 44 HWU060 +Field 43 HWU059 +Field 42 HPD1 +Field 41 HPD0 +Field 40 HD +Field 39 HA +Field 38 TBI1 +Field 37 TBI0 +Field 36 AS +Res0 35 +Field 34:32 IPS +Enum 31:30 TG1 + 0b01 16K + 0b10 4K + 0b11 64K +EndEnum +Enum 29:28 SH1 + 0b00 NONE + 0b10 OUTER + 0b11 INNER +EndEnum +Enum 27:26 ORGN1 + 0b00 NC + 0b01 WBWA + 0b10 WT + 0b11 WBnWA +EndEnum +Enum 25:24 IRGN1 + 0b00 NC + 0b01 WBWA + 0b10 WT + 0b11 WBnWA +EndEnum +Field 23 EPD1 +Field 22 A1 +Field 21:16 T1SZ +Enum 15:14 TG0 + 0b00 4K + 0b01 64K + 0b10 16K +EndEnum +Enum 13:12 SH0 + 0b00 NONE + 0b10 OUTER + 0b11 INNER +EndEnum +Enum 11:10 ORGN0 + 0b00 NC + 0b01 WBWA + 0b10 WT + 0b11 WBnWA +EndEnum +Enum 9:8 IRGN0 + 0b00 NC + 0b01 WBWA + 0b10 WT + 0b11 WBnWA +EndEnum +Field 7 EPD0 +Res0 6 +Field 5:0 T0SZ +EndPrefix +Res0 63:34 +Field 33 MTX +Field 32 DS +Res1 31 +Field 30 TCMA +Field 29 TBID +Field 28 HWU62 +Field 27 HWU61 +Field 26 HWU60 +Field 25 HWU59 +Field 24 HPD +Res1 23 +Field 22 HD +Field 21 HA +Field 20 TBI +Res0 19 +Field 18:16 PS +Enum 15:14 TG0 + 0b00 4K + 0b01 64K + 0b10 16K +EndEnum +Enum 13:12 SH0 + 0b00 NONE + 0b10 OUTER + 0b11 INNER +EndEnum +Enum 11:10 ORGN0 + 0b00 NC + 0b01 WBWA + 0b10 WT + 0b11 WBnWA +EndEnum +Enum 9:8 IRGN0 + 0b00 NC + 0b01 WBWA + 0b10 WT + 0b11 WBnWA +EndEnum +Res0 7:6 +Field 5:0 T0SZ +EndSysreg + Sysreg TCR_EL12 3 5 2 0 2 Mapping TCR_EL1 EndSysreg --=20 2.43.0 From nobody Fri Sep 25 01:20:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CDFE94C10E5 for ; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="AilCQqIG" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 077951596; Thu, 17 Sep 2026 14:42:47 -0700 (PDT) Received: from workstation-e142269.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6697A3F7B4; Thu, 17 Sep 2026 14:42:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789681370; bh=+w+K3RyabmLpuqtKSmYuMaQ4+sQQEcnPLOH8AtHmFDo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AilCQqIGPWmkwXPA3QPx47V8r7tEAHPf6dVVvrVNYkx0D8kz9embwVVG34yron5qN i2I1lbxJKB8XfOwNPUVVHJHRuisSAzYgvRiSxjzcSJWimFU4NnzWyT/k12IH/WPYIF we4ZZ5Fy8DTuYiwQKCeKalfh4INCHl64X5r41rAM= From: Wei-Lin Chang To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Cameron , Mark Brown , Sascha Bischoff , James Clark , Lorenzo Pieralisi , Anshuman Khandual , Thomas Huth , Ganapatrao Kulkarni , Wei-Lin Chang Subject: [PATCH v2 3/4] KVM: arm64: Reset TCR_EL2 according to guest's E2H mode Date: Thu, 17 Sep 2026 22:42:13 +0100 Message-ID: <20260917214215.74135-4-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917214215.74135-1-weilin.chang@arm.com> References: <20260917214215.74135-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Marc Zyngier Previously vCPU TCR_EL2's reset value didn't consider TCR_EL2's different formats based on the value of HCR_EL2.E2H. It always resets to the E2H =3D=3D 0 version. This didn't cause any problem because the bits set in the E2H =3D=3D 0 version (TCR_EL2_RES1) all reset to UNKNOWN for E2H =3D=3D 1 per the architecture. Still, it's better to fix it. Choose the correct reset value by checking KVM_ARM_VCPU_HAS_EL2_E2H0. Signed-off-by: Marc Zyngier Signed-off-by: Wei-Lin Chang Reviewed-by tag, and adds Marc's TCR_EL2 reset patch [1]. Please see --- arch/arm64/kvm/sys_regs.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 44aae52c473d..62c059747fbb 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -3275,6 +3275,14 @@ static u64 reset_mdcr(struct kvm_vcpu *vcpu, const s= truct sys_reg_desc *r) return vcpu->kvm->arch.nr_pmu_counters; } =20 +static u64 reset_tcr_el2(struct kvm_vcpu *vcpu, const struct sys_reg_desc = *r) +{ + __vcpu_assign_sys_reg(vcpu, r->reg, + vcpu_has_feature(vcpu, KVM_ARM_VCPU_HAS_EL2_E2H0) ? + TCR_EL2_RES1 : VHE_TCR_EL2_RES1); + return __vcpu_sys_reg(vcpu, r->reg); +} + /* * Architected system registers. * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 @@ -3853,7 +3861,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { =20 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), - EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), + EL2_REG(TCR_EL2, access_rw, reset_tcr_el2, 0), EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, tcr2_el2_visibility), EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), --=20 2.43.0 From nobody Fri Sep 25 01:20:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7760C4A484F for ; Thu, 17 Sep 2026 21:42:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789681379; cv=none; b=u9M8uXYzMdu96fWjg1ZFGEYgWBDrkEkukViK4P1CX5mh0CvlckZGXe9pAwRx4RFsaYHzi1+cp/ZTjTy65kwVWnE2VWZash7ers+USinKXkM3X0yHpND41pInegz+p1a0U26pYLCMXYWCuJClWsIznYFjtPwXtqU+lBPiHr2QzPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789681379; c=relaxed/simple; bh=pCbhbafE2P97gowU1BfGpspqimxrWR+CMk622HpGJ6k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X5gtAcVBfeJxa9ZBODXeXCmzS2ExbOhk6t/p42CWWy0qkwYWfj/2LAfOnqKoOr4XoGykoYg60ApV9pZp3vO5Ry8j1LveO0yMtmyCDtOhcfinTzaSQ8zwOBVmPTiXjEt2IQN6QpldJq5bMW70+lPraWXyIem8F1PfsAnJgm6UQAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=owxpFCwI; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="owxpFCwI" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7E9F11476; Thu, 17 Sep 2026 14:42:50 -0700 (PDT) Received: from workstation-e142269.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E2CEC3F7B4; Thu, 17 Sep 2026 14:42:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789681374; bh=pCbhbafE2P97gowU1BfGpspqimxrWR+CMk622HpGJ6k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=owxpFCwIZJeN3m6azY6uGOkOEXvRK4oSxKjFr2b6twaeh0o29+CZyYDqoDEiLVVPr H/+NJ0PNM6m4KIr1p8ifDBmO/SMb37QFPA1dH7kmf7K63sY34xCHGfD5VRQVoK+rE5 CbYgmplWUtUHD+jwTsC0ab73i7Y4CVCfEOCfCYMQ= From: Wei-Lin Chang To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Cameron , Mark Brown , Sascha Bischoff , James Clark , Lorenzo Pieralisi , Anshuman Khandual , Thomas Huth , Ganapatrao Kulkarni , Wei-Lin Chang Subject: [PATCH v2 4/4] KVM: arm64: Convert TCR_EL2 to config-driven sanitisation Date: Thu, 17 Sep 2026 22:42:14 +0100 Message-ID: <20260917214215.74135-5-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917214215.74135-1-weilin.chang@arm.com> References: <20260917214215.74135-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Feature dependencies of the fields in TCR_EL2 are extracted from Registers.json of the BSD licenced AARCHMRS (AARCHMRS_OPENSOURCE_A_profile_FAT-2026-06). Places where we slightly deviate from the above: - Stick to the ARM ARM M.c requirement for TCR_EL2.TCMA*, which only depends on FEAT_MTE2. This avoids updating ID_AA64PFR2_EL1 with new VMTE* definitions that we don't know the meaning of, as they aren't present in the ARM ARM yet. - Ignore TCR_EL2.DS's requirement of needing the effective value of TCR2_EL2.D128 be 0. This requires runtime detection of TCR2_EL2.D128 and we don't have D128 support yet. - TCR_EL2.AS is dependent on FEAT_ASID16, this information is missing from the json. Signed-off-by: Wei-Lin Chang Reviewed-by tag, and adds Marc's TCR_EL2 reset patch [1]. Please see --- arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/kvm/config.c | 113 ++++++++++++++++++++++++++++++ arch/arm64/kvm/nested.c | 4 ++ 3 files changed, 118 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 27fe0cd5b2d7..6a5e22ca3430 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -516,7 +516,6 @@ enum vcpu_sysreg { HACR_EL2, /* Hypervisor Auxiliary Control Register */ TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ - TCR_EL2, /* Translation Control Register (EL2) */ PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ PIR_EL2, /* Permission Indirection Register 1 (EL2) */ POR_EL2, /* Permission Overlay Register 2 (EL2) */ @@ -541,6 +540,7 @@ enum vcpu_sysreg { /* Anything from this can be RES0/RES1 sanitised */ MARKER(__SANITISED_REG_START__), SCTLR_EL2, /* System Control Register (EL2) */ + TCR_EL2, /* Translation Control Register (EL2) */ TCR2_EL2, /* Extended Translation Control Register (EL2) */ SCTLR2_EL2, /* System Control Register 2 (EL2) */ MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index 1053676551af..080b3510b783 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -203,8 +203,11 @@ struct reg_feat_map_desc { #define FEAT_CPA2 ID_AA64ISAR3_EL1, CPA, CPA2 #define FEAT_ASID2 ID_AA64MMFR4_EL1, ASID2, IMP #define FEAT_MEC ID_AA64MMFR3_EL1, MEC, IMP +#define FEAT_HAF ID_AA64MMFR1_EL1, HAFDBS, AF #define FEAT_HAFT ID_AA64MMFR1_EL1, HAFDBS, HAFT +#define FEAT_HAFDBS ID_AA64MMFR1_EL1, HAFDBS, DBM #define FEAT_HDBSS ID_AA64MMFR1_EL1, HAFDBS, HDBSS +#define FEAT_HPDS ID_AA64MMFR1_EL1, HPDS, IMP #define FEAT_HPDS2 ID_AA64MMFR1_EL1, HPDS, HPDS2 #define FEAT_BTI ID_AA64PFR1_EL1, BT, IMP #define FEAT_ExS ID_AA64MMFR0_EL1, EXS, IMP @@ -215,6 +218,10 @@ struct reg_feat_map_desc { #define FEAT_MixedEndEL0 ID_AA64MMFR0_EL1, BIGENDEL0, IMP #define FEAT_MTE_ASYNC ID_AA64PFR1_EL1, MTE_frac, ASYNC #define FEAT_MTE_STORE_ONLY ID_AA64PFR2_EL1, MTESTOREONLY, IMP +#define FEAT_MTE_CANONICAL_TAGS ID_AA64PFR1_EL1, MTEX, MTE4 +#define FEAT_MTE_NO_ADDRESS_TAGS ID_AA64PFR1_EL1, MTEX, MTE4 +#define FEAT_E0PD ID_AA64MMFR2_EL1, E0PD, IMP +#define FEAT_SVE ID_AA64PFR0_EL1, SVE, IMP #define FEAT_PAN ID_AA64MMFR1_EL1, PAN, IMP #define FEAT_PAN3 ID_AA64MMFR1_EL1, PAN, PAN3 #define FEAT_SSBS ID_AA64PFR1_EL1, SSBS, IMP @@ -227,6 +234,19 @@ struct reg_feat_map_desc { #define FEAT_GCIE ID_AA64PFR2_EL1, GCIE, IMP #define FEAT_NV3 ID_AA64MMFR4_EL1, NV_frac, NV3 =20 +static bool feat_asid16(struct kvm *kvm) +{ + return kvm_has_feat_enum(kvm, ID_AA64MMFR0_EL1, ASIDBITS, 16); +} + +static bool feat_mte_no_addr_tags_or_canonical_tags(struct kvm *kvm) +{ + bool no_addr_tags =3D kvm_has_feat(kvm, FEAT_MTE_NO_ADDRESS_TAGS); + bool canonical_tags =3D kvm_has_feat(kvm, FEAT_MTE_CANONICAL_TAGS); + + return no_addr_tags || canonical_tags; +} + static bool not_feat_aa64el3(struct kvm *kvm) { return !kvm_has_feat(kvm, FEAT_AA64EL3); @@ -1044,6 +1064,91 @@ static const struct reg_bits_to_feat_map sctlr2_feat= _map[] =3D { static const DECLARE_FEAT_MAP(sctlr2_desc, SCTLR2_EL1, sctlr2_feat_map, FEAT_SCTLR2); =20 +static const struct reg_bits_to_feat_map vhe_tcr_el2_feat_map[] =3D { + NEEDS_FEAT(VHE_TCR_EL2_MTX1 | + VHE_TCR_EL2_MTX0, + feat_mte_no_addr_tags_or_canonical_tags), + NEEDS_FEAT(VHE_TCR_EL2_DS, feat_lpa2), + NEEDS_FEAT(VHE_TCR_EL2_TCMA1 | + VHE_TCR_EL2_TCMA0, + FEAT_MTE2), + NEEDS_FEAT(VHE_TCR_EL2_E0PD1 | + VHE_TCR_EL2_E0PD0, + FEAT_E0PD), + NEEDS_FEAT(VHE_TCR_EL2_NFD1 | + VHE_TCR_EL2_NFD0, + FEAT_SVE), + NEEDS_FEAT(VHE_TCR_EL2_TBID1 | + VHE_TCR_EL2_TBID0, + feat_pauth), + NEEDS_FEAT(VHE_TCR_EL2_HWU162 | + VHE_TCR_EL2_HWU161 | + VHE_TCR_EL2_HWU160 | + VHE_TCR_EL2_HWU159 | + VHE_TCR_EL2_HWU062 | + VHE_TCR_EL2_HWU061 | + VHE_TCR_EL2_HWU060 | + VHE_TCR_EL2_HWU059, + FEAT_HPDS2), + NEEDS_FEAT(VHE_TCR_EL2_HPD1 | + VHE_TCR_EL2_HPD0, + FEAT_HPDS), + NEEDS_FEAT(VHE_TCR_EL2_HD, FEAT_HAFDBS), + NEEDS_FEAT(VHE_TCR_EL2_HA, FEAT_HAF), + NEEDS_FEAT(VHE_TCR_EL2_AS, feat_asid16), + NEEDS_FEAT(VHE_TCR_EL2_TBI1 | + VHE_TCR_EL2_TBI0 | + VHE_TCR_EL2_IPS | + VHE_TCR_EL2_TG1 | + VHE_TCR_EL2_SH1 | + VHE_TCR_EL2_ORGN1 | + VHE_TCR_EL2_IRGN1 | + VHE_TCR_EL2_EPD1 | + VHE_TCR_EL2_A1 | + VHE_TCR_EL2_T1SZ | + VHE_TCR_EL2_TG0 | + VHE_TCR_EL2_SH0 | + VHE_TCR_EL2_ORGN0 | + VHE_TCR_EL2_IRGN0 | + VHE_TCR_EL2_EPD0 | + VHE_TCR_EL2_T0SZ, + FEAT_AA64EL2), + FORCE_RES0(VHE_TCR_EL2_RES0), + FORCE_RES1(VHE_TCR_EL2_RES1), +}; + +static const DECLARE_FEAT_MAP(vhe_tcr_el2_desc, VHE_TCR_EL2, + vhe_tcr_el2_feat_map, FEAT_AA64EL2); + +static const struct reg_bits_to_feat_map tcr_el2_feat_map[] =3D { + NEEDS_FEAT(TCR_EL2_MTX, + feat_mte_no_addr_tags_or_canonical_tags), + NEEDS_FEAT(TCR_EL2_DS, feat_lpa2), + NEEDS_FEAT(TCR_EL2_TCMA, FEAT_MTE2), + NEEDS_FEAT(TCR_EL2_TBID, feat_pauth), + NEEDS_FEAT(TCR_EL2_HWU62 | + TCR_EL2_HWU61 | + TCR_EL2_HWU60 | + TCR_EL2_HWU59, + FEAT_HPDS2), + NEEDS_FEAT(TCR_EL2_HPD, FEAT_HPDS), + NEEDS_FEAT(TCR_EL2_HD, FEAT_HAFDBS), + NEEDS_FEAT(TCR_EL2_HA, FEAT_HAF), + NEEDS_FEAT(TCR_EL2_TBI | + TCR_EL2_PS | + TCR_EL2_TG0 | + TCR_EL2_SH0 | + TCR_EL2_ORGN0 | + TCR_EL2_IRGN0 | + TCR_EL2_T0SZ, + FEAT_AA64EL2), + FORCE_RES0(TCR_EL2_RES0), + FORCE_RES1(TCR_EL2_RES1), +}; + +static const DECLARE_FEAT_MAP(tcr_el2_desc, TCR_EL2, + tcr_el2_feat_map, FEAT_AA64EL2); + static const struct reg_bits_to_feat_map tcr2_el2_feat_map[] =3D { NEEDS_FEAT_FLAG(TCR2_EL2_FNG1 | TCR2_EL2_FNG0 | @@ -1398,6 +1503,8 @@ void __init check_feature_map(void) check_reg_desc(&hcr_desc); check_reg_desc(&nvhcr_desc); check_reg_desc(&sctlr2_desc); + check_reg_desc(&vhe_tcr_el2_desc); + check_reg_desc(&tcr_el2_desc); check_reg_desc(&tcr2_el2_desc); check_reg_desc(&sctlr_el1_desc); check_reg_desc(&sctlr_el2_desc); @@ -1611,6 +1718,12 @@ struct resx get_reg_fixed_bits(struct kvm *kvm, enum= vcpu_sysreg reg) case SCTLR2_EL2: resx =3D compute_reg_resx_bits(kvm, &sctlr2_desc, 0, 0); break; + case TCR_EL2: + if (kvm_has_feat(kvm, FEAT_E2H0)) + resx =3D compute_reg_resx_bits(kvm, &tcr_el2_desc, 0, 0); + else + resx =3D compute_reg_resx_bits(kvm, &vhe_tcr_el2_desc, 0, 0); + break; case TCR2_EL2: resx =3D compute_reg_resx_bits(kvm, &tcr2_el2_desc, 0, 0); break; diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 4a860904c1ce..2536ea4297b0 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1957,6 +1957,10 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu) resx =3D get_reg_fixed_bits(kvm, HFGITR2_EL2); set_sysreg_masks(kvm, HFGITR2_EL2, resx); =20 + /* TCR_EL2 */ + resx =3D get_reg_fixed_bits(kvm, TCR_EL2); + set_sysreg_masks(kvm, TCR_EL2, resx); + /* TCR2_EL2 */ resx =3D get_reg_fixed_bits(kvm, TCR2_EL2); set_sysreg_masks(kvm, TCR2_EL2, resx); --=20 2.43.0