From nobody Fri Sep 25 01:20:28 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ED1444CAC6 for ; Thu, 17 Sep 2026 19:03:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789671799; cv=none; b=dA+DPmPWxz9S8z1bldAiHZZdK6WUIOfMotC7Fxtrm06riFgLCtYHh6gJYYhcawGljiP0bvEsxB/bsv35Oxrk3SBuzs6pCssIn4v756fup+tPDav2oXXAXHcOLe6mC9q5NzxCvb9NuowC/NG41gAo45WHKZQQyjXNXwT80pQO4h8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789671799; c=relaxed/simple; bh=YuTxLUECdgv8wQnjykfLiiSbljluWKlJs1FuE2fg9ac=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u8urZTZzBkj9KykgaGITgYXHrZzv5SsxIJZEHMHpxkL3BlPsFobFehdRxzrfLAjWb1+JamILfgXuaHdQR/gGxQ8La/0c1E5XicfZA1BZUcAql+KEtV6Oy0089WO20A+Wb++uxSuDlKxL2IcpLG9/SEZRcdG4PBf+HpYhlQQ7laQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=bVgQDx0i; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="bVgQDx0i" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1789671796; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oUesHNqg+ZVQdyp3TqOiMgGR4RIEF42DCBqJOEUMffo=; b=bVgQDx0iZw2fLQXXb4GePUtM/Ii/A9WUDcJMvAyU2VDQeF6YiqPo9zLkrAFk0b3e+EfNPe mDXxCho/BQUZH77jx+L37T1cksHLfPaJEhGR94iQTQwc3Jjwvj0+AbJXqLhvpnOP70qW7k I24wm8Yh6cnsvScL2vrKX9DeWVL1q7A= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-90-iDK-JP4kO3WRna3BMUBTAQ-1; Thu, 17 Sep 2026 15:03:11 -0400 X-MC-Unique: iDK-JP4kO3WRna3BMUBTAQ-1 X-Mimecast-MFC-AGG-ID: iDK-JP4kO3WRna3BMUBTAQ_1789671789 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 9F4A4195C26B; Thu, 17 Sep 2026 19:03:08 +0000 (UTC) Received: from ShadowPeak.redhat.com (unknown [10.44.49.1]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id DF81819AC047; Thu, 17 Sep 2026 19:03:04 +0000 (UTC) From: Petr Oros To: netdev@vger.kernel.org Cc: Petr Oros , stable@vger.kernel.org, Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Arkadiusz Kubalewski , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH iwl-net 1/2] ice: fix DPLL registration on boards without the SMA clock mux Date: Thu, 17 Sep 2026 21:02:57 +0200 Message-ID: <20260917190258.3239282-2-poros@redhat.com> In-Reply-To: <20260917190258.3239282-1-poros@redhat.com> References: <20260917190258.3239282-1-poros@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" The SMA and U.FL connectors of an E810-C timing board are routed by a PCA9575 GPIO expander, and ice_dpll_init_info_sw_pins() reaches it through ice_read_sma_ctrl(). On a board that carries a CGU but no such expander the netlist lookup fails with -ENXIO, which aborts ice_dpll_init_info() and with it the whole DPLL registration: ice 0000:cc:00.0: ice_dpll_init_info - fail: d->inputs:... ice 0000:cc:00.0: DPLLs init failure err:-6 Userspace loses the EEC and PPS devices, every CGU pin and the recovered clock pin. The netlist describes the mux with a clock mux node, which ice_init_feature_support() already turns into ICE_F_SMA_CTRL. Key the software controlled pins on that flag. Without the mux the SMA wrappers stay inputs, the state the mux path programs at init anyway, and do not advertise DIRECTION_CAN_CHANGE. The U.FL pins are the other leg of the mux, so they are hidden, and the outgoing CGU pins stay visible as REF-SMA1 and REF-SMA2/U.FL2. The layout is not exotic, the E810_C827_SyncE_SFP_SEC configuration in Intel's 4.80 NVM package has no clock mux node either. Such boards worked until the SMA and U.FL redesign moved the expander access into the DPLL init path. Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control") Cc: stable@vger.kernel.org Signed-off-by: Petr Oros Reviewed-by: Arkadiusz Kubalewski --- drivers/net/ethernet/intel/ice/ice_dpll.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index 85a74cd6ea1f3e..e0362b6bf332e5 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -107,6 +107,9 @@ static const struct dpll_pin_frequency ice_esync_range[= ] =3D { */ static bool ice_dpll_is_sw_pin(struct ice_pf *pf, u8 index, bool input) { + if (!input && !ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) + return false; + if (input && pf->hw.device_id =3D=3D ICE_DEV_ID_E810C_QSFP) index -=3D ICE_DPLL_SW_PIN_INPUT_BASE_QSFP - ICE_DPLL_SW_PIN_INPUT_BASE_SFP; @@ -1213,6 +1216,8 @@ static int ice_dpll_sma_direction_set(struct ice_dpll= _pin *p, =20 if (p->direction =3D=3D direction && p->active) return 0; + if (!ice_is_feature_supported(p->pf, ICE_F_SMA_CTRL)) + return -EOPNOTSUPP; ret =3D ice_read_sma_ctrl(&p->pf->hw, &data); if (ret) return ret; @@ -4510,9 +4515,14 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf = *pf) true, &freq_supp_num); pin->prop.freq_supported_num =3D freq_supp_num; pin->prop.capabilities =3D - (DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE | - DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | - caps); + (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | caps); + if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) { + pin->prop.capabilities |=3D + DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE; + } else { + pin->active =3D true; + pin->direction =3D DPLL_PIN_DIRECTION_INPUT; + } pin->pf =3D pf; pin->prop.board_label =3D ice_dpll_sw_pin_sma[i]; pin->input =3D &d->inputs[pin_abs_idx]; @@ -4526,6 +4536,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *= pf) pin->idx =3D i; pin->prop.type =3D DPLL_PIN_TYPE_EXT; pin->prop.capabilities =3D caps; + pin->hidden =3D !ice_is_feature_supported(pf, ICE_F_SMA_CTRL); pin->pf =3D pf; pin->prop.board_label =3D ice_dpll_sw_pin_ufl[i]; if (i =3D=3D ICE_DPLL_PIN_SW_1_IDX) { @@ -4555,6 +4566,9 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *= pf) ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); } =20 + if (!ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) + return 0; + /* Initialize the SMA control register to a known-good default state. * Without this write the PCA9575 GPIO expander retains its power-on * default (all outputs high) which makes all SW pins appear inactive. --=20 2.55.0 From nobody Fri Sep 25 01:20:28 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77CB14D487F for ; Thu, 17 Sep 2026 19:03:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; 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Thu, 17 Sep 2026 19:03:12 +0000 (UTC) Received: from ShadowPeak.redhat.com (unknown [10.44.49.1]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 0CEC719AC047; Thu, 17 Sep 2026 19:03:08 +0000 (UTC) From: Petr Oros To: netdev@vger.kernel.org Cc: Petr Oros , Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Arkadiusz Kubalewski , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH iwl-net 2/2] ice: skip the SW pin description on boards with generic DPLL pins Date: Thu, 17 Sep 2026 21:02:58 +0200 Message-ID: <20260917190258.3239282-3-poros@redhat.com> In-Reply-To: <20260917190258.3239282-1-poros@redhat.com> References: <20260917190258.3239282-1-poros@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" ice_dpll_init_info_sw_pins() describes the SMA and U.FL wrappers by pointing them at fixed positions of the input and output arrays, inputs 4 and 5 and outputs 0 and 1 on an E810-C SFP, and reads the ref-sync partner of the input it picked. The arrays are sized by the pin counts firmware reports. On a board that does not match the Intel reference layout the driver has already fallen back to generic pins, and when such a board reports fewer pins than the reference the reads run past the end of the arrays. The wrappers are never registered on a generic board, but ice_dpll_init_pins() still calls ice_dpll_pin_ref_sync_register() on them, so a stray nonzero partner from the out of bounds read would pair NULL pins. Describe the wrappers only when the static pin table is in use and keep their ref-sync registration under the same condition. The default programming of the PCA9575 clock mux stays on the generic path, a board that has the mux still needs its SMA connectors switched to inputs. Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control") Signed-off-by: Petr Oros Reviewed-by: Arkadiusz Kubalewski --- drivers/net/ethernet/intel/ice/ice_dpll.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index e0362b6bf332e5..81bb32d2b23012 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -4124,15 +4124,15 @@ static int ice_dpll_init_pins(struct ice_pf *pf, bo= ol cgu) if (ret) goto deinit_sma; count +=3D ICE_DPLL_PIN_SW_NUM; + ret =3D ice_dpll_pin_ref_sync_register(pf->dplls.sma, + ICE_DPLL_PIN_SW_NUM); + if (ret) + goto deinit_ufl; } ret =3D ice_dpll_pin_ref_sync_register(pf->dplls.inputs, pf->dplls.num_inputs); if (ret) goto deinit_ufl; - ret =3D ice_dpll_pin_ref_sync_register(pf->dplls.sma, - ICE_DPLL_PIN_SW_NUM); - if (ret) - goto deinit_ufl; } else { count +=3D pf->dplls.num_outputs + 2 * ICE_DPLL_PIN_SW_NUM; } @@ -4501,6 +4501,8 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *= pf) int i, ret; u8 data; =20 + if (d->generic) + goto init_sma_ctrl; if (pf->hw.device_id =3D=3D ICE_DEV_ID_E810C_QSFP) input_idx_offset =3D ICE_E810_RCLK_PINS_NUM; phase_adj_max =3D max(d->input_phase_adj_max, d->output_phase_adj_max); @@ -4566,6 +4568,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *= pf) ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); } =20 +init_sma_ctrl: if (!ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) return 0; =20 @@ -4584,7 +4587,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *= pf) if (ret) return ret; =20 - ret =3D ice_dpll_pin_state_update(pf, pin, ICE_DPLL_PIN_TYPE_SOFTWARE, + ret =3D ice_dpll_pin_state_update(pf, d->sma, ICE_DPLL_PIN_TYPE_SOFTWARE, NULL); if (ret) return ret; --=20 2.55.0