From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F01C84AAC5A for ; Thu, 17 Sep 2026 14:56:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657016; cv=none; b=QOKQcvFDx48kdo5baZGwdcBlGLwKFirUb14bAiwENM+mKhNepOI1JeMPpiOuixVjjeF37DpMu+oMfVW5+n+fNRj3/bKOBBI6jXehYvbmWyLPzN3JA/u2y35625i78NWUTlPJul4lcDD9d4HcJzR2qhPzIOszTZ+d5OwCFbL99RU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657016; c=relaxed/simple; bh=THmIJ0mblTEQm05OX560oWA4k2851WiXGCm+VIxUKlk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kA7hswnhQ4q9Zsd2MCovyl0USwBU2/kEoib+n5+kzM6LS0+zn1P3UTBJO7GmD+/X9NpO6xWVS4slB5NvQ4xDIgM4Swdz9U/ZpTpN43SAAvkq3LuoG+WDXWZPJBQfbSIPF17WbTwMhq5qL/iFXNkjUu+wGrrBQeBO1PDU40tRaqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=PSr5zSjz; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="PSr5zSjz" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 20CDC1596; Thu, 17 Sep 2026 07:56:25 -0700 (PDT) Received: from e134344.cambridge.arm.com (unknown [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4A2A73F86F; Thu, 17 Sep 2026 07:56:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789656988; bh=THmIJ0mblTEQm05OX560oWA4k2851WiXGCm+VIxUKlk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PSr5zSjzi/w1B/nV+rS3TWGaNq0+wreF4ePi5JzUbMnKFesvnOnOEnfc462c8CMa0 RfgpGj/V2P0iaAoij3XMDIMZv2IL9XFG5+jUY2MmvKnmXTzXQsYgdBp+y7y9G3XvzX lptBvwc2R/tUyKplAO80RB1LOdMEu0rDdxq/MaEg= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com, Gavin Shan Subject: [PATCH v2 01/12] arm_mpam: Move MPAMF_ECR write helpers to allow reuse Date: Thu, 17 Sep 2026 15:56:06 +0100 Message-ID: <20260917145617.2202986-2-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917145617.2202986-1-ben.horgan@arm.com> References: <20260917145617.2202986-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for calling mpam_enable_msc_ecr() from the CPU hotplug handlers move it higher in the file. Move mpam_disable_msc_ecr() too to keep them together. Signed-off-by: Ben Horgan Tested-by: Gavin Shan Reviewed-by: Gavin Shan --- drivers/resctrl/mpam_devices.c | 38 +++++++++++++++++----------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index dd422c56fbb1..580d7ed38569 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1817,6 +1817,25 @@ static void mpam_reprogram_msc(struct mpam_msc *msc) mutex_unlock(&msc->cfg_lock); } =20 +static int mpam_enable_msc_ecr(void *_msc) +{ + struct mpam_msc *msc =3D _msc; + + __mpam_write_reg(msc, MPAMF_ECR, MPAMF_ECR_INTEN); + + return 0; +} + +/* This can run in mpam_disable(), and the interrupt handler on the same C= PU */ +static int mpam_disable_msc_ecr(void *_msc) +{ + struct mpam_msc *msc =3D _msc; + + __mpam_write_reg(msc, MPAMF_ECR, 0); + + return 0; +} + static void _enable_percpu_irq(void *_irq) { int *irq =3D _irq; @@ -2443,25 +2462,6 @@ static char *mpam_errcode_names[16] =3D { [12 ... 15] =3D "Reserved" }; =20 -static int mpam_enable_msc_ecr(void *_msc) -{ - struct mpam_msc *msc =3D _msc; - - __mpam_write_reg(msc, MPAMF_ECR, MPAMF_ECR_INTEN); - - return 0; -} - -/* This can run in mpam_disable(), and the interrupt handler on the same C= PU */ -static int mpam_disable_msc_ecr(void *_msc) -{ - struct mpam_msc *msc =3D _msc; - - __mpam_write_reg(msc, MPAMF_ECR, 0); - - return 0; -} - static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc) { u64 reg; --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7C6EF5A0AA3 for ; Thu, 17 Sep 2026 14:56:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657007; cv=none; b=LPZpNkrg3nKAQ+fd9MOayaGvQr+I39onjzBmmSUozrbuEWEFP+hNXeSm532gzTshHOuZJ3rh5kfgUoaG2RfOMMJCpkv9dsjRuIp2iLLp8rMadAqkk3/CUUiJYT6PEwZX5nDYoeku7Mj1O7rSrr0G3MLQXspOgwVopwAosPO6UG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657007; c=relaxed/simple; bh=EQBvkZtIHffAkr5/QWRSIbFbmywWBucVousASbKrX8o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gWbZETVCaNDqceX7kBAjgD4/8vYELJSNTtc1QpCANthufECz8H0O2ehMLU9J7orccAddzqw+fvOi5mL3eaarYKUJVnKIi/epsK1FVvDgyAzPj7RZdqYfBFwV8CGhA/4DJ95M2MLWSMaI/r/RWyU/mMfILKEIZ7MYMZdGzmiY3zU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=uOkCjQnP; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="uOkCjQnP" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D123E1F02; Thu, 17 Sep 2026 07:56:26 -0700 (PDT) Received: from e134344.cambridge.arm.com (unknown [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 06B663F86F; Thu, 17 Sep 2026 07:56:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789656990; bh=EQBvkZtIHffAkr5/QWRSIbFbmywWBucVousASbKrX8o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uOkCjQnPBTnLED+Ju1Wsd5Ys3DpvforX8qQNzjUaaf+/HOyzl34vFEwDPh1tvVFmT JGHngIm/imqQGLAj1jcWRbDMrIHUceHZuze7jHzq8LHA2I3uzV19KzIruXBXczz6xj hgeHtuXflkeAe9klb8QfQiHRm9lNl+uX8LO7J0JA= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com, Gavin Shan Subject: [PATCH v2 02/12] arm_mpam: Restore the error interrupt enable from mpam_cpu_online() Date: Thu, 17 Sep 2026 15:56:07 +0100 Message-ID: <20260917145617.2202986-3-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917145617.2202986-1-ben.horgan@arm.com> References: <20260917145617.2202986-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When all the associated CPUs to an MSC are offline, possibly caused by PSCI_CPU_OFF, the power supply to the MSC can be cut off and all the registers that are unknown out of reset, including MPAMF_ECR.INTEN, are lost. Afterwards, we need to explicitly set MPAMF_ECR.INTEN when the first associated CPU becomes online and the power supply to the MSC is recovered. Restore MPAMF_ECR.INTEN in mpam_cpu_online() when the first associated CPU of the MSC becomes online. Fixes: 49aa621c4dca ("arm_mpam: Register and enable IRQs") Signed-off-by: Ben Horgan Tested-by: Gavin Shan Reviewed-by: Gavin Shan --- Changes since v1: Update the commit message (Gavin) --- drivers/resctrl/mpam_devices.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 580d7ed38569..32bde94dfbc3 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1856,8 +1856,14 @@ static int mpam_cpu_online(unsigned int cpu) if (msc->reenable_error_ppi) _enable_percpu_irq(&msc->reenable_error_ppi); =20 - if (atomic_fetch_inc(&msc->online_refs) =3D=3D 0) + if (atomic_fetch_inc(&msc->online_refs) =3D=3D 0) { + mutex_lock(&msc->error_irq_lock); + if (msc->error_irq_hw_enabled) + mpam_touch_msc(msc, mpam_enable_msc_ecr, msc); + mutex_unlock(&msc->error_irq_lock); + mpam_reprogram_msc(msc); + } } =20 if (mpam_resctrl_enabled) --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0423759D63B for ; Thu, 17 Sep 2026 14:56:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657010; cv=none; b=lQx9BloCXvE86Mq+kxvLv5GwdL7zTH4ryWwr4QkNkdskzmTgnCKe3cMBrC6cN05iw5uczkf5IKeIvXMZuBiyXY8lYVZQWYySS7wSXVYAPZROJvbUs31QZxxgfsX6zyA2A0dLPNzFY8INivWNmhmxFjKBwOxGEzD06gl8j224oOg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657010; c=relaxed/simple; bh=BOF7ChOk2hTz/uF1IrvSVSlzJ1TxdzunfQ+vnFOetvw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cJpaUCv0JS7ZOKv0dX4qVFVhWGPV3CBR2avMchOXEcx3gtaAQ94wOj7bY3YUcQWeUtmRQLEME8tkHn3YaaPzCDciWu2fIznLUb75zLRCBf1MyjPnb7p0kFpV2SI/NY+RPLUIzIsdbXNXzwSHbw7s9bNTMUKdpF4AeTLfduCG/FQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=nPxbo8ah; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="nPxbo8ah" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6EE551F37; Thu, 17 Sep 2026 07:56:28 -0700 (PDT) Received: from e134344.cambridge.arm.com (unknown [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B77843F86F; Thu, 17 Sep 2026 07:56:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789656992; bh=BOF7ChOk2hTz/uF1IrvSVSlzJ1TxdzunfQ+vnFOetvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nPxbo8ahRo+UuzWnMO0orlrjGfjMXwWcLZ3pTnpejWNdcNf5M1Jz0ghziKLAqnU8t V7/Zu0sOQMHVZsKz82FGKQc31O1kwmn8kCTTvvbUj7pCLSYYrB9FXonBiqJ30kUSKd PZ0TVROBoNlrQbfNKC+UVTm3UE7tC/YhyjktynEs= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com, Gavin Shan Subject: [PATCH v2 03/12] arm_mpam: Set mpam_feat_msmon_mbwu_31counter when there are bandwidth counters Date: Thu, 17 Sep 2026 15:56:08 +0100 Message-ID: <20260917145617.2202986-4-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917145617.2202986-1-ben.horgan@arm.com> References: <20260917145617.2202986-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When MPAMF_MSMON_IDR.MSMON_MBWU is 1, MSMON_MBWU is present and has a VALUE field of 31 bits. If additionally, MPAMF_MBWUMON_IDR.HAS_LONG is 1, then MSMON_MBWU_L is also present and has a VALUE field of 44 or 63 bits as indicated by MPAMF_MBWUMON_IDR.LWD. Hence, if there are memory bandwidth counters then there are always 31 bit counters irrespective of whether there also long counters. Set the 31 bit bandwidth counter feature bit whenever there are bandwidth counters. Fixes: fdc29a141d63 ("arm_mpam: Probe for long/lwd mbwu counters") Signed-off-by: Ben Horgan Tested-by: Gavin Shan Reviewed-by: Gavin Shan --- drivers/resctrl/mpam_devices.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 32bde94dfbc3..e349db525882 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -930,9 +930,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) mpam_set_feature(mpam_feat_msmon_mbwu_63counter, props); else mpam_set_feature(mpam_feat_msmon_mbwu_44counter, props); - } else { - mpam_set_feature(mpam_feat_msmon_mbwu_31counter, props); } + + mpam_set_feature(mpam_feat_msmon_mbwu_31counter, props); } } } --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 77BFA50AC30 for ; Thu, 17 Sep 2026 14:56:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657022; cv=none; b=DdPWiRldNKz0vYd16YsXL37HxAK+WxU6Lq2DovC8jcRZeDYqM9Zn1b68EJImamrIgx6B9GZqUvLhqAkrbOXoZn3j66rc+7pZUdQgVk6Di/q7FMwyIGlQO0iX4TkuXOhWtLrL1TRaNC0pepWcMFrOh3YweRxzbQJx8FwalaMt+BY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657022; c=relaxed/simple; bh=lb4IRP+Y1Hz2fJbSNi4TVLYctKlrDlgtGYuXAuzDSJk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AccOmFWxj1ISzBKvyvKrUX3s4thT9VR1Dl30tJBFH/X+alWfxG985EdiDUM1F4FCE3W1ltxW6/EREbJiVgwDtYe7LbhySdBlGQlRzqRGIgV1MHpI+zNL91e5gBz8gotCtQt8RWg5o6wZRAutcap5YKV1yTrTzktOnr3pTT7Q4bc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=nr/3FAiG; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="nr/3FAiG" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2E4821F91; Thu, 17 Sep 2026 07:56:30 -0700 (PDT) Received: from e134344.cambridge.arm.com (unknown [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 54DBF3F86F; Thu, 17 Sep 2026 07:56:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789656993; bh=lb4IRP+Y1Hz2fJbSNi4TVLYctKlrDlgtGYuXAuzDSJk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nr/3FAiGv7IZVAPqm9GBEIy/0+t1vKHstf/mzx+RjYYIEe7/+PDk81EwkzBgG995Z a/ecN+6wPCPhEMzpyDbaq+QUFGHPkPyXEREU3Irk49O44GJs+eNXfPeiplSo+mzv3H IcIBpYHxf+2jze7w9j2rD/utgrFcwMDxJKk0Kqc0= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com, Gavin Shan Subject: [PATCH v2 04/12] arm_mpam: Add missing mon_sel locking in MBWU save and restore Date: Thu, 17 Sep 2026 15:56:09 +0100 Message-ID: <20260917145617.2202986-5-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917145617.2202986-1-ben.horgan@arm.com> References: <20260917145617.2202986-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mon_sel_lock is used to protect the mbwu_state, as well as h/w accesses that use MPAMCFG_MON_SEL. However, in mpam_restore/save_mbwu_state(), mbwu_state is accessed without holding the mon_sel_lock. Add the missing locking. Fixes: 41e8a14950e1 ("arm_mpam: Track bandwidth counter state for power man= agement") Signed-off-by: Ben Horgan Tested-by: Gavin Shan Reviewed-by: Gavin Shan --- Changes since v1: 'continue' if monitor enabled move locking earlier in mpam_save_mbwu_state() and adjust commit message --- drivers/resctrl/mpam_devices.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index e349db525882..d39d210574a6 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1652,17 +1652,26 @@ static int mpam_restore_mbwu_state(void *_ris) u64 val; struct mon_read mwbu_arg; struct mpam_msc_ris *ris =3D _ris; + struct mpam_msc *msc =3D ris->vmsc->msc; struct mpam_class *class =3D ris->vmsc->comp->class; =20 for (i =3D 0; i < ris->props.num_mbwu_mon; i++) { - if (ris->mbwu_state[i].enabled) { - mwbu_arg.ris =3D ris; - mwbu_arg.ctx =3D &ris->mbwu_state[i].cfg; - mwbu_arg.type =3D mpam_msmon_choose_counter(class); - mwbu_arg.val =3D &val; + if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) + return -EIO; =20 - __ris_msmon_read(&mwbu_arg); + if (!ris->mbwu_state[i].enabled) { + mpam_mon_sel_unlock(msc); + continue; } + + mwbu_arg.ris =3D ris; + mwbu_arg.ctx =3D &ris->mbwu_state[i].cfg; + mwbu_arg.type =3D mpam_msmon_choose_counter(class); + mwbu_arg.val =3D &val; + + mpam_mon_sel_unlock(msc); + + __ris_msmon_read(&mwbu_arg); } =20 return 0; @@ -1680,12 +1689,12 @@ static int mpam_save_mbwu_state(void *arg) struct mpam_msc *msc =3D ris->vmsc->msc; =20 for (i =3D 0; i < ris->props.num_mbwu_mon; i++) { - mbwu_state =3D &ris->mbwu_state[i]; - cfg =3D &mbwu_state->cfg; - if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) return -EIO; =20 + mbwu_state =3D &ris->mbwu_state[i]; + cfg =3D &mbwu_state->cfg; + mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) | FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B03674DAFBD for ; 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charset="utf-8" When an MSC becomes inaccessible due to cpu offline CFG_MBWU_CTL is set to zero in mpam_save_mbwu_state(). This is very likely to mean that the config will mismatch when restoring and so the monitor will be reset. However, the state may have been lost and so there are no guarantees. Ensure the reset happens by setting the reset_on_next_read and remove the unnecessary writes from mpam_save_mbwu_state(). Fixes: 41e8a14950e1 ("arm_mpam: Track bandwidth counter state for power man= agement") Signed-off-by: Ben Horgan Tested-by: Gavin Shan Reviewed-by: Gavin Shan --- Changes since v1: Use local variable mbwu_state consistently (Shaopeng) Only access ris->mbwu_state when have the mon_sel_lock --- drivers/resctrl/mpam_devices.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index d39d210574a6..6cba3ef21cc8 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1652,6 +1652,7 @@ static int mpam_restore_mbwu_state(void *_ris) u64 val; struct mon_read mwbu_arg; struct mpam_msc_ris *ris =3D _ris; + struct msmon_mbwu_state *mbwu_state; struct mpam_msc *msc =3D ris->vmsc->msc; struct mpam_class *class =3D ris->vmsc->comp->class; =20 @@ -1659,16 +1660,20 @@ static int mpam_restore_mbwu_state(void *_ris) if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) return -EIO; =20 - if (!ris->mbwu_state[i].enabled) { + mbwu_state =3D &ris->mbwu_state[i]; + + if (!mbwu_state->enabled) { mpam_mon_sel_unlock(msc); continue; } =20 mwbu_arg.ris =3D ris; - mwbu_arg.ctx =3D &ris->mbwu_state[i].cfg; + mwbu_arg.ctx =3D &mbwu_state->cfg; mwbu_arg.type =3D mpam_msmon_choose_counter(class); mwbu_arg.val =3D &val; =20 + mbwu_state->reset_on_next_read =3D true; + mpam_mon_sel_unlock(msc); =20 __ris_msmon_read(&mwbu_arg); @@ -1701,15 +1706,11 @@ static int mpam_save_mbwu_state(void *arg) =20 cur_flt =3D mpam_read_monsel_reg(msc, CFG_MBWU_FLT); cur_ctl =3D mpam_read_monsel_reg(msc, CFG_MBWU_CTL); - mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0); =20 - if (mpam_ris_has_mbwu_long_counter(ris)) { + if (mpam_ris_has_mbwu_long_counter(ris)) val =3D mpam_msc_read_mbwu_l(msc); - mpam_msc_zero_mbwu_l(msc); - } else { + else val =3D mpam_read_monsel_reg(msc, MBWU); - mpam_write_monsel_reg(msc, MBWU, 0); - } =20 cfg->mon =3D i; cfg->pmg =3D FIELD_GET(MSMON_CFG_x_FLT_PMG, cur_flt); --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1DEE64078CE for ; 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charset="utf-8" mbwu_save_mbwu_state() reads the MBWU counters and adds that to a saved correction value. However, the type of counter to read is determined by the RIS rather than the class and overflow is not taken into account. Fix this and mitigate against further divergence by using a locked variant of the same helper used for user monitor reads, __ris_msmon_read(). Using the locked variant avoids having to drop and retake the mon_sel lock. If the lock was dropped, an interleaved monitor read which detects overflow would cause the overflow not to be accounted for in the saved value of mbwu_state->correction. The correction is no longer updated for disabled counters but this has no effect as the saved values are not expected to be useful for disabled counters. Fixes: 41e8a14950e1 ("arm_mpam: Track bandwidth counter state for power man= agement") Signed-off-by: Ben Horgan Tested-by: Gavin Shan Reviewed-by: Gavin Shan --- Changes since v1: 'continue' if not monitor not enabled add __ris_msmon_read() to avoid race on update of mbwu_state->correction (S= ashiko) update the commit message --- drivers/resctrl/mpam_devices.c | 63 ++++++++++++++++++++++------------ 1 file changed, 42 insertions(+), 21 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 6cba3ef21cc8..62562ce2f9aa 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1029,12 +1029,6 @@ struct mon_read { bool waited_timeout; }; =20 -static bool mpam_ris_has_mbwu_long_counter(struct mpam_msc_ris *ris) -{ - return (mpam_has_feature(mpam_feat_msmon_mbwu_63counter, &ris->props) || - mpam_has_feature(mpam_feat_msmon_mbwu_44counter, &ris->props)); -} - static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc) { int retry =3D 3; @@ -1202,13 +1196,12 @@ static u64 mpam_msmon_overflow_val(enum mpam_device= _features type, return overflow_val; } =20 -static void __ris_msmon_read(void *arg) +static void __ris_msmon_read_locked(struct mon_read *m) { u64 now; bool nrdy =3D false; bool config_mismatch; bool overflow =3D false; - struct mon_read *m =3D arg; struct mon_cfg *ctx =3D m->ctx; bool reset_on_next_read =3D false; struct mpam_msc_ris *ris =3D m->ris; @@ -1216,10 +1209,8 @@ static void __ris_msmon_read(void *arg) struct mpam_msc *msc =3D m->ris->vmsc->msc; u32 mon_sel, ctl_val, flt_val, cur_ctl, cur_flt; =20 - if (!mpam_mon_sel_lock(msc)) { - m->err =3D -EIO; - return; - } + mpam_mon_sel_lock_held(msc); + mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, ctx->mon) | FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); @@ -1312,7 +1303,6 @@ static void __ris_msmon_read(void *arg) default: m->err =3D -EINVAL; } - mpam_mon_sel_unlock(msc); =20 if (nrdy) m->err =3D -EBUSY; @@ -1323,6 +1313,21 @@ static void __ris_msmon_read(void *arg) *m->val +=3D now; } =20 +static void __ris_msmon_read(void *arg) +{ + struct mon_read *m =3D arg; + struct mpam_msc *msc =3D m->ris->vmsc->msc; + + if (!mpam_mon_sel_lock(msc)) { + m->err =3D -EIO; + return; + } + + __ris_msmon_read_locked(m); + + mpam_mon_sel_unlock(msc); +} + static int _msmon_read(struct mpam_component *comp, struct mon_read *arg) { int err, any_err =3D 0; @@ -1674,9 +1679,9 @@ static int mpam_restore_mbwu_state(void *_ris) =20 mbwu_state->reset_on_next_read =3D true; =20 - mpam_mon_sel_unlock(msc); + __ris_msmon_read_locked(&mwbu_arg); =20 - __ris_msmon_read(&mwbu_arg); + mpam_mon_sel_unlock(msc); } =20 return 0; @@ -1688,10 +1693,12 @@ static int mpam_save_mbwu_state(void *arg) int i; u64 val; struct mon_cfg *cfg; + struct mon_read mbwu_arg; u32 cur_flt, cur_ctl, mon_sel; struct mpam_msc_ris *ris =3D arg; struct msmon_mbwu_state *mbwu_state; struct mpam_msc *msc =3D ris->vmsc->msc; + struct mpam_class *class =3D ris->vmsc->comp->class; =20 for (i =3D 0; i < ris->props.num_mbwu_mon; i++) { if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) @@ -1707,17 +1714,31 @@ static int mpam_save_mbwu_state(void *arg) cur_flt =3D mpam_read_monsel_reg(msc, CFG_MBWU_FLT); cur_ctl =3D mpam_read_monsel_reg(msc, CFG_MBWU_CTL); =20 - if (mpam_ris_has_mbwu_long_counter(ris)) - val =3D mpam_msc_read_mbwu_l(msc); - else - val =3D mpam_read_monsel_reg(msc, MBWU); - cfg->mon =3D i; cfg->pmg =3D FIELD_GET(MSMON_CFG_x_FLT_PMG, cur_flt); cfg->match_pmg =3D FIELD_GET(MSMON_CFG_x_CTL_MATCH_PMG, cur_ctl); cfg->partid =3D FIELD_GET(MSMON_CFG_x_FLT_PARTID, cur_flt); - mbwu_state->correction +=3D val; mbwu_state->enabled =3D FIELD_GET(MSMON_CFG_x_CTL_EN, cur_ctl); + + if (!mbwu_state->enabled) { + mpam_mon_sel_unlock(msc); + continue; + } + + val =3D 0; + mbwu_arg =3D (struct mon_read) { + .ris =3D ris, + .ctx =3D cfg, + .type =3D mpam_msmon_choose_counter(class), + .val =3D &val, + }; + + __ris_msmon_read_locked(&mbwu_arg); + + mbwu_state->reset_on_next_read =3D true; + if (!mbwu_arg.err) + mbwu_state->correction =3D val; + mpam_mon_sel_unlock(msc); } =20 --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1F67A59E351 for ; Thu, 17 Sep 2026 14:56:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657027; cv=none; b=WrtvniCEd4jJbm4HZbWnFPE+mVJddVmlh3l1cPhr4mF4cMfqCtzdfx4QtIc6y4BOvP3g6Sr9nPcqnHFKWbx/OY7cyCsQ8opF4gDwdrcLpoj84Ywkle02jIrZl3HWIAncvYfE04wURmnYgFeIi0QWrSsKyjEX4wTlIrbV8d7919Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657027; c=relaxed/simple; bh=MGyp/ALeEy8uuqHVHvuEIqk/S0nAwjOKbP8LJumLzqk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lBxMtLHQwUgGbJ7orFHCZEXFOsL6DEm5EJnD1haEfKvotA18TvmdzGa5wpCEz+EluW66DDssFSmbPEsysEnsxktotWB5JB6vRbZirO0/AudVxk9BviGtpna3NJf4VoNBoPYeigUl+gEuaFzs5R5AguVMaSJT8GbY7QroA0J3s/Y= ARC-Authentication-Results: i=1; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QFpRxlaqHNExmxbF9n3J1atQLgPtiUU4QQzyLYIBvlV8hljnmGqUf4MFwbJT3pde0 DCZAf6WR8si/awQJQMxIdFNboJccRLoclMQLPKbF8z3mpBf3OykpFj0192kZU/1TYR uYyf2fz0EjVfoM4AUKuWW5qM6JpJ+6ReH2VfPVpY= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com, Gavin Shan Subject: [PATCH v2 07/12] arm_mpam: Initialize all of struct mon_read in mpam_restore_mbwu_state() Date: Thu, 17 Sep 2026 15:56:12 +0100 Message-ID: <20260917145617.2202986-8-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917145617.2202986-1-ben.horgan@arm.com> References: <20260917145617.2202986-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" m->err and *m->val may be read before initialization in __ris_msmon_read() when called from mpam_restore_mbwu_state(). Initialize the whole struct mon_read in mpam_restore_mbwu_state() and fix the spelling of mbwu in the name. Fixes: 41e8a14950e1 ("arm_mpam: Track bandwidth counter state for power man= agement") Signed-off-by: Ben Horgan Tested-by: Gavin Shan Reviewed-by: Gavin Shan --- Changes since v1: Set val to 0 (Lee) Use existing mbwu_arg variable --- drivers/resctrl/mpam_devices.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 62562ce2f9aa..cdc2d9d19e19 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1655,7 +1655,7 @@ static int mpam_restore_mbwu_state(void *_ris) { int i; u64 val; - struct mon_read mwbu_arg; + struct mon_read mbwu_arg; struct mpam_msc_ris *ris =3D _ris; struct msmon_mbwu_state *mbwu_state; struct mpam_msc *msc =3D ris->vmsc->msc; @@ -1672,14 +1672,17 @@ static int mpam_restore_mbwu_state(void *_ris) continue; } =20 - mwbu_arg.ris =3D ris; - mwbu_arg.ctx =3D &mbwu_state->cfg; - mwbu_arg.type =3D mpam_msmon_choose_counter(class); - mwbu_arg.val =3D &val; + val =3D 0; + mbwu_arg =3D (struct mon_read) { + .ris =3D ris, + .ctx =3D &mbwu_state->cfg, + .type =3D mpam_msmon_choose_counter(class), + .val =3D &val, + }; =20 mbwu_state->reset_on_next_read =3D true; =20 - __ris_msmon_read_locked(&mwbu_arg); + __ris_msmon_read_locked(&mbwu_arg); =20 mpam_mon_sel_unlock(msc); } --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E89A955820A for ; Thu, 17 Sep 2026 14:56:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657016; cv=none; b=Fm2nuAx65U+pPfmaqziE6L/R7XjBFI/cL0kXo4LOeji6iFU1JvV5xJdmKzcYrP0/DBbVtenEuU4HFRJnqRTjQpOK4CIwFvZAtY3G2ZBg0I+nU7xA4h6oCxOfFjWmTDhfx8uJLAhRSTu8lBy0iDkPEhKB2HDUdcSk8ZDWznXUqSE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657016; c=relaxed/simple; bh=u2/TSWpxe41vfNNykjOzkfh2PggVplqWQaKV/Iwvjkg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZF+0kNG4/gZUWvuaMJgVlhFbqo6KnWtKw22ApW4MNk5okMKxei36UFIeyKEfNesF7y5jxJnxgim6UDgesK3sHdlCPFeDBmy0ga2ep3IgM7Hb7qSNaW0/IMEfLYBIfVzsdU2fnA5SPWy0nRQyEJXFTADk272sGNK0mFFOMaIvn7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=pJZTWcC3; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="pJZTWcC3" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 19E082008; Thu, 17 Sep 2026 07:56:37 -0700 (PDT) Received: from e134344.cambridge.arm.com (unknown [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3B9EB3F86F; Thu, 17 Sep 2026 07:56:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789657000; bh=u2/TSWpxe41vfNNykjOzkfh2PggVplqWQaKV/Iwvjkg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pJZTWcC3qLI4PbTSiaE1hVkqZ127fjuB9Cu9o6gfui5tmS5VuOINoyXH8rJzPlgvS uya6HPBlvw76OVRkz445MJ4pj4PMRhoNSo7ewbx6gpTm0h5hQ+wYJ7pWaxA4d0pGI/ SccKbZ4S3fCJjL/ZZseRXMArTNVdFRETmhNXlNg8= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com, Gavin Shan Subject: [PATCH v2 08/12] arm_mpam: resctrl: Correct check that existing class is L3 Date: Thu, 17 Sep 2026 15:56:13 +0100 Message-ID: <20260917145617.2202986-9-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917145617.2202986-1-ben.horgan@arm.com> References: <20260917145617.2202986-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The class used to back mbm_total_bytes can be either at the L3 or the memory. If a platform had candidate classes at both the memory and the L3 then, as the check for whether the existing class is L3 or not in counter_update_class() is broken, the class that will be chosen depends on which order the classes are considered and so the probe order. Fix the check. Fixes: 1458c4f05335 ("arm_mpam: resctrl: Add support for csu counters") Tested-by: Gavin Shan Signed-off-by: Ben Horgan Reviewed-by: Gavin Shan --- drivers/resctrl/mpam_resctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 9d223057953a..b825bd90d4bd 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -1076,7 +1076,7 @@ static void counter_update_class(enum resctrl_event_i= d evt_id, struct mpam_class *existing_class =3D mpam_resctrl_counters[evt_id].class; =20 if (existing_class) { - if (class->level =3D=3D 3) { + if (existing_class->level =3D=3D 3) { pr_debug("Existing class is L3 - L3 wins\n"); return; } --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8380B55931E for ; Thu, 17 Sep 2026 14:56:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657031; cv=none; b=C5sV4yRxy4uCXFskMQUpaMnE8qcNsmiidMag4O3MJw3TKZlk3DCVeVtzM84ULX/WyvyFb9wTajmj/zyi2g3qGEmdwt95bwrRbWqOquyr1rNZfe/JMZhvfQVudYI+drkFy+WGpa2Zc/p8OfOeK7WPb22uyif7uVSWxvP4M0ix2YE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657031; c=relaxed/simple; bh=2W4vg8a0BH3+OFw+MBFW0cOa1L2xE5ZnqmXZrMtVPsM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cK9jfvjw+LWpuBgkeuyOK9PpxHQJg9lTaXhKszdSPOJMxiaIIn+6KkDPqiQeekXzYhRmXgjwyI+FOevdhA3icuuY7+Ivhz5MTO7mowj9hIIroVE/aekM7czKjLB+zK0uijSYquF51ERrMsQxNvNP8PmXlUaqNZyFKmgANUXAuzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=K/ADxr8L; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="K/ADxr8L" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CC574201B; Thu, 17 Sep 2026 07:56:38 -0700 (PDT) Received: from e134344.cambridge.arm.com (unknown [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 01DEF3F86F; Thu, 17 Sep 2026 07:56:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789657002; bh=2W4vg8a0BH3+OFw+MBFW0cOa1L2xE5ZnqmXZrMtVPsM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K/ADxr8LGT+NRfiYYQX71AUBp4ZCgJLxTOTedZnU/VYIV+CIdfFT+WhA5g/dNvuk4 9RMwKqogC2BGIKZWorYLLZyp76aB/b5FVWKrZT0BkFE8tZJQ+olUswpMXKNMcuM/L+ x517IB1+QrY84D3rFVuhCoYZjQuRA1LOq8q7Igcs= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com, Gavin Shan Subject: [PATCH v2 09/12] arm_mpam: resctrl: Make read_mon_cdp_safe() self consistent Date: Thu, 17 Sep 2026 15:56:14 +0100 Message-ID: <20260917145617.2202986-10-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917145617.2202986-1-ben.horgan@arm.com> References: <20260917145617.2202986-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When read_mon_cdp_safe() is called with cdp_enabled equal to false then the reading returned in val is the sum of the monitor values for the given component. However, when cdp_enabled equal to true it is again the sum of the monitor values but with the initial value of val also added. Both resctrl_arch_cntr_read() and resctrl_arch_rmid_read() call read_mon_cdp_safe() and are documented to return the val directly without consideration of the older value. The val is always zeroed before read_mon_cdp_safe() is called except in __check_limbo() and __l3_mon_event_count_sum() but the latter is not relevant on MPAM systems. The extra accumulation in __check_limbo() means when there are multiple RMIDs in limbo some of them may be marked dirty when they are already clean. Change the cdp_enabled equals true case to match the false case and the documentation of the resctrl arch hooks. Fixes: fb56b29932ca ("arm_mpam: resctrl: Add resctrl_arch_rmid_read()") Signed-off-by: Ben Horgan Tested-by: Gavin Shan Reviewed-by: Gavin Shan --- Add fixes tag as actually fixes an issue (Sashiko) Update commit message --- drivers/resctrl/mpam_resctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index b825bd90d4bd..321741a702fe 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -497,7 +497,7 @@ static int read_mon_cdp_safe(struct mpam_resctrl_mon *m= on, struct mpam_component if (err) return err; =20 - *val +=3D code_val + data_val; + *val =3D code_val + data_val; return 0; } =20 --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2550C5A0AC0 for ; Thu, 17 Sep 2026 14:56:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657045; cv=none; b=PyqY+o9G2kmR2tNR0wDoOn/WnuX8DMPrHrNX7qXVqo4i7+UaF+n1+H5q55RU7fr2zj6Jk/4ZkL5wFrIHlqMWhW9hLA55FCSCh0J4Okokw2eXY4gHMvcWEFKbioCljZboV0w+6klUtvb7m8BkLjsF15W3NlMU01aiHrM/zo7ojAA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657045; c=relaxed/simple; bh=RpO8zOr6jZcL27MkYikOaNk4efDL6B/6X8Hi1ZdtHW4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t71tNenU3DU3p6bp6GANkakzmO9VdMxGWW2AwwnvgleUw/p0lIXlVgfWNyp2o7XeC4ARNM9bDUyK8yPSIYrw76XAbkfGtXMPiCip88PWKdYup3A4e+27gHjk6bpne6sUVJFu2ej4ZA0fZwozZsJtFxJbNi3+Fnmj0InBCD+M5Xw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=RX3NAQJ0; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="RX3NAQJ0" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A1C11476; Thu, 17 Sep 2026 07:56:40 -0700 (PDT) Received: from e134344.cambridge.arm.com (unknown [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B27F83F86F; Thu, 17 Sep 2026 07:56:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789657004; bh=RpO8zOr6jZcL27MkYikOaNk4efDL6B/6X8Hi1ZdtHW4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RX3NAQJ0exD9uuKhKEmGyYyBarHOBOm6jXMVcpW4qKypNCf+oC51ZYTS2oWr9i8mM YhDlcEtzy7C559IwRUVmxfNTHYkAVXzGFCw/0ds4Ll1l/S5LC614axefrxOzgieozW W8QVDlmV9qsvb5VVc9Ouwt2dY9+LgBsUwMEB1mfQ= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com, Gavin Shan Subject: [PATCH v2 10/12] arm_mpam: Don't loop forever if there is the maximum possible amount of PARTIDs Date: Thu, 17 Sep 2026 15:56:15 +0100 Message-ID: <20260917145617.2202986-11-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917145617.2202986-1-ben.horgan@arm.com> References: <20260917145617.2202986-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On a theoretical platform with the maximum possible number of usable PARTIDs, 0XFFFF, the loops iterating over PARTID in mpam_reset_ris() and mpam_reprogram_ris() will never reach their termination condition leading to a system hang when register the cpu hotplug handlers when MPAM is enabling. Fix these loops. Fixes: f188a36ca241 ("arm_mpam: Reset MSC controls from cpuhp callbacks") Fixes: 09b89d2a72f3 ("arm_mpam: Allow configuration to be applied and resto= red during cpu online") Signed-off-by: Ben Horgan Tested-by: Gavin Shan Reviewed-by: Gavin Shan --- drivers/resctrl/mpam_devices.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index cdc2d9d19e19..10fc5168699b 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1754,7 +1754,7 @@ static int mpam_save_mbwu_state(void *arg) */ static int mpam_reset_ris(void *arg) { - u16 partid, partid_max; + u16 partid_max; struct mpam_config reset_cfg =3D {}; struct mpam_msc_ris *ris =3D arg; =20 @@ -1764,7 +1764,7 @@ static int mpam_reset_ris(void *arg) spin_lock(&partid_max_lock); partid_max =3D mpam_partid_max; spin_unlock(&partid_max_lock); - for (partid =3D 0; partid <=3D partid_max; partid++) + for (u32 partid =3D 0; partid <=3D partid_max; partid++) mpam_reprogram_ris_partid(ris, partid, &reset_cfg); =20 return 0; @@ -1811,7 +1811,6 @@ static int __write_config(void *arg) =20 static void mpam_reprogram_msc(struct mpam_msc *msc) { - u16 partid; bool reset; struct mpam_config *cfg; struct mpam_msc_ris *ris; @@ -1835,7 +1834,7 @@ static void mpam_reprogram_msc(struct mpam_msc *msc) arg.comp =3D ris->vmsc->comp; arg.ris =3D ris; reset =3D true; - for (partid =3D 0; partid <=3D mpam_partid_max; partid++) { + for (u32 partid =3D 0; partid <=3D mpam_partid_max; partid++) { cfg =3D &ris->vmsc->comp->cfg[partid]; if (!bitmap_empty(cfg->features, MPAM_FEATURE_LAST)) reset =3D false; --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B499A5A5131 for ; Thu, 17 Sep 2026 14:56:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657030; cv=none; b=trQklb1K52A6VUcaMeNzlVt5+MN5caU7NniaTwTQfWJtNtQp9QwcHiDfbp8cIDyK15pq/9Woq+BqqNzN/rwQ+F2Ele2lnA8LoNjBrYZ6o61E8do5V+htyDlLeVDXcD6VxfrvFZ3M1ngyinqxAywEF6+EFcE7upofDjWy5/zu8TY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657030; c=relaxed/simple; bh=97Sj1papgKbZfZ9Y/oUn8Fq54WwKNnH1rTCLTp8yrc0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FTxloLPWKJkgSeFrqkA1P2xcCzNZOulJmkHent/saq503ZyzW3eI+nx9SXDLe2rILsW7lbXgLNMejMkX7R44fvuIRKccTVsmfgMihNa++t4oHV4KJ63Ej4fZ1NpWx47GRWkWSHTdRmRa1iN76II1UM5eSpvYDq5bIwFR/ucH0TA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=kowBOuii; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="kowBOuii" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E3C0202C; Thu, 17 Sep 2026 07:56:42 -0700 (PDT) Received: from e134344.cambridge.arm.com (unknown [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6F22A3F86F; Thu, 17 Sep 2026 07:56:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789657005; bh=97Sj1papgKbZfZ9Y/oUn8Fq54WwKNnH1rTCLTp8yrc0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kowBOuiirP6gixi9Ls22o4QmnlevEKFEIlEOss2zXha4QR1mVBq/rWQhWSoFZGK2i liqug7r55sox1O/nzcwTJfSnPs1QN/RzxqiDRI9MDcSIHIVYLJTalFQPjpnIuKRRGy vSFk+P9tC76m8i2p97OB5SR+G/GVNqTTktsx8eOg= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com, Gavin Shan Subject: [PATCH v2 11/12] arm_mpam: Switch to kvzmalloc_objs() for allocation of component cfg Date: Thu, 17 Sep 2026 15:56:16 +0100 Message-ID: <20260917145617.2202986-12-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917145617.2202986-1-ben.horgan@arm.com> References: <20260917145617.2202986-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Each component cfg is sized by the size of a per-PARTID multiplied by the number of PARTIDs. On a platform sized to push the limits of the specification, the allocation using kzalloc_objs() will consistently fail. Change to use kvzmalloc_objs() so that large allocations fall back to vmalloc() based allocations. Fixes: 09b89d2a72f3 ("arm_mpam: Allow configuration to be applied and resto= red during cpu online") Signed-off-by: Ben Horgan Tested-by: Gavin Shan Reviewed-by: Gavin Shan --- drivers/resctrl/mpam_devices.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 10fc5168699b..d74292f8cdfd 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -157,7 +157,7 @@ static void mpam_free_garbage(void) if (iter->pdev) devm_kfree(&iter->pdev->dev, iter->to_free); else - kfree(iter->to_free); + kvfree(iter->to_free); } } =20 @@ -2692,7 +2692,7 @@ static int __allocate_component_cfg(struct mpam_compo= nent *comp) if (comp->cfg) return 0; =20 - comp->cfg =3D kzalloc_objs(*comp->cfg, mpam_partid_max + 1); + comp->cfg =3D kvzalloc_objs(*comp->cfg, mpam_partid_max + 1); if (!comp->cfg) return -ENOMEM; =20 --=20 2.43.0 From nobody Fri Sep 25 02:09:14 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 835A059E337 for ; Thu, 17 Sep 2026 14:56:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657037; cv=none; b=b2hmyhh4MnPKERVulR5gY+Ypz2Gr4QkfEDqyj3mzZ6ipqndoBz3+jpMw0YB8i0FKBMTYiIi5Xo0gUIrnTez8v+jTx2ZnBvFW+5r7KH0GUrmsBIBrVGrDH3mhYmrQ+XRw4HwZ+oqfA+wNPqFfECqGUJD/zT606TInFqTCmaalZDo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789657037; c=relaxed/simple; bh=KXTRQ8B7NuAawelRtl9Xn3/aug9ykZjYKPq/c2H+xsk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ml+t9sWhBiyEMoZY4k5lmSWey3wUSQy9huAM4PVn7uZY779aJunvNtBfYo8GlXJ1spaQ0sjvfsZ6ZDBjL9yH7Crvk7ikVvkKRTMudzDy7yBTFQNacFF4Q4h6vaNnLZ8DbOQnBcD3gCZrvl6svMQZnvjQbu94eYeEfZssmiFGbmM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=oPUjhHv+; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="oPUjhHv+" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0C1AF204C; Thu, 17 Sep 2026 07:56:44 -0700 (PDT) Received: from e134344.cambridge.arm.com (unknown [10.2.212.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3498B3F86F; Thu, 17 Sep 2026 07:56:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789657007; bh=KXTRQ8B7NuAawelRtl9Xn3/aug9ykZjYKPq/c2H+xsk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oPUjhHv+ZnTx+s/GIzhBl8HFTp7A2OJXfiOf8PRsemafBk3jxN/BJL3O5/VRupQzP sM/0n+Iw7M81TLFQq7DnHmf4vQ7J2uDd7mc/MqOYIPAYWKFI+tB8lMcS/qI93gce/S DxZLgXcvdN0blyQDKgW5MX+YIBItWPP0KufNMBEc= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, andre.przywara@arm.com, Sashiko Subject: [PATCH v2 12/12] arm_mpam: resctrl: Don't stop early when tearing down a class Date: Thu, 17 Sep 2026 15:56:17 +0100 Message-ID: <20260917145617.2202986-13-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917145617.2202986-1-ben.horgan@arm.com> References: <20260917145617.2202986-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" An MPAM class can back more than one control and more than one monitor. mpam_resctrl_teardown_class() iterates through all the controls but stops if it finds a match which means classes backing more than one class aren't torn down. The same for monitors, in which case the mbwu counters will be leaked. Stop terminating the loops early. As we are already changing mpam_resctrl_teardown_class() remove the misleading comment. It doesn't call resctrl_exit() and isn't required to do so as the only caller does it first. Fixes: fb481ec08699 ("arm_mpam: resctrl: Call resctrl_init() on platforms t= hat can support resctrl") Reported-by: Sashiko Signed-off-by: Ben Horgan --- Changes since v1: New patch --- drivers/resctrl/mpam_resctrl.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 321741a702fe..9cec5843e8fa 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -1943,10 +1943,6 @@ static void mpam_resctrl_teardown_mon(struct mpam_re= sctrl_mon *mon, struct mpam_ mon->mbwu_idx_to_mon =3D NULL; } =20 -/* - * The driver is detaching an MSC from this class, if resctrl was using it, - * pull on resctrl_exit(). - */ void mpam_resctrl_teardown_class(struct mpam_class *class) { struct mpam_resctrl_res *res; @@ -1957,17 +1953,14 @@ void mpam_resctrl_teardown_class(struct mpam_class = *class) might_sleep(); =20 for_each_mpam_resctrl_control(res, rid) { - if (res->class =3D=3D class) { + if (res->class =3D=3D class) res->class =3D NULL; - break; - } } for_each_mpam_resctrl_mon(mon, eventid) { if (mon->class =3D=3D class) { mon->class =3D NULL; =20 mpam_resctrl_teardown_mon(mon, class); - break; } } } --=20 2.43.0