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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli On RK3588, each memory channel has its own DDR bandwidth monitor silicon, and each instance of that has its own clock gate that drives the monitor logic. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- include/dt-bindings/clock/rockchip,rk3588-cru.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-b= indings/clock/rockchip,rk3588-cru.h index 7528034cff56..6ea25019ebb4 100644 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -738,6 +738,10 @@ #define I2S1_8CH_MCLKOUT_TO_IO 723 #define I2S2_2CH_MCLKOUT_TO_IO 724 #define I2S3_2CH_MCLKOUT_TO_IO 725 +#define PCLK_DDR_MON_CH0 726 +#define PCLK_DDR_MON_CH1 727 +#define PCLK_DDR_MON_CH2 728 +#define PCLK_DDR_MON_CH3 729 =20 /* scmi-clocks indices */ =20 --=20 2.53.0 From nobody Fri Sep 25 02:06:05 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A53A548541; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli RK3588's DFI has pclks for each channel. They just weren't noticed as missing until now because nothing ever gates them, and they're ungated by default on power-on. The RK3399 clock situation needs no changes, as there the hardware really just has one monitoring unit for both channels. Add these clocks to the binding, so that drivers for this device can properly know about their existence. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- .../bindings/devfreq/event/rockchip,dfi.yaml | 84 ++++++++++++++++++= ---- 1 file changed, 72 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.y= aml b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml index 50d3fabe958d..d6e06a9bea19 100644 --- a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml @@ -17,11 +17,19 @@ properties: - rockchip,rk3588-dfi =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 =20 clock-names: + minItems: 1 + maxItems: 4 items: - - const: pclk_ddr_mon + - enum: + - pclk_ddr_mon + - pclk_ddr_mon_ch0 + - const: pclk_ddr_mon_ch1 + - const: pclk_ddr_mon_ch2 + - const: pclk_ddr_mon_ch3 =20 interrupts: minItems: 1 @@ -40,17 +48,50 @@ required: - interrupts - reg =20 -if: - properties: - compatible: - contains: - enum: - - rockchip,rk3399-dfi +allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3399-dfi + then: + properties: + clocks: + items: + - description: + clock driving the DDR monitoring logic for all channels + clock-names: + items: + - const: pclk_ddr_mon + required: + - clocks + - clock-names =20 -then: - required: - - clocks - - clock-names + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3588-dfi + then: + properties: + clocks: + items: + - description: + clock driving the DDR monitoring logic for memory channel 0 + - description: + clock driving the DDR monitoring logic for memory channel 1 + - description: + clock driving the DDR monitoring logic for memory channel 2 + - description: + clock driving the DDR monitoring logic for memory channel 3 + clock-names: + items: + - const: pclk_ddr_mon_ch0 + - const: pclk_ddr_mon_ch1 + - const: pclk_ddr_mon_ch2 + - const: pclk_ddr_mon_ch3 =20 additionalProperties: false =20 @@ -72,3 +113,22 @@ examples: clock-names =3D "pclk_ddr_mon"; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260917-rockchip-dfi-cleanup-v1-3-4f00a97a69a6@collabora.com> References: <20260917-rockchip-dfi-cleanup-v1-0-4f00a97a69a6@collabora.com> In-Reply-To: <20260917-rockchip-dfi-cleanup-v1-0-4f00a97a69a6@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Sascha Hauer Cc: Nicolas Frattaroli , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9544; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=y65RBL8I0JRF1EhPVMN7EiGUEBnlIwsg0XksNw4AoAc=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqr7+Fnij/OsEOFye8+laUQi9WXJoNmxfBL4 6+Iao1KkhJfnYkCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqq+/hAAoJENju1/PI O/qaaGsP/RUiYEaltcRqOAl2464GnmWS6SSYVs2ChA4uuDGPYN0+ZvkO6nKOZv14WAc4ZpHkzl9 EJ6la7DDZpKApyjosKs0w8yAFWvDdM8r7BPMO8Jx1fr60tAmTyfVBgxPMeiM7goUueupY4vrYr3 hKKb377dIXlyztX4F5TRqYxkfzcm0lBSWXOtoAw5cGlSZIHo0jsFdtMpEMGQpBDdnv9vWVOPwJl HftuyqgSfvNKp/aW8Y4RoWHakuxM7JkLQLoU41AM+kBWK5El8l36l74mERzgjDctAh3fUpouuM4 AgXhVo7x46ez8F5D4TBTOnnVz3FasC5ZaGi90aZPpbOXQK92j9PfVaSGwAbPM0AATfKoCQKO2Ke dbAfxMNyK4dliL08RywCuqd5D25a98S8ozo/6qqN448+OBFEXULU4VxGkCKK11f+/rLSZTyDM0z ahhvQBWiyuvsWbMUv0zRgxccVwBybAoiM7H56VvMMJhfWQ9J3GEYO2+WaezXmOWU7c7P/YBsnFl Jqbj6xWKLq8hQxkLkzOi6QrZkdm8a0PKWsQmXEWlh5uFH5HEiUsxV0Buy8b/1viBGGacfIDNU0f pEnD3YXgVGBcYLu/LPAwu1wM2GFA6Mxfe5iLmagNhtd2qH4NW+/jYdtRAqAd+jxSayw2Lkhl6Yg KhmK04eR8EI32k6EEqp4t3w== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli The rockchip-dfi driver supports several variants of the DDR monitoring hardware. The differences in these variants are handled with one init function for each variant. However, some of the members that these init functions set are actually constants, specific to that variant, with no runtime involvement from reading registers or anything. Refactor the code to move those values (and the soc_init function pointer) into a new struct. Declare some const instances of this variant struct, and use it wherever needed. Signed-off-by: Nicolas Frattaroli --- drivers/devfreq/event/rockchip-dfi.c | 94 +++++++++++++++++++++-----------= ---- 1 file changed, 54 insertions(+), 40 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/r= ockchip-dfi.c index 255aee1bdd91..5339616f7ca6 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -103,7 +103,6 @@ struct rockchip_dfi { struct mutex mutex; u32 ddr_type; unsigned int channel_mask; - unsigned int max_channels; enum cpuhp_state cpuhp_state; struct hlist_node node; struct pmu pmu; @@ -112,11 +111,17 @@ struct rockchip_dfi { int active_events; int burst_len; int buswidth[DMC_MAX_CHANNELS]; - int ddrmon_stride; - bool ddrmon_ctrl_single; u32 lp5_bank_mode; bool lp5_ckr; /* true if in 4:1 command-to-data clock ratio mode */ unsigned int count_multiplier; /* number of data clocks per count */ + const struct rockchip_dfi_variant *variant; +}; + +struct rockchip_dfi_variant { + int (*init)(struct rockchip_dfi *dfi); + int stride; + bool ctrl_single; + unsigned int max_channels; }; =20 static int rockchip_dfi_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *ctr= l) @@ -188,7 +193,7 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi) if (ret) goto out; =20 - for (i =3D 0; i < dfi->max_channels; i++) { + for (i =3D 0; i < dfi->variant->max_channels; i++) { =20 if (!(dfi->channel_mask & BIT(i))) continue; @@ -197,16 +202,16 @@ static int rockchip_dfi_enable(struct rockchip_dfi *d= fi) writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_TIMER_CNT_EN, 0) | FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 0) | FIELD_PREP_WM16(DDRMON_CTRL_HARDWARE_EN, 0), - dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + dfi_regs + i * dfi->variant->stride + DDRMON_CTRL); =20 - writel_relaxed(ctrl, dfi_regs + i * dfi->ddrmon_stride + + writel_relaxed(ctrl, dfi_regs + i * dfi->variant->stride + DDRMON_CTRL); =20 /* enable count, use software mode */ writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 1), - dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + dfi_regs + i * dfi->variant->stride + DDRMON_CTRL); =20 - if (dfi->ddrmon_ctrl_single) + if (dfi->variant->ctrl_single) break; } out: @@ -229,14 +234,14 @@ static void rockchip_dfi_disable(struct rockchip_dfi = *dfi) if (dfi->usecount > 0) goto out; =20 - for (i =3D 0; i < dfi->max_channels; i++) { + for (i =3D 0; i < dfi->variant->max_channels; i++) { if (!(dfi->channel_mask & BIT(i))) continue; =20 writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 0), - dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + dfi_regs + i * dfi->variant->stride + DDRMON_CTRL); =20 - if (dfi->ddrmon_ctrl_single) + if (dfi->variant->ctrl_single) break; } =20 @@ -250,17 +255,17 @@ static void rockchip_dfi_read_counters(struct rockchi= p_dfi *dfi, struct dmc_coun u32 i; void __iomem *dfi_regs =3D dfi->regs; =20 - for (i =3D 0; i < dfi->max_channels; i++) { + for (i =3D 0; i < dfi->variant->max_channels; i++) { if (!(dfi->channel_mask & BIT(i))) continue; res->c[i].read_access =3D readl_relaxed(dfi_regs + - DDRMON_CH0_RD_NUM + i * dfi->ddrmon_stride); + DDRMON_CH0_RD_NUM + i * dfi->variant->stride); res->c[i].write_access =3D readl_relaxed(dfi_regs + - DDRMON_CH0_WR_NUM + i * dfi->ddrmon_stride); + DDRMON_CH0_WR_NUM + i * dfi->variant->stride); res->c[i].access =3D readl_relaxed(dfi_regs + - DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->ddrmon_stride); + DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->variant->stride); res->c[i].clock_cycles =3D readl_relaxed(dfi_regs + - DDRMON_CH0_COUNT_NUM + i * dfi->ddrmon_stride); + DDRMON_CH0_COUNT_NUM + i * dfi->variant->stride); } } =20 @@ -297,7 +302,7 @@ static int rockchip_dfi_get_event(struct devfreq_event_= dev *edev, rockchip_dfi_read_counters(dfi, &count); =20 /* We can only report one channel, so find the busiest one */ - for (i =3D 0; i < dfi->max_channels; i++) { + for (i =3D 0; i < dfi->variant->max_channels; i++) { u32 a, c; =20 if (!(dfi->channel_mask & BIT(i))) @@ -336,7 +341,7 @@ static void rockchip_ddr_perf_counters_add(struct rockc= hip_dfi *dfi, const struct dmc_count *last =3D &dfi->last_perf_count; int i; =20 - for (i =3D 0; i < dfi->max_channels; i++) { + for (i =3D 0; i < dfi->variant->max_channels; i++) { res->c[i].read_access =3D dfi->total_count.c[i].read_access + (u32)(now->c[i].read_access - last->c[i].read_access); res->c[i].write_access =3D dfi->total_count.c[i].write_access + @@ -477,11 +482,11 @@ static u64 rockchip_ddr_perf_event_get_count(struct p= erf_event *event) count =3D total.c[0].clock_cycles * dfi->count_multiplier; break; case PERF_EVENT_READ_BYTES: - for (i =3D 0; i < dfi->max_channels; i++) + for (i =3D 0; i < dfi->variant->max_channels; i++) count +=3D total.c[i].read_access * blen * dfi->buswidth[i]; break; case PERF_EVENT_WRITE_BYTES: - for (i =3D 0; i < dfi->max_channels; i++) + for (i =3D 0; i < dfi->variant->max_channels; i++) count +=3D total.c[i].write_access * blen * dfi->buswidth[i]; break; case PERF_EVENT_READ_BYTES0: @@ -509,7 +514,7 @@ static u64 rockchip_ddr_perf_event_get_count(struct per= f_event *event) count =3D total.c[3].write_access * blen * dfi->buswidth[3]; break; case PERF_EVENT_BYTES: - for (i =3D 0; i < dfi->max_channels; i++) + for (i =3D 0; i < dfi->variant->max_channels; i++) count +=3D total.c[i].access * blen * dfi->buswidth[i]; break; } @@ -726,14 +731,10 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) dfi->ddr_type =3D FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val); =20 dfi->channel_mask =3D GENMASK(1, 0); - dfi->max_channels =3D 2; =20 dfi->buswidth[0] =3D FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) =3D=3D = 0 ? 4 : 2; dfi->buswidth[1] =3D FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) =3D=3D = 0 ? 4 : 2; =20 - dfi->ddrmon_stride =3D 0x14; - dfi->ddrmon_ctrl_single =3D true; - return 0; }; =20 @@ -756,13 +757,9 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi) dfi->ddr_type |=3D FIELD_GET(RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg= 3) << 3; =20 dfi->channel_mask =3D BIT(0); - dfi->max_channels =3D 1; =20 dfi->buswidth[0] =3D FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) =3D=3D= 0 ? 4 : 2; =20 - dfi->ddrmon_stride =3D 0x0; /* not relevant, we only have a single channe= l on this SoC */ - dfi->ddrmon_ctrl_single =3D true; - return 0; }; =20 @@ -791,9 +788,7 @@ static int rk3588_dfi_init(struct rockchip_dfi *dfi) dfi->buswidth[3] =3D FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) =3D=3D= 0 ? 4 : 2; dfi->channel_mask =3D FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) | FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2; - dfi->max_channels =3D 4; =20 - dfi->ddrmon_stride =3D 0x4000; dfi->count_multiplier =3D 2; =20 if (dfi->ddr_type =3D=3D ROCKCHIP_DDRTYPE_LPDDR5) { @@ -807,10 +802,30 @@ static int rk3588_dfi_init(struct rockchip_dfi *dfi) return 0; }; =20 +static const struct rockchip_dfi_variant rk3399_variant =3D { + .init =3D rk3399_dfi_init, + .stride =3D 0x14, + .ctrl_single =3D true, + .max_channels =3D 2, +}; + +static const struct rockchip_dfi_variant rk3568_variant =3D { + .init =3D rk3568_dfi_init, + .stride =3D 0x0, + .ctrl_single =3D true, + .max_channels =3D 1, +}; + +static const struct rockchip_dfi_variant rk3588_variant =3D { + .init =3D rk3588_dfi_init, + .stride =3D 0x4000, + .max_channels =3D 4, +}; + static const struct of_device_id rockchip_dfi_id_match[] =3D { - { .compatible =3D "rockchip,rk3399-dfi", .data =3D rk3399_dfi_init }, - { .compatible =3D "rockchip,rk3568-dfi", .data =3D rk3568_dfi_init }, - { .compatible =3D "rockchip,rk3588-dfi", .data =3D rk3588_dfi_init }, + { .compatible =3D "rockchip,rk3399-dfi", .data =3D &rk3399_variant }, + { .compatible =3D "rockchip,rk3568-dfi", .data =3D &rk3568_variant }, + { .compatible =3D "rockchip,rk3588-dfi", .data =3D &rk3588_variant }, { }, }; =20 @@ -822,17 +837,16 @@ static int rockchip_dfi_probe(struct platform_device = *pdev) struct rockchip_dfi *dfi; struct devfreq_event_desc *desc; struct device_node *np =3D pdev->dev.of_node, *node; - int (*soc_init)(struct rockchip_dfi *dfi); int ret; =20 - soc_init =3D of_device_get_match_data(&pdev->dev); - if (!soc_init) - return -EINVAL; - dfi =3D devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL); if (!dfi) return -ENOMEM; =20 + dfi->variant =3D of_device_get_match_data(dev); + if (!dfi->variant) + return -EINVAL; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli The perf subsystem's PERF_PMU_CAP_NO_INTERRUPT is a bit of a misnomer.[1] Instead of meaning that the PMU has no interrupt, it actually means that the PMU does support sampling. On CPU PMUs, this is equivalent to not having an interrupt, but for uncore PMUs like the rockchip-dfi PMU is, no meaningful sample data could ever be generated regardless of whether or not there is an interrupt, as it is not a CPU. Since rockchip-dfi doesn't seem to make use of the interrupt the DT provides it with anyway, this was probably never a confusion that existed in this case; the capability flag was likely just forgotten. Add PERF_PMU_CAP_NO_INTERRUPT to the set flags for the pmu struct's capabilities member, so that the perf core knows about this limitation. Fixes: 4d586b5724d3 ("PM / devfreq: rockchip-dfi: Add perf support") Link: https://lore.kernel.org/all/20250619140442.GH1613376@noisy.programmin= g.kicks-ass.net/ [1] Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- drivers/devfreq/event/rockchip-dfi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/r= ockchip-dfi.c index 5339616f7ca6..dd9edfd6a674 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -646,7 +646,7 @@ static int rockchip_ddr_perf_init(struct rockchip_dfi *= dfi) seqlock_init(&dfi->count_seqlock); =20 pmu->module =3D THIS_MODULE; - pmu->capabilities =3D PERF_PMU_CAP_NO_EXCLUDE; + pmu->capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT; pmu->task_ctx_nr =3D perf_invalid_context; pmu->attr_groups =3D attr_groups; pmu->event_init =3D rockchip_ddr_perf_event_init; --=20 2.53.0 From nobody Fri Sep 25 02:06:05 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83E3F550DC2; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli Currently, the only clock rockchip-dfi will ever use is on the rk3399, namely pclk_ddr_mon. However, this is mainly because every other SoC's mainline clock tree and bindings are probably lying and not telling us about some clock gate branches that do exist in hardware, but nothing happens ever gate. Get preparations out of the way to fix this by moving to the bulk clock APIs, which will make handling the one-clock-per-channel cases easier to deal with. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- drivers/devfreq/event/rockchip-dfi.c | 39 +++++++++++++++++++++++++++-----= ---- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/r= ockchip-dfi.c index dd9edfd6a674..b61ec500eaed 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -98,7 +98,7 @@ struct rockchip_dfi { struct device *dev; void __iomem *regs; struct regmap *regmap_pmu; - struct clk *clk; + struct clk_bulk_data *clocks; int usecount; struct mutex mutex; u32 ddr_type; @@ -122,6 +122,8 @@ struct rockchip_dfi_variant { int stride; bool ctrl_single; unsigned int max_channels; + const char * const *clk_names; + unsigned int num_clks; }; =20 static int rockchip_dfi_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *ctr= l) @@ -183,9 +185,10 @@ static int rockchip_dfi_enable(struct rockchip_dfi *df= i) if (dfi->usecount > 1) goto out; =20 - ret =3D clk_prepare_enable(dfi->clk); + ret =3D clk_bulk_prepare_enable(dfi->variant->num_clks, dfi->clocks); if (ret) { - dev_err(&dfi->edev->dev, "failed to enable dfi clk: %d\n", ret); + dev_err(&dfi->edev->dev, "failed to enable dfi clocks: %pe\n", + ERR_PTR(ret)); goto out; } =20 @@ -245,7 +248,7 @@ static void rockchip_dfi_disable(struct rockchip_dfi *d= fi) break; } =20 - clk_disable_unprepare(dfi->clk); + clk_bulk_disable_unprepare(dfi->variant->num_clks, dfi->clocks); out: mutex_unlock(&dfi->mutex); } @@ -721,11 +724,6 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) struct regmap *regmap_pmu =3D dfi->regmap_pmu; u32 val; =20 - dfi->clk =3D devm_clk_get(dfi->dev, "pclk_ddr_mon"); - if (IS_ERR(dfi->clk)) - return dev_err_probe(dfi->dev, PTR_ERR(dfi->clk), - "Cannot get the clk pclk_ddr_mon\n"); - /* get ddr type */ regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); dfi->ddr_type =3D FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val); @@ -802,11 +800,17 @@ static int rk3588_dfi_init(struct rockchip_dfi *dfi) return 0; }; =20 +static const char * const rk3399_clk_names[] =3D { + "pclk_ddr_mon", +}; + static const struct rockchip_dfi_variant rk3399_variant =3D { .init =3D rk3399_dfi_init, .stride =3D 0x14, .ctrl_single =3D true, .max_channels =3D 2, + .clk_names =3D rk3399_clk_names, + .num_clks =3D ARRAY_SIZE(rk3399_clk_names), }; =20 static const struct rockchip_dfi_variant rk3568_variant =3D { @@ -837,6 +841,7 @@ static int rockchip_dfi_probe(struct platform_device *p= dev) struct rockchip_dfi *dfi; struct devfreq_event_desc *desc; struct device_node *np =3D pdev->dev.of_node, *node; + unsigned int i; int ret; =20 dfi =3D devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL); @@ -868,6 +873,22 @@ static int rockchip_dfi_probe(struct platform_device *= pdev) desc->driver_data =3D dfi; desc->name =3D np->name; =20 + if (dfi->variant->num_clks) { + /* NB: CCF is fine with us leaving this NULL if num_clks =3D 0 */ + dfi->clocks =3D devm_kcalloc(dev, dfi->variant->num_clks, + sizeof(*dfi->clocks), GFP_KERNEL); + if (!dfi->clocks) + return -ENOMEM; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli On the Rockchip RK3588, each memory channel has some bandwidth monitoring silicon (hence the "DDR_MON"), which is driven by a clock gated by PCLK_DDR_MON_CH0/1/2/3. These clock branches were left out of the mainline clock tree until now. Add them, with the proper CRU reg bits, and the proper parent. They are given the "CLK_IGNORE_UNUSED" flag, so that older device trees with newer kernels don't turn off the clocks because they're seen as not in use. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- drivers/clk/rockchip/clk-rk3588.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-r= k3588.c index 24baa0ef9bf3..0485faf27163 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -1349,6 +1349,14 @@ static struct rockchip_clk_branch rk3588_early_clk_b= ranches[] __initdata =3D { COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITI= CAL, RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(70), 4, GFLAGS), + GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_center_root", CLK_IGNORE= _UNUSED, + RK3588_CLKGATE_CON(20), 1, GFLAGS), + GATE(PCLK_DDR_MON_CH1, "pclk_ddr_mon_ch1", "pclk_center_root", CLK_IGNORE= _UNUSED, + RK3588_CLKGATE_CON(20), 14, GFLAGS), + GATE(PCLK_DDR_MON_CH2, "pclk_ddr_mon_ch2", "pclk_center_root", CLK_IGNORE= _UNUSED, + RK3588_CLKGATE_CON(23), 1, GFLAGS), + GATE(PCLK_DDR_MON_CH3, "pclk_ddr_mon_ch3", "pclk_center_root", CLK_IGNORE= _UNUSED, + RK3588_CLKGATE_CON(23), 14, GFLAGS), GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0, RK3588_CLKGATE_CON(70), 7, GFLAGS), GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0, --=20 2.53.0 From nobody Fri Sep 25 02:06:05 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4172653ED05; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli So far, RK3588 doesn't have the pclks for DDRMON used in the driver, as they weren't modelled before. However, they are now correctly modelled, so the driver should use them when possible. Instead of unconditionally getting them for this SoC, add a new variant member that specifies whether the driver should let missing clocks slide. This is needed because we want old device trees to keep functioning, as otherwise we'd be introducing a breaking change for literally no functional difference here. Fill out a clock name list for this variant as well, and hand it to it. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- drivers/devfreq/event/rockchip-dfi.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/r= ockchip-dfi.c index b61ec500eaed..380361a231a2 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -117,6 +117,18 @@ struct rockchip_dfi { const struct rockchip_dfi_variant *variant; }; =20 +/** + * struct rockchip_dfi_variant + * @init: pointer to the variant-specific initialisation function + * @stride: address offset between the DDRMON per-channel instances + * @ctrl_single: whether only one DDRMON instance monitors multiple channe= ls + * @max_channels: maximum number of memory channels for this SoC + * @clk_names: pointer to a constant array of constant clock name strings + * @num_clk: the number of elements in the @clk_names array + * @clocks_optional: whether not finding the clocks is non-fatal. Set if t= he + * DT binding for this variant didn't require clocks in = the + * past, so that the driver remains compatible with old = DTs. + */ struct rockchip_dfi_variant { int (*init)(struct rockchip_dfi *dfi); int stride; @@ -124,6 +136,7 @@ struct rockchip_dfi_variant { unsigned int max_channels; const char * const *clk_names; unsigned int num_clks; + bool clocks_optional; }; =20 static int rockchip_dfi_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *ctr= l) @@ -804,6 +817,11 @@ static const char * const rk3399_clk_names[] =3D { "pclk_ddr_mon", }; =20 +static const char * const rk3588_clk_names[] =3D { + "pclk_ddr_mon_ch0", "pclk_ddr_mon_ch1", "pclk_ddr_mon_ch2", + "pclk_ddr_mon_ch3", +}; + static const struct rockchip_dfi_variant rk3399_variant =3D { .init =3D rk3399_dfi_init, .stride =3D 0x14, @@ -824,6 +842,9 @@ static const struct rockchip_dfi_variant rk3588_variant= =3D { .init =3D rk3588_dfi_init, .stride =3D 0x4000, .max_channels =3D 4, + .clk_names =3D rk3588_clk_names, + .num_clks =3D ARRAY_SIZE(rk3588_clk_names), + .clocks_optional =3D true, }; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli The DFI clocks weren't modelled before and the binding didn't know about them either. That has changed though, and now we actually need to specify these clocks. Add all four clocks for all four channels of monitoring. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 376ad04e0786..ac9299e1197b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -2178,6 +2178,10 @@ qos_vop_m1: qos@fdf82200 { dfi: dfi@fe060000 { reg =3D <0x00 0xfe060000 0x00 0x10000>; compatible =3D "rockchip,rk3588-dfi"; + clocks =3D <&cru PCLK_DDR_MON_CH0>, <&cru PCLK_DDR_MON_CH1>, + <&cru PCLK_DDR_MON_CH2>, <&cru PCLK_DDR_MON_CH3>; + clock-names =3D "pclk_ddr_mon_ch0", "pclk_ddr_mon_ch1", + "pclk_ddr_mon_ch2", "pclk_ddr_mon_ch3"; interrupts =3D , , , --=20 2.53.0