From nobody Fri Sep 25 01:29:00 2026 Received: from sm24.hosting.reg.ru (sm24.hosting.reg.ru [31.31.198.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4FB23909A6; Thu, 17 Sep 2026 16:44:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=31.31.198.150 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663461; cv=none; b=jCSdrAOj1yRK0EdYv0QlQ2G1Y5yrdHwMiQIHvNGpAQMhazQmHCrA6BkWvHcYSIEYbqnTOwb4uUvhYfaJ3129/BH5wy+ZlLuzxgi+TAIi5RGlriHIC4qiTi2UWCM4OvpTTUrtKZAkqYs7ty03bLDY8XL4EqLLEbvYHXg8WDlhtAg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663461; c=relaxed/simple; bh=iuCGv5i9sUK5NfEpPCkUnnl7p/aLhogUpELLxhLNOQs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rkcf3M5Lz1vMYvZAbYUY+jErSLy8bv7zHAibbsz9NWj0ycj5pvINwPegF/05YZnzureY5VUQIsqt7fBwS3+UhRqjgEYuqat0KBm08wZlSGne4C77vynFnWAHX4Xh1PUK9Prq5Hwzp+JVPsQqb8pAVL4WbEZ0Y++v/WpsC5IZON8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=minlexx.ru; spf=none smtp.mailfrom=minlexx.ru; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b=Ut4txk8u; arc=none smtp.client-ip=31.31.198.150 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b="Ut4txk8u" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=minlexx.ru; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=U7BxfyRDz/VeeNHxihWp+UO2gt3YHWP+ESOrM0F5a9U=; b=Ut4txk8u5/u8JhDrZLrAg+qTcW dLXZJQDB/KoHbjHvmhwFQVo82gctpYBJUgr19E402ie2czgd/i7BAA5QvDk81ZYIle73a2XD5tzPW TVomQ9PE/3PzIrw9cSftTxsoHvbxXrxTRjEzYlXg+GRwKFMiyHbggq+S713hKK5uBWt8=; Received: by sm24.hosting.reg.ru with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (envelope-from ) id 1x7FDT-0000000Bw3I-2fsT; Thu, 17 Sep 2026 19:44:08 +0300 From: Alexey Minnekhanov Date: Thu, 17 Sep 2026 19:43:03 +0300 Subject: [PATCH v2 1/9] dt-bindings: vendor-prefixes: Add Shenzhen TXD Technology Co., Ltd. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260917-nt36672a-panels-v2-1-f8de8be5b86f@minlexx.ru> References: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> In-Reply-To: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: David Heidelberg , Joel Selvaraj , Chintan Patel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, Alexey Minnekhanov X-Mailer: b4 0.16.0 Add prefix for Shenzhen TXD Technology Co., Ltd., manufacturer of medium sized LCD and camera modules for mobile phones, tablets and automotive. [1] https://en.txdkj.com/ Signed-off-by: Alexey Minnekhanov --- v2: prefix changed from "txd" to "txdkj" --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 4a5cf436eb143..bc87d5e9fdd2b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1773,6 +1773,8 @@ patternProperties: description: Turing Machines, Inc. "^tuxedo,.*": description: TUXEDO Computers GmbH + "^txdkj,.*": + description: Shenzhen TXD Technology Co., Ltd. "^tyan,.*": description: Tyan Computer Corporation "^tyhx,.*": --=20 2.55.0 From nobody Fri Sep 25 01:29:00 2026 Received: from sm24.hosting.reg.ru (sm24.hosting.reg.ru [31.31.198.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A51BF50391A; Thu, 17 Sep 2026 16:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=31.31.198.150 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663463; cv=none; b=YqLhPIFRHCCN7Hc0Qh8BL7oAb4WQQAopYqp209kbcvpJKf2ot4BSsrKgNWDE6x68Y+pJ82AjtFduPU+U0DH04FJrDXg4gEzyNDJfZRn5+ZmBajO267fbee3Zpk3Dtvt+jYFjU4o5wR53jo4WBLF4D7medK+6jsrPozDcYZ9ygVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663463; c=relaxed/simple; bh=rhyIzjZzSdyv44zczMGBcMKVPk3p363Cfcs3OyJUJls=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AGKrLjcNK5nJ38Aqj+SxEPHsUH/mKg/ieL24/p1Ceb2D1d5IFk/NwOrP/9fGe0tqcZyRXb7lzwbBIUoCGZh366j5PzEzijCoQl1MEGLMbNLKnATbboJq8lKc1h4PeR1aX8zLwTqcJ2mrWVp3TXPmCGMTOCTcV7WtisAJBbf2Brc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=minlexx.ru; spf=none smtp.mailfrom=minlexx.ru; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b=Rqe9AszC; arc=none smtp.client-ip=31.31.198.150 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b="Rqe9AszC" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=minlexx.ru; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=k3Dw7OeMuO6OJ1hfSNZ0QpnTkMfkoclywwZPUBVIdp4=; b=Rqe9AszCZwvvVKRNSZIKbGD1xO AH80I6dGRWiqwI0r8MU8IjAp6NznBIj25lOrQsmqdH4toGEIIDnySQ3nEFyw0qsFakHfbHhPmkpZZ iDymkucNa3A7iTX5UCKBRXs5Dvi/gqUK8UMx9gSMrRq2dafkh2u7qsK0VpGe772rNjy0=; Received: by sm24.hosting.reg.ru with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (envelope-from ) id 1x7FDU-0000000Bw3I-3a9R; Thu, 17 Sep 2026 19:44:13 +0300 From: Alexey Minnekhanov Date: Thu, 17 Sep 2026 19:43:04 +0300 Subject: [PATCH v2 2/9] dt-bindings: vendor-prefixes: Add Shen Chao Optoelectronics Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260917-nt36672a-panels-v2-2-f8de8be5b86f@minlexx.ru> References: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> In-Reply-To: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: David Heidelberg , Joel Selvaraj , Chintan Patel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, Alexey Minnekhanov X-Mailer: b4 0.16.0 Shen Chao Optoelectronics Co., Ltd. is a manufacturer of LCD displays based in Shenzhen. According to description in [1], the company specializes in the design, R&D, testing, and manufacturing of TFT-LCD liquid crystal display panels. Its products are widely used in the 3C electronic display field, covering a full range of display products including LCD monitors, laptops, and mobile phones. [1] https://www.qcc.com/firm/5b0330df7040fba496dbb0bd5723f6be.html Signed-off-by: Alexey Minnekhanov --- v2: correct company name, expand description, add a link --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index bc87d5e9fdd2b..0e011b6679847 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1509,6 +1509,8 @@ patternProperties: description: SGX Sensortech "^sharp,.*": description: Sharp Corporation + "^shenchao,.*": + description: Shen Chao Optoelectronics (Shenzhen) Co., Ltd. "^shift,.*": description: SHIFT GmbH "^shimafuji,.*": --=20 2.55.0 From nobody Fri Sep 25 01:29:00 2026 Received: from sm24.hosting.reg.ru (sm24.hosting.reg.ru [31.31.198.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C6BC3AB48F; Thu, 17 Sep 2026 16:44:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=31.31.198.150 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663462; cv=none; b=PsYPOYODYmnbs4KU3OXABGHTImBq5MCkucomlDx9KQ0IStxSMKYwLYhaj6Z6DyCwF4NNyv9u4WX2bFQryq2f2nDPQRa+J4/9mh+T/s7kAE5N0wKNEJZ3akQ3hjeCwxykw5k3TnYR2kQJVvFMRPaB7krDav0fwmAPDacOHq5UXUA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663462; c=relaxed/simple; bh=/zg733qvDfdUgeEltsSHNUEwqjV53GoUhRWd/59VknE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Kv1YgEfh8AN38I2ZbNrxahrP8+GFgBY89weeBIPOlqo0T7yDzhgMdcHbL0p74D/F5Qzt2ViIs4Px6V3IBc0uo9AeBlfGgLxVJUMeKQ8qQqzgkAdNhrRToe9/henHV2SmEIcDat/9CUeDbwrhOP2RpR/A7or+Pb/GGJ+HXVgx84E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=minlexx.ru; spf=none smtp.mailfrom=minlexx.ru; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b=A3Je9w+i; arc=none smtp.client-ip=31.31.198.150 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b="A3Je9w+i" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=minlexx.ru; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=GwjPfRohhdWMpNDZekXkVDZdt75rLGMNzzHtRMExuBY=; b=A3Je9w+iD07MWNN8j9eztQJoil BYEq1pcUSFXqR16AQAU/69grvIs6rok2mujtdNf0UD9lHtib294AHSDW+1XDs6Nm3odOmy6ZuZCiD 6Fyr2IxPv6q/3C22Ri/nfZoILQrD7DerLfu0e8qNBQMo51JwvPWblKYUVNAPIXaGAPEw=; Received: by sm24.hosting.reg.ru with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (envelope-from ) id 1x7FDZ-0000000Bw3I-1fKx; Thu, 17 Sep 2026 19:44:17 +0300 From: Alexey Minnekhanov Date: Thu, 17 Sep 2026 19:43:05 +0300 Subject: [PATCH v2 3/9] dt-bindings: display: novatek,nt36672a: Add 5 new panels Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260917-nt36672a-panels-v2-3-f8de8be5b86f@minlexx.ru> References: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> In-Reply-To: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: David Heidelberg , Joel Selvaraj , Chintan Patel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, Alexey Minnekhanov X-Mailer: b4 0.16.0 Document 5 new panels used in 4 different smartphones produced by Xiaomi and ASUS: * Shenchao panel used in Xiaomi Redmi Note 7 (xiaomi-lavender), the exact model string is unknown * Tianma TL063FVMC43-02 for Xiaomi Redmi Note 6 Pro (xiaomi-tulip) * Tianma TL063FVMCA01-00 for Xiaomi Redmi Note 7 (xiaomi-lavender) * Tianma TL060FVXS16-00 for Xiaomi Mi A2 smartphone (xiaomi-jasmine) * TXD TXDI600YANPA-43V3 Asus Zenfone Max Pro M1 (asus-x00td) Signed-off-by: Alexey Minnekhanov --- v2: * changed description to mention several panels instead of one * fixed alphabetical ordering of compatible strings * changed vendor prefix of TXD: "txd" -> "txdkj" --- .../devicetree/bindings/display/panel/novatek,nt36672a.yaml | 11 +++++++= ---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt3667= 2a.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.= yaml index 5d16d85117254..62ec3294b9b68 100644 --- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml @@ -10,10 +10,8 @@ maintainers: - Sumit Semwal =20 description: | - The nt36672a IC from Novatek is a generic DSI Panel IC used to drive dsi - panels. - Right now, support is added only for a Tianma FHD+ LCD display panel wit= h a - resolution of 1080x2246. It is a video mode DSI panel. + The NT36672A IC from Novatek is a generic DSI Panel IC used to drive dsi + panels. Currently supports 6 panel models for 5 different smartphones. =20 allOf: - $ref: panel-common.yaml# @@ -22,7 +20,12 @@ properties: compatible: items: - enum: + - shenchao,fhdplus-video - tianma,fhd-video + - tianma,tl060fvxs16-00 + - tianma,tl063fvmc43-02 + - tianma,tl063fvmca01-00 + - txdkj,txdi600yanpa-43v3 - const: novatek,nt36672a description: This indicates the panel manufacturer of the panel that is in turn using the NT36672A panel driver. This compatible string --=20 2.55.0 From nobody Fri Sep 25 01:29:00 2026 Received: from sm24.hosting.reg.ru (sm24.hosting.reg.ru [31.31.198.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FED951CF6E; Thu, 17 Sep 2026 16:44:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=31.31.198.150 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663466; cv=none; b=uLGtZegBkdFiZ/P/o/jQgiVxb3UytfpV4CnnCO9LRXYb18t371Re4gwHUecaxeUs/dWXTaSJneZUdFEQaxhKv46pan32vmSXlzfHB2vkz3zOSiBc7JiO+UWtI6CQ/9g2BiTzFR+5AlEfYP9MJbZBc4J7GAjmlXzHx+EWnGdqAjw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663466; c=relaxed/simple; bh=tLiwBTPDWAvibc+P1qQJJrXQEyZOXPy9rqCNLZvj6iU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k/wT9R7ikO/inxchO45wo9kXCsgUklF1bFVn5Po7RgbAWo/ePNgUYXCdIyd2G+EWyL4YHUyaAtL/ei83bppGgG5uwHG3QXepsOeZIxoGqLX+rvrWtnsDjQIVKoVMf+mEJBIQDCFDVsK4n7OsZLZaTaBYV5QPvrtA5VzutVPrgPQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=minlexx.ru; spf=none smtp.mailfrom=minlexx.ru; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b=GhbmoBrg; arc=none smtp.client-ip=31.31.198.150 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b="GhbmoBrg" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=minlexx.ru; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=3O/sSDf4Nmc2qh2JhufK4PyTt46P7UAeOLGyiVV0SO0=; b=GhbmoBrg9FaUusy411BGVUUgEY R4V4bnG+inuV2abPGNBJ//RE+FWg1hcDnA8Y+CA3AdWlXzYYGv04jKTGjjO+fyjj0evYne/AzAsJV 3Y2iReH24sFJUpc9mZgIryI1aRtmsW87uWWzTVp4FZXXLDKPMSqv6u/aiExLGuuqoj5Q=; Received: by sm24.hosting.reg.ru with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (envelope-from ) id 1x7FDd-0000000Bw3I-3ux8; Thu, 17 Sep 2026 19:44:22 +0300 From: Alexey Minnekhanov Date: Thu, 17 Sep 2026 19:43:06 +0300 Subject: [PATCH v2 4/9] drm/panel: novatek-nt36672a: Set driver name to novatek for consistency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260917-nt36672a-panels-v2-4-f8de8be5b86f@minlexx.ru> References: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> In-Reply-To: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: David Heidelberg , Joel Selvaraj , Chintan Patel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, Alexey Minnekhanov X-Mailer: b4 0.16.0 Since this driver should represent not only devices manufactured by Tianma Micro-electronics, but also from other companies, it makes more sense to name it according to what driver file name already is: novatek. This does not change neither module file name nor Kconfig symbol, only driver identification in dmesg. This makes it possible to e.g. grep dmesg for "novatek" and get messages from both nt36672a-based panel and Novatek touchscreen. Reviewed-by: David Heidelberg Signed-off-by: Alexey Minnekhanov --- drivers/gpu/drm/panel/panel-novatek-nt36672a.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c b/drivers/gpu/d= rm/panel/panel-novatek-nt36672a.c index 464d9ce47d87d..73bec4f47ec60 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt36672a.c @@ -479,16 +479,16 @@ static void nt36672a_panel_remove(struct mipi_dsi_dev= ice *dsi) drm_panel_remove(&pinfo->base); } =20 -static const struct of_device_id tianma_fhd_video_of_match[] =3D { +static const struct of_device_id panel_nt36672a_match[] =3D { { .compatible =3D "tianma,fhd-video", .data =3D &tianma_fhd_video_panel_d= esc }, { }, }; -MODULE_DEVICE_TABLE(of, tianma_fhd_video_of_match); +MODULE_DEVICE_TABLE(of, panel_nt36672a_match); =20 static struct mipi_dsi_driver nt36672a_panel_driver =3D { .driver =3D { - .name =3D "panel-tianma-nt36672a", - .of_match_table =3D tianma_fhd_video_of_match, + .name =3D "panel-novatek-nt36672a", + .of_match_table =3D panel_nt36672a_match, }, .probe =3D nt36672a_panel_probe, .remove =3D nt36672a_panel_remove, --=20 2.55.0 From nobody Fri Sep 25 01:29:00 2026 Received: from sm24.hosting.reg.ru (sm24.hosting.reg.ru [31.31.198.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF74451DDE4; Thu, 17 Sep 2026 16:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=31.31.198.150 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663467; cv=none; b=lKtipfw7McnADto11F9I7OphbFBj+6SGuYuMaIi1Soc4kYXlc2kaqAcEr9zOtIpiRAiY2870RoWCKVFXZDmzM6Fd4N3Y636B7QRTnXgjvjfvFw5eW2xQFHCVuOLIdfJrzayF3rROjWf0hC6rIwBTAA8wFmuemWcKVHuaHgLscow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663467; c=relaxed/simple; bh=Pvcn3OGE2w7zSTKavw5qWSgF7EgPQYKh3ZtNY+hb1ZY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CXd+BkSsOERV1KJQnq2PkQMi4OVecF/A25nc8HOVPAZ2kjHTVuNAokHhmOZFm8WrBVlHUOlU9nLv4AUUyMPj1ntMCCrI4ItGHenvyI9KK5zeSxIFe1WNZyoswt9tz+zS7I6+QjdY6Arvo8CKetXyKprFrKsk/XytOBbFXdcf9wM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=minlexx.ru; spf=none smtp.mailfrom=minlexx.ru; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b=togRMzhk; arc=none smtp.client-ip=31.31.198.150 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b="togRMzhk" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=minlexx.ru; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=zUxbVeJDppzpwrVW9tUGBtinYr+rW3ftNjfGxwjtIRk=; b=togRMzhkcsYyzbdcktxpbnTT22 YAmtmjd30smB0RobNkzn2boWR53wbEqYpDT0rWPN1VGZ4zu2u3k5GujDb3833B6G7cc41p67ap6B6 mCpACSKCPEKNX2KAIjZ27viOpu6IvmB+8hruTTCXLNNl9QgIfz4azMx4U1J2IHJ4516I=; Received: by sm24.hosting.reg.ru with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (envelope-from ) id 1x7FDi-0000000Bw3I-1tqM; Thu, 17 Sep 2026 19:44:23 +0300 From: Alexey Minnekhanov Date: Thu, 17 Sep 2026 19:43:07 +0300 Subject: [PATCH v2 5/9] drm/panel: novatek-nt36672a: Combine two init callbacks into one Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260917-nt36672a-panels-v2-5-f8de8be5b86f@minlexx.ru> References: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> In-Reply-To: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: David Heidelberg , Joel Selvaraj , Chintan Patel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, Alexey Minnekhanov X-Mailer: b4 0.16.0 The split between .send_init_cmds_1 and _cmds_2 is completely artificial and unnecessary. Two command sets are split in between by the sequence: - exit_sleep_mode - delay - set_display_on But not every panel driver follows this "split" in their init sequence. Some may have different delay timer, or put exit_sleep_mode/display_on commands into other places in the sequence. In order to make this driver more extensible, combine two init functions into one by puting exit_sleep_mode/delay/display_on in the middle, followed by commands from cmds_2. As part of this step, also move the tianma-beryllium specific deinit sequence with its delays from nt36672a_panel_unprepare() to tianma_fhd_video_send_deinit_cmds(), so that each panel model can have its deinit sequence with its own delays. No functional change - full init sequence with all the delays for the tianma_fhd_video panel is kept the same in the end. Signed-off-by: Alexey Minnekhanov Reviewed-by: Neil Armstrong --- v2: move tianma_fhd deinit commands into its own deinit function (set_display_off, msleep, enter_sleep_mode, msleep) --- drivers/gpu/drm/panel/panel-novatek-nt36672a.c | 61 ++++++++++------------= ---- 1 file changed, 23 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c b/drivers/gpu/d= rm/panel/panel-novatek-nt36672a.c index 73bec4f47ec60..a445c8067aa5f 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt36672a.c @@ -51,8 +51,7 @@ struct nt36672a_panel_desc { enum mipi_dsi_pixel_format format; unsigned int lanes; =20 - void (*send_init_cmds_1)(struct mipi_dsi_multi_context *dsi_ctx); - void (*send_init_cmds_2)(struct mipi_dsi_multi_context *dsi_ctx); + void (*send_init_cmds)(struct mipi_dsi_multi_context *dsi_ctx); void (*send_deinit_cmds)(struct mipi_dsi_multi_context *dsi_ctx); }; =20 @@ -92,20 +91,6 @@ static int nt36672a_panel_unprepare(struct drm_panel *pa= nel) if (pinfo->desc->send_deinit_cmds) pinfo->desc->send_deinit_cmds(&dsi_ctx); =20 - /* Reset error to continue with display off even if send_cmds failed */ - dsi_ctx.accum_err =3D 0; - mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); - /* Reset error to continue power-down even if display off failed */ - dsi_ctx.accum_err =3D 0; - - /* 120ms delay required here as per DCS spec */ - msleep(120); - - mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); - - /* 0x3C =3D 60ms delay */ - msleep(60); - nt36672a_panel_power_off(panel); =20 return 0; @@ -140,22 +125,9 @@ static int nt36672a_panel_prepare(struct drm_panel *pa= nel) =20 dsi_ctx.accum_err =3D nt36672a_panel_power_on(pinfo); =20 - /* send first part of init cmds */ - if (pinfo->desc->send_init_cmds_1) - pinfo->desc->send_init_cmds_1(&dsi_ctx); - - mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); - - /* 0x46 =3D 70 ms delay */ - mipi_dsi_msleep(&dsi_ctx, 70); - - mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - - /* Send rest of the init cmds */ - if (pinfo->desc->send_init_cmds_2) - pinfo->desc->send_init_cmds_2(&dsi_ctx); - - mipi_dsi_msleep(&dsi_ctx, 120); + /* send init cmds */ + if (pinfo->desc->send_init_cmds) + pinfo->desc->send_init_cmds(&dsi_ctx); =20 if (dsi_ctx.accum_err < 0) gpiod_set_value(pinfo->reset_gpio, 0); @@ -192,7 +164,7 @@ static const struct drm_panel_funcs panel_funcs =3D { .get_modes =3D nt36672a_panel_get_modes, }; =20 -static void tianma_fhd_video_send_init_cmds_1(struct mipi_dsi_multi_contex= t *dsi_ctx) +static void tianma_fhd_video_send_init_cmds(struct mipi_dsi_multi_context = *dsi_ctx) { u8 reg; =20 @@ -352,15 +324,19 @@ static void tianma_fhd_video_send_init_cmds_1(struct = mipi_dsi_multi_context *dsi mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x51, 0xff); mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x53, 0x24); mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x55, 0x00); -} =20 -static void tianma_fhd_video_send_init_cmds_2(struct mipi_dsi_multi_contex= t *dsi_ctx) -{ + mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx); + /* 0x46 =3D 70 ms delay */ + mipi_dsi_msleep(dsi_ctx, 70); + mipi_dsi_dcs_set_display_on_multi(dsi_ctx); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x24); mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc3, 0x01); mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc4, 0x54); mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x10); + + mipi_dsi_msleep(dsi_ctx, 120); } =20 static void tianma_fhd_video_send_deinit_cmds(struct mipi_dsi_multi_contex= t *dsi_ctx) @@ -369,6 +345,16 @@ static void tianma_fhd_video_send_deinit_cmds(struct m= ipi_dsi_multi_context *dsi mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc3, 0x01); mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x10); + + /* Reset error to continue with display off even if send_cmds failed */ + dsi_ctx->accum_err =3D 0; + mipi_dsi_dcs_set_display_off_multi(dsi_ctx); + /* Reset error to continue power-down even if display off failed */ + dsi_ctx->accum_err =3D 0; + /* 120ms delay required here as per DCS spec */ + msleep(120); + mipi_dsi_dcs_enter_sleep_mode_multi(dsi_ctx); + msleep(60); /* 0x3C =3D 60ms delay */ } =20 static const struct drm_display_mode tianma_fhd_video_panel_default_mode = =3D { @@ -399,8 +385,7 @@ static const struct nt36672a_panel_desc tianma_fhd_vide= o_panel_desc =3D { | MIPI_DSI_MODE_VIDEO_BURST, .format =3D MIPI_DSI_FMT_RGB888, .lanes =3D 4, - .send_init_cmds_1 =3D tianma_fhd_video_send_init_cmds_1, - .send_init_cmds_2 =3D tianma_fhd_video_send_init_cmds_2, + .send_init_cmds =3D tianma_fhd_video_send_init_cmds, .send_deinit_cmds =3D tianma_fhd_video_send_deinit_cmds, }; =20 --=20 2.55.0 From nobody Fri Sep 25 01:29:00 2026 Received: from sm24.hosting.reg.ru (sm24.hosting.reg.ru [31.31.198.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50CB951DAE0; Thu, 17 Sep 2026 16:44:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=31.31.198.150 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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spf=none smtp.mailfrom=minlexx.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=minlexx.ru header.i=@minlexx.ru header.b="npiYHbzV" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=minlexx.ru; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=vSHMqTD6DTrYG4jyPlHTGH4wyhIEg8VqHx98b7hhbZc=; b=npiYHbzVvIu6G4+zrP6rvcM0i6 tplmqvIN5mJL/1tV0CrTO6S3CmqMwqZbdsvJpsrg3qjfmXICHEiwVUwn9CjsZpHOQAfJPnLCg3ppk f7UDOq932YjdKrj7PyixbMiuLuMmD3c1V+mR7gaxoMy4i82X0WUyItEzH8JV34P+/KFM=; Received: by sm24.hosting.reg.ru with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (envelope-from ) id 1x7FDj-0000000Bw3I-227J; Thu, 17 Sep 2026 19:44:24 +0300 From: Alexey Minnekhanov Date: Thu, 17 Sep 2026 19:43:08 +0300 Subject: [PATCH v2 6/9] drm/panel: novatek-nt36672a: Add 3 panels used in Xiaomi phones Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260917-nt36672a-panels-v2-6-f8de8be5b86f@minlexx.ru> References: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> In-Reply-To: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: David Heidelberg , Joel Selvaraj , Chintan Patel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, Alexey Minnekhanov , Richard Acayan X-Mailer: b4 0.16.0 Add support for 3 panels used in 2 Xiaomi smartphones, all based on Qualcomm SDM636/660 SoC: * Shenchao panel used in Xiaomi Redmi Note 7 (xiaomi-lavender), the exact model string is unknown * Tianma TL063FVMC43-02 for Xiaomi Redmi Note 6 Pro (xiaomi-tulip) * Tianma TL063FVMCA01-00 for Xiaomi Redmi Note 7 (xiaomi-lavender) They all are DSI video mode panels using Novatek NT36672A controller, so they can share almost exactly the same init/off sequences with minimal differences between variants. This allows to avoid a lot of code duplication. Co-developed-by: Richard Acayan Signed-off-by: Richard Acayan Signed-off-by: Alexey Minnekhanov Reviewed-by: Neil Armstrong --- v2: sort compatible strings alphabetically in of_device_id --- drivers/gpu/drm/panel/panel-novatek-nt36672a.c | 166 +++++++++++++++++++++= ++++ 1 file changed, 166 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c b/drivers/gpu/d= rm/panel/panel-novatek-nt36672a.c index a445c8067aa5f..d356348d39608 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt36672a.c @@ -357,6 +357,90 @@ static void tianma_fhd_video_send_deinit_cmds(struct m= ipi_dsi_multi_context *dsi msleep(60); /* 0x3C =3D 60ms delay */ } =20 +static void lavender_tulip_init_cmds(struct mipi_dsi_multi_context *dsi_ct= x) +{ + /* + * This function supports 3 similar panels with minimal differences + * in their init sequences. We assume base to be lavender-tianma + * panel, and 2 variations (lavender-shenchao and tulip) are handled as + * differences to base. + */ + const struct device_node *node =3D dev_of_node(&dsi_ctx->dsi->dev); + bool is_shenchao =3D of_device_is_compatible(node, "shenchao,fhdplus-vide= o"); + bool is_tulip =3D of_device_is_compatible(node, "tianma,tl063fvmc43-02"); + + dsi_ctx->dsi->mode_flags |=3D MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x18, 0x96); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x05, 0x04); + + if (is_shenchao) + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x27); + else + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x20); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + + if (is_shenchao) + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd9, 0x10); + else + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x78, 0x01); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x24); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x82, 0x13); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x84, 0x31); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x88, 0x13); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x8a, 0x31); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x8e, 0xe4); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x8f, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x90, 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x26); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xa9, 0x12); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xaa, 0x10); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xae, 0x8a); + + if (is_shenchao) + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1c, 0xfa); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x10); + + if (is_shenchao) + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb0, 0x01); + + mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx); + mipi_dsi_msleep(dsi_ctx, 80); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb0, 0x01); + mipi_dsi_dcs_set_tear_on_multi(dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + + if (is_tulip) { + mipi_dsi_dcs_set_display_brightness_multi(dsi_ctx, 0x00ff); + } else { + /* lavender tianma + shenchao specific part */ + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x68, 0x03, 0x04); + mipi_dsi_dcs_set_display_brightness_multi(dsi_ctx, 0x00b8); + } + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x2= c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + + mipi_dsi_dcs_set_display_on_multi(dsi_ctx); +} + +static void lavender_tulip_deinit_cmds(struct mipi_dsi_multi_context *dsi_= ctx) +{ + dsi_ctx->dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_set_display_off_multi(dsi_ctx); + mipi_dsi_msleep(dsi_ctx, 20); + mipi_dsi_dcs_enter_sleep_mode_multi(dsi_ctx); + mipi_dsi_msleep(dsi_ctx, 120); +} + static const struct drm_display_mode tianma_fhd_video_panel_default_mode = =3D { .clock =3D 161331, =20 @@ -389,6 +473,85 @@ static const struct nt36672a_panel_desc tianma_fhd_vid= eo_panel_desc =3D { .send_deinit_cmds =3D tianma_fhd_video_send_deinit_cmds, }; =20 +/* common for both lavender-tianma and lavender-shenchao panels */ +static const struct drm_display_mode lavender_panel_default_mode =3D { + .clock =3D (1080 + 90 + 2 + 120) * (2340 + 10 + 3 + 8) * 60 / 1000, + + .hdisplay =3D 1080, + .hsync_start =3D 1080 + 90, + .hsync_end =3D 1080 + 90 + 2, + .htotal =3D 1080 + 90 + 2 + 120, + + .vdisplay =3D 2340, + .vsync_start =3D 2340 + 10, + .vsync_end =3D 2340 + 10 + 3, + .vtotal =3D 2340 + 10 + 3 + 8, + + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct nt36672a_panel_desc shenchao_lavender_panel_desc =3D { + .display_mode =3D &lavender_panel_default_mode, + + .width_mm =3D 67, + .height_mm =3D 145, + + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_CLOCK_NON_CONTINUOUS, + .format =3D MIPI_DSI_FMT_RGB888, + .lanes =3D 4, + .send_init_cmds =3D lavender_tulip_init_cmds, + .send_deinit_cmds =3D lavender_tulip_deinit_cmds, +}; + +static const struct nt36672a_panel_desc tianma_lavender_panel_desc =3D { + .display_mode =3D &lavender_panel_default_mode, + + .width_mm =3D 67, + .height_mm =3D 145, + + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_CLOCK_NON_CONTINUOUS, + .format =3D MIPI_DSI_FMT_RGB888, + .lanes =3D 4, + .send_init_cmds =3D lavender_tulip_init_cmds, + .send_deinit_cmds =3D lavender_tulip_deinit_cmds, +}; + +static const struct drm_display_mode tianmaplus_e7t_tulip_mode =3D { + .clock =3D (1080 + 100 + 28 + 120) * (2280 + 10 + 3 + 8) * 60 / 1000, + + .hdisplay =3D 1080, + .hsync_start =3D 1080 + 100, + .hsync_end =3D 1080 + 100 + 28, + .htotal =3D 1080 + 100 + 28 + 120, + + .vdisplay =3D 2280, + .vsync_start =3D 2280 + 10, + .vsync_end =3D 2280 + 10 + 3, + .vtotal =3D 2280 + 10 + 3 + 8, + + .width_mm =3D 68, + .height_mm =3D 143, + + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct nt36672a_panel_desc tianmaplus_e7t_tulip_panel_desc = =3D { + .display_mode =3D &tianmaplus_e7t_tulip_mode, + + .width_mm =3D 68, + .height_mm =3D 143, + + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_CLOCK_NON_CONTINUOUS, + .format =3D MIPI_DSI_FMT_RGB888, + .lanes =3D 4, + /* tulip panel uses almost the same init/deinit sequences as lavender */ + .send_init_cmds =3D lavender_tulip_init_cmds, + .send_deinit_cmds =3D lavender_tulip_deinit_cmds, +}; + static int nt36672a_panel_add(struct nt36672a_panel *pinfo) { struct device *dev =3D &pinfo->link->dev; @@ -465,7 +628,10 @@ static void nt36672a_panel_remove(struct mipi_dsi_devi= ce *dsi) } =20 static const struct of_device_id panel_nt36672a_match[] =3D { + { .compatible =3D "shenchao,fhdplus-video", .data =3D &shenchao_lavender_= panel_desc }, { .compatible =3D "tianma,fhd-video", .data =3D &tianma_fhd_video_panel_d= esc }, + { .compatible =3D "tianma,tl063fvmc43-02", .data =3D &tianmaplus_e7t_tuli= p_panel_desc }, + { .compatible =3D "tianma,tl063fvmca01-00", .data =3D &tianma_lavender_pa= nel_desc }, { }, }; MODULE_DEVICE_TABLE(of, panel_nt36672a_match); --=20 2.55.0 From nobody Fri Sep 25 01:29:00 2026 Received: from sm24.hosting.reg.ru (sm24.hosting.reg.ru [31.31.198.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50CDC51DAE1; Thu, 17 Sep 2026 16:44:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 17 Sep 2026 19:44:24 +0300 From: Alexey Minnekhanov Date: Thu, 17 Sep 2026 19:43:09 +0300 Subject: [PATCH v2 7/9] drm/panel: novatek-nt36672a: Add Tianma panel for Xiaomi Mi A2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260917-nt36672a-panels-v2-7-f8de8be5b86f@minlexx.ru> References: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> In-Reply-To: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: David Heidelberg , Joel Selvaraj , Chintan Patel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, Alexey Minnekhanov X-Mailer: b4 0.16.0 Add support for Tianma TL060FVXS16-00 video mode panel based on Novatek NT36672A, used in Xiaomi Mi A2 smartphone (xiaomi-jasmine). It shares some code with already supported panel in this driver for xiaomi-lavender, so we can reuse the same panel deinit function. Signed-off-by: Alexey Minnekhanov Reviewed-by: Neil Armstrong --- v2: use mipi_dsi_usleep_range() instead of usleep_range() --- drivers/gpu/drm/panel/panel-novatek-nt36672a.c | 57 ++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c b/drivers/gpu/d= rm/panel/panel-novatek-nt36672a.c index d356348d39608..48dff2279b0e9 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt36672a.c @@ -441,6 +441,29 @@ static void lavender_tulip_deinit_cmds(struct mipi_dsi= _multi_context *dsi_ctx) mipi_dsi_msleep(dsi_ctx, 120); } =20 +static void tianma_jasmine_init_cmds(struct mipi_dsi_multi_context *dsi_ct= x) +{ + dsi_ctx->dsi->mode_flags |=3D MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_PARTIAL_ROWS, 0x10); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_PARTIAL_COLUMNS, 0x50); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x32, 0x2f); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x10); + + mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx); + mipi_dsi_msleep(dsi_ctx, 70); + + mipi_dsi_dcs_set_display_brightness_multi(dsi_ctx, 0x00ff); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x68, 0x03, 0x04); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x2= c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + + mipi_dsi_dcs_set_display_on_multi(dsi_ctx); + mipi_dsi_usleep_range(dsi_ctx, 5000, 6000); +} + static const struct drm_display_mode tianma_fhd_video_panel_default_mode = =3D { .clock =3D 161331, =20 @@ -552,6 +575,39 @@ static const struct nt36672a_panel_desc tianmaplus_e7t= _tulip_panel_desc =3D { .send_deinit_cmds =3D lavender_tulip_deinit_cmds, }; =20 +static const struct drm_display_mode tianma_jasmine_panel_default_mode =3D= { + .clock =3D (1080 + 96 + 4 + 56) * (2160 + 4 + 2 + 33) * 60 / 1000, + + .hdisplay =3D 1080, + .hsync_start =3D 1080 + 96, + .hsync_end =3D 1080 + 96 + 4, + .htotal =3D 1080 + 96 + 4 + 56, + + .vdisplay =3D 2160, + .vsync_start =3D 2160 + 4, + .vsync_end =3D 2160 + 4 + 2, + .vtotal =3D 2160 + 4 + 2 + 33, + + .width_mm =3D 68, + .height_mm =3D 136, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct nt36672a_panel_desc tianma_jasmine_panel_desc =3D { + .display_mode =3D &tianma_jasmine_panel_default_mode, + + .width_mm =3D 68, + .height_mm =3D 136, + + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_CLOCK_NON_CONTINUOUS, + .format =3D MIPI_DSI_FMT_RGB888, + .lanes =3D 4, + .send_init_cmds =3D tianma_jasmine_init_cmds, + /* jasmine panel uses the same deinit sequence as lavender/tulip */ + .send_deinit_cmds =3D lavender_tulip_deinit_cmds, +}; + static int nt36672a_panel_add(struct nt36672a_panel *pinfo) { struct device *dev =3D &pinfo->link->dev; @@ -630,6 +686,7 @@ static void nt36672a_panel_remove(struct mipi_dsi_devic= e *dsi) static const struct of_device_id panel_nt36672a_match[] =3D { { .compatible =3D "shenchao,fhdplus-video", .data =3D &shenchao_lavender_= panel_desc }, { .compatible =3D "tianma,fhd-video", .data =3D &tianma_fhd_video_panel_d= esc }, + { .compatible =3D "tianma,tl060fvxs16-00", .data =3D &tianma_jasmine_pane= l_desc }, { .compatible =3D "tianma,tl063fvmc43-02", .data =3D &tianmaplus_e7t_tuli= p_panel_desc }, { .compatible =3D "tianma,tl063fvmca01-00", .data =3D &tianma_lavender_pa= nel_desc }, { }, --=20 2.55.0 From nobody Fri Sep 25 01:29:00 2026 Received: from sm24.hosting.reg.ru (sm24.hosting.reg.ru [31.31.198.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFE7B51DAEB; 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Thu, 17 Sep 2026 19:44:25 +0300 From: Alexey Minnekhanov Date: Thu, 17 Sep 2026 19:43:10 +0300 Subject: [PATCH v2 8/9] drm/panel: novatek-nt36672a: Add panel for Asus Zenfone Max Pro M1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260917-nt36672a-panels-v2-8-f8de8be5b86f@minlexx.ru> References: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> In-Reply-To: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: David Heidelberg , Joel Selvaraj , Chintan Patel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, Alexey Minnekhanov , Aboothahir U X-Mailer: b4 0.16.0 Add support for TXD TXDI600YANPA-43V3 video mode panel based on Novatek NT36672A, used in Asus Zenfone Max Pro M1 smartphone (asus-x00td). Co-developed-by: Aboothahir U Signed-off-by: Aboothahir U Signed-off-by: Alexey Minnekhanov Reviewed-by: Neil Armstrong --- v2: * change compatible prefix "txd" -> "txdkj" * use co-author's real name in trailers --- drivers/gpu/drm/panel/panel-novatek-nt36672a.c | 281 +++++++++++++++++++++= ++++ 1 file changed, 281 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c b/drivers/gpu/d= rm/panel/panel-novatek-nt36672a.c index 48dff2279b0e9..7d7c79d2502d2 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt36672a.c @@ -464,6 +464,252 @@ static void tianma_jasmine_init_cmds(struct mipi_dsi_= multi_context *dsi_ctx) mipi_dsi_usleep_range(dsi_ctx, 5000, 6000); } =20 +static void txd_x00td_init_cmds(struct mipi_dsi_multi_context *dsi_ctx) +{ + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x06, 0x9e); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x07, 0x94); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0e, 0x35); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0f, 0x24); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x6d, 0x66); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x69, 0x99); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x95, 0xf5); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x96, 0xf5); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x23); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x12, 0x6c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x15, 0xe6); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x16, 0x0c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x24); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x00, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x01, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x02, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x03, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x04, 0x0b); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x05, 0x0c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x06, 0xa9); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x07, 0x06); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x08, 0x04); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x09, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0a, 0x0f); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0b, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0c, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0d, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0e, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0f, 0x17); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x10, 0x15); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x11, 0x13); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x12, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x13, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x14, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x15, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x16, 0x0b); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x17, 0x0c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x18, 0xa9); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x19, 0x05); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1a, 0x03); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1b, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1c, 0x0f); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1d, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1e, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1f, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x20, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x21, 0x17); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x22, 0x15); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x23, 0x13); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2f, 0x04); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x30, 0x08); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x31, 0x04); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x32, 0x08); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x33, 0x02); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x34, 0x02); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x35, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x37, 0x02); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x38, 0x72); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x39, 0x72); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3b, 0x40); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3f, 0x72); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x60, 0x10); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x61, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x68, 0x83); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x78, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x79, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x7a, 0x08); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x7b, 0x9c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x7d, 0x06); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x7e, 0x02); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x45); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x81, 0x06); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x8e, 0xf0); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x90, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x92, 0x76); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x93, 0x0a); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x94, 0x0a); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x99, 0x33); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x9b, 0xff); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb3, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb4, 0x04); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb5, 0x04); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xdc, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xdd, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xde, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xdf, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe0, 0x75); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe9, 0x08); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xed, 0x40); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb0, + 0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00, + 0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98, + 0x00, 0xac); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb1, + 0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01, + 0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22, + 0x02, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb2, + 0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02, + 0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a, + 0x03, 0x68); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb3, + 0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03, + 0xbd, 0x03, 0xd6, 0x03, 0xda); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb4, + 0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00, + 0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98, + 0x00, 0xac); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb5, + 0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01, + 0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22, + 0x02, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb6, + 0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02, + 0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a, + 0x03, 0x68); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb7, + 0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03, + 0xbd, 0x03, 0xd6, 0x03, 0xda); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb8, + 0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00, + 0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98, + 0x00, 0xac); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb9, + 0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01, + 0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22, + 0x02, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xba, + 0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02, + 0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a, + 0x03, 0x68); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbb, + 0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03, + 0xbd, 0x03, 0xd6, 0x03, 0xda); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x21); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb0, + 0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00, + 0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98, + 0x00, 0xac); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb1, + 0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01, + 0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22, + 0x02, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb2, + 0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02, + 0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a, + 0x03, 0x68); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb3, + 0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03, + 0xbd, 0x03, 0xd6, 0x03, 0xda); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb4, + 0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00, + 0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98, + 0x00, 0xac); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb5, + 0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01, + 0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22, + 0x02, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb6, + 0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02, + 0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a, + 0x03, 0x68); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb7, + 0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03, + 0xbd, 0x03, 0xd6, 0x03, 0xda); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb8, + 0x00, 0x00, 0x00, 0x15, 0x00, 0x37, 0x00, + 0x54, 0x00, 0x6d, 0x00, 0x84, 0x00, 0x98, + 0x00, 0xac); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb9, + 0x00, 0xbd, 0x00, 0xf9, 0x01, 0x25, 0x01, + 0x6b, 0x01, 0x9c, 0x01, 0xec, 0x02, 0x22, + 0x02, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xba, + 0x02, 0x5e, 0x02, 0x9e, 0x02, 0xc9, 0x02, + 0xfd, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5a, + 0x03, 0x68); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbb, + 0x03, 0x78, 0x03, 0x8b, 0x03, 0xa1, 0x03, + 0xbd, 0x03, 0xd6, 0x03, 0xda); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x05, 0x0c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0a, 0x81); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0b, 0xd7); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x0c, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x17, 0x82); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x21, 0x1c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x22, 0x1c); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x24, 0x76); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x25, 0x76); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x5c, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x5d, 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x5e, 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x5f, 0x22); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x65, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x69, 0x60); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x6b, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x71, 0x2d); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x8d, 0x04); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd7, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd8, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd9, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xda, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xdb, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xdc, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x26); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x06, 0xc8); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x12, 0x5a); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x19, 0x0a); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1a, 0x97); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1d, 0x0a); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1e, 0x1e); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x99, 0x20); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x27); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x13, 0x0e); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x16, 0xb0); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x17, 0xd0); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xff, 0x10); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfb, 0x01); + mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx); + mipi_dsi_msleep(dsi_ctx, 70); + mipi_dsi_dcs_set_display_on_multi(dsi_ctx); + mipi_dsi_usleep_range(dsi_ctx, 10000, 11000); +} + +static void txd_x00td_deinit_cmds(struct mipi_dsi_multi_context *dsi_ctx) +{ + mipi_dsi_dcs_set_display_off_multi(dsi_ctx); + mipi_dsi_msleep(dsi_ctx, 50); + mipi_dsi_dcs_enter_sleep_mode_multi(dsi_ctx); + mipi_dsi_msleep(dsi_ctx, 120); +} + static const struct drm_display_mode tianma_fhd_video_panel_default_mode = =3D { .clock =3D 161331, =20 @@ -608,6 +854,40 @@ static const struct nt36672a_panel_desc tianma_jasmine= _panel_desc =3D { .send_deinit_cmds =3D lavender_tulip_deinit_cmds, }; =20 +static const struct drm_display_mode txd_x00td_mode =3D { + .clock =3D (1080 + 122 + 8 + 76) * (2160 + 20 + 4 + 28) * 60 / 1000, + + .hdisplay =3D 1080, + .hsync_start =3D 1080 + 122, + .hsync_end =3D 1080 + 122 + 8, + .htotal =3D 1080 + 122 + 8 + 76, + + .vdisplay =3D 2160, + .vsync_start =3D 2160 + 20, + .vsync_end =3D 2160 + 20 + 4, + .vtotal =3D 2160 + 20 + 4 + 28, + + .width_mm =3D 68, + .height_mm =3D 136, + + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct nt36672a_panel_desc txd_x00td_panel_desc =3D { + .display_mode =3D &txd_x00td_mode, + + .width_mm =3D 68, + .height_mm =3D 136, + + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_NO_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM, + .format =3D MIPI_DSI_FMT_RGB888, + .lanes =3D 4, + .send_init_cmds =3D txd_x00td_init_cmds, + .send_deinit_cmds =3D txd_x00td_deinit_cmds, +}; + static int nt36672a_panel_add(struct nt36672a_panel *pinfo) { struct device *dev =3D &pinfo->link->dev; @@ -689,6 +969,7 @@ static const struct of_device_id panel_nt36672a_match[]= =3D { { .compatible =3D "tianma,tl060fvxs16-00", .data =3D &tianma_jasmine_pane= l_desc }, { .compatible =3D "tianma,tl063fvmc43-02", .data =3D &tianmaplus_e7t_tuli= p_panel_desc }, { .compatible =3D "tianma,tl063fvmca01-00", .data =3D &tianma_lavender_pa= nel_desc }, + { .compatible =3D "txdkj,txdi600yanpa-43v3", .data =3D &txd_x00td_panel_d= esc }, { }, }; MODULE_DEVICE_TABLE(of, panel_nt36672a_match); --=20 2.55.0 From nobody Fri Sep 25 01:29:00 2026 Received: from sm24.hosting.reg.ru (sm24.hosting.reg.ru [31.31.198.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCD8A51DAFE; Thu, 17 Sep 2026 16:44:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=31.31.198.150 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663470; cv=none; b=ZcSRzfaINfe4aU0gv3bT7JOshC5C29OM1XF7EhXsgfJMCzco6FVh0Ec0t0HZVBJ3ddNJj4AJ34faseTZQ+arxrNs9fAxu5XrBUJIZATwMmP5Svn77h7gN24b2H4HGyyZga0pOLG6jZx0crRQQelg2CwgDAdik+wUzFPqFRiGv0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789663470; c=relaxed/simple; bh=XB/w2KjdN0WT16TajgKPI5CXgOF71xFdtBEERo7qQug=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MJ+QRlSKl8V7dn/prdn2TIKuA5JLrO8n7r6eqzVEy4znEnNsVuFCRtm6jsaQuQsXHS2x9A0CJViNTCZbM/OvVMwPQXxhIFyiZ1bMXs92ePXQqgWrzqCGv3l9CEVS2kbErsSnkt+qvr8Fm92ozeurShC6xzt1zC9MNDPukYW9Pj8= ARC-Authentication-Results: i=1; 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b=PoyvFpYf2UQeVOovH1gAFrgzFs /aoWP9VKNm2T1VXgD4KKqHECl9/G+sem9GfEJ7QWF/Y6qnju1iugM/gwhVIFNe3bKjyf8qV0kWv+H 3MISOunogeShgNzwvOzra8ff+At/VV4nI/oTYNbFDryaLT5CkiAlDTL+vii86KK1OrEU=; Received: by sm24.hosting.reg.ru with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (envelope-from ) id 1x7FDl-0000000Bw3I-2i0X; Thu, 17 Sep 2026 19:44:26 +0300 From: Alexey Minnekhanov Date: Thu, 17 Sep 2026 19:43:11 +0300 Subject: [PATCH v2 9/9] MAINTAINERS: Add Alexey Minnekhanov as maintainer for NT36672A panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260917-nt36672a-panels-v2-9-f8de8be5b86f@minlexx.ru> References: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> In-Reply-To: <20260917-nt36672a-panels-v2-0-f8de8be5b86f@minlexx.ru> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: David Heidelberg , Joel Selvaraj , Chintan Patel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, Alexey Minnekhanov X-Mailer: b4 0.16.0 List myself as maintainer of Novatek NT36672A panels driver to keep a close eye on it. Signed-off-by: Alexey Minnekhanov --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6e50747a621c2..80a065264aa86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8393,6 +8393,7 @@ F: drivers/gpu/drm/panel/panel-novatek-nt36532.c =20 DRM DRIVER FOR NOVATEK NT36672A PANELS M: Sumit Semwal +M: Alexey Minnekhanov S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml --=20 2.55.0