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This SoC does not provide macro and dcodec clock so reflect that in the bindings. Shikra integrates LPASS codec version 4.1, which is not backwards compatible with the already described compatibles. Signed-off-by: Mohammad Rafi Shaik --- .../devicetree/bindings/sound/qcom,lpass-rx-macro.yaml | 17 +++++++++++++= ++++ .../devicetree/bindings/sound/qcom,lpass-va-macro.yaml | 17 +++++++++++++= ++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml index 4988e7ed6..69d7b7332 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sc7280-lpass-rx-macro + - qcom,shikra-lpass-rx-macro - qcom,sm6115-lpass-rx-macro - qcom,sm8250-lpass-rx-macro - qcom,sm8450-lpass-rx-macro @@ -138,6 +139,22 @@ allOf: - const: dcodec - const: fsgen =20 + - if: + properties: + compatible: + enum: + - qcom,shikra-lpass-rx-macro + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: mclk + - const: npl + - const: fsgen + unevaluatedProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index aea31fbda..683ebf702 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sc7280-lpass-va-macro + - qcom,shikra-lpass-va-macro - qcom,sm6115-lpass-va-macro - qcom,sm8250-lpass-va-macro - qcom,sm8450-lpass-va-macro @@ -168,6 +169,22 @@ allOf: - const: macro - const: dcodec =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,shikra-lpass-va-macro + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: mclk + - const: npl + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Fri Sep 25 03:21:20 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89AE030C146 for ; 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Add the missing case. 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The RX macro register layout of LPASS codec v4.1 matches the v2.5+ layout, so reuse the existing v2.5 register access helpers, controls and widgets for it. v4.1 additionally requires the FS counter to be bypassed before it is enabled during MCLK enable. This is a property of the codec version and not of the board, so key it off the version detected by the VA macro rather than off match data. Signed-off-by: Mohammad Rafi Shaik --- sound/soc/codecs/lpass-macro-common.h | 3 +++ sound/soc/codecs/lpass-rx-macro.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/sound/soc/codecs/lpass-macro-common.h b/sound/soc/codecs/lpass= -macro-common.h index 573b2145e..b52665b11 100644 --- a/sound/soc/codecs/lpass-macro-common.h +++ b/sound/soc/codecs/lpass-macro-common.h @@ -30,6 +30,7 @@ enum lpass_codec_version { LPASS_CODEC_VERSION_2_7, LPASS_CODEC_VERSION_2_8, LPASS_CODEC_VERSION_2_9, + LPASS_CODEC_VERSION_4_1, }; =20 struct lpass_macro { @@ -70,6 +71,8 @@ static inline const char *lpass_macro_get_codec_version_s= tring(int version) return "v2.8"; case LPASS_CODEC_VERSION_2_9: return "v2.9"; + case LPASS_CODEC_VERSION_4_1: + return "v4.1"; default: break; } diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-= macro.c index c41eb8de6..93ceee878 100644 --- a/sound/soc/codecs/lpass-rx-macro.c +++ b/sound/soc/codecs/lpass-rx-macro.c @@ -60,6 +60,7 @@ #define CDC_RX_FS_MCLK_CNT_ENABLE BIT(0) #define CDC_RX_FS_MCLK_CNT_CLR_MASK BIT(1) #define CDC_RX_FS_MCLK_CNT_CLR BIT(1) +#define CDC_RX_FS_CNT_BYPASS BIT(7) #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108) #define CDC_RX_SWR_CLK_EN_MASK BIT(0) #define CDC_RX_SWR_RESET_MASK BIT(1) @@ -652,6 +653,7 @@ struct rx_macro { bool is_ear_mode_on; bool hph_pwr_mode; bool hph_hd2_mode; + bool fs_cnt_bypass; struct snd_soc_component *component; unsigned long active_ch_mask[RX_MACRO_MAX_DAIS]; unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS]; @@ -1613,6 +1615,7 @@ static bool rx_is_rw_register(struct device *dev, uns= igned int reg) case LPASS_CODEC_VERSION_2_6: case LPASS_CODEC_VERSION_2_7: case LPASS_CODEC_VERSION_2_8: + case LPASS_CODEC_VERSION_4_1: return rx_2_5_is_rw_register(dev, reg); default: break; @@ -2045,6 +2048,11 @@ static int rx_macro_mclk_enable(struct rx_macro *rx,= bool mclk_enable) CDC_RX_CLK_MCLK2_ENABLE); regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00); + + if (rx->fs_cnt_bypass) + regmap_set_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, + CDC_RX_FS_CNT_BYPASS); + regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_RX_FS_MCLK_CNT_EN_MASK, CDC_RX_FS_MCLK_CNT_ENABLE); @@ -3652,6 +3660,7 @@ static int rx_macro_component_probe(struct snd_soc_co= mponent *component) case LPASS_CODEC_VERSION_2_6: case LPASS_CODEC_VERSION_2_7: case LPASS_CODEC_VERSION_2_8: + case LPASS_CODEC_VERSION_4_1: controls =3D rx_macro_2_5_snd_controls; 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LPASS codec v4.1 extends the VA macro with four adaptive filter (ADPT) blocks at 0x0800..0x09a4 and requires the FS counter to be bypassed before it is enabled. Add the new registers as a separate reg_default array that is concatenated with the common defaults at probe time. The register layout has to be chosen before the regmap exists, i.e. before CDC_VA_TOP_CSR_CORE_ID_* can be read, so it comes from match data; probe then cross checks it against the version reported by the hardware. Signed-off-by: Mohammad Rafi Shaik --- sound/soc/codecs/lpass-va-macro.c | 233 ++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 226 insertions(+), 7 deletions(-) diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-= macro.c index 03d6434a4..31d399dfa 100644 --- a/sound/soc/codecs/lpass-va-macro.c +++ b/sound/soc/codecs/lpass-va-macro.c @@ -26,6 +26,7 @@ #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) #define CDC_VA_FS_CONTROL_EN BIT(0) #define CDC_VA_FS_COUNTER_CLR BIT(1) +#define CDC_VA_FS_CNT_BYPASS BIT(7) #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008) #define CDC_VA_SWR_RESET_MASK BIT(1) #define CDC_VA_SWR_RESET_ENABLE BIT(1) @@ -156,7 +157,54 @@ #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4) #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8) =20 +/* LPASS codec v4.1 adaptive filter (ADPT) blocks */ +#define CDC_VA_CDC_ADPT0_ADPT_CTRL 0x0800 +#define CDC_VA_ADPT_CTRL_EN_MASK GENMASK(7, 0) +#define CDC_VA_CDC_ADPT0_ADPT_GAIN_0 0x0804 +#define CDC_VA_CDC_ADPT0_ADPT_GAIN_1 0x0808 +#define CDC_VA_CDC_ADPT0_DH_FSM_CTRL 0x080c +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_0 0x0810 +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_1 0x0814 +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_2 0x0818 +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_3 0x081c +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_4 0x0820 +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_5 0x0824 + +#define CDC_VA_CDC_ADPT1_ADPT_CTRL 0x0880 +#define CDC_VA_CDC_ADPT1_ADPT_GAIN_0 0x0884 +#define CDC_VA_CDC_ADPT1_ADPT_GAIN_1 0x0888 +#define CDC_VA_CDC_ADPT1_DH_FSM_CTRL 0x088c +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_0 0x0890 +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_1 0x0894 +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_2 0x0898 +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_3 0x089c +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_4 0x08a0 +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_5 0x08a4 + +#define CDC_VA_CDC_ADPT2_ADPT_CTRL 0x0900 +#define CDC_VA_CDC_ADPT2_ADPT_GAIN_0 0x0904 +#define CDC_VA_CDC_ADPT2_ADPT_GAIN_1 0x0908 +#define CDC_VA_CDC_ADPT2_DH_FSM_CTRL 0x090c +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_0 0x0910 +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_1 0x0914 +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_2 0x0918 +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_3 0x091c +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_4 0x0920 +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_5 0x0924 + +#define CDC_VA_CDC_ADPT3_ADPT_CTRL 0x0980 +#define CDC_VA_CDC_ADPT3_ADPT_GAIN_0 0x0984 +#define CDC_VA_CDC_ADPT3_ADPT_GAIN_1 0x0988 +#define CDC_VA_CDC_ADPT3_DH_FSM_CTRL 0x098c +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_0 0x0990 +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_1 0x0994 +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_2 0x0998 +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_3 0x099c +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_4 0x09a0 +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_5 0x09a4 + #define VA_MAX_OFFSET (0x07A8) +#define VA_4_1_MAX_OFFSET 0x09a4 =20 #define VA_MACRO_NUM_DECIMATORS 4 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ @@ -210,7 +258,8 @@ struct va_macro { u16 dmic_clk_div; bool has_swr_master; bool has_npl_clk; - + bool fs_cnt_bypass; + bool has_adpt; int dec_mode[VA_MACRO_NUM_DECIMATORS]; struct regmap *regmap; struct clk *mclk; @@ -237,6 +286,7 @@ struct va_macro_data { bool has_swr_master; bool has_npl_clk; int version; + const struct regmap_config *regmap_config; }; =20 static const struct va_macro_data sm8250_va_data =3D { @@ -357,6 +407,127 @@ static const struct reg_default va_defaults[] =3D { { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, }; =20 +static const struct reg_default va_4_1_defaults[] =3D { + /* VA macro */ + { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, + { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, + { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, + { CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, + { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, + { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, + { CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, + { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, + { CDC_VA_TOP_CSR_I2S_CLK, 0x00}, + { CDC_VA_TOP_CSR_I2S_RESET, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, + { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, + { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, + { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, + { CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, + /* VA core */ + { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, + { CDC_VA_TX0_TX_PATH_CTL, 0x04}, + { CDC_VA_TX0_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX0_TX_VOL_CTL, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX0_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX0_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX0_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC6, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC7, 0x25}, + { CDC_VA_TX1_TX_PATH_CTL, 0x04}, + { CDC_VA_TX1_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX1_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX1_TX_VOL_CTL, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX1_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX1_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX1_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC6, 0x00}, + { CDC_VA_TX2_TX_PATH_CTL, 0x04}, + { CDC_VA_TX2_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX2_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX2_TX_VOL_CTL, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX2_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX2_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX2_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC6, 0x00}, + { CDC_VA_TX3_TX_PATH_CTL, 0x04}, + { CDC_VA_TX3_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX3_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX3_TX_VOL_CTL, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX3_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX3_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX3_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, + /* ADPT blocks */ + { CDC_VA_CDC_ADPT0_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT0_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT0_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT0_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_5, 0x01}, + { CDC_VA_CDC_ADPT1_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT1_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT1_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT1_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_5, 0x01}, + { CDC_VA_CDC_ADPT2_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT2_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT2_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT2_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_5, 0x01}, + { CDC_VA_CDC_ADPT3_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT3_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT3_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT3_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_5, 0x01}, +}; + static bool va_is_rw_register(struct device *dev, unsigned int reg) { switch (reg) { @@ -430,6 +601,10 @@ static bool va_is_rw_register(struct device *dev, unsi= gned int reg) case CDC_VA_TX3_TX_PATH_SEC4: case CDC_VA_TX3_TX_PATH_SEC5: case CDC_VA_TX3_TX_PATH_SEC6: + case CDC_VA_CDC_ADPT0_ADPT_CTRL: + case CDC_VA_CDC_ADPT1_ADPT_CTRL: + case CDC_VA_CDC_ADPT2_ADPT_CTRL: + case CDC_VA_CDC_ADPT3_ADPT_CTRL: return true; } =20 @@ -463,6 +638,27 @@ static const struct regmap_config va_regmap_config =3D= { .writeable_reg =3D va_is_rw_register, }; =20 +static const struct regmap_config va_4_1_regmap_config =3D { + .name =3D "va_macro", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .cache_type =3D REGCACHE_MAPLE, + .reg_defaults =3D va_4_1_defaults, + .num_reg_defaults =3D ARRAY_SIZE(va_4_1_defaults), + .max_register =3D VA_4_1_MAX_OFFSET, + .volatile_reg =3D va_is_volatile_register, + .readable_reg =3D va_is_readable_register, + .writeable_reg =3D va_is_rw_register, +}; + +static const struct va_macro_data shikra_va_data =3D { + .has_swr_master =3D true, + .has_npl_clk =3D true, + .version =3D LPASS_CODEC_VERSION_4_1, + .regmap_config =3D &va_4_1_regmap_config, +}; + static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable) { struct regmap *regmap =3D va->regmap; @@ -471,10 +667,14 @@ static int va_clk_rsc_fs_gen_request(struct va_macro = *va, bool enable) regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, CDC_VA_MCLK_CONTROL_EN, CDC_VA_MCLK_CONTROL_EN); - /* clear the fs counter */ + regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR, CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR); + + if (va->fs_cnt_bypass) + regmap_set_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, + CDC_VA_FS_CNT_BYPASS); regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR, CDC_VA_FS_CONTROL_EN); @@ -503,7 +703,7 @@ static int va_macro_mclk_enable(struct va_macro *va, bo= ol mclk_enable) if (mclk_enable) { va_clk_rsc_fs_gen_request(va, true); regcache_mark_dirty(regmap); - regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET); + regcache_sync_region(regmap, 0x0, regmap_get_max_register(regmap)); } else { va_clk_rsc_fs_gen_request(va, false); } @@ -749,6 +949,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widg= et *w, unsigned int decimator; u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg; u16 tx_gain_ctl_reg; + u16 adpt_ctrl_reg; u8 hpf_cut_off_freq; =20 struct va_macro *va =3D snd_soc_component_get_drvdata(comp); @@ -763,6 +964,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widg= et *w, VA_MACRO_TX_PATH_OFFSET * decimator; tx_gain_ctl_reg =3D CDC_VA_TX0_TX_VOL_CTL + VA_MACRO_TX_PATH_OFFSET * decimator; + adpt_ctrl_reg =3D CDC_VA_CDC_ADPT0_ADPT_CTRL + decimator * VA_MACRO_TX_PA= TH_OFFSET; =20 switch (event) { case SND_SOC_DAPM_PRE_PMU: @@ -772,6 +974,10 @@ static int va_macro_enable_dec(struct snd_soc_dapm_wid= get *w, /* Enable TX PGA Mute */ break; case SND_SOC_DAPM_POST_PMU: + if (va->has_adpt) + snd_soc_component_update_bits(comp, adpt_ctrl_reg, + CDC_VA_ADPT_CTRL_EN_MASK, 0x00); + /* Enable TX CLK */ snd_soc_component_update_bits(comp, tx_vol_ctl_reg, CDC_VA_TX_PATH_CLK_EN_MASK, @@ -1526,6 +1732,14 @@ static int va_macro_set_lpass_codec_version(struct v= a_macro *va) default: break; } + } else if (maj =3D=3D 4) { + switch (min) { + case 1: + version =3D LPASS_CODEC_VERSION_4_1; + break; + default: + break; + } } =20 if (version =3D=3D LPASS_CODEC_VERSION_UNKNOWN) { @@ -1556,6 +1770,7 @@ static int va_macro_probe(struct platform_device *pde= v) return -ENOMEM; =20 va->dev =3D dev; + data =3D of_device_get_match_data(dev); =20 va->macro =3D devm_clk_get_optional(dev, "macro"); if (IS_ERR(va->macro)) @@ -1592,15 +1807,15 @@ static int va_macro_probe(struct platform_device *p= dev) goto err; } =20 - va->regmap =3D devm_regmap_init_mmio(dev, base, &va_regmap_config); + dev_set_drvdata(dev, va); + + va->regmap =3D devm_regmap_init_mmio(dev, base, + data->regmap_config ?: &va_regmap_config); if (IS_ERR(va->regmap)) { ret =3D -EINVAL; goto err; } =20 - dev_set_drvdata(dev, va); - - data =3D of_device_get_match_data(dev); va->has_swr_master =3D data->has_swr_master; va->has_npl_clk =3D data->has_npl_clk; =20 @@ -1654,6 +1869,9 @@ static int va_macro_probe(struct platform_device *pde= v) goto err_rpm_put; } =20 + va->fs_cnt_bypass =3D (lpass_macro_get_codec_version() =3D=3D LPASS_CODEC= _VERSION_4_1); + va->has_adpt =3D (lpass_macro_get_codec_version() =3D=3D LPASS_CODEC_VERS= ION_4_1); + if (va->has_swr_master) { /* Set default CLK div to 1 */ regmap_update_bits(va->regmap, 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AW1haW4tMjYwOTE3MDAyOSBTYWx0ZWRfX+d8QlOgNXwhQ qWFXhSQDthtRZcCdKbP4rHDy4H3EoOreonxE18TMIjFcYADAHBVoCUxIjl8OnmJP3JlAe5oQJkf Z6cONxGyupzOH2BA+dHcnRVHgw2oupY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-16_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609170029 The VA decimators can currently capture audio only from DMIC inputs. Add support for routing audio from SoundWire microphone (SMIC) inputs as well. Update the decimator source selection logic to switch between DMIC and SMIC sources based on the active input path. Add a helper to detect whether a decimator is using a SoundWire microphone input. Use this information to skip DMIC-specific HPF programming sequences when the decimator is configured for an SMIC source. This enables VA decimators to capture audio from either DMIC or SoundWire microphone inputs. Signed-off-by: Mohammad Rafi Shaik --- sound/soc/codecs/lpass-va-macro.c | 133 ++++++++++++++++++++++++++++++++++= +--- 1 file changed, 124 insertions(+), 9 deletions(-) diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-= macro.c index 31d399dfa..50673b012 100644 --- a/sound/soc/codecs/lpass-va-macro.c +++ b/sound/soc/codecs/lpass-va-macro.c @@ -758,10 +758,22 @@ static int va_macro_put_dec_enum(struct snd_kcontrol = *kcontrol, return -EINVAL; } =20 - if (val !=3D 0) - snd_soc_component_update_bits(component, mic_sel_reg, - CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, - CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC); + if (val !=3D 0) { + /* + * SMIC enums use shift 0 (lower nibble of CFG0), + * DMIC enums use shift 4 (upper nibble of CFG0). + * Use e->shift_l to distinguish them without relying + * on widget name comparisons. + */ + if (e->shift_l =3D=3D 0) + snd_soc_component_update_bits(component, mic_sel_reg, + CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, + CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC); + else + snd_soc_component_update_bits(component, mic_sel_reg, + CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, + CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC); + } =20 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); } @@ -942,6 +954,16 @@ static int va_macro_enable_dmic(struct snd_soc_dapm_wi= dget *w, return 0; } =20 +static bool is_amic_enabled(struct snd_soc_component *comp, int decimator) +{ + u16 adc_mux_reg; + + adc_mux_reg =3D CDC_VA_INP_MUX_ADC_MUX0_CFG1 + + VA_MACRO_ADC_MUX_CFG_OFFSET * decimator; + + return snd_soc_component_read(comp, adc_mux_reg) & BIT(0); +} + static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -951,7 +973,6 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widg= et *w, u16 tx_gain_ctl_reg; u16 adpt_ctrl_reg; u8 hpf_cut_off_freq; - struct va_macro *va =3D snd_soc_component_get_drvdata(comp); =20 decimator =3D w->shift; @@ -982,9 +1003,10 @@ static int va_macro_enable_dec(struct snd_soc_dapm_wi= dget *w, snd_soc_component_update_bits(comp, tx_vol_ctl_reg, CDC_VA_TX_PATH_CLK_EN_MASK, CDC_VA_TX_PATH_CLK_EN); - snd_soc_component_update_bits(comp, hpf_gate_reg, - CDC_VA_TX_HPF_ZERO_GATE_MASK, - CDC_VA_TX_HPF_ZERO_GATE); + if (!is_amic_enabled(comp, decimator)) + snd_soc_component_update_bits(comp, hpf_gate_reg, + CDC_VA_TX_HPF_ZERO_GATE_MASK, + CDC_VA_TX_HPF_ZERO_GATE); =20 usleep_range(1000, 1010); hpf_cut_off_freq =3D (snd_soc_component_read(comp, dec_cfg_reg) & @@ -1010,7 +1032,6 @@ static int va_macro_enable_dec(struct snd_soc_dapm_wi= dget *w, 0x0); } =20 - usleep_range(1000, 1010); snd_soc_component_update_bits(comp, hpf_gate_reg, CDC_VA_TX_HPF_ZERO_GATE_MASK, @@ -1210,6 +1231,39 @@ static const char * const adc_mux_text[] =3D { "VA_DMIC", "SWR_MIC" }; =20 +static const char * const smic_mux_text[] =3D { + "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_MIC0", "SWR_MIC1", + "SWR_MIC2", "SWR_MIC3", "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7" +}; + +static SOC_ENUM_SINGLE_DECL(va_smic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0, + 0, smic_mux_text); + +static SOC_ENUM_SINGLE_DECL(va_smic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0, + 0, smic_mux_text); + +static SOC_ENUM_SINGLE_DECL(va_smic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0, + 0, smic_mux_text); + +static SOC_ENUM_SINGLE_DECL(va_smic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0, + 0, smic_mux_text); + +static const struct snd_kcontrol_new va_smic0_mux =3D SOC_DAPM_ENUM_EXT("v= a_smic0", + va_smic0_enum, snd_soc_dapm_get_enum_double, + va_macro_put_dec_enum); + +static const struct snd_kcontrol_new va_smic1_mux =3D SOC_DAPM_ENUM_EXT("v= a_smic1", + va_smic1_enum, snd_soc_dapm_get_enum_double, + va_macro_put_dec_enum); + +static const struct snd_kcontrol_new va_smic2_mux =3D SOC_DAPM_ENUM_EXT("v= a_smic2", + va_smic2_enum, snd_soc_dapm_get_enum_double, + va_macro_put_dec_enum); + +static const struct snd_kcontrol_new va_smic3_mux =3D SOC_DAPM_ENUM_EXT("v= a_smic3", + va_smic3_enum, snd_soc_dapm_get_enum_double, + va_macro_put_dec_enum); + static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0, adc_mux_text); static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1, @@ -1345,6 +1399,11 @@ static const struct snd_soc_dapm_widget va_macro_dap= m_widgets[] =3D { SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux), SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux), =20 + SND_SOC_DAPM_MUX("VA SMIC MUX0", SND_SOC_NOPM, 0, 0, &va_smic0_mux), + SND_SOC_DAPM_MUX("VA SMIC MUX1", SND_SOC_NOPM, 0, 0, &va_smic1_mux), + SND_SOC_DAPM_MUX("VA SMIC MUX2", SND_SOC_NOPM, 0, 0, &va_smic2_mux), + SND_SOC_DAPM_MUX("VA SMIC MUX3", SND_SOC_NOPM, 0, 0, &va_smic3_mux), + SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0), SND_SOC_DAPM_INPUT("DMIC0 Pin"), SND_SOC_DAPM_INPUT("DMIC1 Pin"), @@ -1489,6 +1548,62 @@ static const struct snd_soc_dapm_route va_audio_map[= ] =3D { {"VA DMIC MUX3", "DMIC6", "VA DMIC6"}, {"VA DMIC MUX3", "DMIC7", "VA DMIC7"}, =20 + {"VA DEC0 MUX", "SWR_MIC", "VA SMIC MUX0"}, + {"VA SMIC MUX0", "ADC0", "VA SWR_ADC0"}, + {"VA SMIC MUX0", "ADC1", "VA SWR_ADC1"}, + {"VA SMIC MUX0", "ADC2", "VA SWR_ADC2"}, + {"VA SMIC MUX0", "ADC3", "VA SWR_ADC3"}, + {"VA SMIC MUX0", "SWR_MIC0", "VA SWR_MIC0"}, + {"VA SMIC MUX0", "SWR_MIC1", "VA SWR_MIC1"}, + {"VA SMIC MUX0", "SWR_MIC2", "VA SWR_MIC2"}, + {"VA SMIC MUX0", "SWR_MIC3", "VA SWR_MIC3"}, + {"VA SMIC MUX0", "SWR_MIC4", "VA SWR_MIC4"}, + {"VA SMIC MUX0", "SWR_MIC5", "VA SWR_MIC5"}, + {"VA SMIC MUX0", "SWR_MIC6", "VA SWR_MIC6"}, + {"VA SMIC MUX0", "SWR_MIC7", "VA SWR_MIC7"}, + + {"VA DEC1 MUX", "SWR_MIC", "VA SMIC MUX1"}, + {"VA SMIC MUX1", "ADC0", "VA SWR_ADC0"}, + {"VA SMIC MUX1", "ADC1", "VA SWR_ADC1"}, + {"VA SMIC MUX1", "ADC2", "VA SWR_ADC2"}, + {"VA SMIC MUX1", "ADC3", "VA SWR_ADC3"}, + {"VA SMIC MUX1", "SWR_MIC0", "VA SWR_MIC0"}, + {"VA SMIC MUX1", "SWR_MIC1", "VA SWR_MIC1"}, + {"VA SMIC MUX1", "SWR_MIC2", "VA SWR_MIC2"}, + {"VA SMIC MUX1", "SWR_MIC3", "VA SWR_MIC3"}, + {"VA SMIC MUX1", "SWR_MIC4", "VA SWR_MIC4"}, + {"VA SMIC MUX1", "SWR_MIC5", "VA SWR_MIC5"}, + {"VA SMIC MUX1", "SWR_MIC6", "VA SWR_MIC6"}, + {"VA SMIC MUX1", "SWR_MIC7", "VA SWR_MIC7"}, + + {"VA DEC2 MUX", "SWR_MIC", "VA SMIC MUX2"}, + {"VA SMIC MUX2", "ADC0", "VA SWR_ADC0"}, + {"VA SMIC MUX2", "ADC1", "VA SWR_ADC1"}, + {"VA SMIC MUX2", "ADC2", "VA SWR_ADC2"}, + {"VA SMIC MUX2", "ADC3", "VA SWR_ADC3"}, + {"VA SMIC MUX2", "SWR_MIC0", "VA SWR_MIC0"}, + {"VA SMIC MUX2", "SWR_MIC1", "VA SWR_MIC1"}, + {"VA SMIC MUX2", "SWR_MIC2", "VA SWR_MIC2"}, + {"VA SMIC MUX2", "SWR_MIC3", "VA SWR_MIC3"}, + {"VA SMIC MUX2", "SWR_MIC4", "VA SWR_MIC4"}, + {"VA SMIC MUX2", "SWR_MIC5", "VA SWR_MIC5"}, + {"VA SMIC MUX2", "SWR_MIC6", "VA SWR_MIC6"}, + {"VA SMIC MUX2", "SWR_MIC7", "VA SWR_MIC7"}, + + {"VA DEC3 MUX", "SWR_MIC", "VA SMIC MUX3"}, + {"VA SMIC MUX3", "ADC0", "VA SWR_ADC0"}, + {"VA SMIC MUX3", "ADC1", "VA SWR_ADC1"}, + {"VA SMIC MUX3", "ADC2", "VA SWR_ADC2"}, + {"VA SMIC MUX3", "ADC3", "VA SWR_ADC3"}, + {"VA SMIC MUX3", "SWR_MIC0", "VA SWR_MIC0"}, + {"VA SMIC MUX3", "SWR_MIC1", "VA SWR_MIC1"}, + {"VA SMIC MUX3", "SWR_MIC2", "VA SWR_MIC2"}, + {"VA SMIC MUX3", "SWR_MIC3", "VA SWR_MIC3"}, + {"VA SMIC MUX3", "SWR_MIC4", "VA SWR_MIC4"}, + {"VA SMIC MUX3", "SWR_MIC5", "VA SWR_MIC5"}, + {"VA SMIC MUX3", "SWR_MIC6", "VA SWR_MIC6"}, + {"VA SMIC MUX3", "SWR_MIC7", "VA SWR_MIC7"}, + { "VA DMIC0", NULL, "DMIC0 Pin" }, { "VA DMIC1", NULL, "DMIC1 Pin" }, { "VA DMIC2", NULL, "DMIC2 Pin" }, --=20 2.34.1