From nobody Fri Sep 25 04:07:20 2026 Received: from mta0.migadu.com (out-138.mta0.migadu.com [91.218.175.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF966448393 for ; Wed, 16 Sep 2026 19:52:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789588363; cv=none; b=Ccoc9qL2VY8MSy/XwadM/ZUcz5f0NvUysPUtdeVuX6Hu12k6RZ4BqI9/DiZvadC5mSvndmInLOLALA99mnbuc9JVaFFqD4c4ayIx9o+Mc5a+9G7FK8cgRKmE1DTjFIoxfNEQ9fQ/kNWp0xyA1PzocTPILJAYh1Mu1fqo2DcIYHs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789588363; c=relaxed/simple; bh=O01c+GQ4RowTdd0nGzCiaa7gltnKZNWMU/WFRv+w2yg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PuXzYXll3cqYIQUQjzT851661aJGJQgzCtumvPczZs4rPx4INJJHFSLIC06EbMfdtm6cgya4OqChzy8YV0IF+o3u3fFqx1IMG2lgGT6lKnhvRpRR2tFCeorokc7JRLWlN2p9ahV8XcMVIGpb3tIxdY4cihwzD5INtZfwkhDy/5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=iuRJwyTY; arc=none smtp.client-ip=91.218.175.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="iuRJwyTY" X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=O01c+GQ4RowTdd0nGzCiaa7gltnKZNWMU/WFRv+w2yg=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1789588346; v=1; x=1790193146; b=iuRJwyTYbJqmYg0/m6AZzgvyFil+xK8e1wek8Squ8C2AWubFaZzFwP3jpe9tfSm5q5dC9jAs gYptK7WWDcicTGL+1ZQAAe7tjwwvYoCaERgyaKIIkXieXI+InLFM7ALDE/Ol/BawQDGAzcSNR7s Huuk0cljP4fas3y7JJ4Yc0D4= X-Envelope-To: linux-kernel@vger.kernel.org Received: by mta11.migadu.com with ESMTPS id b5c48faab47fc563; Wed, 16 Sep 2026 19:52:26 +0000 X-Mizu-Trace-ID: b5c48faab47fc563 X-Migadu-Flow: FLOW_OUT From: Ihor Solodrai To: Borislav Petkov , Dave Hansen , Ingo Molnar , Thomas Gleixner Cc: Alexei Starovoitov , Andrii Nakryiko , Andrey Ryabinin , Andrew Morton , "H . Peter Anvin" , Andrey Konovalov , linux-kernel@vger.kernel.org, x86@kernel.org, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, kernel-team@meta.com Subject: [PATCH v3 1/5] x86/cpu: Factor init_cpu_info() out of identify_cpu() Date: Wed, 16 Sep 2026 12:51:59 -0700 Message-ID: <20260916195203.1099646-2-ihor.solodrai@linux.dev> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260916195203.1099646-1-ihor.solodrai@linux.dev> References: <20260916195203.1099646-1-ihor.solodrai@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" identify_cpu() unconditionally resets the struct cpuinfo_x86 fields to their default values and clears the capability arrays with memset() before rescanning the CPU to fill it in again. However the boot CPU capabilities have already been scanned by early_identify_cpu(), with interrupts disabled. Introduce init_cpu_info() helper in preparation for letting the callers decide whether the reset is needed. No functional changes. Signed-off-by: Ihor Solodrai Suggested-by: Borislav Petkov --- arch/x86/kernel/cpu/common.c | 51 ++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 23 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index c7352827f491..c3dce89ba590 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1782,6 +1782,32 @@ static void __init cpu_parse_early_param(void) } } =20 +static void init_cpu_info(struct cpuinfo_x86 *c) +{ + c->x86_cache_size =3D 0; + c->x86_vendor =3D X86_VENDOR_UNKNOWN; + c->x86_model =3D c->x86_stepping =3D 0; /* So far unknown... */ + c->x86_vendor_id[0] =3D '\0'; /* Unset */ + c->x86_model_id[0] =3D '\0'; /* Unset */ +#ifdef CONFIG_X86_64 + c->x86_clflush_size =3D 64; + c->x86_phys_bits =3D 36; + c->x86_virt_bits =3D 48; +#else + c->cpuid_level =3D -1; /* CPUID not detected */ + c->x86_clflush_size =3D 32; + c->x86_phys_bits =3D 32; + c->x86_virt_bits =3D 32; +#endif + c->x86_cache_alignment =3D c->x86_clflush_size; + memset(&c->x86_capability, 0, sizeof(c->x86_capability)); + memset(&c->cpuid, 0, sizeof(c->cpuid)); +#ifdef CONFIG_X86_VMX_FEATURE_NAMES + memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); +#endif + c->extended_cpuid_level =3D 0; +} + /* * Do minimum CPU detection early. * Fields really needed: vendor, cpuid_level, family, model, mask, @@ -1966,8 +1992,6 @@ void check_null_seg_clears_base(struct cpuinfo_x86 *c) =20 static void generic_identify(struct cpuinfo_x86 *c) { - c->extended_cpuid_level =3D 0; - if (!cpuid_feature()) identify_cpu_without_cpuid(c); =20 @@ -2011,27 +2035,8 @@ static void identify_cpu(struct cpuinfo_x86 *c) int i; =20 c->loops_per_jiffy =3D loops_per_jiffy; - c->x86_cache_size =3D 0; - c->x86_vendor =3D X86_VENDOR_UNKNOWN; - c->x86_model =3D c->x86_stepping =3D 0; /* So far unknown... */ - c->x86_vendor_id[0] =3D '\0'; /* Unset */ - c->x86_model_id[0] =3D '\0'; /* Unset */ -#ifdef CONFIG_X86_64 - c->x86_clflush_size =3D 64; - c->x86_phys_bits =3D 36; - c->x86_virt_bits =3D 48; -#else - c->cpuid_level =3D -1; /* CPUID not detected */ - c->x86_clflush_size =3D 32; - c->x86_phys_bits =3D 32; - c->x86_virt_bits =3D 32; -#endif - c->x86_cache_alignment =3D c->x86_clflush_size; - memset(&c->x86_capability, 0, sizeof(c->x86_capability)); - memset(&c->cpuid, 0, sizeof(c->cpuid)); -#ifdef CONFIG_X86_VMX_FEATURE_NAMES - memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); -#endif + + init_cpu_info(c); =20 generic_identify(c); =20 --=20 2.55.0 From nobody Fri Sep 25 04:07:20 2026 Received: from mta0.migadu.com (out-149.mta0.migadu.com [91.218.175.149]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 532B6443A98 for ; Wed, 16 Sep 2026 19:52:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.149 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789588379; cv=none; b=Ay7WKidweCWmBLYHKlkwhH8zcwXrM7qQ4mwJ1S3Tx72J+1/ZfyjGiawpcIwJJBbJvnj8ZgPdnkxyCFCEFoJjzKD+9kePGUtDhQ6HkwKAMeTPN1je60ecMEudDwyPJnqPzEgs88FkWZE7tBs+Gs4F83oj5SbuFZ629tkI9bdp6Xw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789588379; c=relaxed/simple; bh=uezm5MFaGZMNvW+locU7R+duzoa5ZNNuKXadO7AJik4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hzAiFY1s0Z0RSUnHkAACwHY2DZUcN1AuQyFq3FC9UGijU1l7+JxUiFUHdqTzFs9pYBUPnAJPbrxpEZkDbvvvV/5uM96ru0UkqlBD9+l+t2qspECmdnthYHliKWm+W0yLjfuelKhHDXaF+lkKf3LXlFsaDgGBuF7nCZouJjY/Iyk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=PxPEBXuP; arc=none smtp.client-ip=91.218.175.149 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="PxPEBXuP" X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=uezm5MFaGZMNvW+locU7R+duzoa5ZNNuKXadO7AJik4=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1789588354; v=1; x=1790193154; b=PxPEBXuP1a0yKQW86JkSiyLOtwOD5WqldVHkYt76++OiT/AprvVmI+8fZ4gXHz704tn2ipjr ZvQYjWiQoiXq8J4+ez3qZMy9gKyKl3YM67sNSqPTPXsZQAmdZMLAjcz+TnsYMer3iaB5pBg62rO S4Uwl0ZYK0n+ThOSse1/W0L4= X-Envelope-To: linux-kernel@vger.kernel.org Received: by mta11.migadu.com with ESMTPS id d4694686d251f010; Wed, 16 Sep 2026 19:52:34 +0000 X-Mizu-Trace-ID: d4694686d251f010 X-Migadu-Flow: FLOW_OUT From: Ihor Solodrai To: Borislav Petkov , Dave Hansen , Ingo Molnar , Thomas Gleixner Cc: Alexei Starovoitov , Andrii Nakryiko , Andrey Ryabinin , Andrew Morton , "H . Peter Anvin" , Andrey Konovalov , linux-kernel@vger.kernel.org, x86@kernel.org, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, kernel-team@meta.com Subject: [PATCH v3 2/5] x86/cpu: Initialize boot CPU cpuinfo defaults early Date: Wed, 16 Sep 2026 12:52:00 -0700 Message-ID: <20260916195203.1099646-3-ihor.solodrai@linux.dev> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260916195203.1099646-1-ihor.solodrai@linux.dev> References: <20260916195203.1099646-1-ihor.solodrai@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" early_identify_cpu() clears the capability array, the CPUID table and extended_cpuid_level, but the architectural defaults for the rest of struct cpuinfo_x86 are set only later, in identify_cpu(). Use the same defaults from the start, so that the boot CPU does not depend on a later reset to end up with the right ones. Signed-off-by: Ihor Solodrai Suggested-by: Borislav Petkov --- This change comes before the last patch because that one removes the reset: without the defaults established here the boot CPU would be left at 32 instead of 64 on an x86_64 CPU which does not enumerate CLFLUSH. --- arch/x86/kernel/cpu/common.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index c3dce89ba590..66695addbdf3 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1812,16 +1812,15 @@ static void init_cpu_info(struct cpuinfo_x86 *c) * Do minimum CPU detection early. * Fields really needed: vendor, cpuid_level, family, model, mask, * cache alignment. - * The others are not touched to avoid unwanted side effects. + * The others are reset to their defaults here and only filled in later, + * by identify_cpu(). * * WARNING: this function is only called on the boot CPU. Don't add code * here that is supposed to run on all CPUs. */ static void __init early_identify_cpu(struct cpuinfo_x86 *c) { - memset(&c->x86_capability, 0, sizeof(c->x86_capability)); - memset(&c->cpuid, 0, sizeof(c->cpuid)); - c->extended_cpuid_level =3D 0; + init_cpu_info(c); =20 if (!cpuid_feature()) identify_cpu_without_cpuid(c); --=20 2.55.0 From nobody Fri Sep 25 04:07:20 2026 Received: from mta0.migadu.com (out-160.mta0.migadu.com [91.218.175.160]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC7FB443A84 for ; Wed, 16 Sep 2026 19:52:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.160 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789588375; cv=none; b=apNnMBKf+4hHwE7NJB85EHZCqu0YMpg0MpQQW+QEBR/mY6AkhoYPayfF7rBZWJwKdU4IQCMV6kIBVcqpuscGKrqvCdHf2idqlLQn7vXjGmF8L2R1ZIkam6JxmeMfa6Iz78rr2n2emtSukEtQ62LbXgkEdha6xMnvuGB12srBHZU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789588375; c=relaxed/simple; bh=c2qPDFF4kfts5j40iNg40AreFJxVYAetkHMQoD+HVsY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cZhJAZjqWZlQSZCxo70Z+iuFnpBdVHMpob4ws0OgvE5UmEP9r2IQim1rAiQqrqYBnUYAV/QsZUh/Ik43BG5btnIHaF6RxycoLZW0mv+TmTXOI5b2oa/p4nosCWqMoyw9ReqIiwqBP9BBBZSZLeWG4FJ9/QunJeUfDotxKLVyazY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=dzLH3eKI; arc=none smtp.client-ip=91.218.175.160 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="dzLH3eKI" X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=c2qPDFF4kfts5j40iNg40AreFJxVYAetkHMQoD+HVsY=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1789588358; v=1; x=1790193158; b=dzLH3eKI4Uh6rkWoSJD6vGu6fvM27SKbLD8oX6TFYEH/KRHltqKwWGTtWMJ2kafwc0o57w5j /I2cHbqtygzKk4P7nnAQFcPcW7hNpRe7I+HroH/VUEMhYQU8h/K5U+ytf5SOWJ2sFQ+FDtdP0iZ 0TurEznQTi2yM8/TgfoZeEn0= X-Envelope-To: linux-kernel@vger.kernel.org Received: by mta11.migadu.com with ESMTPS id c4c15b9716180eaa; Wed, 16 Sep 2026 19:52:38 +0000 X-Mizu-Trace-ID: c4c15b9716180eaa X-Migadu-Flow: FLOW_OUT From: Ihor Solodrai To: Borislav Petkov , Dave Hansen , Ingo Molnar , Thomas Gleixner Cc: Alexei Starovoitov , Andrii Nakryiko , Andrey Ryabinin , Andrew Morton , "H . Peter Anvin" , Andrey Konovalov , linux-kernel@vger.kernel.org, x86@kernel.org, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, kernel-team@meta.com Subject: [PATCH v3 3/5] x86/cpu: Inline generic_identify() into identify_cpu() Date: Wed, 16 Sep 2026 12:52:01 -0700 Message-ID: <20260916195203.1099646-4-ihor.solodrai@linux.dev> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260916195203.1099646-1-ihor.solodrai@linux.dev> References: <20260916195203.1099646-1-ihor.solodrai@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" generic_identify() has exactly one call site: at the top of identify_cpu(). Fold it into identify_cpu() so that a single function does the job for both the boot CPU and the secondary CPUs. While at it, fix up both copies of the Cyrix comment. No functional changes. Signed-off-by: Ihor Solodrai Suggested-by: Borislav Petkov --- arch/x86/kernel/cpu/common.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 66695addbdf3..2b2a4c40ef76 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1825,7 +1825,7 @@ static void __init early_identify_cpu(struct cpuinfo_= x86 *c) if (!cpuid_feature()) identify_cpu_without_cpuid(c); =20 - /* cyrix could have cpuid enabled via c_identify()*/ + /* Cyrix could have CPUID enabled via c_identify(). */ if (cpuid_feature()) { cpuid_scan_cpu(c); cpu_detect(c); @@ -1989,14 +1989,23 @@ void check_null_seg_clears_base(struct cpuinfo_x86 = *c) set_cpu_bug(c, X86_BUG_NULL_SEG); } =20 -static void generic_identify(struct cpuinfo_x86 *c) +/* + * This does the hard work of actually picking apart the CPU stuff... + */ +static void identify_cpu(struct cpuinfo_x86 *c) { + int i; + + c->loops_per_jiffy =3D loops_per_jiffy; + + init_cpu_info(c); + if (!cpuid_feature()) identify_cpu_without_cpuid(c); =20 - /* cyrix could have cpuid enabled via c_identify()*/ + /* Cyrix could have CPUID enabled via c_identify(). */ if (!cpuid_feature()) - return; + goto no_cpuid; =20 cpuid_scan_cpu(c); cpu_detect(c); @@ -2024,21 +2033,8 @@ static void generic_identify(struct cpuinfo_x86 *c) #ifdef CONFIG_X86_32 set_cpu_bug(c, X86_BUG_ESPFIX); #endif -} - -/* - * This does the hard work of actually picking apart the CPU stuff... - */ -static void identify_cpu(struct cpuinfo_x86 *c) -{ - int i; - - c->loops_per_jiffy =3D loops_per_jiffy; - - init_cpu_info(c); - - generic_identify(c); =20 +no_cpuid: cpu_parse_topology(c); =20 if (this_cpu->c_identify) --=20 2.55.0 From nobody Fri Sep 25 04:07:20 2026 Received: from mta0.migadu.com (out-172.mta0.migadu.com [91.218.175.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16D374418D7 for ; Wed, 16 Sep 2026 19:52:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789588382; cv=none; b=UUPEVi9mO5OluFzQwuFSVr9RFkhdu89xRFNnAUbSUC1rCohK/bzClSpqHNM2gzcPfcV0NtlkF//iHkcmxgt7i976CcaxGHb6+cE5yMY2sFxvYxgs/c6ESs6JdkYYccnr1N6gEpvYM2k0wXiPFbOi2oNyyC/G3meMjuIMIN+V5og= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789588382; c=relaxed/simple; bh=NkwRWssGXzQfAtXSgywsv6pvQ9Jdw4rpWWvy40Z4lEU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OrT9NMJziDEVK51HO85+bdkcsfP/Z7aMtZIIw38nFQz/ND99N6dc/P8iIyGzabN15az4bBLD/FLZbGJxKWeT5HQv9tueUX+kr1vR16cOljVxSi/CeCKEWhTpWXHsic7s/zZH8ItvYD+9dtIRPg4GSktGZZmnPFFjDbXfHvXq4qE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=JFQef9Gt; arc=none smtp.client-ip=91.218.175.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="JFQef9Gt" X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=NkwRWssGXzQfAtXSgywsv6pvQ9Jdw4rpWWvy40Z4lEU=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1789588367; v=1; x=1790193167; b=JFQef9Gt3KpXMJmayecRqz418APz6tHDMrFI4RZZCL/FjpDUGXoGTfWhJqRr/j8kbdi5j9UA 6c2OkuEUhnUeICRlmKpy2gUoGI6oyPo5/kxNlFz7H3U7zWy3iOAC0Zk+4tNTjaIka2FZ5pa3Ym8 PeRphGun1jYq2mcE2By96a9g= X-Envelope-To: linux-kernel@vger.kernel.org Received: by mta11.migadu.com with ESMTPS id 4af099ac9b2f47f6; Wed, 16 Sep 2026 19:52:46 +0000 X-Mizu-Trace-ID: 4af099ac9b2f47f6 X-Migadu-Flow: FLOW_OUT From: Ihor Solodrai To: Borislav Petkov , Dave Hansen , Ingo Molnar , Thomas Gleixner Cc: Alexei Starovoitov , Andrii Nakryiko , Andrey Ryabinin , Andrew Morton , "H . Peter Anvin" , Andrey Konovalov , linux-kernel@vger.kernel.org, x86@kernel.org, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, kernel-team@meta.com Subject: [PATCH v3 4/5] x86/cpu: Move 32-bit SEP setup into identify_cpu() Date: Wed, 16 Sep 2026 12:52:02 -0700 Message-ID: <20260916195203.1099646-5-ihor.solodrai@linux.dev> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260916195203.1099646-1-ihor.solodrai@linux.dev> References: <20260916195203.1099646-1-ihor.solodrai@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" identify_boot_cpu() and identify_secondary_cpu() both call enable_sep_cpu() under CONFIG_X86_32 immediately after identify_cpu(). Do it once and drop the ifdefs while at it. No functional changes. Reviewed-by: Nikolay Borisov Signed-off-by: Ihor Solodrai Suggested-by: Borislav Petkov --- arch/x86/kernel/cpu/common.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 2b2a4c40ef76..83d613d07997 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2126,6 +2126,9 @@ static void identify_cpu(struct cpuinfo_x86 *c) mcheck_cpu_init(c); =20 numa_add_cpu(smp_processor_id()); + + if (IS_ENABLED(CONFIG_X86_32)) + enable_sep_cpu(); } =20 /* @@ -2163,9 +2166,6 @@ static __init void identify_boot_cpu(void) identify_cpu(&boot_cpu_data); if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) pr_info("CET detected: Indirect Branch Tracking enabled\n"); -#ifdef CONFIG_X86_32 - enable_sep_cpu(); -#endif cpu_detect_tlb(&boot_cpu_data); setup_cr_pinning(); =20 @@ -2185,9 +2185,6 @@ void identify_secondary_cpu(unsigned int cpu) c->cpu_index =3D cpu; =20 identify_cpu(c); -#ifdef CONFIG_X86_32 - enable_sep_cpu(); -#endif x86_spec_ctrl_setup_ap(); update_srbds_msr(); if (boot_cpu_has_bug(X86_BUG_GDS)) --=20 2.55.0 From nobody Fri Sep 25 04:07:20 2026 Received: from mta0.migadu.com (out-183.mta0.migadu.com [91.218.175.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9B8144684B for ; Wed, 16 Sep 2026 19:52:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789588404; cv=none; b=Qxkav6Mwp9GXueXrPMM/lG2h3zbQ/vQ80Em3Qhy07Z3rPaJvvOB/pXCs1qUj5thj5TYIaEU/i30kqmHx7YAI3n7i2edVqmyngPuPwframQEfbxFrg7vTdxI3orAhhIzMMAV3ET7MHSk9G9kjVfPUjmB7ZDbwmILhkyV1afoUwfY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789588404; c=relaxed/simple; bh=NALIzAyd257Q9XRdPDmwZcj4GGaZ5ZdrW+pWs0t+wH0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WdA/xPlsy1c0JXqh65c+Zv76NXv1P21/flsUJ2R+I0a1bkgt825KsHb+FDY49XnWyXuNFSBWgBNb7IPz4+X+lAcxguHnf23zM88WvTp9XSOFMgN4FmcO3abYYfU1ONQosM1e2dVYTfVQqn1Fug4IfU9hOvDDausitZdjkSFJafs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Nj75s8lu; arc=none smtp.client-ip=91.218.175.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Nj75s8lu" X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=NALIzAyd257Q9XRdPDmwZcj4GGaZ5ZdrW+pWs0t+wH0=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1789588373; v=1; x=1790193173; b=Nj75s8luQiePcDHUhOJVN9Qwz62YCYi2E1I9K+KT/omQ4z98CsRkHNkTZITIjTz8aEWqlFs+ O7O62kfXqKOJ+1l8wMFWKaMGf3I5My20sua/6UBq41dTfUMoSeOQ09E8MB6bcrHh+tWvVuX+XRs +tjKKOyvgVnl9DlRU8gJSyBE= X-Envelope-To: linux-kernel@vger.kernel.org Received: by mta11.migadu.com with ESMTPS id a2265ddc4010ca96; Wed, 16 Sep 2026 19:52:53 +0000 X-Mizu-Trace-ID: a2265ddc4010ca96 X-Migadu-Flow: FLOW_OUT From: Ihor Solodrai To: Borislav Petkov , Dave Hansen , Ingo Molnar , Thomas Gleixner Cc: Alexei Starovoitov , Andrii Nakryiko , Andrey Ryabinin , Andrew Morton , "H . Peter Anvin" , Andrey Konovalov , linux-kernel@vger.kernel.org, x86@kernel.org, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, kernel-team@meta.com Subject: [PATCH v3 5/5] x86/cpu: Don't transiently clear the boot CPU's capabilities Date: Wed, 16 Sep 2026 12:52:03 -0700 Message-ID: <20260916195203.1099646-6-ihor.solodrai@linux.dev> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260916195203.1099646-1-ihor.solodrai@linux.dev> References: <20260916195203.1099646-1-ihor.solodrai@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the boot CPU identify_cpu() runs from arch_cpu_finalize_init(), with interrupts enabled and before alternatives are patched. So cpu_feature_enabled() still evaluates against boot_cpu_data. identify_cpu() rebuilds c->x86_capability from scratch: the reset zeroes the array and the CPUID rescan fills it in again. An interrupt delivered in that window finds X86_FEATURE_LA57 clear in boot_cpu_data, so pgtable_l5_enabled() is false and KASAN checks a 5-level address against the 4-level addressability limit. The result is a bogus "wild-memory-access" report, and under kasan_multi_shot a report storm that wedges the boot. The boot CPU has already been scanned by early_identify_cpu(), with interrupts disabled, and its capabilities cannot have changed since. Reset only the CPUs which have not been scanned yet. The window is as old as identify_cpu() rebuilding the capabilities. Commit 39b9552281ab ("x86/mm: Optimize boot-time paging mode switching cost") merely let KASAN notice it by making pgtable_l5_enabled() read the feature bit. So no Fixes: tag. Closes: https://lore.kernel.org/bpf/20260610175651.647515-1-ihor.solodrai@l= inux.dev/ Signed-off-by: Ihor Solodrai Suggested-by: Borislav Petkov --- arch/x86/kernel/cpu/common.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 83d613d07997..496ffe429496 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1998,8 +1998,6 @@ static void identify_cpu(struct cpuinfo_x86 *c) =20 c->loops_per_jiffy =3D loops_per_jiffy; =20 - init_cpu_info(c); - if (!cpuid_feature()) identify_cpu_without_cpuid(c); =20 @@ -2184,6 +2182,7 @@ void identify_secondary_cpu(unsigned int cpu) *c =3D boot_cpu_data; c->cpu_index =3D cpu; =20 + init_cpu_info(c); identify_cpu(c); x86_spec_ctrl_setup_ap(); update_srbds_msr(); --=20 2.55.0