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Wed, 16 Sep 2026 11:59:01 -0700 (PDT) Received: from hu-parihar-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bfb19f8cesm11790987eec.2.2026.09.16.11.58.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Sep 2026 11:59:01 -0700 (PDT) From: Abhinav Parihar To: srinivas.kandagatla@linaro.org, linux-arm-msm@vger.kernel.org Cc: Abhinav Parihar , gregkh@linuxfoundation.org, quic_bkumar@quicinc.com, ekansh.gupta@oss.qualcomm.com, linux-kernel@vger.kernel.org, quic_chennak@quicinc.com, dri-devel@lists.freedesktop.org, arnd@arndb.de Subject: [PATCH] misc: fastrpc: Add cache maintenance for non-coherent platforms Date: Thu, 17 Sep 2026 00:28:50 +0530 Message-Id: <20260916185850.3686010-1-abhinav.parihar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE2MDI2MSBTYWx0ZWRfX1RVVNOjJd0Cs XgsfnnLuegAP0kbuVgYIKVLJkjk2mbt/mmJz3mFDUu/E3olj7xJEmhibj4T3nJmlXriIsv5FIof JPfHsTynrlGH5K7cHGR0ORAiMDLeQ438KL0teR0ukBuNQLckD/vpStrzhwgnhuseSeD0ePaB2ay eIT6UQ6X/M7e4tSBQjpCnhSZVgJPG/D1futJYS0qj6JiBWyTkUq6N3tH+RuEIjFZhq0aw7vTe/6 Jmo8v3u++4reqEN02kkUJocJcvX2WSAhb7Q3DjybqfPWcRiHLdzWTGEgXPkgd8wcoJqCh8PbpbP u8nn4muzBUbzJkNNc1LRTr/TxWe3kP7rFAMPOm/MXdMOuZ0ue/AiesKU9/8CZphsUebhruJW/iv Eetecn5wM3ThMgxKTj82uZlhtAgIFl0p2YO3t4jHhjeGmM876fy11+/HPbRllIIpCcGLv04tqZV kLGuIof16ZSb8cEqI6Q== X-Authority-Analysis: v=2.4 cv=L8aI0OT8 c=1 sm=1 tr=0 ts=6aaae6f7 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=MU9f_CYsPQiu3DAa9dAA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: WJ0soY6gplQF5n8oRfO4Z0rpCINL0_Wi X-Proofpoint-ORIG-GUID: WJ0soY6gplQF5n8oRfO4Z0rpCINL0_Wi X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE2MDI2MSBTYWx0ZWRfXyhQ+hvPkeAE3 pBV6SM4+4AvNr7RsVQJ33vAiU8lH6fdccgHAyKG79OPmB3Km64XFSZ5mjiN2RHJnxZSC7VUxNup n+hHDJlozc7qtDaiA8ubFs3QkGZH4d4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-16_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1011 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609160261 Content-Type: text/plain; charset="utf-8" Some platforms using fastrpc do not support DMA coherency on HLOS. On such systems, explicit cache maintenance is required to ensure data consistency for RPC argument buffers. Add cache maintenance for argument buffers when operating on non-coherent platforms: - Flush input buffers before invoking RPC to ensure CPU writes are visible to the DSP - Invalidate output buffers after RPC completion to ensure DSP writes are visible to the CPU Introduce helper functions fastrpc_flush_args() and fastrpc_inv_args() to perform the required dma-buf cache operations. These are invoked only when the device is not marked as DMA coherent. The coherency capability is determined using the "dma-coherent" device tree property and stored per session context. This ensures correct data synchronization on platforms lacking DMA coherency, while avoiding unnecessary overhead on coherent systems. Signed-off-by: Abhinav Parihar --- Patch [v1]: https://lore.kernel.org/all/20260604194811.2437567-1-abhinav.p= arihar@oss.qualcomm.com/ Changes in v2: - Fix buffer overlap handling to ensure cache maintenance is performed when input and output buffers overlap and the overlap calculation suppresses the buffer's mstart/mend range. - Add a do_cmo flag to track buffers that require cache maintenance even when their overlap range is clipped. - Invalidate output buffers before sending the RPC request, preventing stale CPU cache lines from being written back while the DSP updates the buffers. - Use DMA_FROM_DEVICE consistently for both begin_cpu_access() and end_cpu_access() when invalidating output buffers. drivers/misc/fastrpc.c | 77 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index d4fac2caca86..83d04b9d2ea0 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -217,6 +217,7 @@ struct fastrpc_buf_overlap { u64 mstart; u64 mend; u64 offset; + bool do_cmo; }; =20 struct fastrpc_buf { @@ -292,6 +293,7 @@ struct fastrpc_session_ctx { int sid; bool used; bool valid; + bool coherent; }; =20 struct fastrpc_soc_data { @@ -655,7 +657,9 @@ static int olaps_cmp(const void *a, const void *b) static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) { u64 max_end =3D 0; + int max_raix =3D -1; int i; + int inbufs =3D REMOTE_SCALARS_INBUFS(ctx->sc); =20 for (i =3D 0; i < ctx->nbufs; ++i) { ctx->olaps[i].start =3D ctx->args[i].ptr; @@ -675,6 +679,9 @@ static void fastrpc_get_buff_overlaps(struct fastrpc_in= voke_ctx *ctx) if (ctx->olaps[i].end > max_end) { max_end =3D ctx->olaps[i].end; } else { + if ((max_raix < inbufs && ctx->olaps[i].raix + 1 > inbufs) || + (ctx->olaps[i].raix < inbufs && max_raix + 1 > inbufs)) + ctx->olaps[i].do_cmo =3D true; ctx->olaps[i].mend =3D 0; ctx->olaps[i].mstart =3D 0; } @@ -684,6 +691,7 @@ static void fastrpc_get_buff_overlaps(struct fastrpc_in= voke_ctx *ctx) ctx->olaps[i].mstart =3D ctx->olaps[i].start; ctx->olaps[i].offset =3D 0; max_end =3D ctx->olaps[i].end; + max_raix =3D ctx->olaps[i].raix; } } } @@ -703,6 +711,7 @@ static struct fastrpc_invoke_ctx *fastrpc_context_alloc( =20 INIT_LIST_HEAD(&ctx->node); ctx->fl =3D user; + ctx->sc =3D sc; ctx->nscalars =3D REMOTE_SCALARS_LENGTH(sc); ctx->nbufs =3D REMOTE_SCALARS_INBUFS(sc) + REMOTE_SCALARS_OUTBUFS(sc); @@ -728,7 +737,6 @@ static struct fastrpc_invoke_ctx *fastrpc_context_alloc( /* Take a reference to user, released in fastrpc_context_free() */ fastrpc_user_get(user); =20 - ctx->sc =3D sc; ctx->retval =3D -1; ctx->pid =3D current->pid; ctx->client_id =3D user->client_id; @@ -1067,6 +1075,64 @@ static int fastrpc_create_maps(struct fastrpc_invoke= _ctx *ctx) return 0; } =20 +static void fastrpc_flush_args(struct fastrpc_invoke_ctx *ctx) +{ + union fastrpc_remote_arg *rpra =3D ctx->rpra; + int i, inbufs, outbufs; + + inbufs =3D REMOTE_SCALARS_INBUFS(ctx->sc); + outbufs =3D REMOTE_SCALARS_OUTBUFS(ctx->sc); + + for (i =3D 0; i < inbufs + outbufs; ++i) { + int raix =3D ctx->olaps[i].raix; + struct fastrpc_map *map =3D ctx->maps[raix]; + + if (raix + 1 > inbufs) + continue; + if (!map || !map->buf) + continue; + + if (rpra[raix].buf.len && (ctx->olaps[i].mstart || ctx->olaps[i].do_cmo)= ) { + dma_buf_begin_cpu_access(map->buf, DMA_TO_DEVICE); + dma_buf_end_cpu_access(map->buf, DMA_TO_DEVICE); + } + } +} + +static void fastrpc_inv_args(struct fastrpc_invoke_ctx *ctx) +{ + union fastrpc_remote_arg *rpra =3D ctx->rpra; + int i, inbufs, outbufs; + + inbufs =3D REMOTE_SCALARS_INBUFS(ctx->sc); + outbufs =3D REMOTE_SCALARS_OUTBUFS(ctx->sc); + + for (i =3D 0; i < inbufs + outbufs; ++i) { + int raix =3D ctx->olaps[i].raix; + struct fastrpc_map *map =3D ctx->maps[raix]; + + if (raix + 1 <=3D inbufs) + continue; + if (!rpra[raix].buf.len) + continue; + if (!map || !map->buf) + continue; + + /* + * Skip invalidation if the argument overlaps with the + * RPC control header page. + */ + if (((uintptr_t)rpra & PAGE_MASK) =3D=3D + ((uintptr_t)rpra[raix].buf.pv & PAGE_MASK)) + continue; + + if (ctx->olaps[i].mstart || ctx->olaps[i].do_cmo) { + dma_buf_begin_cpu_access(map->buf, DMA_FROM_DEVICE); + dma_buf_end_cpu_access(map->buf, DMA_FROM_DEVICE); + } + } +} + static struct fastrpc_invoke_buf *fastrpc_invoke_buf_start(union fastrpc_r= emote_arg *pra, int len) { return (struct fastrpc_invoke_buf *)(&pra[len]); @@ -1191,6 +1257,9 @@ static int fastrpc_get_args(u32 kernel, struct fastrp= c_invoke_ctx *ctx) } } =20 + if (!ctx->fl->sctx->coherent) + fastrpc_flush_args(ctx); + for (i =3D ctx->nbufs; i < ctx->nscalars; ++i) { list[i].num =3D ctx->args[i].length ? 1 : 0; list[i].pgidx =3D i; @@ -1376,6 +1445,8 @@ static int fastrpc_internal_invoke(struct fastrpc_use= r *fl, u32 kernel, if (err) goto bail; =20 + if (!fl->sctx->coherent) + fastrpc_inv_args(ctx); /* make sure that all CPU memory writes are seen by DSP */ dma_wmb(); /* Send invoke buffer to remote dsp */ @@ -1396,6 +1467,9 @@ static int fastrpc_internal_invoke(struct fastrpc_use= r *fl, u32 kernel, =20 /* make sure that all memory writes by DSP are seen by CPU */ dma_rmb(); + if (!fl->sctx->coherent) + fastrpc_inv_args(ctx); + /* populate all the output buffers with results */ err =3D fastrpc_put_args(ctx, kernel); if (err) @@ -2393,6 +2467,7 @@ static int fastrpc_cb_probe(struct platform_device *p= dev) sess->used =3D false; sess->valid =3D true; sess->dev =3D dev; + sess->coherent =3D of_property_read_bool(dev->of_node, "dma-coherent"); dev_set_drvdata(dev, sess); sess->sid =3D sid; =20 --=20 2.34.1