From nobody Fri Sep 25 04:44:23 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C72695A515B; Wed, 16 Sep 2026 15:40:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789573214; cv=none; b=pVMx/O7Znrk1lRQRaYylGVeSn/Lw905yJU84E9umialgzr2G7QdTUG35hm1unM8OqNgt7OfctIH3+REwRluZxHfgxcqT9KHejZB0LUEJPcgWt9KcZw+9pakqg+DTTVPHzAMp7VZsdPWMJba5GUE9J+z0XBL6f5htIQ3U3u7iNAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789573214; c=relaxed/simple; bh=ajxFiZpYkVZZ1p1cu+BfzKIJnT1NN7NLrqI/pZyyxa8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SsSG6Y6sgvVl5LIW3ib59vfYAB/eBJufzk4JGvocoaN2B8ciKJrbgd8t34bwwEdZXIXRyopNkXsQpYlPIyJvR7rH6FuA/nnz1+ZLyq8iwzEXboaLmnu8lan48Ttt5EMG5tqIZ0mQvNc7e1XJEJNv8i/+27pySX0NX4flySu0RVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=FM77KUzo; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="FM77KUzo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=+j NVvA23hlsp7KGNObjrBr9Zcw4R6+mc3dMMlXbSnIk=; b=FM77KUzoz/q8V8sDF2 +TE+4kpAcuHGX25nB6VwCaL9r0/gLitmPWkUsAEn3cHc5ySfNe0ZPvtU7g+IZpyt X3l/7hzIOmnykzRKvfG4p6xtFTM10cLLbb/YjiB/2NCOdAqeMGiA5xyMqt7P8n2g qtkhm0ytoTGC7EhNcm3uvdkC4= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnbxQduKpqGzAlBA--.54876S3; Wed, 16 Sep 2026 23:39:11 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de, mani@kernel.org, yue.wang@Amlogic.com Cc: pali@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v9 1/3] PCI: Match the hierarchy's MPS to a device's MPSS as necessary Date: Wed, 16 Sep 2026 23:39:05 +0800 Message-Id: <20260916153907.60344-2-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260916153907.60344-1-18255117159@163.com> References: <20260916153907.60344-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnbxQduKpqGzAlBA--.54876S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxXr4fJFyxJrWfWF45tF17trb_yoWrJw43pa sxWFWS9r4kGryfJa1av3W8uas8Jrs3ZayrAay3J340va1aqFW5tr9Yyr4ftw1xGrWxXFy3 JF4Dt34UC3Z8uaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piGNtfUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxB96HmqquB9tlQAA3g Content-Type: text/plain; charset="utf-8" pci_configure_mps() enumerates top-down and programs each device's Maximum Payload Size (MPS) to match its upstream bridge. When a device's MPS Supported (MPSS) is too small to match, commit 9f0e89359775 ("PCI: Match Root Port's MPS to endpoint's MPSS as necessary") reduces the upstream bridge instead, but only when that bridge is a Root Port. That covers an endpoint directly below a Root Port and nothing else. With a Switch in between, the Switch ports have already inherited the Root Port's larger MPS, the reduction is skipped because the upstream bridge is a Switch Downstream Port, and pcie_set_mps() then fails with -EINVAL for the endpoint. The endpoint is left at 128 bytes below a port programmed for more, so any larger TLP it receives is treated as Malformed. Multi-function devices hit the same hole from the other direction: reducing the Root Port for a function with a small MPSS leaves the sibling functions already programmed to the larger value. Walk the hierarchy from the Root Port down and reduce every device that is above the new value. Reducing only the ports between the device and the Root Port is not sufficient, because a Switch may not fragment or repackage TLPs: an already programmed sibling left at the larger MPS could emit a TLP too large for its egress port. This only affects PCIE_BUS_DEFAULT. PCIE_BUS_SAFE already converges the hierarchy on the smallest MPSS in pcie_bus_configure_settings(), while PCIE_BUS_TUNE_OFF and PCIE_BUS_PEER2PEER return before this point. Fixes: 9f0e89359775 ("PCI: Match Root Port's MPS to endpoint's MPSS as nece= ssary") Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/probe.c | 38 ++++++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 27008e2ea5af..232bce2819f0 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2200,9 +2200,28 @@ int pci_setup_device(struct pci_dev *dev) return 0; } =20 +static int pcie_reduce_mps(struct pci_dev *dev, void *data) +{ + int mps =3D *(int *)data; + int ret; + + /* MPS is of type 'RsvdP' for VFs */ + if (!pci_is_pcie(dev) || dev->is_virtfn) + return 0; + + if (pcie_get_mps(dev) > mps) { + ret =3D pcie_set_mps(dev, mps); + if (ret) + dev_warn(&dev->dev, "failed to set MPS\n"); + } + + return 0; +} + static void pci_configure_mps(struct pci_dev *dev) { struct pci_dev *bridge =3D pci_upstream_bridge(dev); + struct pci_dev *rp; int mps, mpss, p_mps, rc; =20 if (!pci_is_pcie(dev)) @@ -2252,10 +2271,21 @@ static void pci_configure_mps(struct pci_dev *dev) return; =20 mpss =3D 128 << dev->pcie_mpss; - if (mpss < p_mps && pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_ROOT_PORT) { - pcie_set_mps(bridge, mpss); - pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max= %d)\n", - mpss, p_mps, 128 << bridge->pcie_mpss); + rp =3D pcie_find_root_port(bridge); + if (mpss < p_mps && rp) { + /* + * dev cannot be programmed to the MPS already in use above + * it, so reduce the hierarchy to what dev supports. A Switch + * may not repackage TLPs, so reducing only the upstream + * bridge is not enough: every port up to the Root Port has to + * come down as well, and so do the devices already programmed + * below that Root Port, which would otherwise be left sending + * TLPs too large for their egress port. + */ + pcie_reduce_mps(rp, &mpss); + pci_walk_bus(rp->subordinate, pcie_reduce_mps, &mpss); + pci_info(dev, "Max Payload Size of %s hierarchy set to %d (was %d)\n", + pci_name(rp), mpss, p_mps); p_mps =3D pcie_get_mps(bridge); } =20 --=20 2.34.1 From nobody Fri Sep 25 04:44:23 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 457EA5AA673; Wed, 16 Sep 2026 15:40:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789573219; cv=none; b=kz3efg3ZdSQ5IsOlG5zSTaZlqvpbNvXYRk5vbVLIhc+xMOV0oOsow8ErXvw3pyMi+lIQLU1elFq9mbmN3/RGgjPcNju1uHZtqrNxR9WQOSmHZbdJSVgzLoFw0Ex3dvnKJxbeA0KyY4N0jUtFZD8E4zxvLfsPDKBmpxb9ClxDV0w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789573219; c=relaxed/simple; bh=9cNtCcBxaNM9ENDzMLMHnnKX7k7LHPcYLhmV6DXJm3Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=a4ma2wwwcSNS5D6n+8Pp7s9yUMSljuhEOIrD1NWqeER8+vA+XlHcDPdbF/ixv7902J9vrWs/5WsLl04edfEyCG0GzOEZQ4EBoxE3zHHz9M58CGYx50AoXYGZ4+rVqofcQ6qIu5fczEjFwxtsszW5A8MXXxMF9GWAWLt4HIWHQmQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=R4mSVdX0; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="R4mSVdX0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=tX XLyITMJT1yST+MFquna26ESmZnA30Nae1jXyWuEoU=; b=R4mSVdX04i829VBmYT cmXwOwWC7FEurPwMRCcJeY0lIReA6OQdYVbBFjfxBeKwNXP0pHKRfK+uFKw4qmlf tMVnF5VOgpVzljpaGoGx40wnuzRu0CmRZsTGDVEdLTDEuPuwhtOlNVPAgC53Bgbt C1DZTQj8Sl3frPxwHVVqYEhco= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnbxQduKpqGzAlBA--.54876S4; Wed, 16 Sep 2026 23:39:12 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de, mani@kernel.org, yue.wang@Amlogic.com Cc: pali@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com>, Mahesh Vaidya , Ricardo Pardini , Shawn Lin Subject: [PATCH v9 2/3] PCI: Configure Root Port MPS during host probing Date: Wed, 16 Sep 2026 23:39:06 +0800 Message-Id: <20260916153907.60344-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260916153907.60344-1-18255117159@163.com> References: <20260916153907.60344-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnbxQduKpqGzAlBA--.54876S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxJF4fJF15AF47uFWUuw4UArb_yoW5GrWkpa yUWanYyFs7GF4fZFsrZ3WFvFyYqF93Zry3GrZ3Z3s0van8Zr9rJrWaya95Jw1kGrZ7KFya vFn8try8u3ZIvFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEVyIbUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAB7H2qquCBtpwAA3y Content-Type: text/plain; charset="utf-8" Current PCIe initialization logic may leave Root Ports operating with non-optimal Maximum Payload Size (MPS) settings. The existing code in pci_configure_mps() returns early for devices without an upstream bridge which includes Root Ports, so their MPS values remain at firmware defaults. This fails to utilize the controller's full capabilities, leading to suboptimal data transfer efficiency across the PCIe hierarchy. With this patch, during the host controller probing phase: - When PCIe bus tuning is enabled (not PCIE_BUS_TUNE_OFF) and not PCIE_BUS_PEER2PEER (which requires the default 128 bytes for optimal peer-to-peer operation), and - The device is a Root Port, the Root Port's MPS is set to its maximum supported value. Note that this initial maximum MPS setting may be reduced later, during downstream device enumeration, if any downstream device does not support the Root Port's maximum MPS. This change ensures Root Ports are initialized to their maximum MPS before downstream devices negotiate MPS, while maintaining backward compatibility via the PCIE_BUS_TUNE_OFF check and not interfering with the PCIE_BUS_PEER2PEER strategy. Suggested-by: Niklas Cassel Suggested-by: Manivannan Sadhasivam Reviewed-by: Manivannan Sadhasivam Signed-off-by: Hans Zhang <18255117159@163.com> Tested-by: Mahesh Vaidya Tested-by: Ricardo Pardini # on Odroid-HC4 Tested-by: Shawn Lin --- drivers/pci/probe.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 232bce2819f0..08af75aa7366 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2248,6 +2248,21 @@ static void pci_configure_mps(struct pci_dev *dev) return; } =20 + /* + * Unless MPS strategy is PCIE_BUS_TUNE_OFF (don't touch MPS at all) or + * PCIE_BUS_PEER2PEER (use minimum MPS for peer-to-peer), set Root Ports' + * MPS to their maximum supported value. Depending on the MPS strategy + * and MPSS of downstream devices, a Root Port's MPS may be reduced + * later during device enumeration. + */ + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT && + pcie_bus_config !=3D PCIE_BUS_TUNE_OFF && + pcie_bus_config !=3D PCIE_BUS_PEER2PEER) { + rc =3D pcie_set_mps(dev, 128 << dev->pcie_mpss); + if (rc) + dev_warn(&dev->dev, "failed to set root port MPS\n"); + } + if (!bridge || !pci_is_pcie(bridge)) return; =20 --=20 2.34.1 From nobody Fri Sep 25 04:44:23 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B61385A5150; Wed, 16 Sep 2026 15:40:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789573214; cv=none; b=gbWNoYDXLNdJGxPjOhKwHvt+Ldpx1/IQcWYOw0yN7vTm03tLwjKO+52o2j+mi1Qbzixha19MpnsUFi3ddtk2cu+L1UvxsO5YVG4pTDphhniMBrHIn5CyL3Zr1wcNcDrLeROgT2lzzGcWE2Auh05cai4aSnqkulTxlsEdxGzx6gI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789573214; c=relaxed/simple; bh=nWCbNW76GnmrsYZomK9SKcYGm0Naeg21d78OvlYJd7A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IHW8AhtA+sayqHCtlkrPOjWVMPVu/C0vYH10m/TZpS9Ron2spoIkxOa1le+lw1x9qIf5Ih64grH/N28sD4EnMLT+NY0z4PNigGW/at35hsC6TWO3lyMKYiJRhqoM/4tSoDLv5k8btf/I39n2IIjP3zAH7J+QuKZNZ2NxQ3MiKSk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Iwjw8jhD; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Iwjw8jhD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=+C cYzq1fPBKkeFjAunrawbz06tsDi+w7l4bgn1rNWTU=; b=Iwjw8jhDmstaC72nRm WmlNYw2GD3Nnzb13EYpSEXZ5CL5Y5iow7+ve5z3uIgFAwybzkiE6G0y7kOMUgJr9 Wa9H1KnPSwrB+4gkX94+XfIeiAv3lRXLYFfDwpgFbXrnDKBRuhAiqJfqGQj5GeOn znutz6hKemPIM1Q2xikS210eg= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnbxQduKpqGzAlBA--.54876S5; Wed, 16 Sep 2026 23:39:13 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de, mani@kernel.org, yue.wang@Amlogic.com Cc: pali@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v9 3/3] PCI: dwc: Remove redundant MPS configuration Date: Wed, 16 Sep 2026 23:39:07 +0800 Message-Id: <20260916153907.60344-4-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260916153907.60344-1-18255117159@163.com> References: <20260916153907.60344-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnbxQduKpqGzAlBA--.54876S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxury8Kr15XF43Gw4ftrWkWFg_yoW5trWfpF y3WF4vkF4rJr45Wr4qkan5Ca13tFnxAr17Jr9rWw4Sv3ZIyFsrJa4akFWFk3yxXrWDWF9Y krn8Gr48Z3Wrtr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziBT5dUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6wF7H2qquCHiEAAA3l Content-Type: text/plain; charset="utf-8" The Meson PCIe controller driver manually configures maximum payload size (MPS) through meson_set_max_payload, duplicating functionality now centralized in the PCI core. Deprecating redundant code simplifies the driver and aligns it with the consolidated MPS management strategy, improving long-term maintainability. With meson_set_max_payload() gone, meson_size_to_payload() is only used for MRRS. Rename it to meson_size_to_mrrs(), update the warning message, and drop the now-unused PCIE_CAP_MAX_PAYLOAD_SIZE and MAX_PAYLOAD_SIZE macros. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-meson.c | 25 +++---------------------- 1 file changed, 3 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controlle= r/dwc/pci-meson.c index 8559d132dcde..1d3687566dda 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -21,7 +21,6 @@ =20 #define to_meson_pcie(x) dev_get_drvdata((x)->dev) =20 -#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) #define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) =20 /* PCIe specific config registers */ @@ -37,7 +36,6 @@ #define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1) =20 #define PORT_CLK_RATE 100000000UL -#define MAX_PAYLOAD_SIZE 256 #define MAX_READ_REQ_SIZE 256 #define PCIE_RESET_DELAY 500 #define PCIE_SHARED_RESET 1 @@ -256,7 +254,7 @@ static void meson_pcie_ltssm_enable(struct meson_pcie *= mp) meson_cfg_writel(mp, val, PCIE_CFG0); } =20 -static int meson_size_to_payload(struct meson_pcie *mp, int size) +static int meson_size_to_mrrs(struct meson_pcie *mp, int size) { struct device *dev =3D mp->pci.dev; =20 @@ -266,35 +264,19 @@ static int meson_size_to_payload(struct meson_pcie *m= p, int size) * than 2^12, just set to default size 2^(1+7). */ if (!is_power_of_2(size) || size < 128 || size > 4096) { - dev_warn(dev, "payload size %d, set to default 256\n", size); + dev_warn(dev, "MRRS %d, set to default 256\n", size); return 1; } =20 return fls(size) - 8; } =20 -static void meson_set_max_payload(struct meson_pcie *mp, int size) -{ - struct dw_pcie *pci =3D &mp->pci; - u32 val; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - int max_payload_size =3D meson_size_to_payload(mp, size); - - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val &=3D ~PCI_EXP_DEVCTL_PAYLOAD; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); - - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val |=3D PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); -} - static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) { struct dw_pcie *pci =3D &mp->pci; u32 val; u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - int max_rd_req_size =3D meson_size_to_payload(mp, size); + int max_rd_req_size =3D meson_size_to_mrrs(mp, size); =20 val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); val &=3D ~PCI_EXP_DEVCTL_READRQ; @@ -363,7 +345,6 @@ static int meson_pcie_host_init(struct dw_pcie_rp *pp) =20 pp->bridge->ops =3D &meson_pci_ops; =20 - meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); =20 return 0; --=20 2.34.1