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charset="utf-8" QCS8300 and SA8775p PCIe PHYs require dedicated vdda-refgen and refgen LDO supplies for QREF to provide a stable reference clock. Without these supplies, the PCIe PHYs cannot work properly. Mark them as required for the affected compatibles even though it breaks ABI. vdda-refgen-supply is required for all three QCS8300 and SA8775p PHY compatibles. refgen-supply is required for QCS8300 only, as a workaround for a hardware issue where QREF actually depends on refgen3 rather than refgen2 as documented, so the PHY driver votes for refgen3 directly via this supply. Signed-off-by: Ziyue Zhang Reviewed-by: Krzysztof Kozlowski --- .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index b353b7bfb839..bd4c98784142 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -94,6 +94,11 @@ properties: =20 vdda-qref-supply: true =20 + vdda-refgen-supply: true + + # Only required on platforms where the hardware voting doesn't work prop= erly + refgen-supply: true + qcom,4ln-config-sel: description: PCIe 4-lane configuration $ref: /schemas/types.yaml#/definitions/phandle-array @@ -269,6 +274,28 @@ allOf: "#clock-cells": const: 0 =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x4-pcie-phy + then: + required: + - vdda-refgen-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-qmp-gen4x2-pcie-phy + then: + required: + - refgen-supply + examples: - | #include --=20 2.43.0 From nobody Fri Sep 25 05:30:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17F3B4CCDF8; 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charset="utf-8" Add a new sa8775p_qmp_phy_vreg_l that includes vdda-phy, vdda-pll, vdda-qref, vdda-refgen and refgen supplies, and use it for QCS8300 and SA8775p PCIe PHY configurations. This avoids modifying sm8550_qmp_phy_vreg_l and breaking SM8550 and SM8650. These supplies were missing from the original driver, which was found to be the root cause of occasional system crashes observed on QCS8300 and SA8775p platforms. Without voting for these supplies, the PCIe PHY lacks stable reference clock and voltage, so the PHY never becomes ready and initialization times out: [ 7.303119] qcom-qmp-pcie-phy 1c04000.phy: phy initialization timed-out [ 7.309948] phy phy-1c04000.phy.0: phy poweron failed --> -110 Note that due to a hardware issue, QREF actually depends on refgen3 rather than refgen2 as documented; refgen3 is therefore voted manually via the refgen supply as a workaround. Fixes: a05b6d5135ec ("phy: qcom-qmp-pcie: add support for sa8775p") Fixes: ebf198f17b5a ("phy: qcom-qmp-pcie: add dual lane PHY support for QCS= 8300") Signed-off-by: Ziyue Zhang --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index da83358c97ea..ab81c6e584a8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4094,6 +4094,10 @@ static const char * const sm8550_qmp_phy_vreg_l[] = =3D { "vdda-phy", "vdda-pll", "vdda-qref", }; =20 +static const char * const sa8775p_qmp_phy_vreg_l[] =3D { + "vdda-phy", "vdda-pll", "vdda-qref", "vdda-refgen", "refgen", +}; + /* list of resets */ static const char * const ipq8074_pciephy_reset_l[] =3D { "phy", "common", @@ -4585,8 +4589,8 @@ static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pc= iephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sa8775p_qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sa8775p_qmp_phy_vreg_l), .regs =3D pciephy_v5_regs_layout, =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, @@ -5324,8 +5328,8 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pc= iephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sa8775p_qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sa8775p_qmp_phy_vreg_l), .regs =3D pciephy_v5_regs_layout, =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, @@ -5365,8 +5369,8 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pc= iephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sa8775p_qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sa8775p_qmp_phy_vreg_l), .regs =3D pciephy_v5_regs_layout, =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, --=20 2.43.0 From nobody Fri Sep 25 05:30:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 189014D0A04; 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charset="utf-8" The QMP PCIe PHYs on QCS8300 require dedicated qref and refgen voltage supplies for stable operation. Without these supplies, the system may occasionally crash. Add vdda-qref-supply and vdda-refgen-supply in the board files (QCS8300-RIDE, Monaco-EVK and Monaco-Monza-SoM), and add refgen-supply in the SoC DTSI (monaco.dtsi) since refgen is an on-chip regulator shared across boards. The PHY driver votes for refgen3 directly as a workaround for a hardware issue where QREF actually depends on refgen3 rather than refgen2 as documented. Fixes: 33967eadb215 ("arm64: dts: qcom: qcs8300-ride: enable pcie0 interfac= e") Fixes: cdb613a84527 ("arm64: dts: qcom: qcs8300-ride: enable pcie1 interfac= e") Fixes: 41e2424651f7 ("arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.= ") Fixes: 5238f4e7169f ("arm64: dts: qcom: Add Monaco Monza SoM") Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 4 ++++ arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/monaco.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/= qcom/monaco-evk.dts index 9d17ef7d2caf..c1f63a4ee243 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -623,6 +623,8 @@ &pcie0 { &pcie0_phy { vdda-phy-supply =3D <&vreg_l6a>; vdda-pll-supply =3D <&vreg_l5a>; + vdda-qref-supply =3D <&vreg_l4a>; + vdda-refgen-supply =3D <&vreg_l7a>; =20 status =3D "okay"; }; @@ -637,6 +639,8 @@ &pcie1 { &pcie1_phy { vdda-phy-supply =3D <&vreg_l6a>; vdda-pll-supply =3D <&vreg_l5a>; + vdda-qref-supply =3D <&vreg_l4a>; + vdda-refgen-supply =3D <&vreg_l7a>; =20 status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/bo= ot/dts/qcom/monaco-monza-som.dtsi index 36af1ad2105d..b1b3a7773bbe 100644 --- a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi @@ -211,6 +211,8 @@ &pcie0 { &pcie0_phy { vdda-phy-supply =3D <&vreg_l6a>; vdda-pll-supply =3D <&vreg_l5a>; + vdda-qref-supply =3D <&vreg_l4a>; + vdda-refgen-supply =3D <&vreg_l7a>; =20 status =3D "okay"; }; @@ -223,6 +225,8 @@ &pcie1 { &pcie1_phy { vdda-phy-supply =3D <&vreg_l6a>; vdda-pll-supply =3D <&vreg_l5a>; + vdda-qref-supply =3D <&vreg_l4a>; + vdda-refgen-supply =3D <&vreg_l7a>; =20 status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index cfe39f923224..a8e5f7abf686 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2433,6 +2433,8 @@ pcie0_phy: phy@1c04000 { =20 #phy-cells =3D <0>; =20 + refgen-supply =3D <&refgen>; + status =3D "disabled"; }; =20 @@ -2624,6 +2626,8 @@ pcie1_phy: phy@1c14000 { =20 #phy-cells =3D <0>; =20 + refgen-supply =3D <&refgen>; + status =3D "disabled"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index 1ff39530ea3d..c7b36feca4ac 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -638,6 +638,8 @@ wifi@0 { &pcie0_phy { vdda-phy-supply =3D <&vreg_l6a>; vdda-pll-supply =3D <&vreg_l5a>; + vdda-qref-supply =3D <&vreg_l4a>; + vdda-refgen-supply =3D <&vreg_l7a>; =20 status =3D "okay"; }; @@ -657,6 +659,8 @@ &pcieport1 { &pcie1_phy { vdda-phy-supply =3D <&vreg_l6a>; vdda-pll-supply =3D <&vreg_l5a>; + vdda-qref-supply =3D <&vreg_l4a>; + vdda-refgen-supply =3D <&vreg_l7a>; =20 status =3D "okay"; }; --=20 2.43.0 From nobody Fri Sep 25 05:30:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2D23485CDA; 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charset="utf-8" The QMP PCIe PHYs on SA8775p require dedicated qref and refgen voltage supplies for stable operation. Without these supplies, the system may occasionally crash. Add vdda-qref-supply and vdda-refgen-supply in the board files (Lemans-EVK and Lemans-RIDE). Fixes: 94d7d37f6ac3 ("arm64: dts: qcom: lemans-evk: Enable PCIe support") Fixes: 76326da895b8 ("arm64: dts: qcom: lemans: Refactor ride/ride-r3 board= s based on daughter cards") Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 4 ++++ arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/= qcom/lemans-evk.dts index a45485b54a5b..11fb11b161fc 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -851,6 +851,8 @@ &pcie0 { &pcie0_phy { vdda-phy-supply =3D <&vreg_l5a>; vdda-pll-supply =3D <&vreg_l1c>; + vdda-qref-supply =3D <&vreg_l4a>; + vdda-refgen-supply =3D <&vreg_l7a>; =20 status =3D "okay"; }; @@ -868,6 +870,8 @@ &pcie1 { &pcie1_phy { vdda-phy-supply =3D <&vreg_l5a>; vdda-pll-supply =3D <&vreg_l1c>; + vdda-qref-supply =3D <&vreg_l4a>; + vdda-refgen-supply =3D <&vreg_l7a>; =20 status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/= boot/dts/qcom/lemans-ride-common.dtsi index 144f117ba511..c312fbd6ac48 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -983,6 +983,8 @@ &pcie1 { &pcie0_phy { vdda-phy-supply =3D <&vreg_l5a>; vdda-pll-supply =3D <&vreg_l1c>; + vdda-qref-supply =3D <&vreg_l4a>; + vdda-refgen-supply =3D <&vreg_l7a>; =20 status =3D "okay"; }; @@ -990,6 +992,8 @@ &pcie0_phy { &pcie1_phy { vdda-phy-supply =3D <&vreg_l5a>; vdda-pll-supply =3D <&vreg_l1c>; + vdda-qref-supply =3D <&vreg_l4a>; + vdda-refgen-supply =3D <&vreg_l7a>; =20 status =3D "okay"; }; --=20 2.43.0