From nobody Fri Sep 25 06:01:07 2026 Received: from mx1.white.stw.pengutronix.de (mx1.white.stw.pengutronix.de [185.203.200.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 549C044AB90; Wed, 16 Sep 2026 09:01:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.200.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789549293; cv=none; b=chOXh28ZOPHgjEyrfOpcJjpNVGabd1lq/BfBOZSrnSnRkt2C+Z62DwpFfEGvW1ktsK2zaPD2jhRVxec6ythfaltoFHRb20h9PiCisqORqbp6wxFQF15UAMqqOwGOS5hkS0wJkWuzfpB741EZsLh1vQDqtDoaQp4v3jAUyNgv6lQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789549293; c=relaxed/simple; bh=91wbg/bu2gtyMOvzzNBAgNWwZMHv8M2P9CRKkGct2lA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Svx5qk+EE1zofiTI+hQC6jGLWgQiJTU4kEBc4cm3lvmtwKnZy3pb6J7pQg1SZH/vTLDSk9xQiG/XKQnX6gdj3PsH+t2y5dh/sriY9ofgn/m2UAHR1n/johHiUl4SPlJpPOBG2kVbwKTL5TWt4uQV4xGG26UYcQHAnPJuhmGU9m4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.200.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de X-PTX-Original-Recipient: andrew@lunn.ch X-PTX-Original-Recipient: luizluca@gmail.com X-PTX-Original-Recipient: olteanv@gmail.com X-PTX-Original-Recipient: davem@davemloft.net X-PTX-Original-Recipient: edumazet@google.com X-PTX-Original-Recipient: linusw@kernel.org X-PTX-Original-Recipient: kuba@kernel.org X-PTX-Original-Recipient: pabeni@redhat.com X-PTX-Original-Recipient: o.rempel@pengutronix.de X-PTX-Original-Recipient: kernel@pengutronix.de X-PTX-Original-Recipient: a.fatoum@pengutronix.de X-PTX-Original-Recipient: alvin.sipraga@analog.com X-PTX-Original-Recipient: linux-kernel@vger.kernel.org X-PTX-Original-Recipient: netdev@vger.kernel.org Received: from drehscheibe.grey.stw.pengutronix.de (drehscheibe.grey.stw.pengutronix.de [IPv6:2a0a:edc0:0:c01:1d::a2]) (Authenticated sender: relay-from-drehscheibe.grey.stw.pengutronix.de) by mx1.white.stw.pengutronix.de (Postfix) with ESMTPSA id A2A43201F41; Wed, 16 Sep 2026 11:01:03 +0200 (CEST) Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac] helo=dude04) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1x6lVn-001CpY-1b; Wed, 16 Sep 2026 11:01:03 +0200 Received: from ore by dude04 with local (Exim 4.98.2) (envelope-from ) id 1x6lVn-00000001SqV-1lRk; Wed, 16 Sep 2026 11:01:03 +0200 From: Oleksij Rempel To: Linus Walleij , Luiz Angelo Daros de Luca , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, Ahmad Fatoum , =?UTF-8?q?Alvin=20=C5=A0ipraga?= , netdev@vger.kernel.org Subject: [PATCH net-next v3 1/3] net: phy: realtek: use C45 for RTL8365MB-VC internal PHY MMD access Date: Wed, 16 Sep 2026 11:01:00 +0200 Message-ID: <20260916090102.349157-2-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260916090102.349157-1-o.rempel@pengutronix.de> References: <20260916090102.349157-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RTL8365MB-VC PHYs are integrated into the switch and have no MMD registers of their own. What phylib accesses as MMD registers (EEE) actually lives in the switch's OCP registers; the realtek DSA driver maps those MMD requests onto OCP and exposes them over C45. For a C22 PHY, phy_read_mmd()/phy_write_mmd() would use C22 indirect-MMD, which this hardware does not implement. Point .read_mmd/.write_mmd at genphy_{read,write}_mmd_c45() so phylib's MMD accesses go over C45 to the DSA driver's mapping instead. Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn Reviewed-by: Linus Walleij Reviewed-by: Luiz Angelo Daros de Luca --- Anticipated reviewer questions: Q: .read_mmd/.write_mmd now use the C45 helpers, but the DSA user MDIO bus only gains .read_c45/.write_c45 in the next patch -- is this bisect-brok= en? A: No. Until then an MMD access returns -EOPNOTSUPP, but the only one that = runs is the EEE-ability read in phy_probe(), which phylib ignores; probe, lin= k and traffic are unaffected. ethtool --show-eee reports EEE unsupported here = -- the same as before this series, since these ports gain EEE only in the next = patch -- so it is not a regression. Verified on an RTL8365MB-VC. --- drivers/net/phy/realtek/realtek_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realt= ek/realtek_main.c index 97b0b67b9900..b55691681df6 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -3338,6 +3338,8 @@ static struct phy_driver realtek_drvs[] =3D { }, { PHY_ID_MATCH_EXACT(0x001cc942), .name =3D "RTL8365MB-VC Gigabit Ethernet", + .read_mmd =3D genphy_read_mmd_c45, + .write_mmd =3D genphy_write_mmd_c45, /* Interrupt handling analogous to RTL8366RB */ .config_intr =3D genphy_no_config_intr, .handle_interrupt =3D genphy_handle_interrupt_no_ack, --=20 2.47.3 From nobody Fri Sep 25 06:01:07 2026 Received: from mx1.white.stw.pengutronix.de (mx1.white.stw.pengutronix.de [185.203.200.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67DB6479877; Wed, 16 Sep 2026 09:01:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.200.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789549292; cv=none; b=eU1QCoo8twrpkVnwFv8IOe+pRxY+zkB2m0TIH1YvttWZkF3/q1ptrm9cwf9d0Y5oz54ZHfrZs55WG2eOj86/V0P2W3s223kgR7C3YYHWLd4aZ1aV7i487s84vk6PHAdQTwc4p1/3t50OX4kktyoeXtfnwNOhWIy9eGVr+eN1vd0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789549292; c=relaxed/simple; bh=Lh2YpoweQWTV782T1aSpLLm143KnrvMJcpmoWZTmQ8M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jEFwJjF5rW1Wpl12oe/mt5jgb7/dnXJtcLzu+kYp6e8T4juAaNicTWA1ZpOGMInjlgDTBAbPMIbjfcQMHA/1KSNMiuwfxLLLLs7gqx5017Z92d5Z8s835KiHzFPn7EVq6qRkKnPFUaEgDUiKCMGGf+BQFqsDXenF1DW5OGJLi6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.200.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de X-PTX-Original-Recipient: andrew@lunn.ch X-PTX-Original-Recipient: luizluca@gmail.com X-PTX-Original-Recipient: olteanv@gmail.com X-PTX-Original-Recipient: davem@davemloft.net X-PTX-Original-Recipient: edumazet@google.com X-PTX-Original-Recipient: linusw@kernel.org X-PTX-Original-Recipient: kuba@kernel.org X-PTX-Original-Recipient: pabeni@redhat.com X-PTX-Original-Recipient: o.rempel@pengutronix.de X-PTX-Original-Recipient: kernel@pengutronix.de X-PTX-Original-Recipient: a.fatoum@pengutronix.de X-PTX-Original-Recipient: alvin.sipraga@analog.com X-PTX-Original-Recipient: linux-kernel@vger.kernel.org X-PTX-Original-Recipient: netdev@vger.kernel.org Received: from drehscheibe.grey.stw.pengutronix.de (drehscheibe.grey.stw.pengutronix.de [IPv6:2a0a:edc0:0:c01:1d::a2]) (Authenticated sender: relay-from-drehscheibe.grey.stw.pengutronix.de) by mx1.white.stw.pengutronix.de (Postfix) with ESMTPSA id 9B696201E6B; Wed, 16 Sep 2026 11:01:03 +0200 (CEST) Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac] helo=dude04) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1x6lVn-001CpZ-1f; Wed, 16 Sep 2026 11:01:03 +0200 Received: from ore by dude04 with local (Exim 4.98.2) (envelope-from ) id 1x6lVn-00000001Sqg-1r0W; Wed, 16 Sep 2026 11:01:03 +0200 From: Oleksij Rempel To: Linus Walleij , Luiz Angelo Daros de Luca , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, Ahmad Fatoum , =?UTF-8?q?Alvin=20=C5=A0ipraga?= , netdev@vger.kernel.org Subject: [PATCH net-next v3 2/3] net: dsa: realtek: rtl8365mb: extract PHY OCP address halves with FIELD_GET Date: Wed, 16 Sep 2026 11:01:01 +0200 Message-ID: <20260916090102.349157-3-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260916090102.349157-1-o.rempel@pengutronix.de> References: <20260916090102.349157-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extract the two OCP address halves with FIELD_GET() before handing them to FIELD_PREP() to build the ADDRESS register value. rtl8365mb_phy_ocp_prepare() previously fed FIELD_PREP() the raw ocp_addr >> 1 and >> 6. FIELD_PREP() masks the value to the field at run time, so that was correct for the current callers, which all pass a run-time register address. FIELD_PREP()'s compile-time width check only fires for a compile-time constant value. None reached it here: the address is computed as PHYREG_BASE + regnum * 2 from a run-time regnum. The EEE support that follows adds callers with constant OCP addresses (0xa5c4 etc.); clang folds those into the inlined ocp_prepare(), so the shifted constant now reaches the check, overflows the 5-/4-bit field and breaks the build (gcc does not fold it here). FIELD_GET() narrows each half to the field width first, so the value already fits. No functional change. Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn Reviewed-by: Linus Walleij --- New in v3, fixing the clang FIELD_PREP build failure Jakub Kicinski reported against v2. --- drivers/net/dsa/realtek/rtl8365mb_main.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/rea= ltek/rtl8365mb_main.c index f8220d832e46..efde1f3b604e 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -199,6 +199,14 @@ #define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 #define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 =20 +/* The full 16-bit OCP address is split across two registers: bits [15:10]= are + * the prefix (RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK above), and bits [9:1] g= o into + * the ADDRESS register as two fields, [5:1] and [9:6]. Bit 0 is always 0 = - PHY + * OCP registers are 2-byte aligned. + */ +#define RTL8365MB_PHY_OCP_ADDR_5_1_MASK GENMASK(5, 1) +#define RTL8365MB_PHY_OCP_ADDR_9_6_MASK GENMASK(9, 6) + /* The PHY OCP addresses of PHY registers 0~31 start here */ #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 =20 @@ -871,6 +879,8 @@ static int rtl8365mb_phy_poll_busy(struct realtek_priv = *priv) static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, u32 ocp_addr) { + u16 ocp_addr_lo =3D FIELD_GET(RTL8365MB_PHY_OCP_ADDR_5_1_MASK, ocp_addr); + u16 ocp_addr_hi =3D FIELD_GET(RTL8365MB_PHY_OCP_ADDR_9_6_MASK, ocp_addr); u32 val; int ret; =20 @@ -887,9 +897,9 @@ static int rtl8365mb_phy_ocp_prepare(struct realtek_pri= v *priv, int phy, val =3D RTL8365MB_PHY_BASE; val |=3D FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); val |=3D FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, - ocp_addr >> 1); + ocp_addr_lo); val |=3D FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, - ocp_addr >> 6); + ocp_addr_hi); ret =3D regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val); if (ret) --=20 2.47.3 From nobody Fri Sep 25 06:01:07 2026 Received: from mx1.white.stw.pengutronix.de (mx1.white.stw.pengutronix.de [185.203.200.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F79348AE3D; Wed, 16 Sep 2026 09:01:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.200.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789549292; cv=none; b=kawf4TECvFePVIrJwM18/2OAwUQKK36M3RR02S10U5OnqOkfXVazyUT8I73eZePcXY55BRmfbO5TYrNnA2TO3kG4naY+Q3S3txBf7Km35/r18QFzwzKBeonrrUYXIrvfV77aSPosFlc8n+3BMaVa6NqBuek1MBtE6fBAty8JwqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789549292; c=relaxed/simple; bh=DRAX781RyTKWlFTdM4voST0NRvZCZSHk5jRbzQn01sw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k/WhXNd456sWGcLYC/LSV/7Gnd+1L3GP3/CkUYTMgvVDP5/PTChq+8ZghP4UwPWl+zbl9OG2PSoVDZ0w+eRmq9gxXRSBLop9XdarA6wJX9RDcyLGd6rc+D81uuu0d1o6yDUWn60TqASOyQC1k4lOENLQD8J3TaimIPilDnylT/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.200.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de X-PTX-Original-Recipient: andrew@lunn.ch X-PTX-Original-Recipient: luizluca@gmail.com X-PTX-Original-Recipient: olteanv@gmail.com X-PTX-Original-Recipient: davem@davemloft.net X-PTX-Original-Recipient: edumazet@google.com X-PTX-Original-Recipient: linusw@kernel.org X-PTX-Original-Recipient: kuba@kernel.org X-PTX-Original-Recipient: pabeni@redhat.com X-PTX-Original-Recipient: o.rempel@pengutronix.de X-PTX-Original-Recipient: kernel@pengutronix.de X-PTX-Original-Recipient: a.fatoum@pengutronix.de X-PTX-Original-Recipient: alvin.sipraga@analog.com X-PTX-Original-Recipient: linux-kernel@vger.kernel.org X-PTX-Original-Recipient: netdev@vger.kernel.org Received: from drehscheibe.grey.stw.pengutronix.de (drehscheibe.grey.stw.pengutronix.de [IPv6:2a0a:edc0:0:c01:1d::a2]) (Authenticated sender: relay-from-drehscheibe.grey.stw.pengutronix.de) by mx1.white.stw.pengutronix.de (Postfix) with ESMTPSA id A77FD201F42; Wed, 16 Sep 2026 11:01:03 +0200 (CEST) Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac] helo=dude04) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1x6lVn-001Cpa-1p; Wed, 16 Sep 2026 11:01:03 +0200 Received: from ore by dude04 with local (Exim 4.98.2) (envelope-from ) id 1x6lVn-00000001Sqq-1wp6; Wed, 16 Sep 2026 11:01:03 +0200 From: Oleksij Rempel To: Linus Walleij , Luiz Angelo Daros de Luca , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, Ahmad Fatoum , =?UTF-8?q?Alvin=20=C5=A0ipraga?= , netdev@vger.kernel.org Subject: [PATCH net-next v3 3/3] net: dsa: realtek: rtl8365mb: add EEE support Date: Wed, 16 Sep 2026 11:01:02 +0200 Message-ID: <20260916090102.349157-4-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260916090102.349157-1-o.rempel@pengutronix.de> References: <20260916090102.349157-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add EEE support on the integrated-PHY ports, controllable per port via ethtool. The integrated PHYs have no MMD registers; their EEE registers live in the switch's OCP space. phylib accesses EEE as MMD registers, so add phy_{read,write}_c45 realtek_ops that map those MMD accesses onto their OCP addresses, wired as the user MII bus C45 handlers when the chip provides them (rtl8366rb etc. unaffected). The hardware manages LPI on its own, so advertise EEE to phylink with no-op mac_{en,dis}able_tx_lpi callbacks. The LPI timer is a single global per-speed register, so .set_mac_eee rejects the per-port TX LPI knobs rather than silently ignoring them. Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn Reviewed-by: Linus Walleij Reviewed-by: Luiz Angelo Daros de Luca --- Changes since v2: - The clang FIELD_PREP build error reported on v2 (Jakub Kicinski) is now fixed by the preceding patch ("net: dsa: realtek: rtl8365mb: extract PHY OCP address halves with FIELD_GET"); this patch itself is unchanged. Changes since v1: - .set_mac_eee: return -EOPNOTSUPP instead of -EINVAL for the rejected TX LPI cases -- the hardware cannot support them, it is not an invalid configuration (Andrew Lunn). --- drivers/net/dsa/realtek/realtek.h | 4 + drivers/net/dsa/realtek/rtl8365mb_main.c | 123 +++++++++++++++++++++++ drivers/net/dsa/realtek/rtl83xx.c | 20 ++++ 3 files changed, 147 insertions(+) diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/re= altek.h index 75a127545e5d..1c0ca6daf545 100644 --- a/drivers/net/dsa/realtek/realtek.h +++ b/drivers/net/dsa/realtek/realtek.h @@ -156,6 +156,10 @@ struct realtek_ops { int (*phy_read)(struct realtek_priv *priv, int phy, int regnum); int (*phy_write)(struct realtek_priv *priv, int phy, int regnum, u16 val); + int (*phy_read_c45)(struct realtek_priv *priv, int phy, int devad, + int regnum); + int (*phy_write_c45)(struct realtek_priv *priv, int phy, int devad, + int regnum, u16 val); }; =20 struct realtek_variant { diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/rea= ltek/rtl8365mb_main.c index efde1f3b604e..87ec924a0611 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -101,6 +101,7 @@ #include #include #include +#include #include =20 #include "realtek.h" @@ -210,6 +211,10 @@ /* The PHY OCP addresses of PHY registers 0~31 start here */ #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 =20 +#define RTL8365MB_PHY_OCP_ADDR_EEE_ABLE 0xA5C4 +#define RTL8365MB_PHY_OCP_ADDR_EEE_ADV 0xA5D0 +#define RTL8365MB_PHY_OCP_ADDR_EEE_LPABLE 0xA5D2 + /* External interface port mode values - used in DIGITAL_INTERFACE_SELECT = */ #define RTL8365MB_EXT_PORT_MODE_DISABLE 0 #define RTL8365MB_EXT_PORT_MODE_RGMII 1 @@ -1050,6 +1055,66 @@ static int rtl8365mb_phy_write(struct realtek_priv *= priv, int phy, int regnum, return 0; } =20 +static int rtl8365mb_phy_read_c45(struct realtek_priv *priv, int phy, int = devad, + int regnum) +{ + u32 ocp_addr; + u16 val; + int ret; + + if (phy > RTL8365MB_PHYADDRMAX) + return -EINVAL; + + if (devad =3D=3D MDIO_MMD_PCS && regnum =3D=3D MDIO_PCS_EEE_ABLE) + ocp_addr =3D RTL8365MB_PHY_OCP_ADDR_EEE_ABLE; + else if (devad =3D=3D MDIO_MMD_AN && regnum =3D=3D MDIO_AN_EEE_ADV) + ocp_addr =3D RTL8365MB_PHY_OCP_ADDR_EEE_ADV; + else if (devad =3D=3D MDIO_MMD_AN && regnum =3D=3D MDIO_AN_EEE_LPABLE) + ocp_addr =3D RTL8365MB_PHY_OCP_ADDR_EEE_LPABLE; + else + /* Only the EEE registers are mapped; others read as 0, as the + * hardware does, so the generic MMD code is not tripped up by + * an error. + */ + return 0; + + ret =3D rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); + if (ret) { + dev_err(priv->dev, + "failed to read PHY%d OCP %04x, ret %d\n", phy, ocp_addr, + ret); + return ret; + } + + return val; +} + +static int rtl8365mb_phy_write_c45(struct realtek_priv *priv, int phy, + int devad, int regnum, u16 val) +{ + int ret; + + if (phy > RTL8365MB_PHYADDRMAX) + return -EINVAL; + + /* Only the EEE advertisement register is writable; writes to other + * registers are ignored, as the hardware does. + */ + if (devad !=3D MDIO_MMD_AN || regnum !=3D MDIO_AN_EEE_ADV) + return 0; + + ret =3D rtl8365mb_phy_ocp_write(priv, phy, RTL8365MB_PHY_OCP_ADDR_EEE_ADV, + val); + if (ret) { + dev_err(priv->dev, + "failed to write PHY%d OCP %04x, ret %d\n", phy, + RTL8365MB_PHY_OCP_ADDR_EEE_ADV, ret); + return ret; + } + + return 0; +} + static const struct rtl8365mb_extint * rtl8365mb_get_port_extint(struct realtek_priv *priv, int port) { @@ -1649,6 +1714,14 @@ static void rtl8365mb_phylink_get_caps(struct dsa_sw= itch *ds, int port, */ __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); + + /* Integrated PHYs support EEE at 100M/1G; the hardware manages + * LPI on its own, so just advertise LPI awareness to phylink. + */ + memcpy(config->lpi_interfaces, config->supported_interfaces, + sizeof(config->lpi_interfaces)); + config->lpi_capabilities =3D MAC_100FD | MAC_1000FD; + config->eee_enabled_default =3D true; return; } =20 @@ -3285,18 +3358,66 @@ static int rtl8365mb_detect(struct realtek_priv *pr= iv) return 0; } =20 +static int rtl8365mb_phylink_mac_enable_tx_lpi(struct phylink_config *conf= ig, + u32 timer, bool tx_clock_stop) +{ + /* The hardware manages LPI itself; there is no MAC-level LPI control. + * This callback only signals LPI awareness to phylink. + */ + return 0; +} + +static void rtl8365mb_phylink_mac_disable_tx_lpi(struct phylink_config *co= nfig) +{ +} + static const struct phylink_mac_ops rtl8365mb_phylink_mac_ops =3D { .mac_select_pcs =3D rtl8365mb_phylink_mac_select_pcs, .mac_config =3D rtl8365mb_phylink_mac_config, .mac_link_down =3D rtl8365mb_phylink_mac_link_down, .mac_link_up =3D rtl8365mb_phylink_mac_link_up, + .mac_enable_tx_lpi =3D rtl8365mb_phylink_mac_enable_tx_lpi, + .mac_disable_tx_lpi =3D rtl8365mb_phylink_mac_disable_tx_lpi, }; =20 +static bool rtl8365mb_support_eee(struct dsa_switch *ds, int port) +{ + /* Only integrated-PHY ports support EEE, not the external RGMII ports. */ + return !rtl8365mb_get_port_extint(ds->priv, port); +} + +static int rtl8365mb_set_mac_eee(struct dsa_switch *ds, int port, + struct ethtool_keee *e) +{ + struct realtek_priv *priv =3D ds->priv; + + /* The only LPI timing control (tx_lpi_timer) is a single global + * per-speed register shared by all ports, so it cannot be set from this + * per-port callback; leave it at its reset default. Per-port EEE is + * driven through the PHY advertisement. Reject the per-port TX LPI knobs + * rather than silently ignoring them. + */ + if (!e->tx_lpi_enabled) { + dev_err(priv->dev, "disabling EEE TX LPI is not supported\n"); + return -EOPNOTSUPP; + } + + if (e->tx_lpi_timer) { + dev_err(priv->dev, + "setting the EEE TX LPI timer is not supported\n"); + return -EOPNOTSUPP; + } + + return 0; +} + static const struct dsa_switch_ops rtl8365mb_switch_ops =3D { .get_tag_protocol =3D rtl8365mb_get_tag_protocol, .change_tag_protocol =3D rtl8365mb_change_tag_protocol, .setup =3D rtl8365mb_setup, .teardown =3D rtl8365mb_teardown, + .support_eee =3D rtl8365mb_support_eee, + .set_mac_eee =3D rtl8365mb_set_mac_eee, .phylink_get_caps =3D rtl8365mb_phylink_get_caps, .port_bridge_join =3D rtl83xx_port_bridge_join, .port_bridge_leave =3D rtl83xx_port_bridge_leave, @@ -3342,6 +3463,8 @@ static const struct realtek_ops rtl8365mb_ops =3D { .l2_flush =3D rtl8365mb_l2_flush, .phy_read =3D rtl8365mb_phy_read, .phy_write =3D rtl8365mb_phy_write, + .phy_read_c45 =3D rtl8365mb_phy_read_c45, + .phy_write_c45 =3D rtl8365mb_phy_write_c45, }; =20 static const char *const rtl8365mb_supplies[] =3D { diff --git a/drivers/net/dsa/realtek/rtl83xx.c b/drivers/net/dsa/realtek/rt= l83xx.c index 8121ec12fd8b..ad42c05d0a88 100644 --- a/drivers/net/dsa/realtek/rtl83xx.c +++ b/drivers/net/dsa/realtek/rtl83xx.c @@ -62,6 +62,22 @@ static int rtl83xx_user_mdio_write(struct mii_bus *bus, = int addr, int regnum, return priv->ops->phy_write(priv, addr, regnum, val); } =20 +static int rtl83xx_user_mdio_read_c45(struct mii_bus *bus, int addr, int d= evad, + int regnum) +{ + struct realtek_priv *priv =3D bus->priv; + + return priv->ops->phy_read_c45(priv, addr, devad, regnum); +} + +static int rtl83xx_user_mdio_write_c45(struct mii_bus *bus, int addr, int = devad, + int regnum, u16 val) +{ + struct realtek_priv *priv =3D bus->priv; + + return priv->ops->phy_write_c45(priv, addr, devad, regnum, val); +} + /** * rtl83xx_setup_user_mdio() - register the user mii bus driver * @ds: DSA switch associated with this user_mii_bus @@ -95,6 +111,10 @@ int rtl83xx_setup_user_mdio(struct dsa_switch *ds) bus->name =3D "Realtek user MII"; bus->read =3D rtl83xx_user_mdio_read; bus->write =3D rtl83xx_user_mdio_write; + if (priv->ops->phy_read_c45) + bus->read_c45 =3D rtl83xx_user_mdio_read_c45; + if (priv->ops->phy_write_c45) + bus->write_c45 =3D rtl83xx_user_mdio_write_c45; snprintf(bus->id, MII_BUS_ID_SIZE, "%s:user_mii", dev_name(priv->dev)); bus->parent =3D priv->dev; =20 --=20 2.47.3