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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN1PEPF00004686.mail.protection.outlook.com (10.167.243.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.428.7 via Frontend Transport; Wed, 16 Sep 2026 05:10:52 +0000 Received: from ausmlimonci-lx1.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Wed, 16 Sep 2026 00:10:50 -0500 From: Mario Limonciello To: Bjorn Helgaas CC: "open list:PCI SUBSYSTEM" , open list , "Rafael J . Wysocki" , Lukas Wunner , , "Mario Limonciello (AMD)" , Eric Naim Subject: [PATCH v4 1/2] PCI/PM: Split out code from pci_pm_suspend_noirq() into helper Date: Wed, 16 Sep 2026 00:10:33 -0500 Message-ID: <20260916051034.180226-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260916051034.180226-1-mario.limonciello@amd.com> References: <20260916051034.180226-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004686:EE_|SA3PR12MB8810:EE_ X-MS-Office365-Filtering-Correlation-Id: b754feb9-0aba-44c2-785b-08df13b0e10d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|82310400026|1800799024|36860700016|18002099003|10067099003|56012099006|11063799006|22082099003; X-Microsoft-Antispam-Message-Info: VC9KgA25nJ+QnVWNdRNOIeFWLHXi+2m2t9K5+2kiOct+SgxMULYGqiTmnb5gJHu6P9qp5CWgROeXVAClrzyDNln/r7zb84WlVLTCQFs/wn5Ut80N5Zr2YLasdcbg4OzXjgzSEJAV2ZcwomHT2g3MW7wP/4YnTvU/5UcPnpYfD5itvn08ZeVRBhEZLuI8wBVQxUUuW7LmXuoGLz4wMC1IaN5VdvBeQd/N3bC6bOCrAXI7adf9f4rmoYWx1AMHJyzGSfzoAFGZFTjRXqqHiaZD97g+QM5cKK5lISpzDjg10/emYeADNAHfU2OWSJWXnfIlZm+mHHboUz8Evoqc/JQftAsFADjDMkXGhxZF2JjJa6DkepH249UsmtrtCZa6l2762gAJl5AwHwlh+tsaMOIM77fol1nQvKKWJqL0DU6F5rCrztxM3VBFLY8iSY3M/jtP6uFRWIIJrGOdYP/kFesMDTIgALcNIJ6nsb5MZePHJDnhGl+AcnYdMqIRevX7S5NVcMGJGBp/qkDUjckuHJS2fwPuPvKFsy9lPefOgTKcucl7QHV6I+KLFKrOXUsjFsdVzedm/OZwTfCZHX34BCKzbSCa9rVXmL16/7kX3HhnAa5gy38/tTbMG8RLyPItJ3mnQ8WbbvlpTGxxB7Hv+ROq3xhm7oezt9+cFtOL69xTORCIG8J0WqFO4S95Sv5SQAlfFgp76mlHqHDDwR3Ct3j4eQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(23010399003)(82310400026)(1800799024)(36860700016)(18002099003)(10067099003)(56012099006)(11063799006)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 80wAB/dsUlifzyRvg//5E/g0DkL08q8Zlpc/knVcqLxnneLRvuD3F0wcCUIN1TN9+ZgN+xJB9+7SXmcOpJp3mBYnK6by6NJZZ9KsPBRT3B93TU1F2zwh4Yn6PRje2TCZDQPUfnQSTubnNHKFr+SvJvwJabAuhy6SnrS+1kwLs192YYofdkfdniRVNkXoAfp+Q85nZUOAmjVC6HmOaJZTAfe0SUn04DPh2Bf5C81Ku4obD0LreKzO+Ab8K08PZTgQA6AESOJOJwneiIO8nqyHk+Rm4fgElnZN+rgzK/7gN2pxdsrcVOTOuYqnwTAIlqe4AaQ5uLSsag4dawSpxDOgulsQ1t6FJdJEq6TPNwzmihJMffGZHwFyHJeLDnU/Fjmp5LSqtXebpghAmZXv4maCIMgZs+U3a+MMEow2QSC9w/AoJEL8nA1WIL9PQ/uqo3vl X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2026 05:10:52.0389 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b754feb9-0aba-44c2-785b-08df13b0e10d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004686.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8810 Content-Type: text/plain; charset="utf-8" From: "Mario Limonciello (AMD)" In order to unify suspend and hibernate codepaths without code duplication the common code should be in common helpers. Move it from pci_pm_suspend_noirq() into a helper. No intended functional changes. Tested-by: Eric Naim Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Rafael J. Wysocki (Intel) --- v4: * Make pci_pm_suspend_noirq_common() bool instead (Rafael) --- drivers/pci/pci-driver.c | 77 +++++++++++++++++++++++++--------------- 1 file changed, 49 insertions(+), 28 deletions(-) diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index e16aa59dd7ac8..8334214f8c1ed 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -818,6 +818,52 @@ static void pci_pm_complete(struct device *dev) =20 #endif /* !CONFIG_PM_SLEEP */ =20 +#if defined(CONFIG_SUSPEND) +/** + * pci_pm_suspend_noirq_common - prepare a device to enter a low-power sta= te + * @pci_dev: pci device + * + * Save the device state and decide whether bus-level power management sho= uld + * skipped. Returns true if bus-level power management should be skipped, + * false otherwise. + */ +static bool pci_pm_suspend_noirq_common(struct pci_dev *pci_dev) +{ + if (!pci_dev->state_saved) { + pci_save_state(pci_dev); + + /* + * If the device is a bridge with a child in D0 below it, + * it needs to stay in D0, so check skip_bus_pm to avoid + * putting it into a low-power state in that case. + */ + if (!pci_dev->skip_bus_pm && pci_power_manageable(pci_dev)) + pci_prepare_to_sleep(pci_dev); + } + + pci_dbg(pci_dev, "PCI PM: Sleep power state: %s\n", + pci_power_name(pci_dev->current_state)); + + if (pci_dev->current_state =3D=3D PCI_D0) { + pci_dev->skip_bus_pm =3D true; + /* + * Per PCI PM r1.2, table 6-1, a bridge must be in D0 if any + * downstream device is in D0, so avoid changing the power state + * of the parent bridge by setting the skip_bus_pm flag for it. + */ + if (pci_dev->bus->self) + pci_dev->bus->self->skip_bus_pm =3D true; + } + + if (pci_dev->skip_bus_pm && pm_suspend_no_platform()) { + pci_dbg(pci_dev, "PCI PM: Skipped\n"); + return true; + } + + return false; +} +#endif /* CONFIG_SUSPEND */ + #ifdef CONFIG_SUSPEND static void pcie_pme_root_status_cleanup(struct pci_dev *pci_dev) { @@ -907,6 +953,7 @@ static int pci_pm_suspend_noirq(struct device *dev) { struct pci_dev *pci_dev =3D to_pci_dev(dev); const struct dev_pm_ops *pm =3D dev->driver ? dev->driver->pm : NULL; + bool skip_bus_pm; =20 if (dev_pm_skip_suspend(dev)) return 0; @@ -937,36 +984,10 @@ static int pci_pm_suspend_noirq(struct device *dev) } } =20 - if (!pci_dev->state_saved) { - pci_save_state(pci_dev); - - /* - * If the device is a bridge with a child in D0 below it, - * it needs to stay in D0, so check skip_bus_pm to avoid - * putting it into a low-power state in that case. - */ - if (!pci_dev->skip_bus_pm && pci_power_manageable(pci_dev)) - pci_prepare_to_sleep(pci_dev); - } + skip_bus_pm =3D pci_pm_suspend_noirq_common(pci_dev); =20 - pci_dbg(pci_dev, "PCI PM: Suspend power state: %s\n", - pci_power_name(pci_dev->current_state)); - - if (pci_dev->current_state =3D=3D PCI_D0) { - pci_dev->skip_bus_pm =3D true; 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Wed, 16 Sep 2026 05:10:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN1PEPF0000467F.mail.protection.outlook.com (10.167.243.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.428.7 via Frontend Transport; Wed, 16 Sep 2026 05:10:53 +0000 Received: from ausmlimonci-lx1.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Wed, 16 Sep 2026 00:10:51 -0500 From: Mario Limonciello To: Bjorn Helgaas CC: "open list:PCI SUBSYSTEM" , open list , "Rafael J . Wysocki" , Lukas Wunner , , "Mario Limonciello (AMD)" , AceLan Kao , Kai-Heng Feng , Mark Pearson , Denis Benato , =?UTF-8?q?Merthan=20Karaka=C5=9F?= , Eric Naim Subject: [PATCH v4 2/2] PCI: Put PCIe bridges with downstream devices into D3 at hibernate Date: Wed, 16 Sep 2026 00:10:34 -0500 Message-ID: <20260916051034.180226-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260916051034.180226-1-mario.limonciello@amd.com> References: <20260916051034.180226-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|BN7PPFCE25C719B:EE_ X-MS-Office365-Filtering-Correlation-Id: fca6917d-91b0-4347-af9c-08df13b0e1aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|82310400026|36860700016|376014|23010399003|3023799007|10067099003|18002099003|11063799006|56012099006|22082099003; X-Microsoft-Antispam-Message-Info: nwY+DXn0GqZlsX83B6VMNE/bFcL0eARYWQEJq/bR/uchdRAYlM0RkHaQGKpeuQ1l9L+SRV54WmeCjpv2XmoLH1B2vT3jxxanaIcgi4vDWGTvdmuASCXMEalHjnwyvvkvNJMQQDq++zAXqzylOowzZkdWSraJGE76DBmjBSux+fbVuT/aBXfIijgD6ShTn9G92xVJZdA+sQlJLKf4V3vSXjTqkriZj2hTjUfl6pLrRq4ghmy6sRMy6a64zho5Xjt/hVz5QWGJezBKJy4Fi8Y7NBuU8KXbfU3ygiDRzguWdm22nmqnyO09XwuK64fCZoSQlrPyZWFIY6dDnkJ8M9MjdIGiWFq9BSZDOj58vJFqqiFUzunaWdm7vpI83DhWcFwYIgKmwZhfw3GCnOUW3V7eGO78Kr6MP9nKJN05EGJnE0OSKDubyT29caMV0ebBCaAJxBDudMrrFI0t3grLNE+THgpcmoqjjpl39u7xzZ95mS/GXu6/HG8QqmacpDuboIWWOTPP3ylVcvakBbn9WpBXwAT/db8H6X6R9Oj3VK0e3RC1E+kVgXGe8MtHTy/Q04LrZr0fOTuxBOTQ30+Lr4l0amcoFgg9stGxvQyA/h4YUqf9eR6fcue5kAQVXA5o0KXkzdBeN8FsSY1IpiL3skcxI4RRqQTfRdjDgPE9Pjri10tQWPAKztiEsrjYTYrBQgQkj8OwmxXTU1axqvCqOg5VBw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(82310400026)(36860700016)(376014)(23010399003)(3023799007)(10067099003)(18002099003)(11063799006)(56012099006)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uvbSOo+zpUMq9z1dwWyeJI1vcWsWJ2P0jMyTJqq2jt77ZHtu5E1cPxVt2vQrpXk2traZ9mNle49HHQ41ETSCpymEwpYvS6EGJpFrdBuY/b5MNHxUEWOlTGzaQdfvbhfz3VF30I1KJdVWoYOwosHRlWSzdtx4hcC12o9OpHhGm+Iv8xlIHD+KyXti0PbeGvGqi0uYbCGFqnSR6dLVABWxnt8lWYy0RZu3a8pohdLMUg8JjpES027CefQVWWEgrCb5tWW893jJqFTATj7sW1E2z26D2vgOP35mq1afPxjNixFKhs0KsMd4Fea5/lENrHmZcNLYz8dermsE8hz7jb10HpunMyYHO7AB3JOweUqWEQ1CvXzEt66AzAWRGXTPlFCYuI6qrDLmYCo3SoNrAfukT+N0pt+6zVQjShNY+IZH0ox1DxJ8bmwYFk7kU4VpwUFn X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2026 05:10:53.0737 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fca6917d-91b0-4347-af9c-08df13b0e1aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPFCE25C719B From: "Mario Limonciello (AMD)" During S3 suspend, pci_pm_suspend_noirq() puts PCIe bridges with downstream devices into a low-power state (D3hot or D3cold) when the platform allows it. The hibernate poweroff_noirq path never did this: it only called pci_prepare_to_sleep() for devices with no subordinate, so bridges with active children were left in D0. The platform firmware leaves bridges alone when the system enters S4. This prevents being able to meet various energy certification criteria for different parts of the world, particularly in designs with a dGPU. Align the hibernate flow with suspend by making pci_pm_poweroff_noirq() use pci_pm_suspend_noirq_common() instead of the open-coded pci_prepare_to_sleep() call. This reuses exactly the logic the S3 suspend path uses, including the skip_bus_pm handling that keeps a bridge in D0 when a downstream device must stay in D0 (e.g. a configured wakeup source) and the pm_suspend_no_platform() bus-PM skip. No restore-side change is needed: the hibernation image is snapshotted during the freeze phase, before poweroff_noirq runs, so the powered-down bridge state is never part of the image, and resuming from it goes through a full boot that re-enumerates and retrains the PCIe links. Because the poweroff_noirq path now mirrors the already-shipping suspend_noirq path and is guarded identically, bridges that must remain in D0 are unaffected; only bridges that S3 suspend would have powered down are now also powered down at hibernate. Cc: AceLan Kao Cc: Kai-Heng Feng Cc: Mark Pearson Cc: Denis Benato Cc: Merthan Karaka=C5=9F Tested-by: Eric Naim Signed-off-by: Mario Limonciello (AMD) Acked-by: Rafael J. Wysocki (Intel) --- drivers/pci/pci-driver.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 8334214f8c1ed..3f80c8e6e0e52 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -818,7 +818,7 @@ static void pci_pm_complete(struct device *dev) =20 #endif /* !CONFIG_PM_SLEEP */ =20 -#if defined(CONFIG_SUSPEND) +#if defined(CONFIG_SUSPEND) || defined(CONFIG_HIBERNATE_CALLBACKS) /** * pci_pm_suspend_noirq_common - prepare a device to enter a low-power sta= te * @pci_dev: pci device @@ -862,7 +862,7 @@ static bool pci_pm_suspend_noirq_common(struct pci_dev = *pci_dev) =20 return false; } -#endif /* CONFIG_SUSPEND */ +#endif /* CONFIG_SUSPEND || CONFIG_HIBERNATE_CALLBACKS */ =20 #ifdef CONFIG_SUSPEND static void pcie_pme_root_status_cleanup(struct pci_dev *pci_dev) @@ -1217,6 +1217,8 @@ static int pci_pm_poweroff(struct device *dev) struct pci_dev *pci_dev =3D to_pci_dev(dev); const struct dev_pm_ops *pm =3D dev->driver ? dev->driver->pm : NULL; =20 + pci_dev->skip_bus_pm =3D false; + if (pci_has_legacy_pm_support(pci_dev)) return pci_legacy_suspend(dev, PMSG_HIBERNATE); =20 @@ -1259,6 +1261,7 @@ static int pci_pm_poweroff_noirq(struct device *dev) { struct pci_dev *pci_dev =3D to_pci_dev(dev); const struct dev_pm_ops *pm =3D dev->driver ? dev->driver->pm : NULL; + bool skip_bus_pm; =20 if (dev_pm_skip_suspend(dev)) return 0; @@ -1280,8 +1283,9 @@ static int pci_pm_poweroff_noirq(struct device *dev) return error; } =20 - if (!pci_dev->state_saved && !pci_has_subordinate(pci_dev)) - pci_prepare_to_sleep(pci_dev); + skip_bus_pm =3D pci_pm_suspend_noirq_common(pci_dev); + if (skip_bus_pm) + goto Fixup; =20 /* * The reason for doing this here is the same as for the analogous code @@ -1290,6 +1294,7 @@ static int pci_pm_poweroff_noirq(struct device *dev) if (pci_dev->class =3D=3D PCI_CLASS_SERIAL_USB_EHCI) pci_write_config_word(pci_dev, PCI_COMMAND, 0); =20 +Fixup: pci_fixup_device(pci_fixup_suspend_late, pci_dev); =20 return 0; --=20 2.43.0