From nobody Fri Sep 25 05:30:16 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D138D4F055A for ; Wed, 16 Sep 2026 13:58:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789567117; cv=none; b=coVjvAg1NwCZMh9WChowLoX+HgGejPvGjE43FCSWu1nwtL//IpGCLwgyH7nEudObP8sus2Q+klj8nfTW0oBKUAQDSlegmVVuMOiaNNUEcnekkOjmsV4b0ZAdv0yvSz0b5G92c1XArR5H6slS+AX3F30eprA50NYGi8U3pzYBN4g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789567117; c=relaxed/simple; bh=zf+IMIf7sXYnu6i7H7mWWyuhTK/3Fhb0KGmCf5FwydE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Rt4Z2ZIss+iYrs/UPEEEZRQp+jEQzK0OoIcLstpsG3yaZ1R7Jm21Qqr2SAiKE4/Af3IUsaaEA1zg7/w1WRwiNLNW7tg6f6yDSZ78nhKZjbDAEFNUd8b/trjW0iElrwZ/80E0Lp6ARr6IwhAaQkvxYmoa1TndvOpRUOm3lOaPG4w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lCJJ80gU; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lCJJ80gU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789567116; x=1821103116; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=zf+IMIf7sXYnu6i7H7mWWyuhTK/3Fhb0KGmCf5FwydE=; b=lCJJ80gUzvbMEVdGprv2tit86X+Vpb/F2CNxVsp61ydrLF6772o2sPBK DMN+Jp0eHKCexyogm6pZa/1lAqH5LNfVy7zqu7uyma3gyIw0gjxbbsUKS 3yhHd2NQ2cvGA1BVn3qLPHap+ZIQs30IxyWleZOTgS5zmNmPpYIzW00/n JyXyL3O22ILh91JdrJ/8d3JG4m++bVlncakVtgsOhXz2iIlLjAs9hMTxL 7r6KN/SZ82bTF7ZgAo41Ls8j9A8l5bjvZNso4px53oESCdZQB5UXKNXiH F21tTHmLuhmgZ+1q3lfAvloin6SeHBCSJul9NGxripYTCuhRvpIX4ZwsY Q==; X-CSE-ConnectionGUID: GzKVe097S/ydNkvEgNVm5Q== X-CSE-MsgGUID: C4USklBlQwG0SVZcGjATAA== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="89881937" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="89881937" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 06:58:35 -0700 X-CSE-ConnectionGUID: +MRWrjlwQMWkscvNqcf/CQ== X-CSE-MsgGUID: 8pIh7MFxTmesWxLyrE4F6A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="277475759" Received: from sannilnx-dsk.jer.intel.com (HELO [127.0.1.1]) ([10.12.231.107]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 06:58:33 -0700 From: Alexander Usyskin Date: Wed, 16 Sep 2026 16:58:15 +0300 Subject: [PATCH v2 1/2] mtd: mtd_intel_dg: add survivability partition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260916-cri_surviv-v2-1-7de1b5328204@intel.com> References: <20260916-cri_surviv-v2-0-7de1b5328204@intel.com> In-Reply-To: <20260916-cri_surviv-v2-0-7de1b5328204@intel.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Rodrigo Vivi , David Airlie , Simona Vetter Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Menachem Adin , Alexander Usyskin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789567108; l=4298; i=alexander.usyskin@intel.com; s=20260315; h=from:subject:message-id; bh=zf+IMIf7sXYnu6i7H7mWWyuhTK/3Fhb0KGmCf5FwydE=; b=Dm7dnBuV8dMzawqzo1DyqzzVvvcc73k0O8f+2VKpiBBd2WGJrfU2RCjaR11yW1EMuupcxErrH fUCK5IJQkUXCczkEWt63a8zefQxyMdaRVGGeucH5qCpb2TnFKOeidLy X-Developer-Key: i=alexander.usyskin@intel.com; a=ed25519; pk=X+qoF/nFCdDOV04IForWSxnkyoCAbUE10egZi6PSfcU= Add option to expose additional fixed-sized partition starting from the beginning of storage. Xe driver can request this partition exposure if firmware or hardware have detected failure that may involve corrupted partition table. Fixed-sized partition allows full storage re-write in this situation. Signed-off-by: Alexander Usyskin --- drivers/mtd/devices/mtd_intel_dg.c | 66 +++++++++++++++++++++++++++++-----= ---- include/linux/intel_dg_nvm_aux.h | 1 + 2 files changed, 51 insertions(+), 16 deletions(-) diff --git a/drivers/mtd/devices/mtd_intel_dg.c b/drivers/mtd/devices/mtd_i= ntel_dg.c index a566e86eb5e3..962f30779c51 100644 --- a/drivers/mtd/devices/mtd_intel_dg.c +++ b/drivers/mtd/devices/mtd_intel_dg.c @@ -31,6 +31,7 @@ struct intel_dg_nvm { void __iomem *base; void __iomem *base2; bool non_posted_erase; + bool survivability_enabled; =20 size_t size; unsigned int nregions; @@ -430,6 +431,16 @@ static int intel_dg_nvm_init(struct intel_dg_nvm *nvm,= struct device *device, /* clean error register, previous errors are ignored */ idg_nvm_error(nvm); =20 + + if (nvm->survivability_enabled) { + nvm->size =3D nvm->regions[0].offset + nvm->regions[0].size - 1; + dev_dbg(device, "Registered survivability region %s size=3D%lld\n", + nvm->regions[0].name, + nvm->regions[0].size); + n =3D 1; + goto out; + } + ret =3D idg_nvm_is_valid(nvm); if (ret) { dev_err(device, "The MEM is not valid %d\n", ret); @@ -481,6 +492,7 @@ static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, = struct device *device, n++; } =20 +out: nvm->non_posted_erase =3D non_posted_erase; =20 dev_dbg(device, "Registered %d regions\n", n); @@ -753,15 +765,19 @@ static int intel_dg_mtd_probe(struct auxiliary_device= *aux_dev, =20 device =3D &aux_dev->dev; =20 - /* count available regions */ - for (nregions =3D 0, i =3D 0; i < INTEL_DG_NVM_REGIONS; i++) { - if (invm->regions[i].name) - nregions++; - } + if (invm->survivability_size) { + nregions =3D 1; + } else { + /* count available regions */ + for (nregions =3D 0, i =3D 0; i < INTEL_DG_NVM_REGIONS; i++) { + if (invm->regions[i].name) + nregions++; + } =20 - if (!nregions) { - dev_err(device, "no regions defined\n"); - return -ENODEV; + if (!nregions) { + dev_err(device, "no regions defined\n"); + return -ENODEV; + } } =20 nvm =3D kzalloc_flex(*nvm, regions, nregions); @@ -771,21 +787,39 @@ static int intel_dg_mtd_probe(struct auxiliary_device= *aux_dev, kref_init(&nvm->refcnt); mutex_init(&nvm->lock); nvm->nregions =3D nregions; + nvm->survivability_enabled =3D !!invm->survivability_size; =20 - for (n =3D 0, i =3D 0; i < INTEL_DG_NVM_REGIONS; i++) { - if (!invm->regions[i].name) - continue; - + if (invm->survivability_size) { /* survivability partition */ char *name =3D kasprintf(GFP_KERNEL, "%s.%s", - dev_name(&aux_dev->dev), invm->regions[i].name); + dev_name(&aux_dev->dev), "DATA"); if (!name) { ret =3D -ENOMEM; goto err_norpm; } =20 - nvm->regions[n].name =3D name; - nvm->regions[n].id =3D i; - n++; + nvm->regions[0].name =3D name; + nvm->regions[0].id =3D 0; + nvm->regions[0].offset =3D 0; + nvm->regions[0].size =3D invm->survivability_size; + nvm->regions[0].is_readable =3D true; + nvm->regions[0].is_writable =3D true; + n =3D 1; + } else { + for (n =3D 0, i =3D 0; i < INTEL_DG_NVM_REGIONS; i++) { + if (!invm->regions[i].name) + continue; + + char *name =3D kasprintf(GFP_KERNEL, "%s.%s", + dev_name(&aux_dev->dev), invm->regions[i].name); + if (!name) { + ret =3D -ENOMEM; + goto err_norpm; + } + + nvm->regions[n].name =3D name; + nvm->regions[n].id =3D i; + n++; + } } =20 ret =3D devm_pm_runtime_enable(device); diff --git a/include/linux/intel_dg_nvm_aux.h b/include/linux/intel_dg_nvm_= aux.h index 625d46a6b96e..84b5b6e0c4ea 100644 --- a/include/linux/intel_dg_nvm_aux.h +++ b/include/linux/intel_dg_nvm_aux.h @@ -21,6 +21,7 @@ struct intel_dg_nvm_dev { struct auxiliary_device aux_dev; bool writable_override; bool non_posted_erase; + size_t survivability_size; struct resource bar; struct resource bar2; const struct intel_dg_nvm_region *regions; --=20 2.53.0 From nobody Fri Sep 25 05:30:16 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B11C3412BF7 for ; Wed, 16 Sep 2026 13:58:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; 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16 Sep 2026 06:58:39 -0700 X-CSE-ConnectionGUID: y+1ySo3ATyiH3qc3EjZNlg== X-CSE-MsgGUID: /8tjTf7vQxSpqBxablUU0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="277475774" Received: from sannilnx-dsk.jer.intel.com (HELO [127.0.1.1]) ([10.12.231.107]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 06:58:36 -0700 From: Alexander Usyskin Date: Wed, 16 Sep 2026 16:58:16 +0300 Subject: [PATCH v2 2/2] drm/xe/nvm: define survivabilty partition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260916-cri_surviv-v2-2-7de1b5328204@intel.com> References: <20260916-cri_surviv-v2-0-7de1b5328204@intel.com> In-Reply-To: <20260916-cri_surviv-v2-0-7de1b5328204@intel.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Rodrigo Vivi , David Airlie , Simona Vetter Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Menachem Adin , Alexander Usyskin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789567108; l=2014; i=alexander.usyskin@intel.com; s=20260315; h=from:subject:message-id; bh=r6J6OMUuexc90xruyZevzc+hksoDZaaD+TsUNdnaTAg=; b=Am8KStxYAynVDvH7dT+OdnRw/Ic6z/7dUnqsjX3cp/VW5kJv55QASSXI+waec1DbMiJwR2w1g yfhsqlTE/qIAdqi8Y5Sh8/Wdv1VocbAeLjl7CKsBbvOIjv9FNnmWwWw X-Developer-Key: i=alexander.usyskin@intel.com; a=ed25519; pk=X+qoF/nFCdDOV04IForWSxnkyoCAbUE10egZi6PSfcU= Define 8M survivability partition for CRI when storage is open for write override. Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/xe_nvm.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c index 51a1a431ad85..783c3103a8a4 100644 --- a/drivers/gpu/drm/xe/xe_nvm.c +++ b/drivers/gpu/drm/xe/xe_nvm.c @@ -56,10 +56,11 @@ static bool xe_nvm_non_posted_erase(struct xe_device *x= e) } } =20 -static bool xe_nvm_writable_override(struct xe_device *xe) +static bool xe_nvm_writable_override(struct xe_device *xe, size_t *surviva= bility_size) { struct xe_mmio *mmio =3D xe_root_tile_mmio(xe); bool writable_override; + size_t s_size =3D 0; struct xe_reg reg; u32 test_bit, test_val; =20 @@ -68,6 +69,7 @@ static bool xe_nvm_writable_override(struct xe_device *xe) reg =3D PCODE_SCRATCH(0); test_bit =3D FDO_MODE; test_val =3D FDO_MODE; + s_size =3D SZ_8M; break; case XE_BATTLEMAGE: reg =3D HECI_FWSTS2(DG2_GSC_HECI2_BASE); @@ -91,12 +93,17 @@ static bool xe_nvm_writable_override(struct xe_device *= xe) break; default: drm_err(&xe->drm, "Unknown platform\n"); + *survivability_size =3D 0; return true; } =20 writable_override =3D (xe_mmio_read32(mmio, reg) & test_bit) =3D=3D test_= val; - if (writable_override) + if (writable_override) { drm_info(&xe->drm, "NVM access overridden by jumper\n"); + *survivability_size =3D s_size; + } else { + *survivability_size =3D 0; + } return writable_override; } =20 @@ -143,7 +150,7 @@ int xe_nvm_init(struct xe_device *xe) if (!nvm) return -ENOMEM; =20 - nvm->writable_override =3D xe_nvm_writable_override(xe); + nvm->writable_override =3D xe_nvm_writable_override(xe, &nvm->survivabili= ty_size); nvm->non_posted_erase =3D xe_nvm_non_posted_erase(xe); nvm->bar.parent =3D &pdev->resource[0]; nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; --=20 2.53.0