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Initialize the mutex before registering the backend. Fixes: 7ecb8ee5c93b ("iio: adc: adi-axi-adc: support digital interface cali= bration") Signed-off-by: Janani Sunil --- This patch is already queued in the IIO fixes-togreg branch as commit 040c2514b25b ("iio: adc: adi-axi-adc: Initialize state mutex"). --- drivers/iio/adc/adi-axi-adc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 589f03618ecf..fc7cc92b35f0 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -714,6 +714,10 @@ static int adi_axi_adc_probe(struct platform_device *p= dev) if (!st) return -ENOMEM; =20 + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); --=20 2.43.0 From nobody Fri Sep 25 05:30:00 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B21754EC664; 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Acked-by: Conor Dooley Signed-off-by: Janani Sunil --- .../devicetree/bindings/iio/adc/adi,ad7768.yaml | 270 +++++++++++++++++= ++++ MAINTAINERS | 7 + 2 files changed, 277 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7768.yaml new file mode 100644 index 000000000000..d8e489fa1f6f --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml @@ -0,0 +1,270 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7768.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD7768 and AD7768-4 ADC + +maintainers: + - Janani Sunil + +description: | + The AD7768 is an 8-channel, 24-bit simultaneous sampling ADC with config= urable + power and performance modes. The AD7768-4 is a 4-channel version. + + This binding covers SPI mode only (register access via SPI). Pin control= mode, + where configuration is set via hardware pins rather than SPI registers, = is not + supported. + + The io-backend represents the high-speed data output interface, consumin= g the + DOUTx data lines, DCLK (data clock), and DRDY (data ready) signals. + + Datasheet at: + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7768-ad7768-4.pdf + + HDL reference design: + https://github.com/analogdevicesinc/hdl/tree/main/projects/ad7768evb + +properties: + compatible: + enum: + - adi,ad7768 + - adi,ad7768-4 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + description: + Describes the type of master clock (MCLK) attached to the XTAL1 and + XTAL2/MCLK pins. A CMOS clock is supplied on the XTAL2/MCLK pin, a + crystal oscillator is connected between the XTAL1 and XTAL2 pins, an= d an + LVDS differential clock is supplied on the XTAL1/XTAL2 pin pair. CMO= S and + LVDS clocks must operate from 1.15 MHz to 34 MHz. Crystals must oper= ate + from 8 MHz to 34 MHz. + enum: + - mclk + - xtal + - lvds + + avdd1-supply: + description: + Analog supply. Its voltage is used to derive the supply-dependent VCM + output level, so it must be a regulator that can report its voltage. + + avss-supply: + description: + Negative analog supply. If omitted, AVSS is assumed to be at system + ground. + + avdd2-supply: true + + iovdd-supply: true + + ref1p-supply: true + + ref1n-supply: + description: + Negative reference input supply for REF1. If omitted, REF1- is assum= ed + to be connected to ground. + + ref2p-supply: true + + ref2n-supply: + description: + Negative reference input supply for REF2. If omitted, REF2- is assum= ed + to be connected to ground. + + reset-gpios: + maxItems: 1 + description: GPIO connected to the active-low RESET pin + + start-gpios: + maxItems: 1 + description: + GPIO connected to the START pin. An active-low pulse on this pin + synchronizes the device to other AD7768 devices. When not used, this + pin must be tied to a logic high level through a pull-up resistor. + When used, SYNC_OUT must be wired back to SYNC_IN on all devices in + the synchronization chain. + + sync-in-gpios: + maxItems: 1 + description: + GPIO connected to the SYNC_IN pin. Receives the synchronization pulse + generated on SYNC_OUT in response to a START pulse. Must be synchron= ous + to the MCLK clock domain. In multi-device or daisy-chained systems, + two successive synchronization pulses must be applied to guarantee a= ll + ADCs are synchronized. + + gpio-controller: true + + '#gpio-cells': + const: 2 + + adi,data-lines-number: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] + description: + Number of DOUTx lines used for the high-speed data output interface + (distinct from the SPI control interface). AD7768 supports 1, 2, or 8 + lines; AD7768-4 supports 1 or 4 lines. Defaults to the maximum number + of lines for the selected variant if omitted. + + regulators: + type: object + description: Container for the on-chip VCM regulator. + additionalProperties: false + + properties: + vcm-output: + type: object + description: + Buffered common-mode voltage output on the VCM pin. Use + regulator-always-on when no consumer node references this output. + Channel 0 must be present and enabled while VCM is used, since + putting channel 0 in standby disables the VCM output. + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + io-backends: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^channel@[0-7]$": + type: object + description: + Represents the external channels which are connected to the device. + AD7768 supports channels 0-7, AD7768-4 supports channels 0-3. + + properties: + reg: + minimum: 0 + maximum: 7 + description: The channel number + + adi,prechargebuf-pos-enable: + type: boolean + description: Enable positive input precharge buffer + + adi,prechargebuf-neg-enable: + type: boolean + description: Enable negative input precharge buffer + + adi,refbuf-pos-enable: + type: boolean + description: Enable positive reference buffer + + adi,refbuf-neg-enable: + type: boolean + description: Enable negative reference buffer + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - avdd1-supply + - avdd2-supply + - iovdd-supply + - ref1p-supply + - ref2p-supply + - io-backends + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + contains: + const: adi,ad7768-4 + then: + properties: + adi,data-lines-number: + enum: [1, 4] + patternProperties: + "^channel@[0-3]$": + properties: + reg: + maximum: 3 + "^channel@[4-7]$": false + else: + properties: + adi,data-lines-number: + enum: [1, 2, 8] + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad7768"; + reg =3D <0>; + spi-max-frequency =3D <1000000>; + + avdd1-supply =3D <&avdd1_regulator>; + avss-supply =3D <&avss_regulator>; + avdd2-supply =3D <&avdd2_regulator>; + iovdd-supply =3D <&iovdd_regulator>; + ref1p-supply =3D <&ref1p_regulator>; + ref1n-supply =3D <&ref1n_regulator>; + ref2p-supply =3D <&ref2p_regulator>; + ref2n-supply =3D <&ref2n_regulator>; + reset-gpios =3D <&gpio0 86 GPIO_ACTIVE_LOW>; + + clocks =3D <&ad7768_mclk>; + clock-names =3D "mclk"; + + adi,data-lines-number =3D <8>; + gpio-controller; + #gpio-cells =3D <2>; + + io-backends =3D <&iio_backend>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { + reg =3D <0>; + adi,prechargebuf-pos-enable; + adi,refbuf-pos-enable; + }; + + channel@1 { + reg =3D <1>; + adi,prechargebuf-pos-enable; + adi,prechargebuf-neg-enable; + adi,refbuf-pos-enable; + adi,refbuf-neg-enable; + }; + + channel@7 { + reg =3D <7>; + adi,prechargebuf-pos-enable; + adi,refbuf-pos-enable; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 3a19da74d00c..f05e7f4d364a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1657,6 +1657,13 @@ F: Documentation/devicetree/bindings/iio/adc/adi,ad7= 768-1.yaml F: drivers/iio/adc/ad7768-1.c F: include/dt-bindings/iio/adc/adi,ad7768-1.h =20 +ANALOG DEVICES INC AD7768 DRIVER +M: Janani Sunil +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml + ANALOG DEVICES INC AD7780 DRIVER M: Michael Hennerich M: Renato Lui Geh --=20 2.43.0 From nobody Fri Sep 25 05:30:00 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C62913A16B6; Wed, 16 Sep 2026 11:15:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; 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On input data paths, the backend handles CRC data generated by the frontend. On output data paths, the backend generates CRC data for the frontend to verify. Reviewed-by: David Lechner Reviewed-by: Andy Shevchenko Signed-off-by: Janani Sunil --- drivers/iio/industrialio-backend.c | 33 +++++++++++++++++++++++++++++++++ include/linux/iio/backend.h | 6 ++++++ 2 files changed, 39 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index f7a4be8ec320..fbf5c39d7655 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -886,6 +886,39 @@ int iio_backend_num_lanes_set(struct iio_backend *back= , unsigned int num_lanes) } EXPORT_SYMBOL_NS_GPL(iio_backend_num_lanes_set, "IIO_BACKEND"); =20 +/** + * iio_backend_crc_enable - Enable CRC handling + * @back: Backend device + * + * On input data paths, enable backend handling of CRC data generated by t= he + * frontend. On output data paths, enable the backend to generate CRC data= for + * the frontend to verify. + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_crc_enable(struct iio_backend *back) +{ + return iio_backend_op_call(back, crc_enable); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_crc_enable, "IIO_BACKEND"); + +/** + * iio_backend_crc_disable - Disable CRC handling + * @back: Backend device + * + * On input data paths, disable backend handling of CRC data generated by = the + * frontend. On output data paths, disable CRC generation by the backend. + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_crc_disable(struct iio_backend *back) +{ + return iio_backend_op_call(back, crc_disable); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_crc_disable, "IIO_BACKEND"); + /** * iio_backend_ddr_enable - Enable interface DDR (Double Data Rate) mode * @back: Backend device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index 3f95ed1fdf9e..9c16b695a602 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -133,6 +133,8 @@ enum iio_backend_capabilities { * @filter_type_set: Set filter type. * @interface_data_align: Perform the data alignment process. * @num_lanes_set: Set the number of lanes enabled. + * @crc_enable: Enable direction-specific CRC handling. + * @crc_disable: Disable direction-specific CRC handling. * @ddr_enable: Enable interface DDR (Double Data Rate) mode. * @ddr_disable: Disable interface DDR (Double Data Rate) mode. * @data_stream_enable: Enable data stream. @@ -189,6 +191,8 @@ struct iio_backend_ops { enum iio_backend_filter_type type); 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CRC provides data integrity verification for high-speed ADC data streams, ensuring reliable data transfer between the ADC frontend and backend processing systems. Reviewed-by: David Lechner Reviewed-by: Andy Shevchenko Signed-off-by: Janani Sunil --- drivers/iio/adc/adi-axi-adc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index fc7cc92b35f0..8b7c45d51dbe 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -47,6 +47,9 @@ #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) =20 #define ADI_AXI_ADC_REG_CNTRL_3 0x004c +/* Bit 8 is common to all AXI ADC cores; bits 7-0 are per-HDL-project. */ +#define ADI_AXI_ADC_CNTRL_3_CRC_EN_MASK BIT(8) + #define AXI_AD485X_CNTRL_3_OS_EN_MSK BIT(2) #define AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK GENMASK(1, 0) #define AXI_AD485X_PACKET_FORMAT_20BIT 0x0 @@ -596,6 +599,22 @@ static int axi_adc_reg_access(struct iio_backend *back= , unsigned int reg, return regmap_write(st->regmap, reg, writeval); } =20 +static int axi_adc_crc_enable(struct iio_backend *back) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); 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Wed, 16 Sep 2026 07:14:56 -0400 From: Janani Sunil Date: Wed, 16 Sep 2026 13:13:54 +0200 Subject: [PATCH v8 05/17] iio: adc: Add AD7768 and AD7768-4 core support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260916-ad7768-driver-v8-5-27aa24db5225@analog.com> References: <20260916-ad7768-driver-v8-0-27aa24db5225@analog.com> In-Reply-To: <20260916-ad7768-driver-v8-0-27aa24db5225@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , "David Lechner" , Andy Shevchenko , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle , Randy Dunlap CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil , Jonathan Cameron X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; 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Configure supplies, clock and reset, use a custom regmap bus for the SPI protocol, and parse the enabled channels and input buffer settings from devicetree. Connect the converter to an IIO backend for buffered capture with CRC, provide a fixed safe wideband sampling configuration and add runtime power management. Signed-off-by: Janani Sunil --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 14 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad7768.c | 1035 ++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 1051 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f05e7f4d364a..de91903b0b45 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1663,6 +1663,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml +F: drivers/iio/adc/ad7768.c =20 ANALOG DEVICES INC AD7780 DRIVER M: Michael Hennerich diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 415e519ad4eb..5164608fa418 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -431,6 +431,20 @@ config AD7766 To compile this driver as a module, choose M here: the module will be called ad7766. =20 +config AD7768 + tristate "Analog Devices AD7768/AD7768-4 ADC driver" + depends on SPI + depends on REGULATOR || COMPILE_TEST + select IIO_BUFFER + select IIO_BACKEND + select REGMAP + help + Say yes here to build support for Analog Devices AD7768 and AD7768-4 + SPI analog to digital converters. + + To compile this driver as a module, choose M here: the module will be + called ad7768. + config AD7768_1 tristate "Analog Devices AD7768-1 ADC driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index dcec0abb03b7..c84f1a5eeac0 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_AD7606_IFACE_SPI) +=3D ad7606_spi.o obj-$(CONFIG_AD7606) +=3D ad7606.o obj-$(CONFIG_AD7625) +=3D ad7625.o obj-$(CONFIG_AD7766) +=3D ad7766.o +obj-$(CONFIG_AD7768) +=3D ad7768.o obj-$(CONFIG_AD7768_1) +=3D ad7768-1.o obj-$(CONFIG_AD7779) +=3D ad7779.o obj-$(CONFIG_AD7780) +=3D ad7780.o diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c new file mode 100644 index 000000000000..2c5d0657edf9 --- /dev/null +++ b/drivers/iio/adc/ad7768.c @@ -0,0 +1,1035 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD7768 ADC driver + * + * Copyright 2018-2026 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define AD7768_REG_CH_STANDBY 0x00 + +#define AD7768_REG_CH_MODE(x) (0x01 + (x)) +#define AD7768_CH_MODE_FILTER_TYPE_MSK BIT(3) +#define AD7768_CH_MODE_FILTER_TYPE_WIDEBAND 0x0 +#define AD7768_CH_MODE_DEC_RATE_MSK GENMASK(2, 0) +#define AD7768_CH_MODE_DEC_RATE_64 0x1 + +#define AD7768_REG_CH_MODE_SEL 0x03 + +#define AD7768_REG_POWER_MODE 0x04 +#define AD7768_SLEEP_MODE_MSK BIT(7) +#define AD7768_POWER_MODE_POWER_MODE_MSK GENMASK(5, 4) +#define AD7768_POWER_MODE_POWER_MODE_FAST 0x3 +#define AD7768_POWER_MODE_LVDS_ENABLE BIT(3) +#define AD7768_POWER_MODE_MCLK_DIV_MSK GENMASK(1, 0) + +#define AD7768_REG_DATA_CONTROL 0x06 +#define AD7768_DATA_CONTROL_SPI_RESET_1 0x03 +#define AD7768_DATA_CONTROL_SPI_RESET_2 0x02 +#define AD7768_DATA_CONTROL_SPI_SYNC BIT(7) + +#define AD7768_REG_INTERFACE_CFG 0x07 +#define AD7768_INTERFACE_CFG_CRC_SELECT_MSK GENMASK(3, 2) +#define AD7768_INTERFACE_CFG_CRC_SELECT_4 0x1 +#define AD7768_INTERFACE_CFG_DCLK_DIV_MSK GENMASK(1, 0) +#define AD7768_INTERFACE_CFG_DCLK_DIV_8 0x0 +#define AD7768_INTERFACE_CFG_DCLK_DIV_4 0x1 +#define AD7768_INTERFACE_CFG_DCLK_DIV_2 0x2 +#define AD7768_INTERFACE_CFG_DCLK_DIV_1 0x3 + +#define AD7768_REG_REV_ID 0x0A +#define AD7768_REV_ID_VAL 0x06 + +#define AD7768_REG_GPIO_CONTROL 0x0E +#define AD7768_GPIO_UGPIO_ENABLE BIT(7) +#define AD7768_GPIO4_OUTPUT_ENABLE BIT(4) + +#define AD7768_REG_GPIO_WRITE 0x0F + +#define AD7768_REG_PRECHARGE_BUF1 0x11 +#define AD7768_REG_PRECHARGE_BUF2 0x12 +#define AD7768_PREBUF_POS_EN(ch) BIT((ch) * 2 + 0) +#define AD7768_PREBUF_NEG_EN(ch) BIT((ch) * 2 + 1) + +#define AD7768_REG_REFP_BUF 0x13 +#define AD7768_REG_REFN_BUF 0x14 + +#define AD7768_REG_OFFSET_BASE 0x1E +#define AD7768_REG_GAIN_BASE 0x36 +#define AD7768_REG_PHASE_BASE 0x4E +#define AD7768_REG_OFFSET(ch) (AD7768_REG_OFFSET_BASE + 3 * (ch)) +#define AD7768_REG_GAIN(ch) (AD7768_REG_GAIN_BASE + 3 * (ch)) +#define AD7768_REG_PHASE(ch) (AD7768_REG_PHASE_BASE + (ch)) + +#define AD7768_REG_DIAGNOSTIC_RX 0x56 + +#define AD7768_REG_CHOP_CTRL 0x59 + +#define AD7768_SPI_READ_CMD BIT(15) +#define AD7768_SPI_REG_MASK GENMASK(14, 8) +#define AD7768_SPI_DATA_MASK GENMASK(7, 0) + +#define AD7768_MAX_CHANNEL 8 + +enum ad7768_clock_source { + AD7768_CLOCK_SOURCE_MCLK, + AD7768_CLOCK_SOURCE_XTAL, + AD7768_CLOCK_SOURCE_LVDS, +}; + +struct ad7768_precharge_config { + bool prebufp_en; + bool prebufn_en; + bool refbufp; + bool refbufn; +}; + +struct ad7768_chip_info { + const char *name; + const struct regmap_config *regmap_config; + const unsigned int *available_datalines; + unsigned int num_datalines; + unsigned int num_channels; + const u8 *chan_map; + u8 prebuf_split; +}; + +struct ad7768_state { + struct regmap *regmap; + struct clk *mclk; + unsigned int datalines; + enum ad7768_clock_source clock_source; + const struct ad7768_chip_info *chip_info; + struct iio_backend *back; + unsigned int vref_uV[2]; + + /* Used only in regmap_read() callback, hence guarded by regmap lock. */ + __be16 d16 __aligned(IIO_DMA_MINALIGN); +}; + +static const unsigned int ad7768_available_datalines[] =3D { + 1, 2, 8, +}; + +static const unsigned int ad7768_4_available_datalines[] =3D { + 1, 4, +}; + +static const u8 ad7768_chan_map[] =3D { + 0, 1, 2, 3, 4, 5, 6, 7, +}; + +static const u8 ad7768_4_chan_map[] =3D { + 0, 1, 4, 5, +}; + +static const char * const ad7768_supply_names[] =3D { + "avdd2", "iovdd", +}; + +static const char * const ad7768_vref_supply_names[][2] =3D { + { "ref1p", "ref1n" }, + { "ref2p", "ref2n" }, +}; + +static const char * const ad7768_clock_names[] =3D { + [AD7768_CLOCK_SOURCE_MCLK] =3D "mclk", + [AD7768_CLOCK_SOURCE_XTAL] =3D "xtal", + [AD7768_CLOCK_SOURCE_LVDS] =3D "lvds", +}; + +static u8 ad7768_channel_mask(const struct ad7768_state *st, u8 ch) +{ + return BIT(st->chip_info->chan_map[ch]); +} + +static u8 ad7768_all_standby_mask(const struct ad7768_state *st) +{ + return GENMASK(st->chip_info->num_channels - 1, 0); +} + +static void ad7768_keep_xtal_channel_active(const struct ad7768_state *st, + unsigned long *standby_mask) +{ + /* + * Crystal excitation requires channel 4 on AD7768 or channel 2 on + * AD7768-4 to remain active. + */ + if (st->clock_source =3D=3D AD7768_CLOCK_SOURCE_XTAL) + __clear_bit(st->chip_info->num_channels / 2, standby_mask); +} + +static u8 ad7768_precharge_buf1_mask(const struct ad7768_state *st, u16 va= l) +{ + return val & GENMASK(st->chip_info->prebuf_split - 1, 0); +} + +static u8 ad7768_precharge_buf2_mask(const struct ad7768_state *st, u16 va= l) +{ + unsigned int split =3D st->chip_info->prebuf_split; + + return field_get(GENMASK(2 * split - 1, split), val); +} + +static int ad7768_regmap_read(void *context, const void *reg_buf, + size_t reg_size, void *val_buf, size_t val_size) +{ + struct ad7768_state *st =3D spi_get_drvdata(context); + struct spi_device *spi =3D context; + struct spi_transfer t[] =3D { + { + .tx_buf =3D &st->d16, + .len =3D sizeof(st->d16), + .cs_change =3D 1, + }, { + /* + * Register responses are delayed by one CS frame. While + * receiving the response to this read, the device also + * decodes another command on SDI. Repeat the read + * command to avoid sending an unspecified dummy + * command. + */ + .tx_buf =3D &st->d16, + .rx_buf =3D &st->d16, + .len =3D sizeof(st->d16), + }, + }; + u8 *data_val =3D val_buf; + unsigned int reg; + int ret; + + reg =3D *(const u8 *)reg_buf; + + st->d16 =3D be16_replace_bits(cpu_to_be16(AD7768_SPI_READ_CMD), reg, + AD7768_SPI_REG_MASK); + + ret =3D spi_sync_transfer(spi, t, ARRAY_SIZE(t)); + if (ret) + return ret; + + *data_val =3D be16_get_bits(st->d16, AD7768_SPI_DATA_MASK); + + return 0; +} + +static int ad7768_regmap_write(void *spi, const void *data, size_t count) +{ + return spi_write(spi, data, count); +} + +static const struct regmap_bus ad7768_regmap_bus =3D { + .read =3D ad7768_regmap_read, + .write =3D ad7768_regmap_write, + .reg_format_endian_default =3D REGMAP_ENDIAN_BIG, + .val_format_endian_default =3D REGMAP_ENDIAN_BIG, +}; + +static bool ad7768_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case AD7768_REG_CH_STANDBY ... AD7768_REG_REV_ID: + case AD7768_REG_GPIO_CONTROL ... AD7768_REG_REFN_BUF: + case AD7768_REG_OFFSET(0) ... AD7768_REG_OFFSET(7) + 2: + case AD7768_REG_GAIN(0) ... AD7768_REG_GAIN(7) + 2: + case AD7768_REG_PHASE(0) ... AD7768_REG_PHASE(7): + case AD7768_REG_DIAGNOSTIC_RX ... AD7768_REG_CHOP_CTRL: + return true; + default: + return false; + } +} + +static bool ad7768_4_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case AD7768_REG_CH_STANDBY ... AD7768_REG_REV_ID: + case AD7768_REG_GPIO_CONTROL ... AD7768_REG_REFN_BUF: + case AD7768_REG_OFFSET(0) ... AD7768_REG_OFFSET(1) + 2: + case AD7768_REG_OFFSET(4) ... AD7768_REG_OFFSET(5) + 2: + case AD7768_REG_GAIN(0) ... AD7768_REG_GAIN(1) + 2: + case AD7768_REG_GAIN(4) ... AD7768_REG_GAIN(5) + 2: + case AD7768_REG_PHASE(0) ... AD7768_REG_PHASE(1): + case AD7768_REG_PHASE(4) ... AD7768_REG_PHASE(5): + case AD7768_REG_DIAGNOSTIC_RX ... AD7768_REG_CHOP_CTRL: + return true; + default: + return false; + } +} + +static const struct regmap_config ad7768_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D AD7768_REG_CHOP_CTRL, + /* + * Regmap bulk transfers use one starting address, while each register + * access requires a separate 16-bit SPI frame and reads use an off-frame + * response. Split bulk transfers into individual register accesses. Do + * not use a register cache because some readable registers report live + * hardware state. + */ + .use_single_read =3D true, + .use_single_write =3D true, + .readable_reg =3D ad7768_readable_reg, +}; + +static const struct regmap_config ad7768_4_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D AD7768_REG_CHOP_CTRL, + /* + * Regmap bulk transfers use one starting address, while each register + * access requires a separate 16-bit SPI frame and reads use an off-frame + * response. Split bulk transfers into individual register accesses. Do + * not use a register cache because some readable registers report live + * hardware state. + */ + .use_single_read =3D true, + .use_single_write =3D true, + .readable_reg =3D ad7768_4_readable_reg, +}; + +static int ad7768_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; + + PM_RUNTIME_ACQUIRE_AUTOSUSPEND(regmap_get_device(st->regmap), pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static int ad7768_sync(struct ad7768_state *st) +{ + int ret; + + ret =3D regmap_clear_bits(st->regmap, AD7768_REG_DATA_CONTROL, + AD7768_DATA_CONTROL_SPI_SYNC); + if (ret) + return ret; + + return regmap_set_bits(st->regmap, AD7768_REG_DATA_CONTROL, + AD7768_DATA_CONTROL_SPI_SYNC); +} + +static int ad7768_set_clk_divs(struct ad7768_state *st) +{ + unsigned int dclk_div_reg; + unsigned int dclk_div; + + /* + * DCLK(min) is ODR * channels per DOUTx * 32. With fast mode + * (fMOD =3D MCLK / 4) and x64 decimation, this gives: + * MCLK / DCLK =3D 8 * data lines / channels. + */ + dclk_div =3D 8 * st->datalines / st->chip_info->num_channels; + switch (dclk_div) { + case 1: + dclk_div_reg =3D AD7768_INTERFACE_CFG_DCLK_DIV_1; + break; + case 2: + dclk_div_reg =3D AD7768_INTERFACE_CFG_DCLK_DIV_2; + break; + case 4: + dclk_div_reg =3D AD7768_INTERFACE_CFG_DCLK_DIV_4; + break; + case 8: + dclk_div_reg =3D AD7768_INTERFACE_CFG_DCLK_DIV_8; + break; + default: + return -EINVAL; + } + + return regmap_update_bits(st->regmap, AD7768_REG_INTERFACE_CFG, + AD7768_INTERFACE_CFG_DCLK_DIV_MSK, + FIELD_PREP(AD7768_INTERFACE_CFG_DCLK_DIV_MSK, + dclk_div_reg)); +} + +static int ad7768_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + unsigned long channel_mask; + unsigned long standby_mask; + int ret; + + channel_mask =3D ad7768_all_standby_mask(st); + standby_mask =3D channel_mask & ~*scan_mask; + ad7768_keep_xtal_channel_active(st, &standby_mask); + + ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_STANDBY, + channel_mask, standby_mask); + if (ret) + return ret; + + for (unsigned int ch =3D 0; ch < st->chip_info->num_channels; ch++) { + if (test_bit(ch, scan_mask)) + ret =3D iio_backend_chan_enable(st->back, ch); + else + ret =3D iio_backend_chan_disable(st->back, ch); + if (ret) + return ret; + } + + return 0; +} + +static const struct ad7768_chip_info ad7768_chip_info =3D { + .name =3D "ad7768", + .num_channels =3D 8, + .regmap_config =3D &ad7768_regmap_config, + .available_datalines =3D ad7768_available_datalines, + .num_datalines =3D ARRAY_SIZE(ad7768_available_datalines), + .chan_map =3D ad7768_chan_map, + .prebuf_split =3D 8, +}; + +static const struct ad7768_chip_info ad7768_4_chip_info =3D { + .name =3D "ad7768-4", + .num_channels =3D 4, + .regmap_config =3D &ad7768_4_regmap_config, + .available_datalines =3D ad7768_4_available_datalines, + .num_datalines =3D ARRAY_SIZE(ad7768_4_available_datalines), + .chan_map =3D ad7768_4_chan_map, + .prebuf_split =3D 4, +}; + +static int ad7768_buffer_preenable(struct iio_dev *indio_dev) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + return pm_runtime_resume_and_get(regmap_get_device(st->regmap)); +} + +static int ad7768_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + pm_runtime_put_autosuspend(regmap_get_device(st->regmap)); + + return 0; +} + +static const struct iio_buffer_setup_ops ad7768_buffer_ops =3D { + .preenable =3D ad7768_buffer_preenable, + .postdisable =3D ad7768_buffer_postdisable, +}; + +static int ad7768_read_scale(struct ad7768_state *st, + const struct iio_chan_spec *chan, + int *val, int *val2) +{ + unsigned int vref_idx; + + vref_idx =3D chan->channel >=3D st->chip_info->num_channels / 2; + *val =3D 2 * st->vref_uV[vref_idx] / (MICRO / MILLI); + *val2 =3D chan->scan_type.realbits; + + return IIO_VAL_FRACTIONAL_LOG2; +} + +static int ad7768_read_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + int *val, int *val2, long info) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_SCALE: + return ad7768_read_scale(st, chan, val, val2); + default: + return -EINVAL; + } +} + +static const struct iio_info ad7768_info =3D { + .debugfs_reg_access =3D ad7768_reg_access, + .read_raw =3D ad7768_read_raw, + .update_scan_mode =3D ad7768_update_scan_mode, +}; + +static int ad7768_configure_precharge_buffers(struct iio_dev *indio_dev, + struct ad7768_precharge_config *precharge_cfg) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + u8 prebuf1_val, prebuf2_val; + u16 prebuf_mask =3D 0; + u8 refbufp_val =3D 0; + u8 refbufn_val =3D 0; + int ret; + + for (unsigned int ch =3D 0; ch < indio_dev->num_channels; ch++) { + u8 channel =3D indio_dev->channels[ch].channel; + + if (precharge_cfg[channel].prebufp_en) + prebuf_mask |=3D AD7768_PREBUF_POS_EN(channel); + + if (precharge_cfg[channel].prebufn_en) + prebuf_mask |=3D AD7768_PREBUF_NEG_EN(channel); + + if (precharge_cfg[channel].refbufp) + refbufp_val |=3D ad7768_channel_mask(st, channel); + + if (precharge_cfg[channel].refbufn) + refbufn_val |=3D ad7768_channel_mask(st, channel); + } + + prebuf1_val =3D ad7768_precharge_buf1_mask(st, ~prebuf_mask); + prebuf2_val =3D ad7768_precharge_buf2_mask(st, ~prebuf_mask); + + ret =3D regmap_write(st->regmap, AD7768_REG_PRECHARGE_BUF1, prebuf1_val); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD7768_REG_PRECHARGE_BUF2, prebuf2_val); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD7768_REG_REFP_BUF, refbufp_val); + if (ret) + return ret; + + return regmap_write(st->regmap, AD7768_REG_REFN_BUF, refbufn_val); +} + +static int ad7768_configure_capture(struct ad7768_state *st) +{ + unsigned int mode_config; + int ret; + + ret =3D regmap_update_bits(st->regmap, AD7768_REG_POWER_MODE, + AD7768_POWER_MODE_POWER_MODE_MSK | + AD7768_POWER_MODE_MCLK_DIV_MSK, + FIELD_PREP(AD7768_POWER_MODE_POWER_MODE_MSK, + AD7768_POWER_MODE_POWER_MODE_FAST) | + FIELD_PREP(AD7768_POWER_MODE_MCLK_DIV_MSK, + AD7768_POWER_MODE_POWER_MODE_FAST)); + if (ret) + return ret; + + /* + * Start with the wideband filter and a decimation rate of 64. This + * supports every valid data-line configuration at the maximum MCLK. + */ + mode_config =3D FIELD_PREP(AD7768_CH_MODE_FILTER_TYPE_MSK, + AD7768_CH_MODE_FILTER_TYPE_WIDEBAND) | + FIELD_PREP(AD7768_CH_MODE_DEC_RATE_MSK, + AD7768_CH_MODE_DEC_RATE_64); + ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(0), + AD7768_CH_MODE_FILTER_TYPE_MSK | + AD7768_CH_MODE_DEC_RATE_MSK, + mode_config); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD7768_REG_CH_MODE_SEL, 0); + if (ret) + return ret; + + ret =3D ad7768_set_clk_divs(st); + if (ret) + return ret; + + return ad7768_sync(st); +} + +static int ad7768_parse_config(struct iio_dev *indio_dev, + struct device *dev) +{ + struct ad7768_precharge_config precharge_cfg[AD7768_MAX_CHANNEL] =3D { }; + struct ad7768_state *st =3D iio_priv(indio_dev); + const unsigned int *available_datalines; + const char *propname; + bool datalines_valid =3D false; + struct iio_chan_spec *chan; + unsigned int num_channels; + unsigned long standby_mask; + unsigned int len; + int chan_idx =3D 0; + int ret; + + propname =3D "adi,data-lines-number"; + num_channels =3D device_get_named_child_node_count(dev, "channel"); + if (num_channels =3D=3D 0) + return dev_err_probe(dev, -ENOENT, "No channel specified\n"); + if (num_channels > st->chip_info->num_channels) + return dev_err_probe(dev, -ENOSPC, "Invalid number of channels\n"); + + chan =3D devm_kcalloc(dev, num_channels, sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + indio_dev->channels =3D chan; + indio_dev->num_channels =3D num_channels; + + standby_mask =3D ad7768_all_standby_mask(st); + ad7768_keep_xtal_channel_active(st, &standby_mask); + + ret =3D regmap_write(st->regmap, AD7768_REG_CH_STANDBY, standby_mask); + if (ret) + return ret; + + device_for_each_named_child_node_scoped(dev, child, "channel") { + u32 channel; + + ret =3D fwnode_property_read_u32(child, "reg", &channel); + if (ret) + return dev_err_probe(dev, ret, + "Failed to parse reg of %pfwP\n", + child); + + if (channel >=3D st->chip_info->num_channels) + return dev_err_probe(dev, -ECHRNG, + "Invalid channel %u in firmware\n", + channel); + + ret =3D regmap_clear_bits(st->regmap, AD7768_REG_CH_STANDBY, + BIT(channel)); + if (ret) + return ret; + + precharge_cfg[channel].prebufp_en =3D + fwnode_property_read_bool(child, "adi,prechargebuf-pos-enable"); + precharge_cfg[channel].prebufn_en =3D + fwnode_property_read_bool(child, "adi,prechargebuf-neg-enable"); + precharge_cfg[channel].refbufp =3D + fwnode_property_read_bool(child, "adi,refbuf-pos-enable"); + precharge_cfg[channel].refbufn =3D + fwnode_property_read_bool(child, "adi,refbuf-neg-enable"); + + chan[chan_idx++] =3D (struct iio_chan_spec) { + .type =3D IIO_VOLTAGE, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE), + .indexed =3D 1, + .channel =3D channel, + .scan_index =3D channel, + .scan_type =3D { + .sign =3D 's', + .realbits =3D 24, + .storagebits =3D 32, + }, + }; + } + + ret =3D ad7768_configure_precharge_buffers(indio_dev, precharge_cfg); + if (ret) + return ret; + + available_datalines =3D st->chip_info->available_datalines; + len =3D st->chip_info->num_datalines; + if (device_property_present(dev, propname)) { + ret =3D device_property_read_u32(dev, propname, &st->datalines); + if (ret) + return dev_err_probe(dev, ret, "Invalid %s property\n", + propname); + } else { + st->datalines =3D available_datalines[len - 1]; + } + + for (unsigned int i =3D 0; i < len; i++) { + if (available_datalines[i] =3D=3D st->datalines) { + datalines_valid =3D true; + break; + } + } + + if (!datalines_valid) + return dev_err_probe(dev, -EINVAL, + "Invalid %s %u for %s\n", propname, + st->datalines, st->chip_info->name); + + return ad7768_configure_capture(st); +} + +static int ad7768_reset(struct ad7768_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + struct reset_control *reset_ctrl; + unsigned long reset_low_us; + unsigned long mclk; + int ret; + + reset_ctrl =3D devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(reset_ctrl)) + return PTR_ERR(reset_ctrl); + + if (reset_ctrl) { + mclk =3D clk_get_rate(st->mclk); + if (!mclk) + return -EINVAL; + + /* + * Minimum RESET low pulse width: 2 x tMCLK + * (datasheet Table 1). + */ + reset_low_us =3D DIV_ROUND_UP_ULL(2ULL * USEC_PER_SEC, mclk); + + ret =3D reset_control_assert(reset_ctrl); + if (ret) + return ret; + + fsleep(max(1UL, reset_low_us)); + + ret =3D reset_control_deassert(reset_ctrl); + if (ret) + return ret; + } else { + ret =3D regmap_write(st->regmap, AD7768_REG_DATA_CONTROL, + AD7768_DATA_CONTROL_SPI_RESET_1); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD7768_REG_DATA_CONTROL, + AD7768_DATA_CONTROL_SPI_RESET_2); + if (ret) + return ret; + } + + /* ADC start-up time after reset: 1.66 ms max (datasheet Table 1) */ + fsleep(1660); + + return 0; +} + +static void ad7768_disable_clk(void *clk) +{ + clk_disable_unprepare(clk); +} + +static int ad7768_configure_xtal_clock(struct ad7768_state *st) +{ + int ret; + + ret =3D regmap_set_bits(st->regmap, AD7768_REG_GPIO_WRITE, BIT(4)); + if (ret) + return ret; + + return regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL, + AD7768_GPIO_UGPIO_ENABLE | + AD7768_GPIO4_OUTPUT_ENABLE); +} + +static int ad7768_enable_lvds_clock(struct ad7768_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + int ret; + + ret =3D regmap_clear_bits(st->regmap, AD7768_REG_GPIO_WRITE, BIT(4)); + if (ret) + return ret; + + ret =3D regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL, + AD7768_GPIO_UGPIO_ENABLE | + AD7768_GPIO4_OUTPUT_ENABLE); + if (ret) + return ret; + + ret =3D regmap_set_bits(st->regmap, AD7768_REG_POWER_MODE, + AD7768_POWER_MODE_LVDS_ENABLE); + if (ret) + return ret; + + ret =3D clk_prepare_enable(st->mclk); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, ad7768_disable_clk, st->mclk); +} + +static int ad7768_get_enable_vref(struct device *dev, unsigned int index) +{ + const char * const *supply =3D ad7768_vref_supply_names[index]; + int refp_uV; + int refn_uV; + + refp_uV =3D devm_regulator_get_enable_read_voltage(dev, supply[0]); + if (refp_uV < 0) + return dev_err_probe(dev, refp_uV, + "Failed to get %s supply voltage\n", supply[0]); + + refn_uV =3D devm_regulator_get_enable_read_voltage(dev, supply[1]); + if (refn_uV =3D=3D -ENODEV) + refn_uV =3D 0; + else if (refn_uV < 0) + return dev_err_probe(dev, refn_uV, + "Failed to get %s supply voltage\n", supply[1]); + + if (refp_uV <=3D refn_uV) + return dev_err_probe(dev, -EINVAL, + "Invalid reference %u voltage\n", index + 1); + + return refp_uV - refn_uV; +} + +static int ad7768_enter_sleep(struct ad7768_state *st) +{ + return regmap_set_bits(st->regmap, AD7768_REG_POWER_MODE, + AD7768_SLEEP_MODE_MSK); +} + +static void ad7768_power_off(void *data) +{ + struct ad7768_state *st =3D data; + struct device *dev =3D regmap_get_device(st->regmap); + int ret; + + ret =3D ad7768_enter_sleep(st); + if (ret) + dev_err(dev, "Failed to put device to sleep\n"); +} + +static int ad7768_probe(struct spi_device *spi) +{ + unsigned int spi_readback, rev_id; + struct device *dev =3D &spi->dev; + struct iio_dev *indio_dev; + struct ad7768_state *st; + const char *clock_name; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + spi_set_drvdata(spi, st); + + st->chip_info =3D spi_get_device_match_data(spi); + if (!st->chip_info) + return dev_err_probe(dev, -ENODATA, "Failed to get match data\n"); + + ret =3D devm_regulator_get_enable_optional(dev, "avss"); + if (ret =3D=3D -ENODEV) { + /* AVSS may be connected directly to ground instead of a regulator. */ + } else if (ret) { + return dev_err_probe(dev, ret, "Failed to enable AVSS supply\n"); + } + + ret =3D devm_regulator_get_enable(dev, "avdd1"); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable AVDD1 supply\n"); + + ret =3D devm_regulator_bulk_get_enable(dev, + ARRAY_SIZE(ad7768_supply_names), + ad7768_supply_names); + if (ret) + return ret; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(ad7768_vref_supply_names); i++)= { + ret =3D ad7768_get_enable_vref(dev, i); + if (ret < 0) + return ret; + + st->vref_uV[i] =3D ret; + } + + ret =3D device_property_match_property_string(dev, "clock-names", + ad7768_clock_names, + ARRAY_SIZE(ad7768_clock_names)); + if (ret < 0) + return dev_err_probe(dev, ret, "Invalid clock source\n"); + + st->clock_source =3D ret; + clock_name =3D ad7768_clock_names[st->clock_source]; + + /* + * The device must start on its internal clock. Keep the LVDS clock + * disabled until GPIO4 is driven low and the LVDS input is enabled in + * the power mode register. + */ + switch (st->clock_source) { + case AD7768_CLOCK_SOURCE_MCLK: + case AD7768_CLOCK_SOURCE_XTAL: + st->mclk =3D devm_clk_get_enabled(dev, clock_name); + break; + case AD7768_CLOCK_SOURCE_LVDS: + st->mclk =3D devm_clk_get(dev, clock_name); + break; + } + + if (IS_ERR(st->mclk)) + return dev_err_probe(dev, PTR_ERR(st->mclk), + "Failed to get master clock\n"); + + st->regmap =3D devm_regmap_init(dev, &ad7768_regmap_bus, spi, + st->chip_info->regmap_config); + if (IS_ERR(st->regmap)) + return PTR_ERR(st->regmap); + + ret =3D ad7768_reset(st); + if (ret) + return ret; + + /* Discard the reset response with a dummy SPI register read. */ + ret =3D regmap_read(st->regmap, AD7768_REG_REV_ID, &spi_readback); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD7768_REG_REV_ID, &rev_id); + if (ret) + return ret; + + if (rev_id !=3D AD7768_REV_ID_VAL) + dev_info(dev, "Unexpected revision ID 0x%02x\n", rev_id); + + switch (st->clock_source) { + case AD7768_CLOCK_SOURCE_MCLK: + break; + case AD7768_CLOCK_SOURCE_XTAL: + ret =3D ad7768_configure_xtal_clock(st); + if (ret) + return dev_err_probe(dev, ret, + "Failed to configure crystal clock\n"); + break; + case AD7768_CLOCK_SOURCE_LVDS: + ret =3D ad7768_enable_lvds_clock(st); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable LVDS clock\n"); + break; + } + + ret =3D devm_add_action_or_reset(dev, ad7768_power_off, st); + if (ret) + return ret; + + ret =3D ad7768_parse_config(indio_dev, dev); + if (ret) + return ret; + + /* + * Hardware supports CRC every 4 or 16 samples; the backend supports only + * 4-sample CRC. + */ + ret =3D regmap_update_bits(st->regmap, AD7768_REG_INTERFACE_CFG, + AD7768_INTERFACE_CFG_CRC_SELECT_MSK, + FIELD_PREP(AD7768_INTERFACE_CFG_CRC_SELECT_MSK, + AD7768_INTERFACE_CFG_CRC_SELECT_4)); + if (ret) + return ret; + + indio_dev->name =3D st->chip_info->name; + indio_dev->info =3D &ad7768_info; + indio_dev->setup_ops =3D &ad7768_buffer_ops; + + st->back =3D devm_iio_backend_get(dev, NULL); + if (IS_ERR(st->back)) + return PTR_ERR(st->back); + + ret =3D devm_iio_backend_request_buffer(dev, st->back, indio_dev); + if (ret) + return ret; + + ret =3D iio_backend_num_lanes_set(st->back, st->datalines); + if (ret) + return ret; + + ret =3D iio_backend_crc_enable(st->back); + if (ret) + return ret; + + ret =3D devm_iio_backend_enable(dev, st->back); + if (ret) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 2000); + pm_runtime_use_autosuspend(dev); + ret =3D devm_pm_runtime_set_active_enabled(dev); + if (ret) + return ret; + + return devm_iio_device_register(dev, indio_dev); +} + +static int ad7768_runtime_suspend(struct device *dev) +{ + struct ad7768_state *st =3D dev_get_drvdata(dev); + + return ad7768_enter_sleep(st); +} + +static int ad7768_runtime_resume(struct device *dev) +{ + struct ad7768_state *st =3D dev_get_drvdata(dev); + int ret; + + ret =3D regmap_clear_bits(st->regmap, AD7768_REG_POWER_MODE, + AD7768_SLEEP_MODE_MSK); + if (ret) + return ret; + + /* + * The datasheet does not specify a wake-up time. Allow 20 ms for the + * ADC and digital clocks to restart. + */ + fsleep(20 * USEC_PER_MSEC); + + return 0; +} + +static DEFINE_RUNTIME_DEV_PM_OPS(ad7768_pm_ops, ad7768_runtime_suspend, + ad7768_runtime_resume, NULL); + +static const struct of_device_id ad7768_of_match[] =3D { + { .compatible =3D "adi,ad7768", .data =3D &ad7768_chip_info }, + { .compatible =3D "adi,ad7768-4", .data =3D &ad7768_4_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, ad7768_of_match); + +static const struct spi_device_id ad7768_spi_id[] =3D { + { .name =3D "ad7768", .driver_data =3D (kernel_ulong_t)&ad7768_chip_info = }, + { .name =3D "ad7768-4", .driver_data =3D (kernel_ulong_t)&ad7768_4_chip_i= nfo }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad7768_spi_id); + +static struct spi_driver ad7768_driver =3D { + .probe =3D ad7768_probe, + .driver =3D { + .name =3D "ad7768", + .of_match_table =3D ad7768_of_match, + .pm =3D pm_ptr(&ad7768_pm_ops), + }, + .id_table =3D ad7768_spi_id, +}; +module_spi_driver(ad7768_driver); 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External CMOS and LVDS clocks support 1.15 MHz to 34 MHz, while a crystal requires 8 MHz to 34 MHz. Reviewed-by: Andy Shevchenko Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 2c5d0657edf9..7ce0229b5b7c 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -91,6 +91,9 @@ #define AD7768_SPI_REG_MASK GENMASK(14, 8) #define AD7768_SPI_DATA_MASK GENMASK(7, 0) =20 +#define AD7768_MIN_MCLK_FREQ_HZ (1150 * HZ_PER_KHZ) +#define AD7768_MIN_XTAL_FREQ_HZ (8 * HZ_PER_MHZ) +#define AD7768_MAX_MCLK_FREQ_HZ (34 * HZ_PER_MHZ) #define AD7768_MAX_CHANNEL 8 =20 enum ad7768_clock_source { @@ -810,6 +813,23 @@ static void ad7768_power_off(void *data) dev_err(dev, "Failed to put device to sleep\n"); } =20 +static int ad7768_validate_mclk_rate(struct device *dev, + const struct ad7768_state *st) +{ + unsigned long min_rate =3D AD7768_MIN_MCLK_FREQ_HZ; + unsigned long rate =3D clk_get_rate(st->mclk); + + if (st->clock_source =3D=3D AD7768_CLOCK_SOURCE_XTAL) + min_rate =3D AD7768_MIN_XTAL_FREQ_HZ; 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Replace the open-coded fast-mode setup with a helper that records the active mode, preparing for dynamic mode selection. Reviewed-by: Andy Shevchenko Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 48 +++++++++++++++++++++++++++++++++++++++++---= ---- 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 7ce0229b5b7c..5bd01f457a54 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -41,6 +41,8 @@ #define AD7768_REG_POWER_MODE 0x04 #define AD7768_SLEEP_MODE_MSK BIT(7) #define AD7768_POWER_MODE_POWER_MODE_MSK GENMASK(5, 4) +#define AD7768_POWER_MODE_POWER_MODE_LOW 0x0 +#define AD7768_POWER_MODE_POWER_MODE_MEDIAN 0x2 #define AD7768_POWER_MODE_POWER_MODE_FAST 0x3 #define AD7768_POWER_MODE_LVDS_ENABLE BIT(3) #define AD7768_POWER_MODE_MCLK_DIV_MSK GENMASK(1, 0) @@ -102,6 +104,17 @@ enum ad7768_clock_source { AD7768_CLOCK_SOURCE_LVDS, }; =20 +struct ad7768_power_mode_info { + unsigned int mode; + unsigned int mclk_div; +}; + +static const struct ad7768_power_mode_info ad7768_power_modes[] =3D { + { .mode =3D AD7768_POWER_MODE_POWER_MODE_LOW, .mclk_div =3D 32 }, + { .mode =3D AD7768_POWER_MODE_POWER_MODE_MEDIAN, .mclk_div =3D 8 }, + { .mode =3D AD7768_POWER_MODE_POWER_MODE_FAST, .mclk_div =3D 4 }, +}; + struct ad7768_precharge_config { bool prebufp_en; bool prebufn_en; @@ -127,6 +140,7 @@ struct ad7768_state { const struct ad7768_chip_info *chip_info; struct iio_backend *back; unsigned int vref_uV[2]; + unsigned int power_mode_idx; =20 /* Used only in regmap_read() callback, hence guarded by regmap lock. */ __be16 d16 __aligned(IIO_DMA_MINALIGN); @@ -346,6 +360,32 @@ static int ad7768_sync(struct ad7768_state *st) AD7768_DATA_CONTROL_SPI_SYNC); } =20 +static int ad7768_set_power_mode(struct ad7768_state *st, + unsigned int mode_idx) +{ + const struct ad7768_power_mode_info *mode_info; + int ret; + + mode_info =3D &ad7768_power_modes[mode_idx]; + ret =3D regmap_update_bits(st->regmap, AD7768_REG_POWER_MODE, + AD7768_POWER_MODE_POWER_MODE_MSK | + AD7768_POWER_MODE_MCLK_DIV_MSK, + FIELD_PREP(AD7768_POWER_MODE_POWER_MODE_MSK, + mode_info->mode) | + FIELD_PREP(AD7768_POWER_MODE_MCLK_DIV_MSK, + mode_info->mode)); + if (ret) + return ret; + + ret =3D ad7768_sync(st); + if (ret) + return ret; + + st->power_mode_idx =3D mode_idx; + + return 0; +} + static int ad7768_set_clk_divs(struct ad7768_state *st) { unsigned int dclk_div_reg; @@ -532,13 +572,7 @@ static int ad7768_configure_capture(struct ad7768_stat= e *st) unsigned int mode_config; int ret; =20 - ret =3D regmap_update_bits(st->regmap, AD7768_REG_POWER_MODE, - AD7768_POWER_MODE_POWER_MODE_MSK | - AD7768_POWER_MODE_MCLK_DIV_MSK, - FIELD_PREP(AD7768_POWER_MODE_POWER_MODE_MSK, - AD7768_POWER_MODE_POWER_MODE_FAST) | - FIELD_PREP(AD7768_POWER_MODE_MCLK_DIV_MSK, - AD7768_POWER_MODE_POWER_MODE_FAST)); + ret =3D ad7768_set_power_mode(st, ARRAY_SIZE(ad7768_power_modes) - 1); if (ret) return ret; =20 --=20 2.43.0 From nobody Fri Sep 25 05:30:00 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B4FA4EE860; Wed, 16 Sep 2026 11:15:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Replace the fixed x64 decimation with the derived default output rate and a new decimation helper. Extend the existing clock-divider helper to derive the DCLK divider from the selected rate. Select the maximum rate supported by the configured data interface for the initial capture configuration. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 134 ++++++++++++++++++++++++++++++++++++++++---= ---- 1 file changed, 115 insertions(+), 19 deletions(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 5bd01f457a54..2d051d91e1cf 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -34,7 +35,6 @@ #define AD7768_CH_MODE_FILTER_TYPE_MSK BIT(3) #define AD7768_CH_MODE_FILTER_TYPE_WIDEBAND 0x0 #define AD7768_CH_MODE_DEC_RATE_MSK GENMASK(2, 0) -#define AD7768_CH_MODE_DEC_RATE_64 0x1 =20 #define AD7768_REG_CH_MODE_SEL 0x03 =20 @@ -93,9 +93,12 @@ #define AD7768_SPI_REG_MASK GENMASK(14, 8) #define AD7768_SPI_DATA_MASK GENMASK(7, 0) =20 +#define AD7768_SAMPLE_SIZE 32 +#define AD7768_MAX_DCLK_DIV 8 #define AD7768_MIN_MCLK_FREQ_HZ (1150 * HZ_PER_KHZ) #define AD7768_MIN_XTAL_FREQ_HZ (8 * HZ_PER_MHZ) #define AD7768_MAX_MCLK_FREQ_HZ (34 * HZ_PER_MHZ) +#define AD7768_MAX_FREQ_PER_MODE 6 #define AD7768_MAX_CHANNEL 8 =20 enum ad7768_clock_source { @@ -122,6 +125,16 @@ struct ad7768_precharge_config { bool refbufn; }; =20 +struct ad7768_freq_config { + unsigned int freq_hz; + unsigned int dec_rate; +}; + +struct ad7768_avail_freq { + unsigned int n_freqs; + struct ad7768_freq_config freq_cfg[AD7768_MAX_FREQ_PER_MODE]; +}; + struct ad7768_chip_info { const char *name; const struct regmap_config *regmap_config; @@ -138,6 +151,8 @@ struct ad7768_state { unsigned int datalines; enum ad7768_clock_source clock_source; const struct ad7768_chip_info *chip_info; + struct ad7768_avail_freq avail_freq[ARRAY_SIZE(ad7768_power_modes)]; + unsigned int ch_freq[AD7768_MAX_CHANNEL]; struct iio_backend *back; unsigned int vref_uV[2]; unsigned int power_mode_idx; @@ -146,6 +161,10 @@ struct ad7768_state { __be16 d16 __aligned(IIO_DMA_MINALIGN); }; =20 +static const unsigned int ad7768_dec_rate[AD7768_MAX_FREQ_PER_MODE] =3D { + 32, 64, 128, 256, 512, 1024, +}; + static const unsigned int ad7768_available_datalines[] =3D { 1, 2, 8, }; @@ -386,17 +405,45 @@ static int ad7768_set_power_mode(struct ad7768_state = *st, return 0; } =20 -static int ad7768_set_clk_divs(struct ad7768_state *st) +static const struct ad7768_freq_config * +ad7768_find_freq_config(const struct ad7768_state *st, + unsigned int mode_idx, unsigned int freq) { + const struct ad7768_avail_freq *avail_freq =3D &st->avail_freq[mode_idx]; + + for (unsigned int i =3D 0; i < avail_freq->n_freqs; i++) { + if (freq =3D=3D avail_freq->freq_cfg[i].freq_hz) + return &avail_freq->freq_cfg[i]; + } + + return NULL; +} + +static int ad7768_set_clk_divs(struct ad7768_state *st, unsigned int freq) +{ + const struct ad7768_freq_config *freq_cfg; + unsigned int mclk, dclk, dclk_div; + unsigned int chan_per_doutx; unsigned int dclk_div_reg; - unsigned int dclk_div; =20 - /* - * DCLK(min) is ODR * channels per DOUTx * 32. With fast mode - * (fMOD =3D MCLK / 4) and x64 decimation, this gives: - * MCLK / DCLK =3D 8 * data lines / channels. - */ - dclk_div =3D 8 * st->datalines / st->chip_info->num_channels; + freq_cfg =3D ad7768_find_freq_config(st, st->power_mode_idx, freq); + if (!freq_cfg) + return -EINVAL; + + mclk =3D clk_get_rate(st->mclk); + chan_per_doutx =3D st->chip_info->num_channels / st->datalines; + if (!chan_per_doutx) + return -EINVAL; + + dclk =3D freq_cfg->freq_hz * AD7768_SAMPLE_SIZE * chan_per_doutx; + if (dclk > mclk) + return -EINVAL; + + dclk_div =3D DIV_ROUND_CLOSEST(mclk, dclk); + + /* Set the divider to the next-lowest supported power of two. */ + dclk_div =3D rounddown_pow_of_two(min(dclk_div, AD7768_MAX_DCLK_DIV)); + switch (dclk_div) { case 1: dclk_div_reg =3D AD7768_INTERFACE_CFG_DCLK_DIV_1; @@ -420,6 +467,21 @@ static int ad7768_set_clk_divs(struct ad7768_state *st) dclk_div_reg)); } =20 +static int ad7768_set_mode_decimation(struct ad7768_state *st, + unsigned int freq, unsigned int mode) +{ + const struct ad7768_freq_config *freq_cfg; + + freq_cfg =3D ad7768_find_freq_config(st, st->power_mode_idx, freq); + if (!freq_cfg) + return -EINVAL; + + return regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(mode), + AD7768_CH_MODE_DEC_RATE_MSK, + FIELD_PREP(AD7768_CH_MODE_DEC_RATE_MSK, + freq_cfg->dec_rate)); +} + static int ad7768_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) { @@ -567,8 +629,37 @@ static int ad7768_configure_precharge_buffers(struct i= io_dev *indio_dev, return regmap_write(st->regmap, AD7768_REG_REFN_BUF, refbufn_val); } =20 +static void ad7768_set_available_sampling_freqs(struct ad7768_state *st) +{ + unsigned int n_power_modes =3D ARRAY_SIZE(ad7768_power_modes); + unsigned int mclk =3D clk_get_rate(st->mclk); + + for (unsigned int mode_idx =3D 0; mode_idx < n_power_modes; mode_idx++) { + unsigned int dec =3D ARRAY_SIZE(ad7768_dec_rate); + struct ad7768_avail_freq *avail_freq; + unsigned int div; + + avail_freq =3D &st->avail_freq[mode_idx]; + div =3D ad7768_power_modes[mode_idx].mclk_div; + while (dec--) { + struct ad7768_freq_config *freq_cfg; + + freq_cfg =3D &avail_freq->freq_cfg[avail_freq->n_freqs++]; + freq_cfg->dec_rate =3D dec; + freq_cfg->freq_hz =3D mclk / (ad7768_dec_rate[dec] * div); + } + } + + /* One DOUT line cannot carry the AD7768 fast-mode x32 output rate. */ + if (st->datalines =3D=3D 1 && + st->chip_info->num_channels =3D=3D AD7768_MAX_CHANNEL) + st->avail_freq[n_power_modes - 1].n_freqs--; +} + static int ad7768_configure_capture(struct ad7768_state *st) { + const struct ad7768_avail_freq *avail_freq; + unsigned int default_freq; unsigned int mode_config; int ret; =20 @@ -576,17 +667,20 @@ static int ad7768_configure_capture(struct ad7768_sta= te *st) if (ret) return ret; =20 - /* - * Start with the wideband filter and a decimation rate of 64. This - * supports every valid data-line configuration at the maximum MCLK. - */ + avail_freq =3D &st->avail_freq[st->power_mode_idx]; + default_freq =3D avail_freq->freq_cfg[avail_freq->n_freqs - 1].freq_hz; + for (unsigned int channel =3D 0; + channel < st->chip_info->num_channels; channel++) + st->ch_freq[channel] =3D default_freq; + + ret =3D ad7768_set_mode_decimation(st, default_freq, 0); + if (ret) + return ret; + mode_config =3D FIELD_PREP(AD7768_CH_MODE_FILTER_TYPE_MSK, - AD7768_CH_MODE_FILTER_TYPE_WIDEBAND) | - FIELD_PREP(AD7768_CH_MODE_DEC_RATE_MSK, - AD7768_CH_MODE_DEC_RATE_64); + AD7768_CH_MODE_FILTER_TYPE_WIDEBAND); ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(0), - AD7768_CH_MODE_FILTER_TYPE_MSK | - AD7768_CH_MODE_DEC_RATE_MSK, + AD7768_CH_MODE_FILTER_TYPE_MSK, mode_config); if (ret) return ret; @@ -595,7 +689,7 @@ static int ad7768_configure_capture(struct ad7768_state= *st) if (ret) return ret; =20 - ret =3D ad7768_set_clk_divs(st); + ret =3D ad7768_set_clk_divs(st, default_freq); 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Group channels into the two hardware mode profiles and program their decimation, mode selection, and data clock. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 165 +++++++++++++++++++++++++++++++++++++++----= ---- 1 file changed, 138 insertions(+), 27 deletions(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 2d051d91e1cf..fc8226d5d556 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -7,7 +7,9 @@ =20 #include #include +#include #include +#include #include #include #include @@ -16,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -33,7 +36,6 @@ =20 #define AD7768_REG_CH_MODE(x) (0x01 + (x)) #define AD7768_CH_MODE_FILTER_TYPE_MSK BIT(3) -#define AD7768_CH_MODE_FILTER_TYPE_WIDEBAND 0x0 #define AD7768_CH_MODE_DEC_RATE_MSK GENMASK(2, 0) =20 #define AD7768_REG_CH_MODE_SEL 0x03 @@ -100,6 +102,7 @@ #define AD7768_MAX_MCLK_FREQ_HZ (34 * HZ_PER_MHZ) #define AD7768_MAX_FREQ_PER_MODE 6 #define AD7768_MAX_CHANNEL 8 +#define AD7768_NUM_CHANNEL_MODES 2 =20 enum ad7768_clock_source { AD7768_CLOCK_SOURCE_MCLK, @@ -147,6 +150,8 @@ struct ad7768_chip_info { =20 struct ad7768_state { struct regmap *regmap; + /* Protects device register access and configuration. */ + struct mutex lock; struct clk *mclk; unsigned int datalines; enum ad7768_clock_source clock_source; @@ -201,6 +206,17 @@ static u8 ad7768_channel_mask(const struct ad7768_stat= e *st, u8 ch) return BIT(st->chip_info->chan_map[ch]); } =20 +static u8 ad7768_channel_mode_mask(const struct ad7768_state *st, u8 ch) +{ + /* + * AD7768-4 channels 2 and 3 use bits 4 and 5 for CH_x_MODE, while + * their CH_x_MDE_EN fields are in bits 2 and 3 and must be programmed + * to the same value. On AD7768, chan_map[] is an identity map, so the + * OR produces a single bit. + */ + return BIT(ch) | ad7768_channel_mask(st, ch); +} + static u8 ad7768_all_standby_mask(const struct ad7768_state *st) { return GENMASK(st->chip_info->num_channels - 1, 0); @@ -482,23 +498,131 @@ static int ad7768_set_mode_decimation(struct ad7768_= state *st, freq_cfg->dec_rate)); } =20 -static int ad7768_update_scan_mode(struct iio_dev *indio_dev, - const unsigned long *scan_mask) +static int ad7768_set_lowest_noise_mode(struct ad7768_state *st, + const unsigned long *scan_mask) +{ + unsigned int mode_idx =3D ARRAY_SIZE(ad7768_power_modes); + + /* + * The output data rate ranges overlap between the power modes. At a + * common ODR, the faster mode has lower noise, so prefer the fastest + * mode that supports every enabled channel. + */ + while (mode_idx--) { + unsigned int channel; + + for_each_set_bit(channel, scan_mask, st->chip_info->num_channels) { + if (!ad7768_find_freq_config(st, mode_idx, + st->ch_freq[channel])) + break; + } + + /* All enabled channels support their requested frequency. */ + if (channel =3D=3D st->chip_info->num_channels) + return ad7768_set_power_mode(st, mode_idx); + } + + return -EINVAL; +} + +static int ad7768_find_matching_mode(const bool *mode_used, + const unsigned int *mode_freq, + unsigned int freq) +{ + for (unsigned int mode =3D 0; mode < AD7768_NUM_CHANNEL_MODES; mode++) { + if (!mode_used[mode] || mode_freq[mode] =3D=3D freq) + return mode; + } + + return -EINVAL; +} + +static int ad7768_apply_channel_modes(struct iio_dev *indio_dev, + const unsigned long *scan_mask) { + unsigned int mode_freq[AD7768_NUM_CHANNEL_MODES] =3D { }; + bool mode_used[AD7768_NUM_CHANNEL_MODES] =3D { }; struct ad7768_state *st =3D iio_priv(indio_dev); + struct device *dev =3D indio_dev->dev.parent; unsigned long channel_mask; unsigned long standby_mask; + unsigned int max_freq; + unsigned int c; int ret; =20 + guard(mutex)(&st->lock); + + ret =3D ad7768_set_lowest_noise_mode(st, scan_mask); + if (ret =3D=3D -EINVAL) + return dev_err_probe(dev, ret, + "No power mode supports all ODRs\n"); + if (ret) + return ret; + channel_mask =3D ad7768_all_standby_mask(st); standby_mask =3D channel_mask & ~*scan_mask; ad7768_keep_xtal_channel_active(st, &standby_mask); =20 + for_each_set_bit(c, scan_mask, st->chip_info->num_channels) { + unsigned int mask; + int mode; + + mode =3D ad7768_find_matching_mode(mode_used, mode_freq, + st->ch_freq[c]); + if (mode < 0) + return dev_err_probe(dev, -EINVAL, + "Over %d channel modes required\n", + AD7768_NUM_CHANNEL_MODES); + + mode_freq[mode] =3D st->ch_freq[c]; + mode_used[mode] =3D true; + + mask =3D ad7768_channel_mode_mask(st, c); + ret =3D regmap_assign_bits(st->regmap, AD7768_REG_CH_MODE_SEL, + mask, mode); + if (ret) + return ret; + } + ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_STANDBY, channel_mask, standby_mask); if (ret) return ret; =20 + max_freq =3D 0; + for (unsigned int mode =3D 0; mode < AD7768_NUM_CHANNEL_MODES; mode++) { + if (!mode_used[mode]) + continue; + + ret =3D ad7768_set_mode_decimation(st, mode_freq[mode], mode); + if (ret) + return ret; + + ret =3D regmap_clear_bits(st->regmap, AD7768_REG_CH_MODE(mode), + AD7768_CH_MODE_FILTER_TYPE_MSK); + if (ret) + return ret; + + max_freq =3D max(max_freq, mode_freq[mode]); + } + + ret =3D ad7768_set_clk_divs(st, max_freq); + if (ret) + return ret; + + return ad7768_sync(st); +} + +static int ad7768_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D ad7768_apply_channel_modes(indio_dev, scan_mask); + if (ret) + return ret; + for (unsigned int ch =3D 0; ch < st->chip_info->num_channels; ch++) { if (test_bit(ch, scan_mask)) ret =3D iio_backend_chan_enable(st->back, ch); @@ -656,11 +780,10 @@ static void ad7768_set_available_sampling_freqs(struc= t ad7768_state *st) st->avail_freq[n_power_modes - 1].n_freqs--; } =20 -static int ad7768_configure_capture(struct ad7768_state *st) +static int ad7768_init_sampling_freqs(struct ad7768_state *st) { const struct ad7768_avail_freq *avail_freq; unsigned int default_freq; - unsigned int mode_config; int ret; =20 ret =3D ad7768_set_power_mode(st, ARRAY_SIZE(ad7768_power_modes) - 1); @@ -673,27 +796,7 @@ static int ad7768_configure_capture(struct ad7768_stat= e *st) channel < st->chip_info->num_channels; channel++) st->ch_freq[channel] =3D default_freq; =20 - ret =3D ad7768_set_mode_decimation(st, default_freq, 0); - if (ret) - return ret; - - mode_config =3D FIELD_PREP(AD7768_CH_MODE_FILTER_TYPE_MSK, - AD7768_CH_MODE_FILTER_TYPE_WIDEBAND); - ret =3D regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(0), - AD7768_CH_MODE_FILTER_TYPE_MSK, - mode_config); - if (ret) - return ret; - - ret =3D regmap_write(st->regmap, AD7768_REG_CH_MODE_SEL, 0); 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Wed, 16 Sep 2026 07:15:12 -0400 From: Janani Sunil Date: Wed, 16 Sep 2026 13:13:59 +0200 Subject: [PATCH v8 10/17] iio: adc: ad7768: Add sampling frequency controls Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260916-ad7768-driver-v8-10-27aa24db5225@analog.com> References: <20260916-ad7768-driver-v8-0-27aa24db5225@analog.com> In-Reply-To: <20260916-ad7768-driver-v8-0-27aa24db5225@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , "David Lechner" , Andy Shevchenko , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle , Randy Dunlap CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil , Jonathan Cameron X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Validate requests against the rates supported by the power mode tables and apply them when buffered capture starts. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 101 +++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 99 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index fc8226d5d556..1bd86dc41b2c 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -121,6 +121,9 @@ static const struct ad7768_power_mode_info ad7768_power= _modes[] =3D { { .mode =3D AD7768_POWER_MODE_POWER_MODE_FAST, .mclk_div =3D 4 }, }; =20 +#define AD7768_MAX_FREQS \ + (AD7768_MAX_FREQ_PER_MODE + ARRAY_SIZE(ad7768_power_modes)) + struct ad7768_precharge_config { bool prebufp_en; bool prebufn_en; @@ -157,10 +160,12 @@ struct ad7768_state { enum ad7768_clock_source clock_source; const struct ad7768_chip_info *chip_info; struct ad7768_avail_freq avail_freq[ARRAY_SIZE(ad7768_power_modes)]; + unsigned int n_freqs; + int freqs[AD7768_MAX_FREQS]; unsigned int ch_freq[AD7768_MAX_CHANNEL]; + unsigned int power_mode_idx; struct iio_backend *back; unsigned int vref_uV[2]; - unsigned int power_mode_idx; =20 /* Used only in regmap_read() callback, hence guarded by regmap lock. */ __be16 d16 __aligned(IIO_DMA_MINALIGN); @@ -525,6 +530,32 @@ static int ad7768_set_lowest_noise_mode(struct ad7768_= state *st, return -EINVAL; } =20 +static bool ad7768_freq_supported_in_any_mode(const struct ad7768_state *s= t, + unsigned int freq) +{ + for (unsigned int mode_idx =3D 0; + mode_idx < ARRAY_SIZE(ad7768_power_modes); mode_idx++) { + if (ad7768_find_freq_config(st, mode_idx, freq)) + return true; + } + + return false; +} + +static int ad7768_set_sampling_freq(struct iio_dev *indio_dev, + unsigned int freq, unsigned int channel) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + if (!freq || !ad7768_freq_supported_in_any_mode(st, freq)) + return -EINVAL; + + guard(mutex)(&st->lock); + st->ch_freq[channel] =3D freq; + + return 0; +} + static int ad7768_find_matching_mode(const bool *mode_used, const unsigned int *mode_freq, unsigned int freq) @@ -698,14 +729,63 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, switch (info) { case IIO_CHAN_INFO_SCALE: return ad7768_read_scale(st, chan, val, val2); + case IIO_CHAN_INFO_SAMP_FREQ: { + guard(mutex)(&st->lock); + *val =3D st->ch_freq[chan->channel]; + + return IIO_VAL_INT; + } default: return -EINVAL; } } =20 +static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long info) +{ + if (info =3D=3D IIO_CHAN_INFO_SAMP_FREQ) + return IIO_VAL_INT; + + return -EINVAL; +} + +static int ad7768_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + if (info =3D=3D IIO_CHAN_INFO_SAMP_FREQ) + return ad7768_set_sampling_freq(indio_dev, val, chan->channel); + + return -EINVAL; +} + +static int ad7768_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + if (info !=3D IIO_CHAN_INFO_SAMP_FREQ) + return -EINVAL; + + *vals =3D st->freqs; + *type =3D IIO_VAL_INT; + *length =3D st->n_freqs; + + return IIO_AVAIL_LIST; +} + static const struct iio_info ad7768_info =3D { .debugfs_reg_access =3D ad7768_reg_access, .read_raw =3D ad7768_read_raw, + .write_raw_get_fmt =3D ad7768_write_raw_get_fmt, + .write_raw =3D ad7768_write_raw, + .read_avail =3D ad7768_read_avail, .update_scan_mode =3D ad7768_update_scan_mode, }; =20 @@ -778,6 +858,20 @@ static void ad7768_set_available_sampling_freqs(struct= ad7768_state *st) if (st->datalines =3D=3D 1 && st->chip_info->num_channels =3D=3D AD7768_MAX_CHANNEL) st->avail_freq[n_power_modes - 1].n_freqs--; + + for (unsigned int mode_idx =3D 0; mode_idx < n_power_modes; mode_idx++) { + const struct ad7768_avail_freq *avail_freq; + + avail_freq =3D &st->avail_freq[mode_idx]; + for (unsigned int i =3D 0; i < avail_freq->n_freqs; i++) { + unsigned int freq =3D avail_freq->freq_cfg[i].freq_hz; + + if (st->n_freqs && st->freqs[st->n_freqs - 1] >=3D freq) + continue; + + st->freqs[st->n_freqs++] =3D freq; + } + } } =20 static int ad7768_init_sampling_freqs(struct ad7768_state *st) @@ -865,7 +959,10 @@ static int ad7768_parse_config(struct iio_dev *indio_d= ev, =20 chan[chan_idx++] =3D (struct iio_chan_spec) { .type =3D IIO_VOLTAGE, - .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE), + .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_separate_available =3D + BIT(IIO_CHAN_INFO_SAMP_FREQ), .indexed =3D 1, .channel =3D channel, .scan_index =3D channel, --=20 2.43.0 From nobody Fri Sep 25 05:30:00 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69D544F4749; Wed, 16 Sep 2026 11:15:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Group enabled channels by their requested sampling frequency and filter pairs and program each pair into one of the two hardware mode profiles. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 72 ++++++++++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 66 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 1bd86dc41b2c..b2e129e6fa33 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -104,6 +104,11 @@ #define AD7768_MAX_CHANNEL 8 #define AD7768_NUM_CHANNEL_MODES 2 =20 +enum ad7768_filter_type { + AD7768_FILTER_TYPE_WIDEBAND, + AD7768_FILTER_TYPE_SINC5, +}; + enum ad7768_clock_source { AD7768_CLOCK_SOURCE_MCLK, AD7768_CLOCK_SOURCE_XTAL, @@ -164,6 +169,7 @@ struct ad7768_state { int freqs[AD7768_MAX_FREQS]; unsigned int ch_freq[AD7768_MAX_CHANNEL]; unsigned int power_mode_idx; + enum ad7768_filter_type ch_filter[AD7768_MAX_CHANNEL]; struct iio_backend *back; unsigned int vref_uV[2]; =20 @@ -556,12 +562,59 @@ static int ad7768_set_sampling_freq(struct iio_dev *i= ndio_dev, return 0; } =20 +static int ad7768_set_filter_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + guard(mutex)(&st->lock); + st->ch_filter[chan->channel] =3D mode; + + return 0; +} + +static int ad7768_get_filter_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + return st->ch_filter[chan->channel]; +} + +static const char *const ad7768_filter_types[] =3D { + [AD7768_FILTER_TYPE_WIDEBAND] =3D "wideband", + [AD7768_FILTER_TYPE_SINC5] =3D "sinc5", +}; + +static const struct iio_enum ad7768_filter_types_enum =3D { + .items =3D ad7768_filter_types, + .num_items =3D ARRAY_SIZE(ad7768_filter_types), + .set =3D ad7768_set_filter_mode, + .get =3D ad7768_get_filter_mode, +}; + +static struct iio_chan_spec_ext_info ad7768_ext_info[] =3D { + IIO_ENUM("filter_type", IIO_SEPARATE, &ad7768_filter_types_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, &ad7768_filter_types_enum= ), + { } +}; + static int ad7768_find_matching_mode(const bool *mode_used, const unsigned int *mode_freq, - unsigned int freq) + const enum ad7768_filter_type *mode_filter, + unsigned int freq, + enum ad7768_filter_type filter) { for (unsigned int mode =3D 0; mode < AD7768_NUM_CHANNEL_MODES; mode++) { - if (!mode_used[mode] || mode_freq[mode] =3D=3D freq) + if (!mode_used[mode] || + (mode_freq[mode] =3D=3D freq && mode_filter[mode] =3D=3D filter)) return mode; } =20 @@ -571,6 +624,7 @@ static int ad7768_find_matching_mode(const bool *mode_u= sed, static int ad7768_apply_channel_modes(struct iio_dev *indio_dev, const unsigned long *scan_mask) { + enum ad7768_filter_type mode_filter[AD7768_NUM_CHANNEL_MODES] =3D { }; unsigned int mode_freq[AD7768_NUM_CHANNEL_MODES] =3D { }; bool mode_used[AD7768_NUM_CHANNEL_MODES] =3D { }; struct ad7768_state *st =3D iio_priv(indio_dev); @@ -599,13 +653,15 @@ static int ad7768_apply_channel_modes(struct iio_dev = *indio_dev, int mode; =20 mode =3D ad7768_find_matching_mode(mode_used, mode_freq, - st->ch_freq[c]); + mode_filter, st->ch_freq[c], + st->ch_filter[c]); if (mode < 0) return dev_err_probe(dev, -EINVAL, "Over %d channel modes required\n", AD7768_NUM_CHANNEL_MODES); =20 mode_freq[mode] =3D st->ch_freq[c]; + mode_filter[mode] =3D st->ch_filter[c]; mode_used[mode] =3D true; =20 mask =3D ad7768_channel_mode_mask(st, c); @@ -629,8 +685,9 @@ static int ad7768_apply_channel_modes(struct iio_dev *i= ndio_dev, if (ret) return ret; =20 - ret =3D regmap_clear_bits(st->regmap, AD7768_REG_CH_MODE(mode), - AD7768_CH_MODE_FILTER_TYPE_MSK); + ret =3D regmap_assign_bits(st->regmap, AD7768_REG_CH_MODE(mode), + AD7768_CH_MODE_FILTER_TYPE_MSK, + mode_filter[mode]); if (ret) return ret; =20 @@ -887,8 +944,10 @@ static int ad7768_init_sampling_freqs(struct ad7768_st= ate *st) avail_freq =3D &st->avail_freq[st->power_mode_idx]; default_freq =3D avail_freq->freq_cfg[avail_freq->n_freqs - 1].freq_hz; for (unsigned int channel =3D 0; - channel < st->chip_info->num_channels; channel++) + channel < st->chip_info->num_channels; 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Derive the delay from the selected output data rate and the datasheet filter-settling limits. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index b2e129e6fa33..bd0f5cdac187 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -103,6 +103,8 @@ #define AD7768_MAX_FREQ_PER_MODE 6 #define AD7768_MAX_CHANNEL 8 #define AD7768_NUM_CHANNEL_MODES 2 +#define AD7768_WIDEBAND_SETTLING_SAMPLES 68 +#define AD7768_SINC5_SETTLING_SAMPLES 7 =20 enum ad7768_filter_type { AD7768_FILTER_TYPE_WIDEBAND, @@ -621,6 +623,33 @@ static int ad7768_find_matching_mode(const bool *mode_= used, return -EINVAL; } =20 +static void ad7768_filter_wait(const unsigned int *mode_freq, + const enum ad7768_filter_type *mode_filter, + const bool *mode_used) +{ + unsigned int t_settle_us =3D 0; + + for (unsigned int mode =3D 0; mode < AD7768_NUM_CHANNEL_MODES; mode++) { + unsigned int t_mode_us; + u8 settling_samples; + + if (!mode_used[mode] || !mode_freq[mode]) + continue; + + if (mode_filter[mode] =3D=3D AD7768_FILTER_TYPE_SINC5) + settling_samples =3D AD7768_SINC5_SETTLING_SAMPLES; + else + settling_samples =3D AD7768_WIDEBAND_SETTLING_SAMPLES; + + t_mode_us =3D DIV_ROUND_UP(settling_samples * USEC_PER_SEC, + mode_freq[mode]); + t_settle_us =3D max(t_settle_us, t_mode_us); + } + + if (t_settle_us) + fsleep(t_settle_us); +} + static int ad7768_apply_channel_modes(struct iio_dev *indio_dev, const unsigned long *scan_mask) { @@ -698,7 +727,14 @@ static int ad7768_apply_channel_modes(struct iio_dev *= indio_dev, if (ret) return ret; =20 - return ad7768_sync(st); + ret =3D ad7768_sync(st); + if (ret) + return ret; + + /* Apply a filter settling time (datasheet Tables 28 and 29). */ + ad7768_filter_wait(mode_freq, mode_filter, mode_used); + + return 0; } =20 static int ad7768_update_scan_mode(struct iio_dev *indio_dev, --=20 2.43.0 From nobody Fri Sep 25 05:30:00 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFC714F7984; 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Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 119 +++++++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 113 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index bd0f5cdac187..e9462278a812 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -27,6 +27,7 @@ #include #include #include +#include #include =20 #include @@ -103,6 +104,8 @@ #define AD7768_MAX_FREQ_PER_MODE 6 #define AD7768_MAX_CHANNEL 8 #define AD7768_NUM_CHANNEL_MODES 2 +#define AD7768_CALIB_SIGN_BIT 23 +#define AD7768_CALIB_REG_MSK GENMASK(AD7768_CALIB_SIGN_BIT, 0) #define AD7768_WIDEBAND_SETTLING_SAMPLES 68 #define AD7768_SINC5_SETTLING_SAMPLES 7 =20 @@ -246,6 +249,18 @@ static void ad7768_keep_xtal_channel_active(const stru= ct ad7768_state *st, __clear_bit(st->chip_info->num_channels / 2, standby_mask); } =20 +static unsigned int ad7768_offset_reg(const struct ad7768_state *st, + unsigned int ch) +{ + return AD7768_REG_OFFSET(st->chip_info->chan_map[ch]); +} + +static unsigned int ad7768_gain_reg(const struct ad7768_state *st, + unsigned int ch) +{ + return AD7768_REG_GAIN(st->chip_info->chan_map[ch]); +} + static u8 ad7768_precharge_buf1_mask(const struct ad7768_state *st, u16 va= l) { return val & GENMASK(st->chip_info->prebuf_split - 1, 0); @@ -376,6 +391,67 @@ static const struct regmap_config ad7768_4_regmap_conf= ig =3D { .readable_reg =3D ad7768_4_readable_reg, }; =20 +static unsigned int ad7768_get_calib_reg_base(struct ad7768_state *st, + const struct iio_chan_spec *chan, + bool is_gain) +{ + if (is_gain) + return ad7768_gain_reg(st, chan->channel); + + return ad7768_offset_reg(st, chan->channel); +} + +static int ad7768_read_calib_value(struct ad7768_state *st, + unsigned int base_reg, bool is_signed, + int *val) +{ + unsigned int regval; + u8 data[3]; + int ret; + + PM_RUNTIME_ACQUIRE_AUTOSUSPEND(regmap_get_device(st->regmap), pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + guard(mutex)(&st->lock); + + ret =3D regmap_bulk_read(st->regmap, base_reg, data, sizeof(data)); + if (ret) + return ret; + + regval =3D get_unaligned_be24(data); + *val =3D is_signed ? sign_extend32(regval, AD7768_CALIB_SIGN_BIT) : regva= l; + + return 0; +} + +static int ad7768_write_calib_value(struct ad7768_state *st, + unsigned int base_reg, bool is_signed, + int val) +{ + u8 data[3]; + int ret; + + if (is_signed && + val !=3D sign_extend32(val, AD7768_CALIB_SIGN_BIT)) + return -EINVAL; + + if (!is_signed && (val < 0 || val > AD7768_CALIB_REG_MSK)) + return -EINVAL; + + put_unaligned_be24(val, data); + + PM_RUNTIME_ACQUIRE_AUTOSUSPEND(regmap_get_device(st->regmap), pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + guard(mutex)(&st->lock); + + return regmap_bulk_write(st->regmap, base_reg, data, sizeof(data)); +} + static int ad7768_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, @@ -818,6 +894,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long info) { struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; =20 switch (info) { case IIO_CHAN_INFO_SCALE: @@ -828,6 +905,19 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, =20 return IIO_VAL_INT; } + + case IIO_CHAN_INFO_CALIBBIAS: + case IIO_CHAN_INFO_CALIBSCALE: { + bool is_gain =3D info =3D=3D IIO_CHAN_INFO_CALIBSCALE; + unsigned int base_reg; + + base_reg =3D ad7768_get_calib_reg_base(st, chan, is_gain); + ret =3D ad7768_read_calib_value(st, base_reg, !is_gain, val); + if (ret) + return ret; + + return IIO_VAL_INT; + } default: return -EINVAL; } @@ -836,24 +926,39 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, long info) { - if (info =3D=3D IIO_CHAN_INFO_SAMP_FREQ) + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + case IIO_CHAN_INFO_CALIBBIAS: + case IIO_CHAN_INFO_CALIBSCALE: return IIO_VAL_INT; - - return -EINVAL; + default: + return -EINVAL; + } } =20 static int ad7768_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long info) { + struct ad7768_state *st =3D iio_priv(indio_dev); + unsigned int base_reg; + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); if (IIO_DEV_ACQUIRE_FAILED(claim)) return -EBUSY; =20 - if (info =3D=3D IIO_CHAN_INFO_SAMP_FREQ) + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: return ad7768_set_sampling_freq(indio_dev, val, chan->channel); - - return -EINVAL; + case IIO_CHAN_INFO_CALIBBIAS: + base_reg =3D ad7768_get_calib_reg_base(st, chan, false); + return ad7768_write_calib_value(st, base_reg, true, val); + case IIO_CHAN_INFO_CALIBSCALE: + base_reg =3D ad7768_get_calib_reg_base(st, chan, true); + return ad7768_write_calib_value(st, base_reg, false, val); + default: + return -EINVAL; + } } =20 static int ad7768_read_avail(struct iio_dev *indio_dev, @@ -1055,6 +1160,8 @@ static int ad7768_parse_config(struct iio_dev *indio_= dev, chan[chan_idx++] =3D (struct iio_chan_spec) { .type =3D IIO_VOLTAGE, .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_CALIBBIAS) | + BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), --=20 2.43.0 From nobody Fri Sep 25 05:30:00 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6B724FECC6; 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Derive the delay resolution from MCLK, power mode and decimation rate. Validate the requested delay and program the corresponding phase register when applying the active channel configuration. Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 136 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 136 insertions(+) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index e9462278a812..be2eb21c5b63 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -146,6 +146,12 @@ struct ad7768_freq_config { unsigned int dec_rate; }; =20 +struct ad7768_convdelay_params { + unsigned int shift; + unsigned int max_raw; + u64 step_ps; +}; + struct ad7768_avail_freq { unsigned int n_freqs; struct ad7768_freq_config freq_cfg[AD7768_MAX_FREQ_PER_MODE]; @@ -172,6 +178,7 @@ struct ad7768_state { struct ad7768_avail_freq avail_freq[ARRAY_SIZE(ad7768_power_modes)]; unsigned int n_freqs; int freqs[AD7768_MAX_FREQS]; + u64 ch_convdelay_ps[AD7768_MAX_CHANNEL]; unsigned int ch_freq[AD7768_MAX_CHANNEL]; unsigned int power_mode_idx; enum ad7768_filter_type ch_filter[AD7768_MAX_CHANNEL]; @@ -261,6 +268,12 @@ static unsigned int ad7768_gain_reg(const struct ad776= 8_state *st, return AD7768_REG_GAIN(st->chip_info->chan_map[ch]); } =20 +static unsigned int ad7768_phase_reg(const struct ad7768_state *st, + unsigned int ch) +{ + return AD7768_REG_PHASE(st->chip_info->chan_map[ch]); +} + static u8 ad7768_precharge_buf1_mask(const struct ad7768_state *st, u16 va= l) { return val & GENMASK(st->chip_info->prebuf_split - 1, 0); @@ -699,6 +712,99 @@ static int ad7768_find_matching_mode(const bool *mode_= used, return -EINVAL; } =20 +static int ad7768_get_convdelay_params(struct ad7768_state *st, unsigned i= nt ch, + struct ad7768_convdelay_params *params) +{ + const struct ad7768_freq_config *freq_cfg; + unsigned int dec_rate; + unsigned int mclk_div; + unsigned long mclk; + u64 mult; + + freq_cfg =3D ad7768_find_freq_config(st, st->power_mode_idx, + st->ch_freq[ch]); + if (!freq_cfg) + return -EINVAL; + + dec_rate =3D ad7768_dec_rate[freq_cfg->dec_rate]; + switch (dec_rate) { + case 32: + params->shift =3D 3; + params->max_raw =3D 31; + mult =3D 1; + break; + case 64: + params->shift =3D 2; + params->max_raw =3D 63; + mult =3D 1; + break; + case 128: + params->shift =3D 1; + params->max_raw =3D 127; + mult =3D 1; + break; + case 256: + params->shift =3D 0; + params->max_raw =3D 255; + mult =3D 1; + break; + case 512: + params->shift =3D 0; + params->max_raw =3D 255; + mult =3D 2; + break; + case 1024: + params->shift =3D 0; + params->max_raw =3D 255; + mult =3D 4; + break; + default: + return -EINVAL; + } + + mclk =3D clk_get_rate(st->mclk); + if (!mclk || mclk > U32_MAX) + return -EINVAL; + + mclk_div =3D ad7768_power_modes[st->power_mode_idx].mclk_div; + params->step_ps =3D + DIV_ROUND_CLOSEST_ULL(mult * PSEC_PER_SEC * mclk_div, (u32)mclk); + if (params->step_ps > U32_MAX) + return -EINVAL; + + return 0; +} + +static int ad7768_set_channel_convdelay(struct ad7768_state *st, + unsigned int ch) +{ + u64 delay_ps =3D st->ch_convdelay_ps[ch]; + struct ad7768_convdelay_params params; + u64 max_delay_ps; + u64 raw; + int ret; + + ret =3D ad7768_get_convdelay_params(st, ch, ¶ms); + if (ret) + return ret; + + /* + * Validate the requested delay before rounding so an out-of-range value + * cannot round down into the valid range. Then verify that the rounded + * value fits in the hardware register. + */ + max_delay_ps =3D (u64)params.max_raw * params.step_ps; + if (delay_ps > max_delay_ps) + return -EINVAL; + + raw =3D DIV_ROUND_CLOSEST_ULL(delay_ps, (u32)params.step_ps); + if (raw > params.max_raw) + return -EINVAL; + + return regmap_write(st->regmap, ad7768_phase_reg(st, ch), + raw << params.shift); +} + static void ad7768_filter_wait(const unsigned int *mode_freq, const enum ad7768_filter_type *mode_filter, const bool *mode_used) @@ -799,6 +905,16 @@ static int ad7768_apply_channel_modes(struct iio_dev *= indio_dev, max_freq =3D max(max_freq, mode_freq[mode]); } =20 + for_each_set_bit(c, scan_mask, st->chip_info->num_channels) { + ret =3D ad7768_set_channel_convdelay(st, c); + if (ret =3D=3D -EINVAL) + return dev_err_probe(regmap_get_device(st->regmap), ret, + "Invalid conversion delay for channel %u\n", + c); + if (ret) + return ret; + } + ret =3D ad7768_set_clk_divs(st, max_freq); if (ret) return ret; @@ -918,6 +1034,13 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, =20 return IIO_VAL_INT; } + case IIO_CHAN_INFO_CONVDELAY: { + guard(mutex)(&st->lock); + iio_val_s64_decompose(st->ch_convdelay_ps[chan->channel], + val, val2); + + return IIO_VAL_DECIMAL64_PICO; + } default: return -EINVAL; } @@ -931,6 +1054,8 @@ static int ad7768_write_raw_get_fmt(struct iio_dev *in= dio_dev, case IIO_CHAN_INFO_CALIBBIAS: case IIO_CHAN_INFO_CALIBSCALE: return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + return IIO_VAL_DECIMAL64_PICO; default: return -EINVAL; } @@ -942,6 +1067,7 @@ static int ad7768_write_raw(struct iio_dev *indio_dev, { struct ad7768_state *st =3D iio_priv(indio_dev); unsigned int base_reg; + s64 delay_ps; =20 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); if (IIO_DEV_ACQUIRE_FAILED(claim)) @@ -956,6 +1082,15 @@ static int ad7768_write_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_CALIBSCALE: base_reg =3D ad7768_get_calib_reg_base(st, chan, true); return ad7768_write_calib_value(st, base_reg, false, val); + case IIO_CHAN_INFO_CONVDELAY: { + delay_ps =3D iio_val_s64_compose(val, val2); + if (delay_ps < 0) + return -EINVAL; + + guard(mutex)(&st->lock); + st->ch_convdelay_ps[chan->channel] =3D delay_ps; + return 0; + } default: return -EINVAL; } @@ -1162,6 +1297,7 @@ static int ad7768_parse_config(struct iio_dev *indio_= dev, .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_CALIBSCALE) | + BIT(IIO_CHAN_INFO_CONVDELAY) | BIT(IIO_CHAN_INFO_SAMP_FREQ), .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), --=20 2.43.0 From nobody Fri Sep 25 05:30:00 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B346C4F4745; Wed, 16 Sep 2026 11:16:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789557393; 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Wed, 16 Sep 2026 07:15:27 -0400 From: Janani Sunil Date: Wed, 16 Sep 2026 13:14:04 +0200 Subject: [PATCH v8 15/17] iio: adc: ad7768: Add VCM regulator support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260916-ad7768-driver-v8-15-27aa24db5225@analog.com> References: <20260916-ad7768-driver-v8-0-27aa24db5225@analog.com> In-Reply-To: <20260916-ad7768-driver-v8-0-27aa24db5225@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , "David Lechner" , Andy Shevchenko , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle , Randy Dunlap CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil , Jonathan Cameron X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; 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Support the three fixed output levels and the supply-dependent AVDD1/2 setting. Keep the ADC runtime active while VCM is enabled and release the runtime PM reference when the output is disabled. Signed-off-by: Janani Sunil --- drivers/iio/adc/Kconfig | 2 +- drivers/iio/adc/ad7768.c | 162 +++++++++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 161 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 5164608fa418..c784bee0fd65 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -434,7 +434,7 @@ config AD7766 config AD7768 tristate "Analog Devices AD7768/AD7768-4 ADC driver" depends on SPI - depends on REGULATOR || COMPILE_TEST + select REGULATOR select IIO_BUFFER select IIO_BACKEND select REGMAP diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index be2eb21c5b63..33b1b124d4d1 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +51,10 @@ #define AD7768_POWER_MODE_LVDS_ENABLE BIT(3) #define AD7768_POWER_MODE_MCLK_DIV_MSK GENMASK(1, 0) =20 +#define AD7768_REG_GENERAL_CONFIG 0x05 +#define AD7768_GEN_CONFIG_VCM_SEL_MSK GENMASK(1, 0) +#define AD7768_GEN_CONFIG_VCM_PD BIT(4) + #define AD7768_REG_DATA_CONTROL 0x06 #define AD7768_DATA_CONTROL_SPI_RESET_1 0x03 #define AD7768_DATA_CONTROL_SPI_RESET_2 0x02 @@ -183,12 +188,158 @@ struct ad7768_state { unsigned int power_mode_idx; enum ad7768_filter_type ch_filter[AD7768_MAX_CHANNEL]; struct iio_backend *back; + struct regulator_dev *vcm_rdev; + unsigned int avdd1_uV; unsigned int vref_uV[2]; =20 /* Used only in regmap_read() callback, hence guarded by regmap lock. */ __be16 d16 __aligned(IIO_DMA_MINALIGN); }; =20 +static const unsigned int ad7768_vcm_voltage_table[] =3D { + 0, 1650000, 2500000, 2140000, +}; + +static int ad7768_vcm_list_voltage(struct regulator_dev *rdev, + unsigned int selector) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + + if (selector >=3D ARRAY_SIZE(ad7768_vcm_voltage_table)) + return -EINVAL; + + if (!selector) + return DIV_ROUND_CLOSEST(st->avdd1_uV, 2); + + return ad7768_vcm_voltage_table[selector]; +} + +static int ad7768_vcm_enable(struct regulator_dev *rdev) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + int ret; + + ret =3D pm_runtime_resume_and_get(regmap_get_device(st->regmap)); + if (ret < 0) + return ret; + + ret =3D regmap_clear_bits(st->regmap, AD7768_REG_GENERAL_CONFIG, + AD7768_GEN_CONFIG_VCM_PD); + if (ret) + pm_runtime_put_autosuspend(regmap_get_device(st->regmap)); + + return ret; +} + +static int ad7768_vcm_disable(struct regulator_dev *rdev) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + int ret; + + ret =3D regmap_set_bits(st->regmap, AD7768_REG_GENERAL_CONFIG, + AD7768_GEN_CONFIG_VCM_PD); + if (ret) + return ret; + + pm_runtime_put_autosuspend(regmap_get_device(st->regmap)); + + return 0; +} + +static int ad7768_vcm_is_enabled(struct regulator_dev *rdev) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + int ret; + + PM_RUNTIME_ACQUIRE_AUTOSUSPEND(regmap_get_device(st->regmap), pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + ret =3D regmap_test_bits(st->regmap, AD7768_REG_GENERAL_CONFIG, + AD7768_GEN_CONFIG_VCM_PD); + if (ret < 0) + return ret; + + return !ret; +} + +static int ad7768_vcm_set_voltage_sel(struct regulator_dev *rdev, + unsigned int selector) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + int ret; + + PM_RUNTIME_ACQUIRE_AUTOSUSPEND(regmap_get_device(st->regmap), pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + return regmap_update_bits(st->regmap, AD7768_REG_GENERAL_CONFIG, + AD7768_GEN_CONFIG_VCM_SEL_MSK, + FIELD_PREP(AD7768_GEN_CONFIG_VCM_SEL_MSK, + selector)); +} + +static int ad7768_vcm_get_voltage_sel(struct regulator_dev *rdev) +{ + struct ad7768_state *st =3D rdev_get_drvdata(rdev); + unsigned int val; + int ret; + + PM_RUNTIME_ACQUIRE_AUTOSUSPEND(regmap_get_device(st->regmap), pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD7768_REG_GENERAL_CONFIG, &val); + if (ret) + return ret; + + return FIELD_GET(AD7768_GEN_CONFIG_VCM_SEL_MSK, val); +} + +static const struct regulator_ops ad7768_vcm_ops =3D { + .enable =3D ad7768_vcm_enable, + .disable =3D ad7768_vcm_disable, + .is_enabled =3D ad7768_vcm_is_enabled, + .list_voltage =3D ad7768_vcm_list_voltage, + .set_voltage_sel =3D ad7768_vcm_set_voltage_sel, + .get_voltage_sel =3D ad7768_vcm_get_voltage_sel, +}; + +static const struct regulator_desc ad7768_vcm_desc =3D { + .name =3D "vcm", + .of_match =3D "vcm-output", + .regulators_node =3D "regulators", + .n_voltages =3D ARRAY_SIZE(ad7768_vcm_voltage_table), + .ops =3D &ad7768_vcm_ops, + .type =3D REGULATOR_VOLTAGE, + .owner =3D THIS_MODULE, +}; + +static int ad7768_register_vcm_regulator(struct device *dev, + struct ad7768_state *st) +{ + struct regulator_config config =3D { + .dev =3D dev, + .driver_data =3D st, + }; + int ret; + + /* + * Start with VCM disabled so each enabled state is paired with the + * runtime PM reference acquired by ad7768_vcm_enable(). + */ + ret =3D regmap_set_bits(st->regmap, AD7768_REG_GENERAL_CONFIG, + AD7768_GEN_CONFIG_VCM_PD); + if (ret) + return ret; + + st->vcm_rdev =3D devm_regulator_register(dev, &ad7768_vcm_desc, &config); + return PTR_ERR_OR_ZERO(st->vcm_rdev); +} + static const unsigned int ad7768_dec_rate[AD7768_MAX_FREQ_PER_MODE] =3D { 32, 64, 128, 256, 512, 1024, }; @@ -1534,11 +1685,13 @@ static int ad7768_probe(struct spi_device *spi) return dev_err_probe(dev, ret, "Failed to enable AVSS supply\n"); } =20 - ret =3D devm_regulator_get_enable(dev, "avdd1"); - if (ret) + ret =3D devm_regulator_get_enable_read_voltage(dev, "avdd1"); + if (ret < 0) return dev_err_probe(dev, ret, "Failed to enable AVDD1 supply\n"); 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This allows the GPIO driver to share the parent regmap and runtime power-management state. Reviewed-by: Bartosz Golaszewski Signed-off-by: Janani Sunil --- drivers/iio/adc/Kconfig | 1 + drivers/iio/adc/ad7768.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index c784bee0fd65..dea25315ed20 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -435,6 +435,7 @@ config AD7768 tristate "Analog Devices AD7768/AD7768-4 ADC driver" depends on SPI select REGULATOR + select AUXILIARY_BUS select IIO_BUFFER select IIO_BACKEND select REGMAP diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 33b1b124d4d1..1fb14907b2b7 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -1273,6 +1274,30 @@ static const struct iio_info ad7768_info =3D { .update_scan_mode =3D ad7768_update_scan_mode, }; =20 +static int ad7768_gpio_adev_init(struct ad7768_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); 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Signed-off-by: Janani Sunil --- Documentation/iio/ad7768.rst | 275 +++++++++++++++++++++++++++++++++++++++= ++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 277 insertions(+) diff --git a/Documentation/iio/ad7768.rst b/Documentation/iio/ad7768.rst new file mode 100644 index 000000000000..9f5fbcae7173 --- /dev/null +++ b/Documentation/iio/ad7768.rst @@ -0,0 +1,275 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +AD7768 driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +ADC driver for Analog Devices Inc. AD7768 and AD7768-4 devices. The module= name +is ``ad7768``. + +Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following chips are supported by this driver: + +* `AD7768 `_ - + 8-channel, 24-bit simultaneous sampling ADC +* `AD7768-4 `_ - + 4-channel, 24-bit simultaneous sampling ADC + +Supported features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Clock sources +------------- + +The master clock source is selected using the ``clock-names`` device tree +property: + +* ``mclk`` selects a CMOS clock on XTAL2/MCLK. CLK_SEL must be low and XTA= L1 + must be connected to DGND. +* ``xtal`` selects a crystal connected between XTAL1 and XTAL2. CLK_SEL mu= st + be high. The driver drives FILTER/GPIO4 high and keeps channel 4 on the + AD7768 or channel 2 on the AD7768-4 enabled to maintain crystal excitati= on. +* ``lvds`` selects a differential clock on XTAL1 and XTAL2. CLK_SEL must be + high. The driver drives FILTER/GPIO4 low before enabling the LVDS input. + +GPIO4 is reserved when ``xtal`` or ``lvds`` is selected. + +Power modes +----------- + +The AD7768 family supports three power and performance modes: + +* **Low power mode** - Optimized for lowest power consumption +* **Median mode** - Balanced power and performance +* **Fast mode** - Highest performance with maximum sampling rates + +The driver initializes the device in fast mode and uses the maximum fast-m= ode +output data rate as the default sampling frequency. + +When buffered capture starts, the driver selects the lowest-noise mode tha= t can +produce the requested output data rates for all enabled channels. Where ou= tput +data rates overlap, fast mode is preferred over median mode, and median mo= de is +preferred over low power mode. This prioritizes the lower RMS noise and hi= gher +dynamic range offered by a faster mode at the same output data rate. + +Data output configuration +------------------------- + +The devices support flexible serial data output configurations: + +AD7768 data lines +^^^^^^^^^^^^^^^^^ + +* 1 data line (DOUT0) - Standard single-lane output +* 2 data lines (DOUT0, DOUT1) - Dual-lane output for higher throughput +* 8 data lines (DOUT0-DOUT7) - Maximum throughput, one line per channel + +AD7768-4 data lines +^^^^^^^^^^^^^^^^^^^ + +* 1 data line (DOUT0) - Standard single-lane output +* 4 data lines (DOUT0-DOUT3) - Maximum throughput, one line per channel + +The number of data lines can be configured via the ``adi,data-lines-number= `` +device tree property. If omitted, the driver uses the maximum supported by= the +selected variant: eight lines for AD7768 and four lines for AD7768-4. + +Channel configuration +--------------------- + +Each channel can be individually configured with: + +Channel modes +^^^^^^^^^^^^^ + +* **Mode A** - First set of filter and decimation settings +* **Mode B** - Second set of filter and decimation settings + +The hardware provides two mode profiles (A and B), each holding one +(frequency, filter) combination. When buffered capture is started, +enabled channels are grouped by their configured (frequency, filter) +pair. Up to two distinct groups are supported; the driver automatically +assigns each group to a mode slot and programs the hardware accordingly. +If the enabled channels request more than two distinct pairs, buffer setup +fails and capture does not start. + +Precharge and reference buffers +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Per-channel buffer control for optimal signal integrity: + +* Positive input precharge buffer (``adi,prechargebuf-pos-enable``) +* Negative input precharge buffer (``adi,prechargebuf-neg-enable``) +* Positive reference buffer (``adi,refbuf-pos-enable``) +* Negative reference buffer (``adi,refbuf-neg-enable``) + +Common mode voltage +------------------- + +The VCM pin provides a buffered common-mode voltage output used to bias +the analog inputs. The driver exposes this as a standard voltage regulator +provider under a ``regulators`` subnode in the device tree. Supported +output voltage levels are: + +* (AVDD1 - AVSS) / 2 - Mid-supply (hardware default), reported as half the + voltage provided by ``avdd1-supply`` +* 1,650,000 =C2=B5V - 1.65V +* 2,500,000 =C2=B5V - 2.5V +* 2,140,000 =C2=B5V - 2.14V + +The regulator can be enabled and disabled at runtime using the standard +regulator framework interfaces. + +The VCM circuitry is associated with channel 0. When VCM is used externall= y, +``channel@0`` must be present in the device tree and channel 0 must remain +enabled in the active scan mask. Placing channel 0 in standby disables the= VCM +output. + +Filter types +------------ + +Two digital filter types are available: + +* **Wideband** - Optimized for wide bandwidth applications +* **Sinc5** - Fifth-order sinc filter for high rejection of out-of-band no= ise + +IIO backend support +------------------- + +The driver integrates with IIO backends (e.g., AXI ADC) for high-speed data +capture and DMA operations. Features include: + +* Automatic channel enable/disable based on scan mask +* CRC on data interface. CRC replaces the header every 4th output sample. +* High-throughput buffered data acquisition + +GPIO controller +--------------- + +The AD7768 includes a 5-pin GPIO controller for auxiliary digital I/O +operations. The GPIO pins can be configured as inputs or outputs. + +GPIO4 is reserved when a crystal or LVDS master clock is used. GPIO0 throu= gh +GPIO3 remain available in these configurations. + +Device attributes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following IIO attributes are available for each enabled channel: + +Voltage scale +------------- + +.. list-table:: + :header-rows: 1 + :widths: 40 60 + + * - Attribute + - Description + * - ``in_voltage_scale`` + - Scale in millivolts per least significant bit for signed 24-bit dat= a, + calculated as twice the differential reference voltage used by chan= nel + N divided by 2\ :sup:`24`. + +Sampling frequency +------------------ + +.. list-table:: + :header-rows: 1 + :widths: 40 60 + + * - Attribute + - Description + * - ``in_voltage_sampling_frequency`` + - Requested sampling frequency in Hz for channel N. Enabled channels = are + grouped into up to two profiles at capture time. + * - ``in_voltage_sampling_frequency_available`` + - Available sampling frequencies in Hz for channel N across all power + modes, based on the master clock frequency. Buffer setup fails if no + single power mode supports the frequencies requested by all enabled + channels. + +Filter configuration +--------------------- + +.. list-table:: + :header-rows: 1 + :widths: 40 60 + + * - Attribute + - Description + * - ``in_voltage_filter_type`` + - Requested filter type for channel N: "wideband" or "sinc5". It is + grouped with sampling frequency at capture time. + * - ``in_voltage_filter_type_available`` + - Available filter types for channel N: "wideband sinc5". + +Per-channel calibration +----------------------- + +.. list-table:: + :header-rows: 1 + :widths: 40 60 + + * - Attribute + - Description + * - ``in_voltage_calibbias`` + - Signed 24-bit two's complement channel offset register value. + * - ``in_voltage_calibscale`` + - Raw unsigned 24-bit channel gain register value. + * - ``in_voltage_convdelay`` + - Per-channel conversion delay. The driver exposes the sync phase off= set + value in seconds with picosecond precision. Resolution and valid ra= nge + depend on the decimation ratio in use (see datasheet + Table 32). + +Device buffers +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This driver supports IIO buffered data acquisition through IIO backends. +When used with compatible backends like the AXI ADC, it provides: + +* High-speed simultaneous sampling across all enabled channels +* Hardware-driven data capture +* DMA-based data transfer for minimal CPU overhead +* CRC error detection + +See :doc:`iio_devbuf` for more information about IIO device buffers. + +Example usage +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +.. code-block:: bash + + # Read current sampling frequency for channel 0 + cat /sys/bus/iio/devices/iio:device0/in_voltage0_sampling_frequency + + # Update sampling frequency for channel 0 + echo 8000 > /sys/bus/iio/devices/iio:device0/in_voltage0_sampling_frequen= cy + + # Read current filter type for channel 0 + cat /sys/bus/iio/devices/iio:device0/in_voltage0_filter_type + + # List available filter types for channel 0 + cat /sys/bus/iio/devices/iio:device0/in_voltage0_filter_type_available + + # Update filter type for channel 0 to wideband + echo wideband > /sys/bus/iio/devices/iio:device0/in_voltage0_filter_type + + # Buffer setup fails if enabled channels request more than two distinct + # (sampling frequency, filter type) combinations. + + # Read calibration scale for channel 0 + cat /sys/bus/iio/devices/iio:device0/in_voltage0_calibscale + + # Read conversion delay for channel 0 + cat /sys/bus/iio/devices/iio:device0/in_voltage0_convdelay + + +Unimplemented features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* CRC message every 16 samples (CRC_SEL configuration) - currently only + supports CRC every 4 samples diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index b02b879b053a..73c58cec7620 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -29,6 +29,7 @@ Industrial I/O Kernel Drivers ad7380 ad7606 ad7625 + ad7768 ad7944 ade9000 adf41513 diff --git a/MAINTAINERS b/MAINTAINERS index de91903b0b45..93eab996c529 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1663,6 +1663,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml +F: Documentation/iio/ad7768.rst F: drivers/iio/adc/ad7768.c =20 ANALOG DEVICES INC AD7780 DRIVER --=20 2.43.0