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Tue, 15 Sep 2026 04:35:15 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Akiva Goldberger , Gal Pressman , Leon Romanovsky , open list , , Mark Bloch , Saeed Mahameed , Shay Drory , Tariq Toukan Subject: [PATCH net V3 1/3] net/mlx5: devcom, Base component size on linked devices Date: Tue, 15 Sep 2026 14:34:57 +0300 Message-ID: <20260915113459.3934760-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260915113459.3934760-1-tariqt@nvidia.com> References: <20260915113459.3934760-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00029929:EE_|LV2PR12MB5824:EE_ X-MS-Office365-Filtering-Correlation-Id: d89cce0d-11af-4e66-79ef-08df131d7f1a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|23010399003|36860700016|18002099003|22082099003|10067099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: y7nvmiNhrB7IKeIpn2znlUdv9ep8VCuJhYs7gJ98sCG5dLB8nkEfk4UZopHUcIep5vmomz3+w65aIQW/fT31IHGc8LKtYNwMM81y8X9gdC+vb96Mdg891u5Eb8b0C0aqlUApjlWxa+DlHvQo0ipIbci1ZDj1ZPfNuqW5E7h3YMNB5islYKSCZ29fh/YijdR+1ww42mXK/xbs+t+hXAR6/NfsKgJAvCqcvTNL1h5Q/Vj2ipxg9LbFcPrqSBplnYVU1M15q7KsxJYMx5FyL8tZSsfvPSiwSolIT/Ru4gGZA7y7DS6XbHqE46IUbmMl4iKEE6ijjJVqeZgGDiQ1U1aUyQE3utdQi5gm1bGdroATU9liAfkmeEkfMpylR7yT0HbVXcYq3Wsa35Y91YM/rFJnR6ZuAExXmc3pmPiKuvwaa68M/TjDkayIPGOzy5f09XQt/ZYpi/A/7a9RTDnV19qhgCj4mBcfNpeDGfnSjemxCjd5v6Z0JlNqFMNM2xVq+3U6VKxBtV5xgUT4s7itS4g0DJzHaUyb+pD9dM6gELOAi5h+iRejLdatsWjHXnNL4p+aRD6jV8kBsi6vk+5DZ30t3eFP8zWZvZJIu/o/XXIWEInuEDdk5yhaCrNbcAUql3KU8NOdtl7MpujP+lp0pagDV3xX8gAuY4s38p5/VnQXRN7lBeXAQLoTUBXfYQwrmod6Q3tyFTyXqVXKOOOAP8abvg== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(23010399003)(36860700016)(18002099003)(22082099003)(10067099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2jHi3M0FcPIGi+78WDGcoaWi0giWuOLVlhtq05FbObR4/1ER3GjcPEMP4oXUy8NaVXkHA2j+scQ5fKcyJLHkKcA5Nhh+emmuDUQH7H1bjz3Wm/JpfxjOryuwaudjxBGBLHuwZPpIE2wl+pq60D9yHJi+NP+1Stuh8QKvC3CqIsDCpa/qyzwa82nABogHTw0LzZQmtdqrogz7iuFIHmcHbTGnXniEZ/0xQzIf6leIncBbFcPtF/TbR52xmO8kE9f4uuqrbcoSrgZaK9m5Z0bchrrW5gnEDx09TAuqvZg3XU54gZV5K2jI/z3Tmj7p0mltdNLvdtT0cIUr8pdDDn85rOkMK8o4TmM7wEiMYet4DY++g1wNl/ARwhFo531BjpZiulij0uDpu9wTCETW3c9SWIUD/I1mdadAD1WXaO6cZyxQqgjeXMKgjc766T6WLwgb X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2026 11:35:51.5374 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d89cce0d-11af-4e66-79ef-08df131d7f1a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029929.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5824 Content-Type: text/plain; charset="utf-8" From: Shay Drory mlx5_devcom_comp_get_size() returns the component's kref count. That kref is bumped in mlx5_devcom_register_component() under comp_list_lock, before the comp_dev is linked onto comp_dev_list_head under comp->sem. The event broadcast (mlx5_devcom_locked_send_event()) walks that list. Hence, a caller can read the expected size, but send_event won't be sent to all peers. In the SD group registration path, this lets a member broadcast its role-election event over an incomplete list, electing a primary that never completes the group, is never marked ready, and leaves the group with a stale primary. Track the number of linked comp_devs in a dedicated counter, maintained under comp->sem together with the list add/remove, and return it from mlx5_devcom_comp_get_size(). Fixes: 9bb1ac80738a ("net/mlx5: devcom, Add component size getter") Signed-off-by: Shay Drory Reviewed-by: Akiva Goldberger Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c b/drivers= /net/ethernet/mellanox/mlx5/core/lib/devcom.c index 64f92427602d..75855481522b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c @@ -37,6 +37,7 @@ struct mlx5_devcom_comp { struct mlx5_devcom_key key; mlx5_devcom_event_handler_t handler; struct kref ref; + int nr_devs; bool ready; struct rw_semaphore sem; struct lock_class_key lock_key; @@ -170,6 +171,7 @@ devcom_alloc_comp_dev(struct mlx5_devcom_dev *devc, =20 down_write(&comp->sem); list_add_tail(&devcom->list, &comp->comp_dev_list_head); + WRITE_ONCE(comp->nr_devs, comp->nr_devs + 1); up_write(&comp->sem); =20 return devcom; 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Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Akiva Goldberger , Gal Pressman , Leon Romanovsky , open list , , Mark Bloch , Saeed Mahameed , Shay Drory , Tariq Toukan Subject: [PATCH net V3 2/3] net/mlx5: SD, unload reps on shared FDB create error path Date: Tue, 15 Sep 2026 14:34:58 +0300 Message-ID: <20260915113459.3934760-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260915113459.3934760-1-tariqt@nvidia.com> References: <20260915113459.3934760-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F3:EE_|DS0PR12MB6440:EE_ X-MS-Office365-Filtering-Correlation-Id: af1e2e22-6af2-487a-5731-08df131d7afd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|36860700016|82310400026|1800799024|56012099006|10067099003|18002099003|22082099003|11063799006; X-Microsoft-Antispam-Message-Info: Wc81d0Df/Bllix/t+Ycm+P8BD9ClZuJZr5JInPlZd+6JFoB0+VjyDkJs9m00B9r3N5ejkRQJWgqeQQV627H05ygb6mtY/g2Xt9X/tb/Rv+V/n9izgKDRJ+1rY8R/3AuSt/0i23xlk5zIANSH4ryDaNYLb5qTdv4fUGQ9KyuDosr+itDq1hpEb2p/liScX56E3BozlMpoN3f6JMBuExL3LA6Lq0zhCM81VJ5R/x25jB6PGlpLH3H/d1EAwpwpcL72yf25mgxtrpAJZ3d4B/JekwR2WRnN5gwDYy5QQCT5p8i1S7p4jD/AlWUQfCIWXSiHDYbfqu3mcwpmtAoQ425nXQdKsBEyfaf54xQNVADBH5w2ak11jgshEbA3kH/c4izd44iDEGuHIWkRwtcJxQalq6mWRrdlZm9+21hmvxhegYN/DqbMrCfXg7PM13v+Q6iR2Lj3Bmb/wKpZH+lMQ73VaGeB+nzSvyndJCrwn6/Lvw+TOtEDJL2hhqJnJ6dzjlqW0zM5PMEctnk4oG/IXUuN8r+bnKO8gR2E7q8Z718+t1SkJjE+s22Z7gOaQrLVSBoFS28p7l7LLNJcBcTv6fScC5sDuXQZYiGwgWlZu0wXGJAcVuVez3DT3oWUXVEWHr+N3YkEgxNjWHHemBtc2L1mYVaq//bdXbwkNvN+nHqL/ylsuXvr2ax6NAvl+MOtAnucnU/Gxbkx4/DkGaE7k3jPQw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(376014)(36860700016)(82310400026)(1800799024)(56012099006)(10067099003)(18002099003)(22082099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9m3f2A9IUeaJUTc8mYafVI/Dir4QrCqHG218KdFSdadXYiUpobhbuPLymSMOWZEFJlTqLwpRivN1x1TnwPfm1sNOL3qom/gbTxm7X8etdEAVMIa5wz4epDFa4BeyhjiVSRiP21Bthk1NJr1LFOvoR5K9rRAiodOEQdBbAsnt5rYp+EZDyz/cQs8yNMxuSwgBtLoS2TNsP1JKiKiIzlp/ByOHA2v0fAbk8hpZ7bN52kX2UxoCJYq4fOLPT6nApKJuQKNCR0zidWspA/hCm6a1wNf2ibnd7umOF3A2ZqPzojfOV8lbY0UpzKE0O4osLdiiMorzxtt2fIIugJyXJ3fTKas4L9k4b+WIPQ/qcpZsv6tc74TBIoo2BTMta4POEOQ4hxSztQXfE3atjlfnLCZ6Iz+o2LghpCYU8bomVDIEqRoOAS7MUx0fhgflMwk8ahmW X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2026 11:35:44.6864 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af1e2e22-6af2-487a-5731-08df131d7afd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6440 Content-Type: text/plain; charset="utf-8" From: Shay Drory mlx5_lag_shared_fdb_create() sets sd_fdb_active on every group member before reloading the representors, so mlx5_lag_is_active() is already true and the guard in mlx5_esw_offloads_rep_load() does not skip the VF/SF reps. If the reload then fails, the error path clears sd_fdb_active and destroys the shared FDB, leaving the reps loaded while SD LAG is inactive - the state cited commit was written to prevent. Unload the reps in the error path as well. Fixes: 68c2dd59a6c7 ("net/mlx5: E-Switch, Tie rep load/unload to SD LAG sta= te") Signed-off-by: Shay Drory Reviewed-by: Akiva Goldberger Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c b/dri= vers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c index 6b4ad3c53f2f..424040918fa3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c @@ -270,6 +270,7 @@ int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev, pf->sd_fdb_active =3D false; } mlx5_lag_destroy_single_fdb_filter(ldev, group_id); + mlx5_lag_unload_reps_from_locked(ldev, filter); } err_add_devices: mlx5_lag_add_devices_filter(ldev, filter); --=20 2.44.0 From nobody Fri Sep 25 07:56:19 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011071.outbound.protection.outlook.com [40.107.208.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DA594E56C4; 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Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Akiva Goldberger , Gal Pressman , Leon Romanovsky , open list , , Mark Bloch , Saeed Mahameed , Shay Drory , Tariq Toukan Subject: [PATCH net V3 3/3] net/mlx5: LAG, reload IB reps of LAG master before the rest Date: Tue, 15 Sep 2026 14:34:59 +0300 Message-ID: <20260915113459.3934760-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260915113459.3934760-1-tariqt@nvidia.com> References: <20260915113459.3934760-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075ED:EE_|CY0PR12MB825472:EE_ X-MS-Office365-Filtering-Correlation-Id: 0556b786-958b-485c-57ab-08df131d7f13 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|82310400026|1800799024|36860700016|11063799006|56012099006|10067099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: bdhMpgwwMH1+6cEx1fqvOrDUi37L3lXBP/svX0YlSwkGrfG05qI5h54AH5M6+mi71aM+vh90dcf4aSbVGNUy9A6L1+0j9NydQN7lz/gIAeuN7o4yrZL6/iPq+P2i7oaAXLICX39GtevkkoD3rfg12BYikOUuaPBna02zKIAmdlnm9U69K6QPODoN2xZm/aMUN9o0boBsmhGTJxriGpNB/cnn3mNfKLyHw4CxLthCQ4dXBh2uGnpgVRobHP1/sjuQFXM1TVOc2Ra/KBZ39FB8pcxUvj7Jx+K6ExCnp6gwjxQd62IhF4KDcQPxuomHEA0LkIs4S50ULTDMzuwJ10S5SjpAHRm+NZ0IyAk+kR2uxaRgNHm7f23X+vY3ArKPJijRlxk0W7OyFySwR+EMHJLrrDLYWzXIwJcmh63kpu9TppBi6XD+Bo0bRJuiF0Iuhf05nYnUWZFaVghs8OdSQ9llfJTdVIv+3aVc8wzZVJxQZIN2WmirZbZjqxWybALPRYehk62TwLGpzOWQTYU1cXBfS1z4M0rN0DNbwTB7sdR5jNjORdWFNYUV2wkmLfdhIl79+zSrqY80PG1quvyZ6N5HRuT8wd0k/VqyjtVzM68KpZjLmOZ6B3WycQOeD4F3AOexOQOMHtTCEa9KFKLEZNLHo36o6sDAI1YL6skPL2N30rAzpnyfbjv/OjQ6rGibQ5JCd5qCffY/N+9maOhz8DaYxg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(23010399003)(82310400026)(1800799024)(36860700016)(11063799006)(56012099006)(10067099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mlBcC81HQsD3GBrU5AHbaYqvkpmdStpDu9hQShA77QVp0A5GzceEAX0saKIm2HZNg4KKWJ8zDX/nm4IGk7wG/LIB+OJZ1vTUP5ylpRMI3Po90hM06j1xFJgQ6tglLTxR1+HGQNYke6ua4L7+H3yBuYg9/qRjP6hxRQycKV49q9MhsYmhvb+eex/4TqFZaMbjaNc06o7gD+jGdSq4CjwuNTG69WRHGNkMwQZ6PkYL5gjS4/GNg6zOffWpq6QXVCJ22/rJKi2Dw17zwDzPVkkmTKZnkI402kGQYp3SG0X6M1FjRwQHpulN/lOcykKpVjEiWaT2FDoF9cmg+PCJj8xtyL3pMOI/648AnKUpVPQr2cY7u6m/fXNPd+bf5fVDcjoM7viAJQl3zwHheu88PpfF3akJDHEqN+gk57Mngx/CjVUdB2MyZ5jTM3PQ6olfy9vL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2026 11:35:51.5460 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0556b786-958b-485c-57ab-08df131d7f13 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075ED.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY0PR12MB825472 Content-Type: text/plain; charset="utf-8" From: Shay Drory In a shared-FDB LAG the master device creates the bond IB device; the other LAG members do not create their own, they populate a port inside the master's IB device. mlx5_lag_reload_ib_reps_unlocked() reloaded the members' IB reps in iteration order, with no guarantee the master is reloaded first. When a non-master member is reloaded before the master, it tries to populate its port in an IB device that has not been recreated yet. Hence, reload the master's IB reps first, then every other member. Fixes: 2b204cdb1206 ("net/mlx5: LAG, use xa_alloc to manage LAG device indi= ces") Signed-off-by: Shay Drory Reviewed-by: Akiva Goldberger Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 44 ++++++++++++++----- 1 file changed, 32 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index c655f6e32e9b..dd14cdc378de 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -1266,25 +1266,45 @@ void mlx5_lag_remove_devices(struct mlx5_lag *ldev) mlx5_lag_remove_devices_filter(ldev, MLX5_LAG_FILTER_PORTS); } =20 +static int mlx5_lag_reload_ib_reps_idx(struct mlx5_lag *ldev, int idx, + u32 flags) +{ + struct lag_func *pf =3D mlx5_lag_pf(ldev, idx); + struct mlx5_eswitch *esw; + int ret; + + if (pf->dev->priv.flags & flags) + return 0; + + esw =3D pf->dev->priv.eswitch; + mlx5_esw_reps_block(esw); + ret =3D mlx5_eswitch_reload_ib_reps(esw); + mlx5_esw_reps_unblock(esw); + + return ret; +} + static int mlx5_lag_reload_ib_reps_unlocked(struct mlx5_lag *ldev, u32 fla= gs, u32 filter, bool cont_on_fail) { - struct lag_func *pf; + int master_idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, + filter); int ret; int i; =20 + if (master_idx < 0) + return -EINVAL; + + ret =3D mlx5_lag_reload_ib_reps_idx(ldev, master_idx, flags); + if (ret && !cont_on_fail) + return ret; + mlx5_lag_for_each(i, 0, ldev, filter) { - pf =3D mlx5_lag_pf(ldev, i); - if (!(pf->dev->priv.flags & flags)) { - struct mlx5_eswitch *esw; - - esw =3D pf->dev->priv.eswitch; - mlx5_esw_reps_block(esw); - ret =3D mlx5_eswitch_reload_ib_reps(esw); - mlx5_esw_reps_unblock(esw); - if (ret && !cont_on_fail) - return ret; - } + if (i =3D=3D master_idx) + continue; + ret =3D mlx5_lag_reload_ib_reps_idx(ldev, i, flags); + if (ret && !cont_on_fail) + return ret; } =20 return 0; --=20 2.44.0