From nobody Fri Sep 25 07:56:39 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADEF238C438; Tue, 15 Sep 2026 10:36:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789468606; cv=none; b=WBAc5ljX5Nt3TfQcJkDumC0oygnaGE6ffU6zCJKz+IjJv/pEIU91UJP6FK2kM2q9Oc1hSsCpfVWwapUmjjTLKCQk/s7t1uBYpDSTx+LbuRMi/lYz7i03hxZ6OC+XND9bEN+3KyfJBac+g0JUCZnxJ7iRALh7gstwXbPMnqqAUYE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789468606; c=relaxed/simple; bh=Q3OkuS7N/l3ssQFyXrs+rq4u1D327NteZulqsS2CVFk=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=tMh7+7Z35weS09G6buaoFA5BMr1zg8CQb0a5l1t7JC2I2Nt6mdHgI5Qovd7x5iYKC2DpOgzWqu4XNF8pxiHAWxD1OAf3YFxm5UMn2d8XWXlm0MwbP8PjycNsj5xQC2AnZ+BK84Lk4y4MLhRbsgR9uzKNFBnnE4bQBeachNzUsK4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=pass smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=Jm3Jx9a6; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="Jm3Jx9a6" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 60FCA477DB6; Tue, 15 Sep 2026 12:36:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1789468601; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding; bh=K2vfaOnFC7/1nB20cS53MVssmSMJc4X+W5RiRjOHV4U=; b=Jm3Jx9a6tYw3fTkcU6hTEPftfoIJK9sHuHZJ7rCc5E5UCLe296b3E4aja8sRYUIOiZi86A AIe+e0BgxtP57oUV95thz3/BAcCqks+Q7yVN5/PcihFn9WPJzUyNPfkALTMam0HW3eR/1D oeIxGrM33tEnX0PE0kGgGXL2ondBiiMin3qXXiv8DK+94Ff836IORKyOiJwcE5zXUUi7To km+WTfLFNBiZyEcsJrf1v001kqWUrzr8HQgU2pB6cUEe8qw8plo4xxpM55s0W3Dqza+Xp8 mtpLH3XCcRko/SxQCg2hzBh9ZXjCbsQvj7ucR9W+rBOOEUl+eT9X7xst+AvVqQ== From: Caleb James DeLisle To: netdev@vger.kernel.org Cc: daniel@makrotopia.org, dqfext@gmail.com, SkyLake.Huang@mediatek.com, andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Caleb James DeLisle , Matheus Sampaio Queiroga Subject: [PATCH v4 net-next] net: phy: mediatek: support MT7530 PHYs on EN71221 MCM Date: Tue, 15 Sep 2026 10:35:50 +0000 Message-Id: <20260915103550.79957-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The EcoNet EN751221 multi-chip module implementation of the MT7530 requires some additional configuration of the PHYs on startup. The reason for this is not known, but it is possible that it has to do with the fact that the EN751221 MCM implementation of the MT7530 runs at an abnormal PLL frequency (362.5Mhz). Detect whether the MT7530 PHY is attached to the MDIO bus of an EcoNet EN751221 switch and if so, apply the necessary register updates. Additionally, never attempt to configure an MT7530 identified PHY which does not have gigabit support because the same ID is used for another (FE) PHY. Co-developed-by: Matheus Sampaio Queiroga Signed-off-by: Matheus Sampaio Queiroga Signed-off-by: Caleb James DeLisle --- drivers/net/phy/mediatek/mtk-ge.c | 77 +++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/net/phy/mediatek/mtk-ge.c b/drivers/net/phy/mediatek/m= tk-ge.c index 96d8ac5154e5..07687b0aa59d 100644 --- a/drivers/net/phy/mediatek/mtk-ge.c +++ b/drivers/net/phy/mediatek/mtk-ge.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include @@ -101,6 +102,65 @@ static int mt7530_phy_config_init(struct phy_device *p= hydev) return 0; } =20 +/* + * The EcoNet EN751221 "G" multi-chip module MT7530 requires additional PHY + * configuration. + */ +static int en751221_mcm_phy_config_init(struct phy_device *phydev) +{ + int ret; + + ret =3D genphy_soft_reset(phydev); + if (ret) + return ret; + + ret =3D phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_1, + MTK_PHY_AUX_CTRL_AND_STATUS, 0x3a04); + if (ret < 0) + return ret; + + /* Clause 45 global/local data from mt7530GePhyCfgLoad(E3.0). */ + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x0417, 0x7775); + if (ret < 0) + return ret; + + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x00a6, 0x0350); + if (ret < 0) + return ret; + + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0012, 0xd210); + if (ret < 0) + return ret; + + return mt7530_phy_config_init(phydev); +} + +static bool en751221_is_mcm_phy(struct phy_device *phydev) +{ + struct device *parent =3D phydev->mdio.bus->parent; + + return parent && parent->of_node && + of_device_is_compatible(parent->of_node, "econet,en751221"); +} + +/* + * MTK_GPHY_ID_MT7530 ID is also used for an EcoNet SoC FE phy, but that P= HY + * does not advertise ESTATUS_1000_TFULL. + */ +static int mt7530_phy_match(struct phy_device *phydev, + const struct phy_driver *phydrv) +{ + return (phy_read(phydev, MII_ESTATUS) & ESTATUS_1000_TFULL) !=3D 0 && + !en751221_is_mcm_phy(phydev); +} + +static int en751221_phy_match(struct phy_device *phydev, + const struct phy_driver *phydrv) +{ + return (phy_read(phydev, MII_ESTATUS) & ESTATUS_1000_TFULL) !=3D 0 && + en751221_is_mcm_phy(phydev); +} + static int mt7531_phy_config_init(struct phy_device *phydev) { mtk_gephy_config_init(phydev); @@ -135,6 +195,23 @@ static struct phy_driver mtk_gephy_driver[] =3D { */ .config_intr =3D genphy_no_config_intr, .handle_interrupt =3D genphy_handle_interrupt_no_ack, + .match_phy_device =3D mt7530_phy_match, + .suspend =3D genphy_suspend, + .resume =3D genphy_resume, + .read_page =3D mtk_phy_read_page, + .write_page =3D mtk_phy_write_page, + }, + { + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530), + .name =3D "EcoNet EN751221 MCM PHY", + .probe =3D mt7530_phy_probe, + .config_init =3D en751221_mcm_phy_config_init, + /* Interrupts are handled by the switch, not the PHY + * itself. + */ + .config_intr =3D genphy_no_config_intr, + .handle_interrupt =3D genphy_handle_interrupt_no_ack, + .match_phy_device =3D en751221_phy_match, .suspend =3D genphy_suspend, .resume =3D genphy_resume, .read_page =3D mtk_phy_read_page, --=20 2.39.5