From nobody Fri Sep 25 07:56:18 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 502E8332601 for ; Tue, 15 Sep 2026 08:05:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.225.76 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789459513; cv=none; b=XXvnDtGrnoDCFqCrDKflEBRLQmnx2g2ZMnyuij7cGo2eZGXp7njdRhq8a3E9IyMwOw9Z09znlaPi9TCA5Z7txx7zPtWnNkeR1f0leRkIkp0yPxKRx+IrwPj0OD6IuNX9eODL3tdQFfZ9ljteB1nxUzb/QRnupN2OX1MNCfiZcig= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789459513; c=relaxed/simple; bh=jPCS3jau8LEmDTrYHNirj4CmDgyzg7ELGoC7TYTJC8M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Aca18O7kOHr23OSmThinUWV33n7ZTx8W7198WlxaZ6CRrfYHCAwjx/b9Nwn3oZyBAm7jCHcWnLvjCBi7r7kmsvHuYpiMCfDJ/nbHKUr81URVzcZAl+3viJiSOEKBVGsmZ7BWMnmS8vDjsbrw6QeaGTpGuj0GjCm8Qs3Cf5YyryU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=q6uXx3cM; arc=none smtp.client-ip=74.125.225.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="q6uXx3cM" Received: by mail-wr2-f12.google.com with SMTP id ffacd0b85a97d-485933b2522so2352113f8f.0 for ; Tue, 15 Sep 2026 01:05:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1789459505; x=1790064305; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=71D314ftdlfb4St+4Xu8DWbrNAQlQ6pwzo/wolPd+lI=; b=q6uXx3cMnb1Ovbmg3f95ZqdbuIwZN3p7tKyp9YF0OB2S3WOzoN8awK1xzun4ckWAmC BSS5UV4/yUz1vDV6P6J4zj/6ps4kUrvMboNxwVwAbqVGR+ZI1dw30IazEOgQ2891telv igqpz/8EycMqaoJlJCFBT6Z2Flv21ipyT0vX3S8FQiFl23par0IvYLdr53rvPp2E4SY9 1DA6dcKeWqtMT03iqSCe6Uu7iydXvkSMzbj2IGuOrIVeaZVKjduVfT/uEhcR5m+WwOiV R9vtcbC1xPf9pNeedsrUNap3aWWD7w00OmQW3okYKMjE9MOt72roEO/EXLVOn+4qKIzf 1G5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1789459505; x=1790064305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=71D314ftdlfb4St+4Xu8DWbrNAQlQ6pwzo/wolPd+lI=; b=kzsem9Cuf1Hf0KakBqfZFDF6zd7WXo2VX3HpGWsyuNeNOirbEJamyo41Y/pFnkJ0D2 8MyuA88t9VubEpRB900ZJLGLqJL4skIfSmDOo0ped6oZg0XlQELrcw0eT4VeQanZuXbQ orFvCE3dJS1einVMRQ1i7i6Gm6l5Iko8xOUKAXpoFcRg6zZ0rW1Nfd0FzBcf/mOxrASm JuS7wDO7IQAmO1E2BZtuthqx/5pssNhJzzBAhAbjil+LtIqqaS0eSKrUcH27GLFxKZUN kfFCd+Ph26mM10DY0ZNv998zYtYldZqxI2auyK6E8blvsWS7WzHpbFdC7JBppoiN598F 4VKw== X-Forwarded-Encrypted: i=1; AKwUvBwotSig9RMc0hvh9KD8F7CJ1XBnZOcg4nlBa8O8hAo18O9duDbvPHyITdygPeyMeXttgsU3JfKygfRUGZw=@vger.kernel.org X-Gm-Message-State: AFuF++ny1WoLiHSAMFOzaxAKtF7pJ+eXaF3tJBNucklD8bS6j9DyYsrl 5WRSotRSCIQ4dx7MTmkwOrBLuVbahSK86Q/1SkubVe8bX8TX1mUyMrTw X-Gm-Gg: AYBFou0nfx6Z2Jp49Y2B21roGB4w9FyE/SMhjAGrc14ipovWmfaAqwB5NH6pxnHak97 pBQQc5qhNzFVZbbz5zQ9Gha81S4iRjNmoOaGT4o9uxbvOUpf6T85wKAR7OOONt4uznG+6Ir7dvt RwuJWhVN/3ApJweBxRbtPTck5Fq66rixIIa8fH/ew0Uz0zXP0I5fgUPpK9O7BW97Ap3CYWB5UyW 8s6rFwZi6eSw5qJWLr5saHp4GY2Tdbc3AkN7VQMfSqkrAD9hYf7RaHiT//sX5/gorMex9E4Kz67 Op+wEKJzghcTTDFH5WDoTC/zzA8DRHhSO8VWgim9eUmO0uwjPStPBEhYsN6WE56VDP7dg5a8D5G 8mUugmoFBzvf7IlaNcRjSuBHj8nWh6QnUZU9jOxSFHXSdRgLJ58JlBZHWALefRDxpHlX5hfK27t wOaElGggCfOrbvHQgQvPtALc1Lmlu53M5+Tcb2TE1SnoC9LFHfmJSr+TIM+7MhwpwhsDYiYba7a YGzLPQVEtHyGWY= X-Received: by 2002:a05:600c:1909:b0:49c:f89b:f82 with SMTP id 5b1f17b1804b1-49e7a677ab1mr118558985e9.12.1789459504354; Tue, 15 Sep 2026 01:05:04 -0700 (PDT) Received: from deb05.proceq.com ([213.160.61.66]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e7d27315csm48588365e9.2.2026.09.15.01.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 01:05:03 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Haibo Chen , Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH v6 1/4] pinctrl: make the CONFIG_PINCTRL=n gpio config stubs return -ENOTSUPP Date: Tue, 15 Sep 2026 10:04:58 +0200 Message-ID: <20260915080501.329424-2-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260915080501.329424-1-mehmet.fide@gmail.com> References: <20260915080501.329424-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide With CONFIG_PINCTRL=3Dn, pinctrl_gpio_get_config() and pinctrl_gpio_set_config() are stubs that return 0. The getter reports success without touching the config it was asked to fill, so a caller reads the packed parameter it passed in back as if it were the pin's state; the setter reports success for a configuration nobody applied. With CONFIG_PINCTRL=3Dy the same callers already get -ENOTSUPP from gpiochip_generic_config() and gpiochip_generic_get_config() for a chip without pin ranges, and gpiolib treats that value as "the backend cannot do this" and carries on. Return it from the stubs too, so a kernel without pinctrl behaves like a chip without pin ranges instead of claiming success. Suggested-by: Haibo Chen Signed-off-by: Mehmet Fide Reviewed-by: Bartosz Golaszewski --- include/linux/pinctrl/consumer.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consu= mer.h index 11b8f0b8da0c..7be49d447426 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -107,14 +107,14 @@ static inline int pinctrl_gpio_get_config(struct gpio_chip *gc, unsigned int offset, unsigned long *config) { - return 0; + return -ENOTSUPP; } =20 static inline int pinctrl_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config) { - return 0; + return -ENOTSUPP; } =20 static inline struct pinctrl * __must_check pinctrl_get(struct device *dev) base-commit: 7257c35db0fdb4fb02d857a8197a16afa84d92c0 --=20 2.55.0 From nobody Fri Sep 25 07:56:18 2026 Received: from mail-wm2-f12.google.com (mail-wm2-f12.google.com [74.125.225.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA2E1361668 for ; Tue, 15 Sep 2026 08:05:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.225.140 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789459513; cv=none; b=MvxXrqWrHewpTNRp+FW7098tXHkPuuEt+0alPdI4kq42Kj8zfxD1sGkufYPQXgh8GEpsZY7Xx42WHEdA3m5x8U2+qScahtEsoczmWyGoL9l5h2xM69USF9w1cPHQWm200+CZ+sOm6tp9nG0ZYneO3NE1psGculbWimfzUDmT2zc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789459513; c=relaxed/simple; bh=mUeECvre9N/g2AeEciKDvfrTAyCAo+pbekzbwT4/uBk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RNz4pScp+tqs6f6qpCjqQvvBYTyq2J5NWL9wSyfiZ/SoU2Sk84eJsWr0tt/LBIuO8ag10NQpvLw0wGj/v9Rf7+Nop1hkdSqATwjdHTZ7l0CM6pLGrUiHRJuHwmePCHk6gNk49TYkLadMfB5lTK16ytFWpcol9s2fFUsTTXATXiY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=b2Sf0p5b; arc=none smtp.client-ip=74.125.225.140 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="b2Sf0p5b" Received: by mail-wm2-f12.google.com with SMTP id 5b1f17b1804b1-49cd4ba9f68so190575e9.1 for ; Tue, 15 Sep 2026 01:05:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1789459506; x=1790064306; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=rh1GYOmyo/w6ySQPuPwCmll79vIZ+StwKSaTeDc/e6E=; b=b2Sf0p5b1fnEYh6hJcuDuGGyDG8qzy+i3ZHdDuWBZUPgqucR513FU+zFKrdlsabAt9 qT4fuR0Lz1Yw6Xk21U3pReeNOdQ94LG/xo9YHdODtXjDmtt52pz5appMjzqyzuu3fs+Y KW29O4o4fPESnrYLgFgSenjgvdqQZMK81pPRCIi2wN80IXeLHZokStZxJ0Ayquwldzop LYr1wdmhJ5IMjpKPD4EXKNY8X2VQJIKgAafH2HD7GjfRS2ZLaJqpgkLf32xIk1ozvFpp GB2RlDRncQD7+0LSQwdw8/SjVGnT+5nljY4qFc+gmexO5PpK5SRATeC5OOPLF7Acgxeu GzSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1789459506; x=1790064306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=rh1GYOmyo/w6ySQPuPwCmll79vIZ+StwKSaTeDc/e6E=; b=JDPAYsCsQwq1kuEUu7csqU69z26KzmVXLABG5fReMdjO9CV1DC+iGjHEt2OYz0YVKN m9BLznOLINuFEvcQ6diBFaTey8ifHAvvxSkj+E9WfSehxh6ZKH+vWUiiwwQ/GTvxFuac awwZrhC7/Rbu/mjbKmx6Eyt9SM1P7Mvp+VogzD5NXbx9LFN+NEXvwdOfLIhoezdGBAPn 0BFiBm0Eb1k1Nw4I7GQ+wVh9rUUXxJTJ/ecoI7D1gaaEiQYWK7rwpF9ElCZUeZkAeKpE urYxaA6pNty+8kFf9R55oJA0i8/3AtsQCSIRU2cvhnBW5igbHJCRyZU2V46Jqxs8eBXo 3IKw== X-Forwarded-Encrypted: i=1; AKwUvBzodg2EiQy1vaEcAeK89HJlyMKPZeLs/trbOSLWlJIK98id7qO5m/IixwhgUMSpTRC6UHBu6KHJVHNNVfQ=@vger.kernel.org X-Gm-Message-State: AFuF++lCzPZJfU5TKDx1xGjuXBsCytelXCq7s61INMsSOUh2JHGqYlY5 1s7wagg+1v2dB0HOFtdGOJkjwuZnjwM3rDs5OMXVvt5L3kZgSPyJkoSU X-Gm-Gg: AYBFou0c5WqiIiyqcCZNpKWNlViFezV/Guu6Rf5SGdPXC3uez3aS1VGBVfZkxPN6waD MeSfz9vpA7Rx4c2jhk+Vpt9hEkhOJMw3yP/rdfKc5+mGwaZfcHH7MfkCPdi0SP1sUb2Pyy9GduX 3ifSsXIsDGFmSmdXwh0gjjj8b7NFoMwc/FGjOH954JMgmooT2Ycn8Vo3fPX3Isu/NlL8tOQrrAl HpVmoIuRVI0Z2oK8k4UYZZod+gVyZJpZ9WG4J3Lq86SyZ2iKy7KmBFyKIxQMg85IpRhK5VaEfn6 KSoJvq8ISp9LGPo36DiD325Zas33UVzLMgjALG6a+okJvdBtebWJZ/4PBl0s3av4ECVB4dy7m9W Yskgt0zDT24Jx7y05O1DV3w7OwSCHPkrJVygC5VrG3JZJutcuBETk41jF5smD24AYjm0DjObVOH lP6oWrAbE/D7qg0Ck2eglUX+Cg9z54fUN9E8pLiPDWe8rqfWyQxYCsKjeEpUCWGjUHoXVMymMsZ nIPAFJbRAcKXXA= X-Received: by 2002:a05:600c:4f46:b0:49c:cfbe:5a76 with SMTP id 5b1f17b1804b1-49e82213d4bmr1619135e9.2.1789459505886; Tue, 15 Sep 2026 01:05:05 -0700 (PDT) Received: from deb05.proceq.com ([213.160.61.66]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e7d27315csm48588365e9.2.2026.09.15.01.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 01:05:05 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Haibo Chen , Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH v6 2/4] pinctrl: imx: answer OUTPUT_ENABLE/INPUT_ENABLE queries from the pad register Date: Tue, 15 Sep 2026 10:04:59 +0200 Message-ID: <20260915080501.329424-3-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260915080501.329424-1-mehmet.fide@gmail.com> References: <20260915080501.329424-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide The mmio pinconf get callback ignores which parameter was requested and returns the raw conf register, so a generic query through pinctrl_gpio_get_config() gets register bits back instead of the packed parameter it asked for. Decode the requested parameter and answer PIN_CONFIG_OUTPUT_ENABLE and PIN_CONFIG_INPUT_ENABLE on SoCs that declare where those bits live in the pad register; Vybrid has OBE at bit 1 and IBE at bit 0. The answer is 0 with the bit value as the argument, which is what the pinctrl_gpio_get_config() users (gpio-by-pinctrl, and gpio-mmio in the next patch) expect. Other parameters and the SCU based SoCs, whose firmware call returns the raw pad value as well, get -ENOTSUPP; a pin the device tree never configured gets -EINVAL, as the raw helper already does, so a caller can tell "no answer for this pin" from "this controller never answers". The only in-tree user of the raw register was the debugfs group dump, which called the callback with an uninitialized config; it now reads the register through its own helper, like the single pin dump already did. The set callback is not touched: the fsl,pins binding hands it the raw pad register value and that stays the only thing it accepts. Nothing in-tree sends generic parameters to it on these SoCs; making it understand them is a separate change. This gives gpio-mmio a way to read back the line direction on chips whose direction lives in the pin controller. Suggested-by: Bartosz Golaszewski Signed-off-by: Mehmet Fide Reviewed-by: Haibo Chen Reviewed-by: Linus Walleij Reviewed-by: Bartosz Golaszewski --- drivers/pinctrl/freescale/pinctrl-imx.c | 54 +++++++++++++++++++++-- drivers/pinctrl/freescale/pinctrl-imx.h | 4 ++ drivers/pinctrl/freescale/pinctrl-vf610.c | 2 + 3 files changed, 56 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/free= scale/pinctrl-imx.c index 9a45b376d36f..f08ef52bf4f8 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -21,6 +21,7 @@ =20 #include #include +#include #include #include =20 @@ -291,8 +292,8 @@ struct pinmux_ops imx_pmx_ops =3D { .set_mux =3D imx_pmx_set, }; =20 -static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_= id, - unsigned long *config) +static int imx_pinconf_get_raw_mmio(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) { struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info =3D ipctl->info; @@ -312,16 +313,61 @@ static int imx_pinconf_get_mmio(struct pinctrl_dev *p= ctldev, unsigned pin_id, return 0; } =20 +static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info =3D ipctl->info; + const struct imx_pin_reg *pin_reg =3D &ipctl->pin_regs[pin_id]; + enum pin_config_param param =3D pinconf_to_config_param(*config); + unsigned int mask; + u32 raw; + + switch (param) { + case PIN_CONFIG_OUTPUT_ENABLE: + mask =3D info->obe_mask; + break; + case PIN_CONFIG_INPUT_ENABLE: + mask =3D info->ibe_mask; + break; + default: + mask =3D 0; + break; + } + + if (!mask) + return -ENOTSUPP; + if (pin_reg->conf_reg =3D=3D -1) + return -EINVAL; + + raw =3D readl(ipctl->base + pin_reg->conf_reg); + *config =3D pinconf_to_config_packed(param, !!(raw & mask)); + + return 0; +} + static int imx_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned long *config) { struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info =3D ipctl->info; =20 + if (info->flags & IMX_USE_SCU) + return -ENOTSUPP; + + return imx_pinconf_get_mmio(pctldev, pin_id, config); +} + +static int imx_pinconf_get_raw(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info =3D ipctl->info; + if (info->flags & IMX_USE_SCU) return info->imx_pinconf_get(pctldev, pin_id, config); else - return imx_pinconf_get_mmio(pctldev, pin_id, config); + return imx_pinconf_get_raw_mmio(pctldev, pin_id, config); } =20 static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, @@ -426,7 +472,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_d= ev *pctldev, struct imx_pin *pin =3D &((struct imx_pin *)(grp->data))[i]; =20 name =3D pin_get_name(pctldev, pin->pin); - ret =3D imx_pinconf_get(pctldev, pin->pin, &config); + ret =3D imx_pinconf_get_raw(pctldev, pin->pin, &config); if (ret) return; seq_printf(s, " %s: 0x%lx\n", name, config); diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/free= scale/pinctrl-imx.h index f65ff45b4003..8fa7e1e2521d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -91,6 +91,10 @@ struct imx_pinctrl_soc_info { unsigned int mux_mask; u8 mux_shift; =20 + /* OBE/IBE bits in the conf register, 0 if the pad does not have them */ + unsigned int obe_mask; + unsigned int ibe_mask; + int (*gpio_set_direction)(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/fr= eescale/pinctrl-vf610.c index 76a4bc0181a0..77d077618782 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -319,6 +319,8 @@ static const struct imx_pinctrl_soc_info vf610_pinctrl_= info =3D { .gpio_set_direction =3D vf610_pmx_gpio_set_direction, .mux_mask =3D 0x700000, .mux_shift =3D 20, + .obe_mask =3D 0x2, + .ibe_mask =3D 0x1, }; =20 static const struct of_device_id vf610_pinctrl_of_match[] =3D { --=20 2.55.0 From nobody Fri Sep 25 07:56:18 2026 Received: from mail-wm2-f12.google.com (mail-wm2-f12.google.com [74.125.225.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 776FA346ACE for ; Tue, 15 Sep 2026 08:05:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.225.140 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789459513; cv=none; b=iMF8DXA8ZdeapMzY5tSpY5PSE0KVMxkNCCLL3YOw692apS2izLyfNv++NHv70zLfLD6s6SlrImE8eRBs5iumQibWAY+PGs/avHNJn79VSkxvwVPuypQfM45hiLq/rSEOTJdssunYqk+Cry/SwnuLH1oQ3S3snGa3L323qs3gUS4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789459513; c=relaxed/simple; bh=j2+zPwCu/tcPTMIRdv2LcEAv8lu7jVFYREhBmWgopj8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AmoJf9qhmOridS2AkCk0u6tooO9YEf/NOHEvZ15Hx4PnU8X3C9jVg8ImWWD7dA/gx/7shc5zyiqjqAao/e45ajhTF5XazyffwDkMlDwoY0qXW0ENVxbffnqxNk9jr/zxO3HV8/hD4MfvLf7j3fslG53VxBbhT6dddY8nUiAlik8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=pEchBQSg; arc=none smtp.client-ip=74.125.225.140 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pEchBQSg" Received: by mail-wm2-f12.google.com with SMTP id 5b1f17b1804b1-49ccf3ca626so12088825e9.0 for ; Tue, 15 Sep 2026 01:05:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1789459507; x=1790064307; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=zhuxraLn+BRCMp0d+GHEVuibFLIukV2Tl86N4IJdTu0=; b=pEchBQSgB1JXW6RxbxRTb5E8RMPc4Mu3UBqgr8OJjNGd5nBPX8bujideEwhAsY9vQG X12MZthRla9XhtjTkWhyx+BvrMDASKC5KXu2RV+hIJLRbkPcVfJWTa9L1UEmroDwEr36 qtFF6IVMqPbWkAW56BImS0WBCMfrFCd27GnMvMNUIWDtDfdfIpmbuzFmF+14JSZADrtf Wr4KQDD4p2LwKzJArL6l7N4SeojxdZAYzMUYR9JmfqkPI7FXGtKOhh1FEe1EiW5Qq4CO KjDQ6SYNSlpjTBMoAniC8+GCGYW9XH10fwFWar0LQ/nPY3+Vlruot9+SaiwPP/FmjtYl 9Mlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1789459507; x=1790064307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=zhuxraLn+BRCMp0d+GHEVuibFLIukV2Tl86N4IJdTu0=; b=xrmKOkHXnhyvO0NYBbyCxJDJK/MVLmh9bbiTSWzojZ+sjXcO8ia6tOOnQHC1WKg2MB x1T01BuKXBhKJDWGlOFXZ+UQsuOlYO5cUPA4OPuTghp3r4GaA1eVKWKfpkXUsnokAL1g gdcZ/qgPKpQfdTvllyxuD9Xdty9cKCQ3zgwcJq4XThRwOEP6Y0Hu4OANqxprjwW6WFwj LQ6aua3GrLaC0nyax97C04j1tt6w7TzjRyc/de3A8jvZbyWFfc5zTXGa8w7p9Vnr/o8J yoUTyxnf75LwjNmE7uNC54dmWeMH4PhzdeeZpAiaWfsuFsLSQz3T5TUwl+xq70sNmxkn 8cOA== X-Forwarded-Encrypted: i=1; AKwUvByrDopd7QartQA4jGnQR1okipSdGRNH1zHpCBVLMg49FeqVBhXEARH7m6N/OgnNFDT+cm++ZIXE/Yp+SD0=@vger.kernel.org X-Gm-Message-State: AFuF++nKRxbqkJZgJ1rcicPIJKRXsYXNCbbt7PFUQBhUqMp5l0oy+SKo D2mX97EIH180XgX6YqGU1ckbSmsO4BRIh20Vc0bIYVy5P3lkCMEcvkGg X-Gm-Gg: AYBFou0my6mXMCUO3NrAxQbV2sHoYIbv8HLEOR+0BFuovNtYWE42lUIgcF01OPUwNBk CpBLYzWluPhZRnIwcOo4DCS7B8TBroIk3vhp9QJafw5rNWJb/B7mSyuDc+YZZm1B2j2IrrUMn63 VmoQH4uanNMQWzvqAut7ik4P4J9mFPT4VHNHhx9ebEnR1Q8RQFaaUzTaAfkpVdm7A3CmJM4TDI4 Wecgo8zeh3gM+ns1XHeLTvWd6kPoX2m9IqrXCf1Q5qOEbntDYBL8Ck4LSTilexRmBPskxrxAp8x /fqxe+h5P7LgtKnqAoD0+k74nZGi/9GEn6/+6fFlClONRbTDbyqs2tTwT3MXhquIHpldfYY20dw qQUpQYbtiPcGBU4mq7eh0pjxzKPu73bUtJFc+elw2iaW8c/tJ3TA6HN/1eZ9tlFYaLPYKvUVD8a vLukIW2r5SKx/jjlA/gMCTG1aOhplrxAgM6YEgLKfAfjkKe5AEcrrMLgIcWS3xUO3CNgrlBZNxD bF8 X-Received: by 2002:a05:600c:860b:b0:49c:dadb:18a7 with SMTP id 5b1f17b1804b1-49e7a6489bemr67096545e9.10.1789459507015; Tue, 15 Sep 2026 01:05:07 -0700 (PDT) Received: from deb05.proceq.com ([213.160.61.66]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e7d27315csm48588365e9.2.2026.09.15.01.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 01:05:06 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Haibo Chen , Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH v6 3/4] gpiolib: add get_config() and gpiochip_generic_get_config() Date: Tue, 15 Sep 2026 10:05:00 +0200 Message-ID: <20260915080501.329424-4-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260915080501.329424-1-mehmet.fide@gmail.com> References: <20260915080501.329424-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide A chip with a pin control backend sets a line's configuration through set_config() and gpiochip_generic_config(), but has no way to read one back. gpio-mmio needs that to learn the direction of a line whose direction lives in the pin controller. Add the optional get_config() callback, taking the packed parameter to query and returning its bare argument the way pinctrl_gpio_get_config() does, and gpiochip_generic_get_config() as the pin control backed implementation, the mirror of gpiochip_generic_config(): a chip without pin ranges, or a kernel without pinctrl, gets -ENOTSUPP. Nothing in gpiolib calls get_config() and there is no consumer API; it is for the chip's own use. Suggested-by: Linus Walleij Signed-off-by: Mehmet Fide Reviewed-by: Linus Walleij --- Documentation/driver-api/gpio/driver.rst | 7 +++++++ drivers/gpio/gpiolib.c | 21 +++++++++++++++++++++ include/linux/gpio/driver.h | 9 +++++++++ 3 files changed, 37 insertions(+) diff --git a/Documentation/driver-api/gpio/driver.rst b/Documentation/drive= r-api/gpio/driver.rst index a4f160b95089..3e53374c7e9f 100644 --- a/Documentation/driver-api/gpio/driver.rst +++ b/Documentation/driver-api/gpio/driver.rst @@ -134,6 +134,13 @@ ending up in the pin control back-end "behind" the GPI= O controller, usually closer to the actual pins. This way the pin controller can manage the below listed GPIO configurations. =20 +The optional .get_config() callback reads a configuration back: the packed +parameter to query goes in, its bare argument comes out, the way +pinctrl_gpio_get_config() answers. gpiochip_generic_get_config() is its pin +control backed counterpart. Nothing in gpiolib calls it; it is for the GPIO +driver's own use, for example to learn the direction of a line when the pin +controller owns it. + If a pin controller back-end is used, the GPIO controller or hardware description needs to provide "GPIO ranges" mapping the GPIO line offsets t= o pin numbers on the pin controller so they can properly cross-reference each ot= her. diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index ef8ccaf17c9c..0586fc1f9564 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -2440,6 +2440,27 @@ int gpiochip_generic_config(struct gpio_chip *gc, un= signed int offset, } EXPORT_SYMBOL_GPL(gpiochip_generic_config); =20 +/** + * gpiochip_generic_get_config() - read back the configuration of a pin + * @gc: the gpiochip owning the GPIO + * @offset: the offset of the GPIO to query + * @config: the packed parameter to query, replaced by its bare argument + * + * Returns: + * 0 on success, or negative errno on failure. + */ +int gpiochip_generic_get_config(struct gpio_chip *gc, unsigned int offset, + unsigned long *config) +{ +#ifdef CONFIG_PINCTRL + if (list_empty(&gc->gpiodev->pin_ranges)) + return -ENOTSUPP; +#endif + + return pinctrl_gpio_get_config(gc, offset, config); +} +EXPORT_SYMBOL_GPL(gpiochip_generic_get_config); + #ifdef CONFIG_PINCTRL =20 /** diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 17511434ed07..4077dc678cae 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -359,6 +359,10 @@ struct gpio_irq_chip { * @set_config: optional hook for all kinds of settings. Uses the same * packed config format as generic pinconf. Must return 0 on success and * a negative error number on failure. + * @get_config: optional hook to read back a setting. Takes the packed + * generic pinconf parameter to query and returns its bare argument in + * the same variable, like pinctrl_gpio_get_config(). Must return 0 on + * success and a negative error number on failure. * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings; * implementation may not sleep * @dbg_show: optional routine to show contents in debugfs; default code @@ -434,6 +438,9 @@ struct gpio_chip { int (*set_config)(struct gpio_chip *gc, unsigned int offset, unsigned long config); + int (*get_config)(struct gpio_chip *gc, + unsigned int offset, + unsigned long *config); int (*to_irq)(struct gpio_chip *gc, unsigned int offset); =20 @@ -708,6 +715,8 @@ int gpiochip_generic_request(struct gpio_chip *gc, unsi= gned int offset); void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset); int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset, unsigned long config); +int gpiochip_generic_get_config(struct gpio_chip *gc, unsigned int offset, + unsigned long *config); =20 /** * struct gpio_pin_range - pin range controlled by a gpio chip --=20 2.55.0 From nobody Fri Sep 25 07:56:18 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3219A3B47CB for ; Tue, 15 Sep 2026 08:05:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.225.76 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789459514; cv=none; b=XCqJ1ZMIMxIl/9r4h9MkM5ixoReIIvHHCOep+hbo2n8JVnzfjBfM7/Cwki0b79knILeIaPDe+FBa2BQjZ6jKz3m7Mysvfrq/qn/6RDivVQJMUgs4Td7ezxiRXwNnirVN0UBaX/IOI6WzmaZQrbIpQpLMAyWVG0BaaIhTwj6rfRw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789459514; c=relaxed/simple; bh=+kqeTqpcEjn+LLVVihM/uu8q4NnBEHCrxafwfSxU/xA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Et97Wzje8d0R0SJv8VSX7fgNby4JDVn2VB0InU7rxiHiBx/o7oep4xYE61sozyje1HC5TGhiS78DsZIXdyonyrODWq6Og1wmtjfVSbIvHFNNB+X4htd//WWuCKykSKgysIuUzKvGXT3lXYEiacTa7UrGN7XWI251WuqwKDNTOKc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PuPjSEno; arc=none smtp.client-ip=74.125.225.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PuPjSEno" Received: by mail-wr2-f12.google.com with SMTP id ffacd0b85a97d-485b1d2874fso915189f8f.0 for ; Tue, 15 Sep 2026 01:05:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1789459508; x=1790064308; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=H137qfG3h8enrbCR8FlT5MD3WdEANP9LGcr88jAxASI=; b=PuPjSEnoftskUjhjdtF/0myv9nDRwJAk78WCJU4IjA8cLNITL+eY4dnLYXVYkEFi78 CW0LuU4YQBCvbqL/oMStQN7nSmde38HaOq16KhKQs/u0lfu/YPM77On8i/FtLF99l9+4 eVb093EHH9LihKoC41RvBX/OeWE2k3BVuykdUsjcj5cBo3SiROLulrk7QX3N5YNhfATo 96G4GT2CbWjyHEBMVRDUhdm1XAHatiK3d6aAgz7b9nWNft/nfAbLZHQctXShf6brjZbc 4CUXoA8HaTp/NtbYbuW9AUNKbk+8WObryH4JpkxJqG1q8SdMgqa/ym9wpVGweyCMflxn 9mhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1789459508; x=1790064308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=H137qfG3h8enrbCR8FlT5MD3WdEANP9LGcr88jAxASI=; b=KuELTYFf5a4qabfcV0Lo0UTs6W210z0bspV6q/bed44MWCpdqPoL/IEH1UGTC6Unuq 8rI2HrgY7g1fdosH0KxkElrO8HwV3pUbDrLv1tQfTpByzjin7znEt5Fu5z5wMLxjR8CL f777mXXvn6q5SF8izjkQ2k8zC0W+mNHl2dCN3N/J7wtGip/1b+dNuyM/FHSpwTOJHrqg /jHw9m/gRSLMCs6pJGwmtRgBNwn14LP4kntZxYDzHjUYSTofveXIyku3OfU4c81tOHie B6QWR8VC5hdoGe8aRbDKQLUUWgT2VtnnBK3JWVME1iJW2yYdZFqZTGCZ4kCdheQcOcn6 xpmQ== X-Forwarded-Encrypted: i=1; AKwUvBwa446TadcrKyjVzrLcb1Jle/0LTP8m0ZM4UExYbLmgEGTpMD1I/axqIt7EwypeEEWEdZJkKHA26kOslME=@vger.kernel.org X-Gm-Message-State: AFuF++lLVnVcEYw2cvpn5qxMCSReNttRFBN792NAmo1x6wnvZ23aQ6Lf KbL3an8GyGNTvBmmzUFUE2hmU4G9PbVVUjUhP4BjL0gVwHlPKmA0c6g0 X-Gm-Gg: AYBFou0tdgutKuseOrKZen47MpQSru69DHw6izNmloYj+cNBQkI8CzeWu7F1sZPtY8o 4EHg252OqcSZsWYl0f09BTz2iEPGgbPxxe9sPykgXoFmdPky+w8sUxzqFA0nD6oyaU9kpksAP1c PcGPzx3aNxImEg0BNPg7o/nTZ7jUi91u/SULbqIqP7dx4ZtCpKg1NWtI/tJ6s6+Y9Kv8wy6bVTT veB2j8P4dWRPs+ctOxvesWnn1T/DvPIVBIEblTtJUaUFpoJaO8JaSaCby5x4P6K4NUYtOGjCTL5 UQmy8NCtLmLe27DC0uuw/gP2Otta0FmpaNiTOjKlsPVfqYEE9jUDZ49GE/zE57wptF5cazUUQmV 3vHiQIrlOIvaknF0DygpnmHBvCGBgdttxiLwqKGthkzl4aj5C15KV+ukjuSdQ/p+uVfKfN5Tdxf xz4I2U0GGnMdASmjpvrpvk21cGe6y8D43M56jBHOxnQi1hzw/XGqflvXgtNMp8vWbxAiEeykNiI /6U X-Received: by 2002:a05:600c:3e10:b0:49d:2936:8ad1 with SMTP id 5b1f17b1804b1-49e7d722aa2mr32668075e9.1.1789459508063; Tue, 15 Sep 2026 01:05:08 -0700 (PDT) Received: from deb05.proceq.com ([213.160.61.66]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e7d27315csm48588365e9.2.2026.09.15.01.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 01:05:07 -0700 (PDT) From: Mehmet Fide To: Bartosz Golaszewski , Linus Walleij Cc: Haibo Chen , Dong Aisheng , Fabio Estevam , Frank Li , Jacky Bai , Sascha Hauer , Pengutronix Kernel Team , imx@lists.linux.dev, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mehmet Fide Subject: [PATCH v6 4/4] gpio: mmio: track the direction of chips without direction registers Date: Tue, 15 Sep 2026 10:05:01 +0200 Message-ID: <20260915080501.329424-5-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260915080501.329424-1-mehmet.fide@gmail.com> References: <20260915080501.329424-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mehmet Fide A generic chip with GPIO_GENERIC_PINCTRL_BACKEND and no direction registers sets the direction through pinctrl but has no get_direction callback, so every gpiod_get_direction() call trips the WARN in gpiolib and the direction gpiolib reports is whatever it assumed. On a Vybrid Colibri module the i2c core, asking for the SDA line's direction before bus recovery, gets that backtrace on every boot, and so does any other caller outside gpiolib. Keep the direction of such a chip in the existing shadow: the direction setters update sdir under the chip lock, and get_direction() is the shadow-reading path already used for unreadable direction registers. That keeps the callback usable in atomic context, which it has to be: gpiochip_lock_as_irq() calls it for !can_sleep chips from gpiochip_irq_domain_activate(), under the irq descriptor lock. The pad's actual state is read once, in process context, when a line is requested: gpiolib calls request() right before get_direction() for a new line, so the shadow is seeded there from PIN_CONFIG_OUTPUT_ENABLE through the chip's get_config(), which is gpiochip_generic_get_config() for the pinctrl backend, and the line reports what the pin controller says. Lines pinctrl cannot answer for keep the input default, which is what gpiolib assumed before. dir_unreadable, so far set only for GPIO_GENERIC_UNREADABLE_REG_DIR, is now also set for a pinctrl-backed chip without direction registers: both kinds of chip have no register to read the direction from and serve it from the shadow. The answers depend on the pinctrl driver decoding the parameter. On Vybrid that is the preceding pinctrl-imx patch: without it pin_config_get() returns the raw pad register, which would seed every requested line as an output, so this patch must not land ahead of it. Suggested-by: Bartosz Golaszewski Signed-off-by: Mehmet Fide Reviewed-by: Haibo Chen --- drivers/gpio/gpio-mmio.c | 60 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index 7e4b3e8d609f..0709ffaab4de 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -49,6 +49,7 @@ o ` ~~~~\___/~~~~ ` control= ler in FPGA is ,.` #include #include #include +#include #include #include #include @@ -372,7 +373,17 @@ static int gpio_mmio_dir_in_err(struct gpio_chip *gc, = unsigned int gpio) =20 static int gpio_mmio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) { - return gpio_mmio_dir_return(gc, gpio, false); + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + int ret; + + ret =3D gpio_mmio_dir_return(gc, gpio, false); + if (ret) + return ret; + + guard(raw_spinlock_irqsave)(&chip->lock); + chip->sdir &=3D ~gpio_mmio_line2mask(gc, gpio); + + return 0; } =20 static int gpio_mmio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, @@ -384,9 +395,19 @@ static int gpio_mmio_dir_out_err(struct gpio_chip *gc,= unsigned int gpio, static int gpio_mmio_simple_dir_out(struct gpio_chip *gc, unsigned int gpi= o, int val) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + int ret; + gc->set(gc, gpio, val); =20 - return gpio_mmio_dir_return(gc, gpio, true); + ret =3D gpio_mmio_dir_return(gc, gpio, true); + if (ret) + return ret; + + guard(raw_spinlock_irqsave)(&chip->lock); + chip->sdir |=3D gpio_mmio_line2mask(gc, gpio); + + return 0; } =20 static int gpio_mmio_dir_in(struct gpio_chip *gc, unsigned int gpio) @@ -601,20 +622,51 @@ static int gpio_mmio_setup_direction(struct gpio_gene= ric_chip *chip, gc->direction_input =3D gpio_mmio_dir_in_err; else gc->direction_input =3D gpio_mmio_simple_dir_in; + + if (cfg->flags & GPIO_GENERIC_PINCTRL_BACKEND) { + chip->dir_unreadable =3D true; + gc->get_direction =3D gpio_mmio_get_dir; + gc->get_config =3D gpiochip_generic_get_config; + } } =20 return 0; } =20 +static void gpio_mmio_seed_dir_from_pinctrl(struct gpio_chip *gc, + unsigned int gpio) +{ + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + unsigned long config; + + if (!gc->get_config || chip->reg_dir_out || chip->reg_dir_in) + return; + + config =3D pinconf_to_config_packed(PIN_CONFIG_OUTPUT_ENABLE, 0); + if (gc->get_config(gc, gpio, &config)) + return; + + guard(raw_spinlock_irqsave)(&chip->lock); + if (config) + chip->sdir |=3D gpio_mmio_line2mask(gc, gpio); + else + chip->sdir &=3D ~gpio_mmio_line2mask(gc, gpio); +} + static int gpio_mmio_request(struct gpio_chip *gc, unsigned int gpio_pin) { struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + int ret; =20 if (gpio_pin >=3D gc->ngpio) return -EINVAL; =20 - if (chip->pinctrl) - return gpiochip_generic_request(gc, gpio_pin); + if (chip->pinctrl) { + ret =3D gpiochip_generic_request(gc, gpio_pin); + if (ret) + return ret; + gpio_mmio_seed_dir_from_pinctrl(gc, gpio_pin); + } =20 return 0; } --=20 2.55.0