From nobody Fri Sep 25 08:46:27 2026 Received: from out30-132.freemail.mail.aliyun.com (out30-132.freemail.mail.aliyun.com [115.124.30.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94F0F3DA7E3 for ; Tue, 15 Sep 2026 03:28:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.132 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789442922; cv=none; b=EG+GdNkOED3OXFyn/QVIFFBP3Jifz/zuUZfZpwqnCCp3DkjYUpwDlLr7PrO4pGxSHhboyKcziUdfdkpj2hAb45uFQlgRpoaTh+aS9LcHS8eaDEReAC9zN67ArF23UU17J1fUyU14B35LfjR4aJdQYWzyfWB7GcSrRbN+XwFdoLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789442922; c=relaxed/simple; bh=T9WWqFJHchi/0d/r1QqY1VcFw/wXeEsnz4BNMR0PRPE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BrI8NEHYVs9neDiH2FeQ9iSEhCmAzUBneZoNGQgg/xgfYkfa+Ccg6WUZPUggoUZO7rAE547a5ovNzo3QyEwETyCPo1ljZYJgfG6g3T0koN9yJpK/JVvYm5TM3w2cX1yiAYKCnwFcy0UrKZYTv5RcAtxh7AtDSngyXMCRWCfpW/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=gAkeWCFU; arc=none smtp.client-ip=115.124.30.132 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="gAkeWCFU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1789442916; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=vV2Y5T1kVnTXHiV+qTqs8GbZEVnLFhK5H2hev57N6Io=; b=gAkeWCFUHZ3rFcp4f4D325IjRULrl/pFfrR0H0i7WPBxVb3z1RJKTacURCXRsBoChBJ7lpQ8NoOd++BnvbC2GOlZ/CZ/vdh19Q/8dfaAl9v1Art6QMOl3oinq9likhyNGoX9xzsJcqxlnkIVFspQknnJO5SQ/SZBy/PInjsVMYA= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R191e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033045133197;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=26;SR=0;TI=SMTPD_---0XB.uvNY_1789442913; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0XB.uvNY_1789442913 cluster:ay36) by smtp.aliyun-inc.com; Tue, 15 Sep 2026 11:28:34 +0800 From: fangyu.yu@linux.alibaba.com To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de, zong.li@sifive.com, andrew.jones@oss.qualcomm.com, anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com, joerg.roedel@amd.com Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [RFC PATCH v4 01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support Date: Tue, 15 Sep 2026 11:28:20 +0800 Message-Id: <20260915032828.11250-2-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> References: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Add support for Sv39x4/Sv48x4/Sv57x4 Second-stage page tables used by the RISC-V IOMMU iohgatp register. The x4 root page table is 16 KiB instead of the usual 4 KiB, covering 2 extra GPA bits (hw_max_vasz_lg2 =3D 41/50/59). Signed-off-by: Fangyu Yu --- drivers/iommu/generic_pt/fmt/iommu_riscv64.c | 2 +- drivers/iommu/generic_pt/fmt/riscv.h | 109 +++++++++++++++---- include/linux/generic_pt/common.h | 4 + include/linux/generic_pt/iommu.h | 11 ++ 4 files changed, 102 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/generic_pt/fmt/iommu_riscv64.c b/drivers/iommu/g= eneric_pt/fmt/iommu_riscv64.c index 1bb74114fb02..fa61839e5599 100644 --- a/drivers/iommu/generic_pt/fmt/iommu_riscv64.c +++ b/drivers/iommu/generic_pt/fmt/iommu_riscv64.c @@ -8,7 +8,7 @@ (BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE) | \ BIT(PT_FEAT_RISCV_SVNAPOT_64K) | \ BIT(PT_FEAT_DETAILED_GATHER) | \ - BIT(PT_FEAT_RISCV_SVPBMT)) + BIT(PT_FEAT_RISCV_SVPBMT) | BIT(PT_FEAT_RISCV_S2)) #define PT_FORCE_ENABLED_FEATURES BIT(PT_FEAT_DETAILED_GATHER) =20 #include "iommu_template.h" diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_p= t/fmt/riscv.h index ae9a76514416..d4445e463fa9 100644 --- a/drivers/iommu/generic_pt/fmt/riscv.h +++ b/drivers/iommu/generic_pt/fmt/riscv.h @@ -37,7 +37,16 @@ enum { PT_MAX_OUTPUT_ADDRESS_LG2 =3D 34, PT_MAX_TOP_LEVEL =3D 1, #else - PT_MAX_VA_ADDRESS_LG2 =3D 57, + /* + * PT_MAX_VA_ADDRESS_LG2 is the upper bound accepted by the generic + * pt_iommu_init() range check. It must cover both first-stage and + * second-stage (G-stage) modes: + * + * First-stage (fsc/iosatp): Sv39=3D39, Sv48=3D48, Sv57=3D57 + * Second-stage (iohgatp): Sv39x4=3D41, Sv48x4=3D50, Sv57x4=3D59 + * + */ + PT_MAX_VA_ADDRESS_LG2 =3D 59, PT_MAX_OUTPUT_ADDRESS_LG2 =3D 56, PT_MAX_TOP_LEVEL =3D 4, #endif @@ -126,6 +135,12 @@ riscvpt_entry_num_contig_lg2(const struct pt_state *pt= s) =20 static inline unsigned int riscvpt_num_items_lg2(const struct pt_state *pt= s) { + /* + * It is not allowed to call pt_num_items_lg2() at the top level, this + * API restriction is specifically an optimization avoid overheads + * dealing with concatenated tables here. + */ + PT_WARN_ON(pts->level =3D=3D pts->range->top_level); return PT_TABLEMEM_LG2SZ - ilog2(sizeof(u64)); } #define pt_num_items_lg2 riscvpt_num_items_lg2 @@ -261,20 +276,41 @@ riscvpt_iommu_fmt_init(struct pt_iommu_riscv_64 *iomm= u_table, const struct pt_iommu_riscv_64_cfg *cfg) { struct pt_riscv *table =3D &iommu_table->riscv_64pt; - - switch (cfg->common.hw_max_vasz_lg2) { - case 39: - pt_top_set_level(&table->common, 2); - break; - case 48: - pt_top_set_level(&table->common, 3); - break; - case 57: - pt_top_set_level(&table->common, 4); - break; - default: - return -EINVAL; + unsigned int top_level; + + if (pt_feature(&table->common, PT_FEAT_RISCV_S2)) { + /* Second-stage (iohgatp): Sv39x4 / Sv48x4 / Sv57x4. */ + switch (cfg->common.hw_max_vasz_lg2) { + case 41: + top_level =3D 2; + break; + case 50: + top_level =3D 3; + break; + case 59: + top_level =3D 4; + break; + default: + return -EINVAL; + } + } else { + /* First-stage (fsc/iosatp): Sv39 / Sv48 / Sv57. */ + switch (cfg->common.hw_max_vasz_lg2) { + case 39: + top_level =3D 2; + break; + case 48: + top_level =3D 3; + break; + case 57: + top_level =3D 4; + break; + default: + return -EINVAL; + } } + + pt_top_set_level(&table->common, top_level); table->common.max_oasz_lg2 =3D min(PT_MAX_OUTPUT_ADDRESS_LG2, cfg->common.hw_max_oasz_lg2); return 0; @@ -292,30 +328,57 @@ riscvpt_iommu_fmt_hw_info(struct pt_iommu_riscv_64 *t= able, PT_WARN_ON(top_phys & ~PT_TOP_PHYS_MASK); =20 /* - * See Table 3. Encodings of iosatp.MODE field" for DC.tx.SXL =3D 0: - * 8 =3D Sv39 =3D top level 2 - * 9 =3D Sv38 =3D top level 3 - * 10 =3D Sv57 =3D top level 4 + * Both first-stage (fsc/iosatp) and second-stage (iohgatp) share the + * same MODE numeric values for a given top level: + * top_level 2 -> MODE 8 (Sv39 / Sv39x4) + * top_level 3 -> MODE 9 (Sv48 / Sv48x4) + * top_level 4 -> MODE 10 (Sv57 / Sv57x4) + * + * See "Table 3. Encodings of iosatp.MODE field" (DC.tc.SXL =3D 0) and + * "Table 2. Encoding of iohgatp.MODE field" in the RISC-V IOMMU spec. */ - info->fsc_iosatp_mode =3D top_range->top_level + 6; + if (pt_feature(&table->riscv_64pt.common, PT_FEAT_RISCV_S2)) + info->iohgatp_mode =3D top_range->top_level + 6; + else + info->fsc_iosatp_mode =3D top_range->top_level + 6; } #define pt_iommu_fmt_hw_info riscvpt_iommu_fmt_hw_info =20 #if defined(GENERIC_PT_KUNIT) static const struct pt_iommu_riscv_64_cfg riscv_64_kunit_fmt_cfgs[] =3D { - [0] =3D { .common.features =3D BIT(PT_FEAT_RISCV_SVNAPOT_64K), + /* First-stage (fsc/iosatp): Sv39 / Sv48 / Sv57 */ + [0] =3D { .common.features =3D BIT(PT_FEAT_SIGN_EXTEND) | + BIT(PT_FEAT_RISCV_SVNAPOT_64K), .common.hw_max_oasz_lg2 =3D 56, .common.hw_max_vasz_lg2 =3D 39 }, - [1] =3D { .common.features =3D 0, + [1] =3D { .common.features =3D BIT(PT_FEAT_SIGN_EXTEND), .common.hw_max_oasz_lg2 =3D 56, .common.hw_max_vasz_lg2 =3D 48 }, - [2] =3D { .common.features =3D BIT(PT_FEAT_RISCV_SVNAPOT_64K), + [2] =3D { .common.features =3D BIT(PT_FEAT_SIGN_EXTEND) | + BIT(PT_FEAT_RISCV_SVNAPOT_64K), .common.hw_max_oasz_lg2 =3D 56, .common.hw_max_vasz_lg2 =3D 57 }, + /* + * Second-stage (iohgatp): Sv39x4 / Sv48x4 / Sv57x4. + */ + [3] =3D { .common.features =3D BIT(PT_FEAT_RISCV_S2) | + BIT(PT_FEAT_RISCV_SVNAPOT_64K), + .common.hw_max_oasz_lg2 =3D 56, + .common.hw_max_vasz_lg2 =3D 41 }, + [4] =3D { .common.features =3D BIT(PT_FEAT_RISCV_S2), + .common.hw_max_oasz_lg2 =3D 56, + .common.hw_max_vasz_lg2 =3D 50 }, + [5] =3D { .common.features =3D BIT(PT_FEAT_RISCV_S2) | + BIT(PT_FEAT_RISCV_SVNAPOT_64K), + .common.hw_max_oasz_lg2 =3D 56, + .common.hw_max_vasz_lg2 =3D 59 }, }; #define kunit_fmt_cfgs riscv_64_kunit_fmt_cfgs +/* Sign extension is only valid for first-stage configs, not S2. */ enum { - KUNIT_FMT_FEATURES =3D BIT(PT_FEAT_RISCV_SVNAPOT_64K), + KUNIT_FMT_FEATURES =3D BIT(PT_FEAT_SIGN_EXTEND) | + BIT(PT_FEAT_RISCV_SVNAPOT_64K) | + BIT(PT_FEAT_RISCV_S2), }; #endif =20 diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/c= ommon.h index 07ef1c8341a4..f2e130c2b804 100644 --- a/include/linux/generic_pt/common.h +++ b/include/linux/generic_pt/common.h @@ -197,6 +197,10 @@ enum { * Support Svpbmt extension: encode page-based memory type (PBMT) in PTEs. */ PT_FEAT_RISCV_SVPBMT, + /* + * Using second-stage / iohgatp address translation. + */ + PT_FEAT_RISCV_S2, =20 }; =20 diff --git a/include/linux/generic_pt/iommu.h b/include/linux/generic_pt/io= mmu.h index dd0edd02a48a..2eed9b78f56c 100644 --- a/include/linux/generic_pt/iommu.h +++ b/include/linux/generic_pt/iommu.h @@ -328,7 +328,18 @@ struct pt_iommu_riscv_64_cfg { =20 struct pt_iommu_riscv_64_hw_info { u64 ppn; + /* + * First-stage (fsc/iosatp) MODE encoding: + * 8 =3D Sv39, 9 =3D Sv48, 10 =3D Sv57 + * Used to program DC.fsc.iosatp.MODE. + */ u8 fsc_iosatp_mode; + /* + * Second-stage (iohgatp) MODE encoding: + * 8 =3D Sv39x4, 9 =3D Sv48x4, 10 =3D Sv57x4 + * Used to program DC.iohgatp.MODE. + */ + u8 iohgatp_mode; }; =20 IOMMU_FORMAT(riscv_64, riscv_64pt); --=20 2.50.1 From nobody Fri Sep 25 08:46:27 2026 Received: from out30-100.freemail.mail.aliyun.com (out30-100.freemail.mail.aliyun.com [115.124.30.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C1774052D9 for ; Tue, 15 Sep 2026 03:28:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789442927; cv=none; b=czhw7MyauQVfIQ84+SXxbYlST05X6V1I/PeXV+dirr5YfnmYauF1jKfxGDYURNJr11kq/VwrZ3jDla8EPHaO+atBnGZRxSaNAdngG3uiXmxh61URr0sUHfQZuXKWR1W62sKRhK44BmEe3Yo8agTKQpLOEgvSlhDhzBR7bZn8WRQ= ARC-Message-Signature: i=1; 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charset="utf-8" From: Fangyu Yu Implement the three dirty-tracking hooks required by the generic page table framework for the RISC-V format: pt_entry_is_write_dirty(): Check the D bit (bit 7) in the PTE. pt_entry_make_write_clean(): Clear the D bit across the full contiguous range. pt_entry_make_write_dirty(): Atomically set D via try_cmpxchg64() on a single PTE. Signed-off-by: Fangyu Yu --- drivers/iommu/generic_pt/fmt/riscv.h | 49 ++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_p= t/fmt/riscv.h index d4445e463fa9..2f4838eb44af 100644 --- a/drivers/iommu/generic_pt/fmt/riscv.h +++ b/drivers/iommu/generic_pt/fmt/riscv.h @@ -223,6 +223,55 @@ static inline void riscvpt_attr_from_entry(const struc= t pt_state *pts, } #define pt_attr_from_entry riscvpt_attr_from_entry =20 +/* + * Dirty tracking: RISC-V PTEs use D (bit 7) as the hardware dirty bit. + * When Svnapot 64K is active a leaf entry spans 16 consecutive PTEs; we + * must check / clear all of them so that no dirty indication is lost. + */ +static inline bool riscvpt_entry_is_write_dirty(const struct pt_state *pts) +{ + unsigned int num_contig_lg2 =3D riscvpt_entry_num_contig_lg2(pts); + const pt_riscv_entry_t *tablep =3D + pt_cur_table(pts, pt_riscv_entry_t) + + log2_set_mod(pts->index, 0, num_contig_lg2); + const pt_riscv_entry_t *end =3D tablep + log2_to_int(num_contig_lg2); + + for (; tablep !=3D end; tablep++) + if (READ_ONCE(*tablep) & RISCVPT_D) + return true; + return false; +} +#define pt_entry_is_write_dirty riscvpt_entry_is_write_dirty + +static inline void riscvpt_entry_make_write_clean(struct pt_state *pts) +{ + unsigned int num_contig_lg2 =3D riscvpt_entry_num_contig_lg2(pts); + pt_riscv_entry_t *tablep =3D + pt_cur_table(pts, pt_riscv_entry_t) + + log2_set_mod(pts->index, 0, num_contig_lg2); + pt_riscv_entry_t *end =3D tablep + log2_to_int(num_contig_lg2); + + for (; tablep !=3D end; tablep++) + WRITE_ONCE(*tablep, READ_ONCE(*tablep) & ~(pt_riscv_entry_t)RISCVPT_D); +} +#define pt_entry_make_write_clean riscvpt_entry_make_write_clean + +static inline bool riscvpt_entry_make_write_dirty(struct pt_state *pts) +{ + pt_riscv_entry_t *tablep =3D + pt_cur_table(pts, pt_riscv_entry_t) + pts->index; + pt_riscv_entry_t new =3D pts->entry | RISCVPT_D; + + return try_cmpxchg64(tablep, &pts->entry, new); +} +#define pt_entry_make_write_dirty riscvpt_entry_make_write_dirty + +static inline bool riscvpt_dirty_supported(struct pt_common *common) +{ + return pt_feature(common, PT_FEAT_RISCV_S2); +} +#define pt_dirty_supported riscvpt_dirty_supported + /* --- iommu */ #include #include --=20 2.50.1 From nobody Fri Sep 25 08:46:27 2026 Received: from out30-133.freemail.mail.aliyun.com (out30-133.freemail.mail.aliyun.com [115.124.30.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 757CC406818 for ; Tue, 15 Sep 2026 03:28:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.133 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789442925; cv=none; b=CbPRH7Y3C8IpstKnzvp/+zP6zT2LR8TEsoetlQYRIrlZYZcumfEfSYxLF5OCdDQAdjuYf9xKGoWIBzLJPkx42ayiMLEmXiub2P/QlpC6e3h1dlxHFI16y8cLNt2+PW2XCP+xauPI9LAidhgnMYm6ruSyeunBstPD9YxXGR2bNRM= ARC-Message-Signature: i=1; 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charset="utf-8" From: Tomasz Jeznach Report RISC-V IOMMU capabilities required by VFIO subsystem to enable PCIe device assignment. Signed-off-by: Tomasz Jeznach Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index cec3ddd7ab10..a6c8307e82ea 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1422,6 +1422,16 @@ static struct iommu_group *riscv_iommu_device_group(= struct device *dev) return generic_device_group(dev); } =20 +static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) +{ + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: + return true; + default: + return false; + } +} + static int riscv_iommu_of_xlate(struct device *dev, const struct of_phandl= e_args *args) { return iommu_fwspec_add_ids(dev, args->args, 1); @@ -1483,6 +1493,7 @@ static void riscv_iommu_release_device(struct device = *dev) =20 static const struct iommu_ops riscv_iommu_ops =3D { .of_xlate =3D riscv_iommu_of_xlate, + .capable =3D riscv_iommu_capable, .identity_domain =3D &riscv_iommu_identity_domain, .blocked_domain =3D &riscv_iommu_blocking_domain, .release_domain =3D &riscv_iommu_blocking_domain, --=20 2.50.1 From nobody Fri Sep 25 08:46:27 2026 Received: from out30-118.freemail.mail.aliyun.com (out30-118.freemail.mail.aliyun.com [115.124.30.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1685E40315F for ; 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Tue, 15 Sep 2026 11:28:40 +0800 From: fangyu.yu@linux.alibaba.com To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de, zong.li@sifive.com, andrew.jones@oss.qualcomm.com, anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com, joerg.roedel@amd.com Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [RFC PATCH v4 04/10] iommu/riscv: use data structure instead of individual values Date: Tue, 15 Sep 2026 11:28:23 +0800 Message-Id: <20260915032828.11250-5-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> References: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zong Li The parameter will be increased when we need to set up more bit fields in the device context. Use a data structure to wrap them up. Signed-off-by: Zong Li Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index a6c8307e82ea..c5b6214ee672 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1165,7 +1165,7 @@ static void riscv_iommu_iodir_iotinval(struct riscv_i= ommu_device *iommu, * interim translation faults. */ static void riscv_iommu_iodir_update(struct riscv_iommu_device *iommu, - struct device *dev, u64 fsc, u64 ta) + struct device *dev, struct riscv_iommu_dc *new_dc) { struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); struct riscv_iommu_dc *dc; @@ -1204,10 +1204,10 @@ static void riscv_iommu_iodir_update(struct riscv_i= ommu_device *iommu, for (i =3D 0; i < fwspec->num_ids; i++) { dc =3D riscv_iommu_get_dc(iommu, fwspec->ids[i]); tc =3D READ_ONCE(dc->tc); - tc |=3D ta & RISCV_IOMMU_DC_TC_V; + tc |=3D new_dc->ta & RISCV_IOMMU_DC_TC_V; =20 - WRITE_ONCE(dc->fsc, fsc); - WRITE_ONCE(dc->ta, ta & RISCV_IOMMU_PC_TA_PSCID); + WRITE_ONCE(dc->fsc, new_dc->fsc); + WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1288,22 +1288,22 @@ static int riscv_iommu_attach_paging_domain(struct = iommu_domain *iommu_domain, struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); struct pt_iommu_riscv_64_hw_info pt_info; - u64 fsc, ta; + struct riscv_iommu_dc dc =3D {0}; =20 pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info); =20 if (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode)) return -ENODEV; =20 - fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | + dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn); - ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | + dc.ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | RISCV_IOMMU_PC_TA_V; =20 if (riscv_iommu_bond_link(domain, dev)) return -ENOMEM; =20 - riscv_iommu_iodir_update(iommu, dev, fsc, ta); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D domain; =20 @@ -1378,9 +1378,12 @@ static int riscv_iommu_attach_blocking_domain(struct= iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + struct riscv_iommu_dc dc =3D {0}; + + dc.fsc =3D RISCV_IOMMU_FSC_BARE; =20 /* Make device context invalid, translation requests will fault w/ #258 */ - riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, 0); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D NULL; =20 @@ -1400,8 +1403,12 @@ static int riscv_iommu_attach_identity_domain(struct= iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); 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charset="utf-8" From: Zong Li This patch adds a ID Allocator for GSCID and a wrap for setting up GSCID in IOTLB invalidation command. Set up iohgatp to enable second stage table and flush stage-2 table if the GSCID is set. The GSCID of domain should be freed when release domain. GSCID will be allocated for parent domain in nested IOMMU process. Signed-off-by: Zong Li Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu-bits.h | 7 ++++ drivers/iommu/riscv/iommu.c | 62 ++++++++++++++++++++++++++------ 2 files changed, 58 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-b= its.h index f2ef9bd3cde9..65d1f2250011 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -720,6 +720,13 @@ static inline void riscv_iommu_cmd_inval_vma(struct ri= scv_iommu_command *cmd) cmd->dword1 =3D 0; } =20 +static inline void riscv_iommu_cmd_inval_gvma(struct riscv_iommu_command *= cmd) +{ + cmd->dword0 =3D FIELD_PREP(RISCV_IOMMU_CMD0_OPCODE, RISCV_IOMMU_CMD_IOTIN= VAL_OPCODE) | + FIELD_PREP(RISCV_IOMMU_CMD0_FUNC, RISCV_IOMMU_CMD_IOTINVAL_FUNC_GV= MA); + cmd->dword1 =3D 0; +} + static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_comma= nd *cmd, u64 addr) { diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index c5b6214ee672..99f05f1db35b 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -48,6 +48,10 @@ static DEFINE_IDA(riscv_iommu_pscids); #define RISCV_IOMMU_MAX_PSCID (BIT(20) - 1) =20 +/* IOMMU GSCID allocation namespace. */ +static DEFINE_IDA(riscv_iommu_gscids); +#define RISCV_IOMMU_MAX_GSCID (BIT(16) - 1) + /* Device resource-managed allocations */ struct riscv_iommu_devres { void *addr; @@ -819,6 +823,7 @@ struct riscv_iommu_domain { struct list_head bonds; spinlock_t lock; /* protect bonds list updates. */ int pscid; + int gscid; }; PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain); =20 @@ -981,7 +986,7 @@ static void riscv_iommu_tlbi_calc(struct riscv_iommu_tl= bi *tlbi, } =20 static void riscv_iommu_iotlb_inval_iommu(struct riscv_iommu_device *iommu, - int pscid, + int pscid, int gscid, struct riscv_iommu_tlbi *tlbi) { bool use_nl =3D tlbi->non_leaf && @@ -989,8 +994,13 @@ static void riscv_iommu_iotlb_inval_iommu(struct riscv= _iommu_device *iommu, struct riscv_iommu_command cmd; unsigned int i; =20 - riscv_iommu_cmd_inval_vma(&cmd); - riscv_iommu_cmd_inval_set_pscid(&cmd, pscid); + if (gscid) { + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, gscid); + } else { + riscv_iommu_cmd_inval_vma(&cmd); + riscv_iommu_cmd_inval_set_pscid(&cmd, pscid); + } =20 /* * If non-leaf entries were changed and the IOMMU doesn't @@ -1074,7 +1084,7 @@ static void riscv_iommu_iotlb_inval(struct riscv_iomm= u_domain *domain, if (iommu =3D=3D prev) continue; =20 - riscv_iommu_iotlb_inval_iommu(iommu, domain->pscid, &tlbi); + riscv_iommu_iotlb_inval_iommu(iommu, domain->pscid, domain->gscid, &tlbi= ); prev =3D iommu; } =20 @@ -1208,6 +1218,7 @@ static void riscv_iommu_iodir_update(struct riscv_iom= mu_device *iommu, =20 WRITE_ONCE(dc->fsc, new_dc->fsc); WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); + WRITE_ONCE(dc->iohgatp, new_dc->iohgatp); /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1258,16 +1269,19 @@ static void riscv_iommu_free_paging_domain(struct i= ommu_domain *iommu_domain) =20 WARN_ON(!list_empty(&domain->bonds)); =20 - if ((int)domain->pscid > 0) + if (domain->pscid > 0) ida_free(&riscv_iommu_pscids, domain->pscid); + if (domain->gscid > 0) + ida_free(&riscv_iommu_gscids, domain->gscid); =20 pt_iommu_deinit(&domain->riscvpt.iommu); kfree(domain); } =20 -static bool riscv_iommu_pt_supported(struct riscv_iommu_device *iommu, int= pgd_mode) +static bool riscv_iommu_fsc_supported(struct riscv_iommu_device *iommu, + int mode) { - switch (pgd_mode) { + switch (mode) { case RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39: return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39; =20 @@ -1280,6 +1294,22 @@ static bool riscv_iommu_pt_supported(struct riscv_io= mmu_device *iommu, int pgd_m return false; } =20 +static bool riscv_iommu_iohgatp_supported(struct riscv_iommu_device *iommu, + int mode) +{ + switch (mode) { + case RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4: + return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39X4; + + case RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4: + return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48X4; + + case RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4: + return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57X4; + } + return false; +} + static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_dom= ain, struct device *dev, struct iommu_domain *old) @@ -1292,11 +1322,21 @@ static int riscv_iommu_attach_paging_domain(struct = iommu_domain *iommu_domain, =20 pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info); =20 - if (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode)) - return -ENODEV; + if (domain->gscid) { + if (!riscv_iommu_iohgatp_supported(iommu, pt_info.iohgatp_mode)) + return -ENODEV; + + dc.iohgatp =3D + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) | + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn); + } else { + if (!riscv_iommu_fsc_supported(iommu, pt_info.fsc_iosatp_mode)) + return -ENODEV; =20 - dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | - FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn); + dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | + FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn); 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charset="utf-8" From: Tomasz Jeznach Enable KVM/VFIO support on RISC-V architecture. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Signed-off-by: Fangyu Yu --- arch/riscv/kvm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index ec2cee0a39e0..54ee90f010ef 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -30,8 +30,10 @@ config KVM select KVM_GENERIC_HARDWARE_ENABLING select KVM_MMIO select VIRT_XFER_TO_GUEST_WORK + select KVM_VFIO select SCHED_INFO select GUEST_PERF_EVENTS if PERF_EVENTS + select SRCU help Support hosting virtualized guest machines. =20 --=20 2.50.1 From nobody Fri Sep 25 08:46:27 2026 Received: from out30-133.freemail.mail.aliyun.com (out30-133.freemail.mail.aliyun.com [115.124.30.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B31540B6E0 for ; Tue, 15 Sep 2026 03:28:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.133 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789442932; cv=none; b=q+/qYo4RPehFKSIB9xLKDsd20jiBahJ/kjxmPpKX8MSHShgjmVlg86hZCqePfXsrIKBlPegCTT85UOUfNL4LDevYzUccccptP40+JGuW/HZDGiUQp1cNFuFD7yy/4Xpj88ccHAv8AQilSIQlaVrrbHvIFvKu0jUtb/c+YjME5Vw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789442932; c=relaxed/simple; bh=p27qs+OtcJzBDVBD0rm8C1yrc1YHIBZl7bpq//CT/fk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iWTlsFGv879CXLc1YmgmJ9HNcy5QOGV5Kv4jC4nmYm44vtKCkLcTuOPx+WvncqGVrQP+CpmJuqK9xyC1VhEEG3AMmXeqkA2nucRHexvxSi1nEzBwcOmWM8OB7zL+tzTDU9Q8U+weMHKlSyBcWRWvKOEHHAUrorMmQwadvYAhGDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=klDlAS35; arc=none smtp.client-ip=115.124.30.133 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="klDlAS35" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1789442928; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=LCjuUl5Vg31ifAecAxqfu+fj9ihDR4CFl7OLN0cLKZ4=; b=klDlAS35C1I0yfbm9XyZ5pfzKREHfh3AWfRCjU+41K+NCxOGWEppi65x1jfKrhdhXxoUOSLAvT3jFBonQnGZejk+JGoPX0H1dsP99I9J3XJaBgLlS800CZdi/qQjXaGhiEyDHdCCJg/Fza++wKBn63V3u/qBPBC/+eezDyMGmEk= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R161e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam011083073210;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=26;SR=0;TI=SMTPD_---0XB.uvRg_1789442925; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0XB.uvRg_1789442925 cluster:ay36) by smtp.aliyun-inc.com; Tue, 15 Sep 2026 11:28:46 +0800 From: fangyu.yu@linux.alibaba.com To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de, zong.li@sifive.com, andrew.jones@oss.qualcomm.com, anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com, joerg.roedel@amd.com Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [RFC PATCH v4 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain Date: Tue, 15 Sep 2026 11:28:26 +0800 Message-Id: <20260915032828.11250-8-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> References: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Replace .domain_alloc_paging with .domain_alloc_paging_flags so callers can pass allocation flags to select the appropriate page-table type. When IOMMU_HWPT_ALLOC_NEST_PARENT or IOMMU_HWPT_ALLOC_DIRTY_TRACKING is set in @flags, allocate a second-stage (iohgatp) domain. When @flags is 0 the behaviour is identical to the previous domain_alloc_paging: first-stage (iosatp) domain. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 94 +++++++++++++++++++++++++++---------- 1 file changed, 69 insertions(+), 25 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 99f05f1db35b..16779877351b 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1358,25 +1358,21 @@ static const struct iommu_domain_ops riscv_iommu_pa= ging_domain_ops =3D { .flush_iotlb_all =3D riscv_iommu_iotlb_flush_all, }; =20 -static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device = *dev) +static struct iommu_domain * +riscv_iommu_domain_alloc_paging_flags(struct device *dev, u32 flags, + const struct iommu_user_data *user_data) { struct pt_iommu_riscv_64_cfg cfg =3D {}; struct riscv_iommu_domain *domain; struct riscv_iommu_device *iommu; int ret; + const u32 supported_flags =3D IOMMU_HWPT_ALLOC_DIRTY_TRACKING | + IOMMU_HWPT_ALLOC_NEST_PARENT; =20 - iommu =3D dev_to_iommu(dev); - if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57) { - cfg.common.hw_max_vasz_lg2 =3D 57; - } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48) { - cfg.common.hw_max_vasz_lg2 =3D 48; - } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39) { - cfg.common.hw_max_vasz_lg2 =3D 39; - } else { - dev_err(dev, "cannot find supported page table mode\n"); - return ERR_PTR(-ENODEV); - } - cfg.common.hw_max_oasz_lg2 =3D 56; + if (flags & ~supported_flags) + return ERR_PTR(-EOPNOTSUPP); + if (user_data) + return ERR_PTR(-EOPNOTSUPP); =20 domain =3D kzalloc_obj(*domain); if (!domain) @@ -1384,12 +1380,13 @@ static struct iommu_domain *riscv_iommu_alloc_pagin= g_domain(struct device *dev) =20 INIT_LIST_HEAD_RCU(&domain->bonds); spin_lock_init(&domain->lock); + iommu =3D dev_to_iommu(dev); + cfg.common.hw_max_oasz_lg2 =3D 56; /* * 6.4 IOMMU capabilities [..] IOMMU implementations must support the * Svnapot standard extension for NAPOT Translation Contiguity. */ - cfg.common.features =3D BIT(PT_FEAT_SIGN_EXTEND) | - BIT(PT_FEAT_FLUSH_RANGE) | + cfg.common.features =3D BIT(PT_FEAT_FLUSH_RANGE) | BIT(PT_FEAT_RISCV_SVNAPOT_64K) | BIT(PT_FEAT_DETAILED_GATHER); if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT) @@ -1397,19 +1394,66 @@ static struct iommu_domain *riscv_iommu_alloc_pagin= g_domain(struct device *dev) domain->riscvpt.iommu.nid =3D dev_to_node(iommu->dev); domain->domain.ops =3D &riscv_iommu_paging_domain_ops; =20 - domain->pscid =3D ida_alloc_range(&riscv_iommu_pscids, 1, - RISCV_IOMMU_MAX_PSCID, GFP_KERNEL); - if (domain->pscid < 0) { - riscv_iommu_free_paging_domain(&domain->domain); - return ERR_PTR(-ENOMEM); + switch (flags) { + case 0: + cfg.common.features |=3D BIT(PT_FEAT_SIGN_EXTEND); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57) { + cfg.common.hw_max_vasz_lg2 =3D 57; + } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48) { + cfg.common.hw_max_vasz_lg2 =3D 48; + } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39) { + cfg.common.hw_max_vasz_lg2 =3D 39; + } else { + ret =3D -ENODEV; + goto err_free; + } + domain->pscid =3D ida_alloc_range(&riscv_iommu_pscids, 1, + RISCV_IOMMU_MAX_PSCID, GFP_KERNEL); + if (domain->pscid < 0) { + ret =3D -ENOMEM; + goto err_free; + } + break; + case IOMMU_HWPT_ALLOC_NEST_PARENT: + case IOMMU_HWPT_ALLOC_DIRTY_TRACKING: + case IOMMU_HWPT_ALLOC_DIRTY_TRACKING | IOMMU_HWPT_ALLOC_NEST_PARENT: + /* + * Second-stage (iohgatp) page table for KVM VFIO device + * pass-through and dirty tracking. The GPA space is 2 bits + * wider than the corresponding first-stage VA space (x4 root + * page table), so hw_max_vasz_lg2 values are 41/50/59. + */ + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57X4) { + cfg.common.hw_max_vasz_lg2 =3D 59; + } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48X4) { + cfg.common.hw_max_vasz_lg2 =3D 50; + } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39X4) { + cfg.common.hw_max_vasz_lg2 =3D 41; + } else { + ret =3D -ENODEV; + goto err_free; + } + domain->gscid =3D ida_alloc_range(&riscv_iommu_gscids, 1, + RISCV_IOMMU_MAX_GSCID, GFP_KERNEL); + if (domain->gscid < 0) { + ret =3D -ENOMEM; + goto err_free; + } + cfg.common.features |=3D BIT(PT_FEAT_RISCV_S2); + break; + default: + ret =3D -EOPNOTSUPP; + goto err_free; } =20 ret =3D pt_iommu_riscv_64_init(&domain->riscvpt, &cfg, GFP_KERNEL); - if (ret) { - riscv_iommu_free_paging_domain(&domain->domain); - return ERR_PTR(ret); - } + if (ret) + goto err_free; return &domain->domain; + +err_free: + riscv_iommu_free_paging_domain(&domain->domain); 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Tue, 15 Sep 2026 11:28:48 +0800 From: fangyu.yu@linux.alibaba.com To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de, zong.li@sifive.com, andrew.jones@oss.qualcomm.com, anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com, joerg.roedel@amd.com Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [RFC PATCH v4 08/10] iommu/riscv: Pre-enable GADE for second-stage domains Date: Tue, 15 Sep 2026 11:28:27 +0800 Message-Id: <20260915032828.11250-9-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> References: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Pre-enable RISCV_IOMMU_DC_TC_GADE in the device context when attaching a second-stage domain, if the IOMMU supports AMO_HWAD. Software pre-populates second-stage page tables with D set, so enabling GADE by default does not change normal behavior. When dirty tracking is enabled, iommufd clears the pre-set D bits and GADE becomes necessary for hardware to update the dirty bit on write access. This avoids toggling GADE dynamically and keeps device context setup consistent with second-stage domain attachment. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 16779877351b..f01fd4e2f840 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1330,6 +1330,8 @@ static int riscv_iommu_attach_paging_domain(struct io= mmu_domain *iommu_domain, FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) | FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD) + dc.tc |=3D RISCV_IOMMU_DC_TC_GADE; } else { if (!riscv_iommu_fsc_supported(iommu, pt_info.fsc_iosatp_mode)) return -ENODEV; --=20 2.50.1 From nobody Fri Sep 25 08:46:27 2026 Received: from out30-99.freemail.mail.aliyun.com (out30-99.freemail.mail.aliyun.com [115.124.30.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7BB540681E for ; Tue, 15 Sep 2026 03:29:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.99 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789442942; cv=none; b=EueDMbXMAUxNyk3V2g6bsEp6hc1St3Im/Gvv/h/CO9t3VPJk1bUMstxhF8Lj0OiMxuttL2h7WdRcKV4U4jI5zOcR8hR+QS2YOt9BDDrAjGf1Si1tU/Ky9GdWpR/GLJebxIBAPW5hFdgP2OwxSsSyq6NQ1It3IfPACJl3/8NxREc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789442942; c=relaxed/simple; bh=UJS9DOCrsoCGIwsSYHWDVLuRjPpoOj+rrTHKwDqF2vs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dngAzIYgrtpzG+JKPHEd73u8mpeuO4bt1lkO59PHNyZntwAMUeop8UcSTaM3H4A0U27+U4qJMtxIbVtu6Vo752UuF6nuwHImwJWIxNaxekZutEgWBkQ06kvdnHkDQe3rv5epIYHXlTQspWZwSiPeXYA5Vz9BMvHDj7IKOYHk65w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=R7aj9coy; arc=none smtp.client-ip=115.124.30.99 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="R7aj9coy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1789442932; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=bJah1AVjklnltP+n9003t/Lfq0Y0xBXEyF9SiWfTvEg=; b=R7aj9coyj+ECNvKXzrHQPeEq3QCNcyRqGplccq5vGSKbxGyzw6+WSZlQmLtdphzYeJVlWIAgVlwq/XFwDWBX2BNgPDzjOX6dB1Ix5FqLhUFf0a5D2QGDvRKEQVY4olo56WlypaOpCgHtyDRqYWJMXnKQkE2GGdo97IYhnVniy6A= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R161e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037026112;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=26;SR=0;TI=SMTPD_---0XB.uvT3_1789442928; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0XB.uvT3_1789442928 cluster:ay36) by smtp.aliyun-inc.com; Tue, 15 Sep 2026 11:28:50 +0800 From: fangyu.yu@linux.alibaba.com To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de, zong.li@sifive.com, andrew.jones@oss.qualcomm.com, anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com, joerg.roedel@amd.com Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [RFC PATCH v4 09/10] iommu/riscv: Add dirty tracking support for second-stage domains Date: Tue, 15 Sep 2026 11:28:28 +0800 Message-Id: <20260915032828.11250-10-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> References: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Add hardware dirty tracking support for second-stage (iohgatp) domains used in KVM VFIO device pass-through. The RISC-V IOMMU can automatically set the dirty bit in PTEs on write access when DC.tc.GADE is set and the hardware has AMO_HWAD capability. Wire this up to the iommufd dirty tracking interface: - riscv_iommu_set_dirty_tracking(): Always enabled dirty tracking for second-stage domain. - riscv_iommu_dirty_ops: Exposes set_dirty_tracking and the generic page-table read_and_clear_dirty via IOMMU_PT_DIRTY_OPS(riscv_64). - domain_alloc_paging_flags: Assigns dirty_ops to second-stage domains when AMO_HWAD is advertised in hardware capabilities. - riscv_iommu_capable: Reports IOMMU_CAP_DIRTY_TRACKING when AMO_HWAD is present. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index f01fd4e2f840..41b593def1f5 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1352,6 +1352,21 @@ static int riscv_iommu_attach_paging_domain(struct i= ommu_domain *iommu_domain, return 0; } =20 +static int riscv_iommu_set_dirty_tracking(struct iommu_domain *iommu_domai= n, + bool enable) +{ + /* + * Always enabled and the dirty bitmap is cleared prior to + * set_dirty_tracking(). + */ + return 0; +} + +static const struct iommu_dirty_ops riscv_iommu_dirty_ops =3D { + IOMMU_PT_DIRTY_OPS(riscv_64), + .set_dirty_tracking =3D riscv_iommu_set_dirty_tracking, +}; + static const struct iommu_domain_ops riscv_iommu_paging_domain_ops =3D { IOMMU_PT_DOMAIN_OPS(riscv_64), .attach_dev =3D riscv_iommu_attach_paging_domain, @@ -1442,6 +1457,8 @@ riscv_iommu_domain_alloc_paging_flags(struct device *= dev, u32 flags, goto err_free; } cfg.common.features |=3D BIT(PT_FEAT_RISCV_S2); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD) + domain->domain.dirty_ops =3D &riscv_iommu_dirty_ops; break; default: ret =3D -EOPNOTSUPP; @@ -1517,9 +1534,13 @@ static struct iommu_group *riscv_iommu_device_group(= struct device *dev) =20 static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) { + struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); + switch (cap) { case IOMMU_CAP_CACHE_COHERENCY: return true; + case IOMMU_CAP_DIRTY_TRACKING: + return !!(iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD); default: return false; } --=20 2.50.1 From nobody Fri Sep 25 08:46:27 2026 Received: from out30-101.freemail.mail.aliyun.com (out30-101.freemail.mail.aliyun.com [115.124.30.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 480B137D100 for ; Thu, 17 Sep 2026 02:56:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 17 Sep 2026 10:56:02 +0800 From: fangyu.yu@linux.alibaba.com To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de, zong.li@sifive.com, andrew.jones@oss.qualcomm.com, anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com, gsh517025@gmail.com, joerg.roedel@amd.com Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [RFC PATCH v4 10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries Date: Thu, 17 Sep 2026 10:54:46 +0800 Message-Id: <20260917025446.4070-1-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> References: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Previously, only IOTINVAL.VMA was issued, which is insufficient for second-stage address translation consistency. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 41b593def1f5..e848a7f97771 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1153,12 +1153,15 @@ static void riscv_iommu_iodir_iotinval(struct riscv= _iommu_device *iommu, /* * else: IOTINVAL.VMA with GV=3D1,AV=3DPSCV=3D0,and * GSCID=3DDC.iohgatp.GSCID - * + */ + riscv_iommu_cmd_send(iommu, &cmd); + /* * IOTINVAL.GVMA with GV=3D1,AV=3D0,and * GSCID=3DDC.iohgatp.GSCID - * TODO: For now, the Second-Stage feature have not yet been merged, - * also issue IOTINVAL.GVMA once second-stage support is merged. */ + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, + FIELD_GET(RISCV_IOMMU_DC_IOHGATP_GSCID, iohgatp)); } riscv_iommu_cmd_send(iommu, &cmd); } --=20 2.50.1