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Mon, 14 Sep 2026 19:29:12 -0700 (PDT) From: Nicholas Dudar To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, James.Bottomley@HansenPartnership.com, deller@gmx.de Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, bpf@vger.kernel.org, linux-parisc@vger.kernel.org, linux-kernel@vger.kernel.org, visitorckw@gmail.com Subject: [PATCH bpf-next v2 1/2] bpf, parisc: Add support for BPF_SDIV and BPF_SMOD in the parisc64 JIT Date: Mon, 14 Sep 2026 22:29:04 -0400 Message-ID: <20260915022905.1535566-2-main.kalliope@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260915022905.1535566-1-main.kalliope@gmail.com> References: <20260915022905.1535566-1-main.kalliope@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" emit_call_libgcc_ll() zero-extends the ALU32 operands and calls the unsigned hppa_div64()/hppa_div64_rem() helpers regardless of the BPF instruction's signedness, so the parisc64 JIT does not implement signed BPF_SDIV and BPF_SMOD (off =3D=3D 1). Signed ALU32 and ALU64 div/mod get an unsigned quotient and remainder rather than the verifier's and the interpreter's signed result for negative operands. Add hppa_sdiv64()/hppa_sdiv64_rem() wrapping div64_s64(), thread is_signed =3D (insn->off =3D=3D 1) through the div/mod emit sites, and on t= he signed path sign-extend the ALU32 operands (and the immediate divisor) instead of zero-extending them before calling the signed helpers. bpf_do_misc_fixups() rewrites the zero-divisor and INT_MIN/-1 cases out of the instruction stream before the JIT runs. Acked-by: Helge Deller Tested-by: Helge Deller Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Nicholas Dudar --- arch/parisc/net/bpf_jit.h | 2 ++ arch/parisc/net/bpf_jit_comp64.c | 35 ++++++++++++++++++++++++-------- arch/parisc/net/bpf_jit_core.c | 14 +++++++++++++ 3 files changed, 42 insertions(+), 9 deletions(-) diff --git a/arch/parisc/net/bpf_jit.h b/arch/parisc/net/bpf_jit.h index 8b8896959f044..074115c93c909 100644 --- a/arch/parisc/net/bpf_jit.h +++ b/arch/parisc/net/bpf_jit.h @@ -467,6 +467,8 @@ static inline u32 hppa_t21_insn(u8 opcode, u8 r2, u8 r1= , u8 ext8, u8 t) =20 u64 hppa_div64(u64 div, u64 divisor); u64 hppa_div64_rem(u64 div, u64 divisor); +u64 hppa_sdiv64(u64 div, u64 divisor); +u64 hppa_sdiv64_rem(u64 div, u64 divisor); =20 /* Helper functions that emit HPPA instructions when possible. */ =20 diff --git a/arch/parisc/net/bpf_jit_comp64.c b/arch/parisc/net/bpf_jit_com= p64.c index 54b0d5e25e024..c326fa737ec8c 100644 --- a/arch/parisc/net/bpf_jit_comp64.c +++ b/arch/parisc/net/bpf_jit_comp64.c @@ -502,14 +502,19 @@ static void emit_call(u64 addr, bool fixed, struct hp= pa_jit_context *ctx) emit_hppa_copy(HPPA_REG_RET0, regmap[BPF_REG_0], ctx); } =20 -static void emit_call_libgcc_ll(void *func, const s8 arg0, - const s8 arg1, u8 opcode, struct hppa_jit_context *ctx) +static void emit_call_libgcc_ll(void *func, const s8 arg0, const s8 arg1, + u8 opcode, bool is_signed, struct hppa_jit_context *ctx) { u64 func_addr; =20 if (BPF_CLASS(opcode) =3D=3D BPF_ALU) { - emit_hppa64_zext32(arg0, HPPA_REG_ARG0, ctx); - emit_hppa64_zext32(arg1, HPPA_REG_ARG1, ctx); + if (is_signed) { + emit_hppa64_sext32(arg0, HPPA_REG_ARG0, ctx); + emit_hppa64_sext32(arg1, HPPA_REG_ARG1, ctx); + } else { + emit_hppa64_zext32(arg0, HPPA_REG_ARG0, ctx); + emit_hppa64_zext32(arg1, HPPA_REG_ARG1, ctx); + } } else { emit_hppa_copy(arg0, HPPA_REG_ARG0, ctx); emit_hppa_copy(arg1, HPPA_REG_ARG1, ctx); @@ -600,6 +605,8 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, stru= ct hppa_jit_context *ctx, u8 rd =3D -1, rs =3D -1, code =3D insn->code; s16 off =3D insn->off; s32 imm =3D insn->imm; + bool is_signed; + void *func; =20 init_regs(&rd, &rs, insn, ctx); =20 @@ -656,29 +663,39 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, st= ruct hppa_jit_context *ctx, fallthrough; case BPF_ALU | BPF_MUL | BPF_X: case BPF_ALU64 | BPF_MUL | BPF_X: - emit_call_libgcc_ll(__muldi3, rd, rs, code, ctx); + emit_call_libgcc_ll(__muldi3, rd, rs, code, false, ctx); if (!is64 && !aux->verifier_zext) emit_zext_32(rd, ctx); break; case BPF_ALU | BPF_DIV | BPF_K: case BPF_ALU64 | BPF_DIV | BPF_K: - emit_imm(HPPA_REG_T1, is64 ? (s64)(s32)imm : (u32)imm, HPPA_REG_T2, ctx); + is_signed =3D (off =3D=3D 1); + emit_imm(HPPA_REG_T1, + is64 || is_signed ? (s64)(s32)imm : (u32)imm, + HPPA_REG_T2, ctx); rs =3D HPPA_REG_T1; fallthrough; case BPF_ALU | BPF_DIV | BPF_X: case BPF_ALU64 | BPF_DIV | BPF_X: - emit_call_libgcc_ll(&hppa_div64, rd, rs, code, ctx); + is_signed =3D (off =3D=3D 1); + func =3D is_signed ? &hppa_sdiv64 : &hppa_div64; + emit_call_libgcc_ll(func, rd, rs, code, is_signed, ctx); if (!is64 && !aux->verifier_zext) emit_zext_32(rd, ctx); break; case BPF_ALU | BPF_MOD | BPF_K: case BPF_ALU64 | BPF_MOD | BPF_K: - emit_imm(HPPA_REG_T1, is64 ? (s64)(s32)imm : (u32)imm, HPPA_REG_T2, ctx); + is_signed =3D (off =3D=3D 1); + emit_imm(HPPA_REG_T1, + is64 || is_signed ? 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Mon, 14 Sep 2026 19:29:16 -0700 (PDT) Received: from Turin ([187.15.143.6]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9121a4fb3e4sm90358906d6.24.2026.09.14.19.29.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 19:29:16 -0700 (PDT) From: Nicholas Dudar To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, James.Bottomley@HansenPartnership.com, deller@gmx.de Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, bpf@vger.kernel.org, linux-parisc@vger.kernel.org, linux-kernel@vger.kernel.org, visitorckw@gmail.com Subject: [PATCH bpf-next v2 2/2] bpf, parisc: Add support for BPF_SDIV and BPF_SMOD in the parisc32 JIT Date: Mon, 14 Sep 2026 22:29:05 -0400 Message-ID: <20260915022905.1535566-3-main.kalliope@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260915022905.1535566-1-main.kalliope@gmail.com> References: <20260915022905.1535566-1-main.kalliope@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" emit_alu_r32() and emit_alu_r64() call the unsigned millicode ($$divU/$$remU) and libgcc-style (hppa_div64()/hppa_div64_rem()) divide/remainder helpers for BPF_DIV and BPF_MOD regardless of the BPF instruction's signedness, so the parisc32 JIT does not implement signed BPF_SDIV and BPF_SMOD (off =3D=3D 1). Signed ALU32 and ALU64 div/mod get an unsigned quotient and remainder rather than the verifier's and the interpreter's signed result for negative operands. Thread is_signed =3D (insn->off =3D=3D 1) through emit_alu_r32()/ emit_alu_r64(), and on the signed path use the $$divI/$$remI signed millicode routines (32-bit) or the hppa_sdiv64()/hppa_sdiv64_rem() helpers added in patch 1 (64-bit) instead of their unsigned counterparts. $$divI and $$remI are extern-declared and exported next to $$divU/$$remU in arch/parisc/kernel/parisc_ksyms.c. bpf_do_misc_fixups() rewrites the zero-divisor and INT_MIN/-1 cases out of the instruction stream before the JIT runs. Acked-by: Helge Deller Tested-by: Helge Deller Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Nicholas Dudar --- arch/parisc/net/bpf_jit_comp32.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/arch/parisc/net/bpf_jit_comp32.c b/arch/parisc/net/bpf_jit_com= p32.c index 5ff0cf925fe95..eea0a34a3bfee 100644 --- a/arch/parisc/net/bpf_jit_comp32.c +++ b/arch/parisc/net/bpf_jit_comp32.c @@ -321,6 +321,8 @@ static void bpf_put_reg32(const s8 *reg, const s8 *src, extern void $$mulI(void); extern void $$divU(void); extern void $$remU(void); +extern void $$divI(void); +extern void $$remI(void); =20 static void emit_call_millicode(void *func, const s8 arg0, const s8 arg1, u8 opcode, struct hppa_jit_context *ctx) @@ -562,12 +564,14 @@ static void emit_alu_i32(const s8 *dst, s32 imm, } =20 static void emit_alu_r64(const s8 *dst, const s8 *src, - struct hppa_jit_context *ctx, const u8 op) + struct hppa_jit_context *ctx, const u8 op, + bool is_signed) { const s8 *tmp1 =3D regmap[TMP_REG_1]; const s8 *tmp2 =3D regmap[TMP_REG_2]; const s8 *rd; const s8 *rs =3D bpf_get_reg64(src, tmp2, ctx); + void *func; =20 if (op =3D=3D BPF_MOV) rd =3D bpf_get_reg64_ref(dst, tmp1, false, ctx); @@ -604,10 +608,12 @@ static void emit_alu_r64(const s8 *dst, const s8 *src, emit_call_libgcc_ll(__muldi3, rd, rs, op, ctx); break; case BPF_DIV: - emit_call_libgcc_ll(&hppa_div64, rd, rs, op, ctx); + func =3D is_signed ? &hppa_sdiv64 : &hppa_div64; + emit_call_libgcc_ll(func, rd, rs, op, ctx); break; case BPF_MOD: - emit_call_libgcc_ll(&hppa_div64_rem, rd, rs, op, ctx); + func =3D is_signed ? &hppa_sdiv64_rem : &hppa_div64_rem; + emit_call_libgcc_ll(func, rd, rs, op, ctx); break; case BPF_LSH: emit_call_libgcc_ll(__ashldi3, rd, rs, op, ctx); @@ -630,7 +636,8 @@ static void emit_alu_r64(const s8 *dst, const s8 *src, } =20 static void emit_alu_r32(const s8 *dst, const s8 *src, - struct hppa_jit_context *ctx, const u8 op) + struct hppa_jit_context *ctx, const u8 op, + bool is_signed) { const s8 *tmp1 =3D regmap[TMP_REG_1]; const s8 *tmp2 =3D regmap[TMP_REG_2]; @@ -666,10 +673,12 @@ static void emit_alu_r32(const s8 *dst, const s8 *src, emit_call_millicode($$mulI, lo(rd), lo(rs), op, ctx); break; case BPF_DIV: - emit_call_millicode($$divU, lo(rd), lo(rs), op, ctx); + emit_call_millicode(is_signed ? $$divI : $$divU, + lo(rd), lo(rs), op, ctx); break; case BPF_MOD: - emit_call_millicode($$remU, lo(rd), lo(rs), op, ctx); + emit_call_millicode(is_signed ? $$remI : $$remU, + lo(rd), lo(rs), op, ctx); break; case BPF_LSH: emit(hppa_subi(0x1f, lo(rs), HPPA_REG_T0), ctx); @@ -1163,12 +1172,12 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, = struct hppa_jit_context *ctx, emit_imm32(tmp2, imm, ctx); src =3D tmp2; } - emit_alu_r64(dst, src, ctx, BPF_OP(code)); + emit_alu_r64(dst, src, ctx, BPF_OP(code), off =3D=3D 1); break; =20 /* dst =3D -dst */ case BPF_ALU64 | BPF_NEG: - emit_alu_r64(dst, tmp2, ctx, BPF_OP(code)); + emit_alu_r64(dst, tmp2, ctx, BPF_OP(code), false); break; =20 case BPF_ALU64 | BPF_MOV | BPF_K: @@ -1211,7 +1220,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, st= ruct hppa_jit_context *ctx, emit_imm32(tmp2, imm, ctx); src =3D tmp2; } - emit_alu_r32(dst, src, ctx, BPF_OP(code)); + emit_alu_r32(dst, src, ctx, BPF_OP(code), off =3D=3D 1); break; =20 /* dst =3D dst OP imm */ @@ -1236,7 +1245,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, st= ruct hppa_jit_context *ctx, * src is ignored---choose tmp2 as a dummy register since it * is not on the stack. */ - emit_alu_r32(dst, tmp2, ctx, BPF_OP(code)); + emit_alu_r32(dst, tmp2, ctx, BPF_OP(code), false); break; =20 /* dst =3D BSWAP##imm(dst) */