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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33ba4fa50e3sm31115791eec.29.2026.09.14.18.56.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 18:56:56 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Krishna Chaitanya Chundru , Yu Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Bartosz Golaszewski , Shawn Guo Subject: [PATCH v2 1/5] arm64: dts: qcom: nord: Add PCIe PHY and controller nodes Date: Tue, 15 Sep 2026 09:56:28 +0800 Message-ID: <20260915015632.283642-2-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> References: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=G+KJgNk5 c=1 sm=1 tr=0 ts=6aa8a5ea cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=7rqOJILHKxEwWM2FdFwA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfX3mcGhT3eFcVz uSYOT4bFQ1Sikxp4BSbVoApfB9K2NS4gGlb8ifuxyVEcz6yIdZgZPjUidg+RemZI/qeP7R6jHKM ZhlqXhhoQn5kIEAOXxEC+Fmj/Cktr5pK0SDJ0zRNekiQNGJ8uUGKGzchV5vqpr4mayRI7z2myAs NAoljetWy0Dsj8xDJJ+k879RqseaHo6BARwrH/jtOmAh6037l0wCzggQ44dC5DkdCl5ZRl3cHiI PRwBJs/Bsif35e5lSNoMod6zCX+XpKqX7YAJ1ME0oH/PTGb5y16FRAFCNoAYA5V39Vv31N8jDvd vb42ktc9EAzHVRSqafxKzBOEzzQN4z3g03Ij/VgbXxmRVF3Et/QNAl8I9DguqEIdzgN3rxWNoBN JW1JgtRHjw++oZfpUQeeT5HgjkYi56MkaEmaQVnpnM8tg3fcn+uOqSCotnUlrzGI/+I1NwfLHdp svuYw1yFamXJi8Qnbfg== X-Proofpoint-GUID: z8SOGSxedmJtFeBSbPc6oUTaCf6WZoR2 X-Proofpoint-ORIG-GUID: z8SOGSxedmJtFeBSbPc6oUTaCf6WZoR2 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfX5CjzkFgoYcxI +Y7dPcE2L8U5Mg8MQJ5mX5E/rdHoVcjqLH4zm/oescLAIWsBpDDndDcS4vSOEwyL3wS5WFC44+z QikXr7upE7EasLZZTy6TjH+74jwn0JM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-14_05,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 impostorscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 adultscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150024 Content-Type: text/plain; charset="utf-8" From: Krishna Chaitanya Chundru Nord has four PCIe controllers backed by a single quadfurcated Gen5 QMP PHY with four ports (A/B/C/D) and a common PCIe SMMU. The ports can be ganged into x16, x8+x8, x8+x4+x4 or x8+x4+x2+x2 topologies; the topology in effect is selected by firmware through the TCSR link-config mode register, which the PHY driver reads at probe time. Describe the x8+x4+x2+x2 topology, i.e. all four controllers usable, as that is the configuration the boards ship with. Add the controller and SMMU nodes to nord.dtsi, and the PHY node along with the per-controller clocks, resets, GDSCs, interconnects, OPP tables and TLMM pin states to nord-embedded.dtsi. The four PCIe pipe clocks also become available now, so hook them up as GCC parents in place of the <0> placeholders. The controllers and the PHY are left disabled here and enabled per board. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 926 +++++++++++++++++++- arch/arm64/boot/dts/qcom/nord.dtsi | 297 +++++++ 2 files changed, 1219 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/= dts/qcom/nord-embedded.dtsi index c7ac2e66632e..6e79f3cb20e9 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -342,6 +342,738 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, pinctrl-names =3D "default"; }; =20 +&pcie0 { + clocks =3D <&gcc GCC_PCIE_A_AUX_CLK>, + <&gcc GCC_PCIE_A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_A_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_A_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_data_inbound MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + power-domains =3D <&gcc GCC_PCIE_A_GDSC>; + + resets =3D <&gcc GCC_PCIE_A_BCR>, + <&gcc GCC_PCIE_A_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + pinctrl-0 =3D <&pcie0_default>; + pinctrl-names =3D "default"; + + operating-points-v2 =3D <&pcie0_opp_table>; + + pcie0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x8 */ + opp-20000000-1 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x16 */ + opp-40000000-1 { + opp-hz =3D /bits/ 64 <40000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <4000000 1>; + opp-level =3D <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x8 */ + opp-40000000-2 { + opp-hz =3D /bits/ 64 <40000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <4000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x16 */ + opp-80000000-2 { + opp-hz =3D /bits/ 64 <80000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <8000000 1>; + opp-level =3D <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x8 */ + opp-64000000-3 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x16 */ + opp-128000000-3 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x8 */ + opp-128000000-4 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x16 */ + opp-256000000-4 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <31506000 1>; + opp-level =3D <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x8 */ + opp-256000000-5 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <31506000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x16 */ + opp-512000000-5 { + opp-hz =3D /bits/ 64 <512000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <63012000 1>; + opp-level =3D <5>; + }; + }; +}; + +&pcie0_port0 { + phys =3D <&pcie_phy 0>; +}; + +&pcie1 { + clocks =3D <&gcc GCC_PCIE_B_AUX_CLK>, + <&gcc GCC_PCIE_B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_B_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_B_SLV_AXI_CLK>, + <&gcc GCC_PCIE_B_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_B_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_data_inbound MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + power-domains =3D <&gcc GCC_PCIE_B_GDSC>; + + resets =3D <&gcc GCC_PCIE_B_BCR>, + <&gcc GCC_PCIE_B_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + pinctrl-0 =3D <&pcie1_default>; + pinctrl-names =3D "default"; + + operating-points-v2 =3D <&pcie1_opp_table>; + + pcie1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x8 */ + opp-20000000-1 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x8 */ + opp-40000000-2 { + opp-hz =3D /bits/ 64 <40000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <4000000 1>; + opp-level =3D <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x8 */ + opp-64000000-3 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x8 */ + opp-128000000-4 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x8 */ + opp-256000000-5 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <31506000 1>; + opp-level =3D <5>; + }; + }; +}; + +&pcie1_port0 { + phys =3D <&pcie_phy 1>; +}; + +&pcie2 { + clocks =3D <&gcc GCC_PCIE_C_AUX_CLK>, + <&gcc GCC_PCIE_C_CFG_AHB_CLK>, + <&gcc GCC_PCIE_C_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_C_SLV_AXI_CLK>, + <&gcc GCC_PCIE_C_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_C_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_data_inbound MASTER_PCIE_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + power-domains =3D <&gcc GCC_PCIE_C_GDSC>; + + resets =3D <&gcc GCC_PCIE_C_BCR>, + <&gcc GCC_PCIE_C_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + pinctrl-0 =3D <&pcie2_default>; + pinctrl-names =3D "default"; + + operating-points-v2 =3D <&pcie2_opp_table>; + + pcie2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <5>; + }; + }; +}; + +&pcie2_port0 { + phys =3D <&pcie_phy 2>; +}; + +&pcie3 { + clocks =3D <&gcc GCC_PCIE_D_AUX_CLK>, + <&gcc GCC_PCIE_D_CFG_AHB_CLK>, + <&gcc GCC_PCIE_D_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_D_SLV_AXI_CLK>, + <&gcc GCC_PCIE_D_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_D_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_data_inbound MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + power-domains =3D <&gcc GCC_PCIE_D_GDSC>; + + resets =3D <&gcc GCC_PCIE_D_BCR>, + <&gcc GCC_PCIE_D_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + pinctrl-0 =3D <&pcie3_default>; + pinctrl-names =3D "default"; + + operating-points-v2 =3D <&pcie3_opp_table>; + + pcie3_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <5>; + }; + }; +}; + +&pcie3_port0 { + phys =3D <&pcie_phy 3>; +}; + &qupv3_0 { clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_M_AHB_CLK>, <&segcc SE_GCC_QUPV3_WRAP0_S_AHB_CLK>; @@ -704,10 +1436,10 @@ gcc: clock-controller@100000 { reg =3D <0x0 0x00100000 0x0 0x1f4200>; clocks =3D <&bi_tcxo_div2>, <&sleep_clk>, - <0>, - <0>, - <0>, - <0>; + <&pcie_phy 0>, + <&pcie_phy 1>, + <&pcie_phy 2>, + <&pcie_phy 3>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; @@ -774,6 +1506,100 @@ mmss_noc: interconnect@1780000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + pcie_phy: phy@1b00000 { + compatible =3D "qcom,nord-qmp-gen5x16-pcie-phy"; + + reg =3D <0x0 0x01b00000 0x0 0x10000>, + <0x0 0x01b10000 0x0 0x10000>, + <0x0 0x01b20000 0x0 0x10000>, + <0x0 0x01b30000 0x0 0x10000>; + reg-names =3D "port_a", + "port_b", + "port_c", + "port_d"; + + clocks =3D <&gcc GCC_PCIE_A_PHY_AUX_CLK>, + <&gcc GCC_PCIE_A_CFG_AHB_CLK>, + <&tcsrcc TCSR_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_A_PIPE_CLK>, + <&gcc GCC_PCIE_B_PHY_AUX_CLK>, + <&gcc GCC_PCIE_B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_B_PIPE_CLK>, + <&gcc GCC_PCIE_C_PHY_AUX_CLK>, + <&gcc GCC_PCIE_C_CFG_AHB_CLK>, + <&gcc GCC_PCIE_C_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_C_PIPE_CLK>, + <&gcc GCC_PCIE_D_PHY_AUX_CLK>, + <&gcc GCC_PCIE_D_CFG_AHB_CLK>, + <&gcc GCC_PCIE_D_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_D_PIPE_CLK>; + clock-names =3D "aux_a", + "cfg_ahb_a", + "ref", + "rchng_a", + "pipe_a", + "aux_b", + "cfg_ahb_b", + "rchng_b", + "pipe_b", + "aux_c", + "cfg_ahb_c", + "rchng_c", + "pipe_c", + "aux_d", + "cfg_ahb_d", + "rchng_d", + "pipe_d"; + + assigned-clocks =3D <&gcc GCC_PCIE_A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_C_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_D_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>, + <100000000>, + <100000000>, + <100000000>; + + power-domains =3D <&gcc GCC_PCIE_A_PHY_GDSC>, + <&gcc GCC_PCIE_B_PHY_GDSC>, + <&gcc GCC_PCIE_C_PHY_GDSC>, + <&gcc GCC_PCIE_D_PHY_GDSC>; + power-domain-names =3D "port_a", + "port_b", + "port_c", + "port_d"; + + resets =3D <&gcc GCC_PCIE_A_PHY_COM_BCR>, + <&gcc GCC_PCIE_A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_B_PHY_COM_BCR>, + <&gcc GCC_PCIE_B_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_C_PHY_COM_BCR>, + <&gcc GCC_PCIE_C_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_D_PHY_COM_BCR>, + <&gcc GCC_PCIE_D_NOCSR_COM_PHY_BCR>; + reset-names =3D "port_a", + "port_a_nocsr", + "port_b", + "port_b_nocsr", + "port_c", + "port_c_nocsr", + "port_d", + "port_d_nocsr"; + + qcom,link-mode =3D <&tcsr 0x71050>; + + #clock-cells =3D <1>; + clock-output-names =3D "pcie_a_pipe_clk", + "pcie_b_pipe_clk", + "pcie_c_pipe_clk", + "pcie_d_pipe_clk"; + #phy-cells =3D <1>; + + status =3D "disabled"; + }; + pcie_cfg: interconnect@1ba0000 { compatible =3D "qcom,nord-pcie-cfg"; reg =3D <0x0 0x01ba0000 0x0 0x7200>; @@ -998,6 +1824,98 @@ nsp_data_noc_3: interconnect@1fe00000 { }; =20 &tlmm { + pcie0_default: pcie0-default-state { + wake-pins { + pins =3D "gpio0"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clkreq-pins { + pins =3D "gpio1"; + function =3D "pcie0_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + pcie1_default: pcie1-default-state { + wake-pins { + pins =3D "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clkreq-pins { + pins =3D "gpio4"; + function =3D "pcie1_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + pcie2_default: pcie2-default-state { + wake-pins { + pins =3D "gpio6"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clkreq-pins { + pins =3D "gpio7"; + function =3D "pcie2_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio8"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + pcie3_default: pcie3-default-state { + wake-pins { + pins =3D "gpio9"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clkreq-pins { + pins =3D "gpio10"; + function =3D "pcie3_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + qup_i2c0_default: qup-i2c0-default-state { pins =3D "gpio111", "gpio112"; function =3D "qup0_se0"; diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/= nord.dtsi index 83760341456b..0fb292074b99 100644 --- a/arch/arm64/boot/dts/qcom/nord.dtsi +++ b/arch/arm64/boot/dts/qcom/nord.dtsi @@ -1587,6 +1587,290 @@ rng: rng@10c3000 { reg =3D <0x0 0x010c3000 0x0 0x1000>; }; =20 + pcie0: pci@1b80000 { + compatible =3D "qcom,nord-pcie", "qcom,pcie-sa8775p"; + + reg =3D <0x00 0x01b80000 0x00 0x00004000>, + <0x00 0x40000000 0x00 0x00000f20>, + <0x00 0x40000f20 0x00 0x000000a8>, + <0x00 0x40010000 0x00 0x00020000>, + <0x00 0x40100000 0x00 0x00100000>, + <0x00 0x01b84000 0x00 0x00001000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0xfd00000>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <8>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + + iommu-map =3D <0x0 &pcie_smmu 0x0000 0x10000>; + + msi-map =3D <0x0 &gic_its 0x80000 0x10000>; + + status =3D "disabled"; + + pcie0_port0: pcie@0 { + compatible =3D "pciclass,0604"; + reg =3D <0 0 0 0 0>; + bus-range =3D <0x01 0xff>; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie1: pci@1b88000 { + compatible =3D "qcom,nord-pcie", "qcom,pcie-sa8775p"; + + reg =3D <0x00 0x01b88000 0x00 0x00004000>, + <0x00 0x50000000 0x00 0x00000f20>, + <0x00 0x50000f20 0x00 0x000000a8>, + <0x00 0x50010000 0x00 0x00010000>, + <0x00 0x50100000 0x00 0x00100000>, + <0x00 0x01b8c000 0x00 0x00001000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x50200000 0x0 0x100000>, + <0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0xfd00000>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + num-lanes =3D <4>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 835 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 351 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 830 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 348 IRQ_TYPE_LEVEL_HIGH>; + + msi-map =3D <0x0 &gic_its 0x90000 0x10000>; + + iommu-map =3D <0x0 &pcie_smmu 0x10000 0x10000>; + + status =3D "disabled"; + + pcie1_port0: pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0 0 0 0 0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie2: pci@1b90000 { + compatible =3D "qcom,nord-pcie", "qcom,pcie-sa8775p"; + + reg =3D <0x00 0x01b90000 0x00 0x00004000>, + <0x00 0x60000000 0x00 0x00000f20>, + <0x00 0x60000f20 0x00 0x000000a8>, + <0x00 0x60010000 0x00 0x00010000>, + <0x00 0x60100000 0x00 0x00100000>, + <0x00 0x01b94000 0x00 0x00001000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xfd00000>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <2>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 263 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 154 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 258 IRQ_TYPE_LEVEL_HIGH>; + + iommu-map =3D <0x0 &pcie_smmu 0x20000 0x10000>; + + msi-map =3D <0x0 &gic_its 0xa0000 0x10000>; + + status =3D "disabled"; + + pcie2_port0: pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0 0 0 0 0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie3: pci@1b98000 { + compatible =3D "qcom,nord-pcie", "qcom,pcie-sa8775p"; + + reg =3D <0x00 0x01b98000 0x00 0x00004000>, + <0x00 0x70000000 0x00 0x00000f20>, + <0x00 0x70000f20 0x00 0x000000a8>, + <0x00 0x70010000 0x00 0x00010000>, + <0x00 0x70100000 0x00 0x00100000>, + <0x00 0x01b9c000 0x00 0x00001000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0xfd00000>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <3>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 246 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 239 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 234 IRQ_TYPE_LEVEL_HIGH>; + + msi-map =3D <0x0 &gic_its 0xb0000 0x10000>; + + iommu-map =3D <0x0 &pcie_smmu 0x30000 0x10000>; + + status =3D "disabled"; + + pcie3_port0: pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0 0 0 0 0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + ufs_mem_hc: ufshc@1d44000 { compatible =3D "qcom,nord-ufshc", "qcom,ufshc", @@ -1736,6 +2020,19 @@ ipcc0: mailbox@9007000 { #mbox-cells =3D <2>; }; =20 + pcie_smmu: iommu@9980000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x09980000 0x0 0x20000>; + interrupts =3D , + , + ; + interrupt-names =3D "eventq", + "cmdq-sync", + "gerror"; + dma-coherent; + #iommu-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,nord-pdc", "qcom,pdc"; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33ba4fa50e3sm31115791eec.29.2026.09.14.18.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 18:57:00 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Krishna Chaitanya Chundru , Yu Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Abel Vesa , Bartosz Golaszewski , Shawn Guo Subject: [PATCH v2 2/5] arm64: dts: qcom: nord-rrd: Enable PCIe controllers and PHY Date: Tue, 15 Sep 2026 09:56:29 +0800 Message-ID: <20260915015632.283642-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> References: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 1Rg5uF-3PR-74KafUtE5PscMqny_qYwn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfX9SFFoaZVs7uU OM71lw8wk+sTL9X4OHV7mb/hkqyGL5sEYY9v1FYsUAwnkYnk3SQtprsNyop8KFOVCzsdiFiY4vr MzI3V7FatmlZ562Hp3XlLO5C62fr32SKI2QnFDfhvEeuog6YxD7lLLwZbn47BjlkFFE854N4SRP z85jCsim/aJ6y7aePCVoVMf3ulM/7pNvbny/MM3UubzxIxeWHfZmwssXeBp4NEa9ufymPPIi4pK WPnZFmsD/jh1ErW0ZIakobplTY1UeaDiAeOXaE1FSXeuJApNhQBPzijMiOVRK4YWrzIQuPw5M79 sL4g8s3hVOZR6tH94by8VEKHLR0SDbtceI/Psz1luPGjP4yJ8iYPJWwbv2o96jyqzoeJkKRE/le Z2qH9hkK9wniC2sHaCs94ETrcwEh7wLb//PKKXqolRfEXg+xGhSj7gAygrd7FDovT+zR6GyI6vj KOtlZY8NgBLGpVBbgnA== X-Proofpoint-GUID: 1Rg5uF-3PR-74KafUtE5PscMqny_qYwn X-Authority-Analysis: v=2.4 cv=M7TYuCws c=1 sm=1 tr=0 ts=6aa8a5ee cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=f6-OUQb2phOXiqkgZ7QA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfXzfKjg42098hn 6uLxId9Tis9eS+KxDpdK14wKHh6cpDLpl2TVhibxQ3CkFAm2tsVzN6AmUwdWgY47YsLT0iXOJXF 8vcsUpL1etAEIjmRzF4viCnI8oITnbY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-14_05,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 suspectscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150024 Content-Type: text/plain; charset="utf-8" From: Krishna Chaitanya Chundru The Nord Robotics Reference Design board routes all four PCIe links, so enable pcie0-pcie3 and the QMP PHY, supply the per-port PHY and PLL rails, and describe the PERST# and WAKE# lines of each root port. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-rrd.dts | 49 +++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qc= om/nord-rrd.dts index c547963371b4..4c4d54d7aa90 100644 --- a/arch/arm64/boot/dts/qcom/nord-rrd.dts +++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts @@ -377,6 +377,55 @@ rtc@32 { }; }; =20 +&pcie_phy { + vdda-phy-a-supply =3D <&vreg_l6a_1p2>; + vdda-phy-b-supply =3D <&vreg_l4a_1p2>; + vdda-phy-c-supply =3D <&vreg_l4a_1p2>; + vdda-phy-d-supply =3D <&vreg_l4a_1p2>; + vdda-pll-a-supply =3D <&vreg_l1e_0p9>; + vdda-pll-b-supply =3D <&vreg_l1e_0p9>; + vdda-pll-c-supply =3D <&vreg_l1e_0p9>; + vdda-pll-d-supply =3D <&vreg_l1e_0p9>; + + status =3D "okay"; +}; + +&pcie0 { + status =3D "okay"; +}; + +&pcie0_port0 { + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_LOW>; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33ba4fa50e3sm31115791eec.29.2026.09.14.18.57.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 18:57:05 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Krishna Chaitanya Chundru , Yu Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Abel Vesa , Bartosz Golaszewski , Shawn Guo Subject: [PATCH v2 3/5] arm64: dts: qcom: nord-ride-embedded: Enable PCIe controllers and PHY Date: Tue, 15 Sep 2026 09:56:30 +0800 Message-ID: <20260915015632.283642-4-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> References: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfX0GkpWcSmQm4f 7pUE5d1YhKsj1RcDsmGkaz5yUCWpvEkBnAF92XRgZZkN9SLywJ4nlElsJkP9o2hjKGN4iebNeV7 Jrpuv+L80O+8mJHthJYj8Y5XmAkIil2lgBSkHWgbIoHKc2SRNE8EF9O2dvFM9wd9MlSMlDy3j3k i0ERmxhdtEUe9ZV55TTCUfL0vyoU4jMYkK3Zs5PDScSFCxN2HaN6hA7dbSOqNAuVXGn7uSyg5k8 3QxsNCYDL5XSlJATA0FtB2fLLsxgsIXxzJCoK0qHtSrELMa3hR+ynLVqcuGoFglm676BR4Wd0C3 qmVu40uxpn5Bbs8jzfZQhRwIYNPcgmjqgcqtfhjPmANvkzH6D9To/v1MOEV4TdO+KolE5SBgDhO CGHum+5vh44Q2P84qerF/927b1PKEQR3XRAuudMtG76wGVPcf3Up4cUWiclYYz1JCkbFI918Dsn dIdgxoRo61Ji/91H3cg== X-Proofpoint-GUID: PPBrzw0De2EGAgxqRADHqkYkOGVf6d6- X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfX5pVT8SnXhEJw 1Mts9l0K7Y2HllRW8eIkGrzvIon1ygkwL/EPKnnajiT58/raGbCr4fGuq1hGtzZ94O8fyIBpiF4 zJloe+Ag6uJmTsuTDyi4jWnmqqKd0/g= X-Proofpoint-ORIG-GUID: PPBrzw0De2EGAgxqRADHqkYkOGVf6d6- X-Authority-Analysis: v=2.4 cv=MsrHeGae c=1 sm=1 tr=0 ts=6aa8a5f2 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=ccc3-NsNM3ZFeKEqOdcA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-14_05,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 malwarescore=0 suspectscore=0 clxscore=1015 adultscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150024 Content-Type: text/plain; charset="utf-8" From: Krishna Chaitanya Chundru The Nord Ride Embedded board routes all four PCIe links, so enable pcie0-pcie3 and the QMP PHY, supply the per-port PHY and PLL rails, and describe the PERST# and WAKE# lines of each root port. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- .../boot/dts/qcom/nord-ride-embedded.dts | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/b= oot/dts/qcom/nord-ride-embedded.dts index 09ee525764ef..0b230551a49f 100644 --- a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts +++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts @@ -366,6 +366,55 @@ vreg_l3l_1p8: ldo3 { }; }; =20 +&pcie_phy { + vdda-phy-a-supply =3D <&vreg_l6a_1p2>; + vdda-phy-b-supply =3D <&vreg_l4a_1p2>; + vdda-phy-c-supply =3D <&vreg_l4a_1p2>; + vdda-phy-d-supply =3D <&vreg_l4a_1p2>; + vdda-pll-a-supply =3D <&vreg_l1e_0p9>; + vdda-pll-b-supply =3D <&vreg_l1e_0p9>; + vdda-pll-c-supply =3D <&vreg_l1e_0p9>; + vdda-pll-d-supply =3D <&vreg_l1e_0p9>; + + status =3D "okay"; +}; + +&pcie0 { + status =3D "okay"; +}; + +&pcie0_port0 { + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33ba4fa50e3sm31115791eec.29.2026.09.14.18.57.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 18:57:09 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Krishna Chaitanya Chundru , Yu Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Konrad Dybcio , Bartosz Golaszewski , Shawn Guo Subject: [PATCH v2 4/5] arm64: dts: qcom: nord-ride-embedded: Add WCN7850 WLAN support Date: Tue, 15 Sep 2026 09:56:31 +0800 Message-ID: <20260915015632.283642-5-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> References: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfX1wvCnBPQhIPq ZCVL54d9iuhz8qVTY8l5SCwmqZeeM3AUPpyB+D16w0rVOT4MSJxGstu/Aoi9Q1WYlhCKHWO3iJQ ezMF+jpUFy45KNnRTts04s4IxBhvg60E3gWVHHe596XQHLlVZxxKEfnpPx80vv6YHYoWHClxktu gl+9SUUP0DdgTuSJanZPs8m/BUohrS4oepk81oyjnoM4JPErsuqzDZwtcwiHkRwHGHmmBOEjeTJ voztYZzDQQ88gO7XhOyY6N10nI9jtp7O6iV+Q7m18JSlI9L9AjfVFGjJ4mp+zZX4LVqR0oJR9Uw yz1J/SUPE/8FTzeFEwbhwKZ7ijKhEKb9vpsWhI9VQfE3XhEQHjJP5X0QfmmGbB4ezUkokB9vrZR q/VjPkSZvQKETej4WJKhvTqhI9RFT64WjE4M95hNMLMnpC8DAFegN+B2tyMfR0QLOkrzheeJLBq BybPiD+DIVKrgn428DA== X-Authority-Analysis: v=2.4 cv=TrFzFzXh c=1 sm=1 tr=0 ts=6aa8a5f7 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=btXJogeg36QJwmQpmpwA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-ORIG-GUID: d4vWfioHq72wpfkxxXeLpoIHntsvZiXh X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfXzkvQjpf8Tsv0 eSFsdym9WDgzil4v0ax9/8N2Mcvy+1iqjXlyYYSWPEWBTwitqr6WSW3PTWAS0/ugx6LYQEdpm6k MrQ5baZCodfmghqzj4Q3Tj4JF8+sjLw= X-Proofpoint-GUID: d4vWfioHq72wpfkxxXeLpoIHntsvZiXh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-14_05,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 clxscore=1015 suspectscore=0 impostorscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150024 Content-Type: text/plain; charset="utf-8" From: "Yu Zhang(Yuriy)" The Nord Ride Embedded board carries a QCA6797AQ (WCN7850) LGA module on a connectivity adapter card hanging off PCIe2. Two PMIC GPIOs gate the module supplies: PWR_CORE (pmau0102_e GPIO6) enables the DBU_CORE_VL, DBU_CORE_VM and DBU_CORE_VH regulators feeding VDD_CORE_VL/VM/VH, and PWR_CTRL1 (pmau0102_e GPIO8) enables DBU4, which produces the 3.3 V rail. PWR_CTRL2 drives DBU3, which is not populated, so it is left alone. Describe those rails, the WCN7850 PMU that derives the chip supplies from them, and the PCIe endpoint node consuming the PMU outputs. Signed-off-by: Yu Zhang (Yuriy) Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- .../boot/dts/qcom/nord-ride-embedded.dts | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/b= oot/dts/qcom/nord-ride-embedded.dts index 0b230551a49f..38d50f040c4d 100644 --- a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts +++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts @@ -53,6 +53,93 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-div =3D <2>; }; }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_wcn_3p3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&pmau0102_e_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_wcn_core_vl_0p95: regulator-wcn-core-vl-0p95 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_wcn_core_vl_0p95"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <950000>; + gpio =3D <&pmau0102_e_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_wcn_core_vm_1p35: regulator-wcn-core-vm-1p35 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_wcn_core_vm_1p35"; + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1350000>; + gpio =3D <&pmau0102_e_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_wcn_core_vh_1p95: regulator-wcn-core-vh-1p95 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_wcn_core_vh_1p95"; + regulator-min-microvolt =3D <1950000>; + regulator-max-microvolt =3D <1950000>; + gpio =3D <&pmau0102_e_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + wlan-enable-gpios =3D <&pmau0102_e_gpios 10 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <&vreg_wcn_3p3>; + vddio-supply =3D <&vreg_s3a_1p8>; + vddaon-supply =3D <&vreg_wcn_core_vl_0p95>; + vdddig-supply =3D <&vreg_wcn_core_vl_0p95>; + vddrfa1p2-supply =3D <&vreg_wcn_core_vm_1p35>; + vddrfa1p8-supply =3D <&vreg_wcn_core_vh_1p95>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; }; =20 &apps_rsc { @@ -404,6 +491,21 @@ &pcie2 { &pcie2_port0 { reset-gpios =3D <&tlmm 8 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 6 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible =3D "pci17cb,1107"; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33ba4fa50e3sm31115791eec.29.2026.09.14.18.57.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 18:57:14 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Krishna Chaitanya Chundru , Yu Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , Abel Vesa , Konrad Dybcio , Bartosz Golaszewski Subject: [PATCH v2 5/5] arm64: dts: qcom: nord-rrd: Add WCN7850 WLAN support Date: Tue, 15 Sep 2026 09:56:32 +0800 Message-ID: <20260915015632.283642-6-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> References: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: F264nFVMSM47TBeBngpoPY9CRsE5vrRW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfXwRyLqwM9gHqW s9zsmQgmdA8svvSA9seIkS4k9j6n/VMDqLxcNCF2TlujwGrcYrTQnWV1LJ5aFXf3aKlI3MauGbU WsQCobz22vCDF1H7yLW/Qd4MWk7MUT6oPnb6yrkZ7FjMEcBzm2RvD60uLVw9Fv/diD2vjZYd5zW WgGUrBeccgYJv7ClVLpT9a1m86x4Q498EhWznSEd7rmNHldYgAmt6RkMbFW04DDXnbZj2C4T8zG 9fBC6yroqE3AUHfBC5lpe2qMLttMvUFYMWwVYYBoA410LMrlDHu+VATBuOo6HOkeM/JxLp5dSiu WY8bfcf6nCaTeHWdAdshL/E/F/otZW9JyiPB25rEVLgsABMSc5Lx9GWm/qfUnVXcDYQHEYlPtSQ 90lBP7wozXnathx9C0pQqwXJqmZ0167puIKLBAeO/BhYTErIQCOZ5aAQVTnaaSMhFwIhowPzbtW 7yu8SB6MhDLhyZxUL/A== X-Proofpoint-GUID: F264nFVMSM47TBeBngpoPY9CRsE5vrRW X-Authority-Analysis: v=2.4 cv=M7TYuCws c=1 sm=1 tr=0 ts=6aa8a5fb cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=3uEAWm1Q5IaYrG0nJHIA:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfXzm6aVuPdO+7N LeAq4r+/OP7nht5hGVfupiRng4QWr2KqWyIiJxBoeGLL6zoXvQJTgv3i29GvpX8FFxad7Hyc51s H6lkGf5RiOGizRf9qbQ9KN0ZMKdoWHc= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-14_05,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 suspectscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150024 Content-Type: text/plain; charset="utf-8" The IQ10 Robotics Reference Design carries a Hamilton (WCN7850) module on a board-to-board connector hanging off PCIe2, using two lanes. Unlike the Ride Embedded board, the RRD generates the module supplies itself rather than relying on the module DBUs: three discrete buck converters produce VDD_CORE_VL, VDD_CORE_VM and VDD_CORE_VH (0.95 V, 1.35 V and 1.95 V), all gated by WLAN0_CORE_PWR_EN on pmau0102_e GPIO6, while the 3.3 V and 1.8 V I/O rails are strapped to the always-on peripheral rails. WLAN0_EN on pmau0102_e GPIO10 releases the module itself. Describe those rails, the WCN7850 PMU that derives the chip supplies from them, and the PCIe endpoint node consuming the PMU outputs. Assisted-by: LLM Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-rrd.dts | 109 ++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qc= om/nord-rrd.dts index 4c4d54d7aa90..c8a6df21fa87 100644 --- a/arch/arm64/boot/dts/qcom/nord-rrd.dts +++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts @@ -53,6 +53,100 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-div =3D <2>; }; }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_wcn_3p3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + vreg_wcn_vddio_1p8: regulator-wcn-vddio-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_wcn_vddio_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + vreg_wcn_core_vl_0p95: regulator-wcn-core-vl-0p95 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_wcn_core_vl_0p95"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <950000>; + gpio =3D <&pmau0102_e_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_wcn_core_vm_1p35: regulator-wcn-core-vm-1p35 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_wcn_core_vm_1p35"; + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1350000>; + gpio =3D <&pmau0102_e_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_wcn_core_vh_1p95: regulator-wcn-core-vh-1p95 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_wcn_core_vh_1p95"; + regulator-min-microvolt =3D <1950000>; + regulator-max-microvolt =3D <1950000>; + gpio =3D <&pmau0102_e_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + wlan-enable-gpios =3D <&pmau0102_e_gpios 10 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <&vreg_wcn_3p3>; + vddio-supply =3D <&vreg_wcn_vddio_1p8>; + vddaon-supply =3D <&vreg_wcn_core_vl_0p95>; + vdddig-supply =3D <&vreg_wcn_core_vl_0p95>; + vddrfa1p2-supply =3D <&vreg_wcn_core_vm_1p35>; + vddrfa1p8-supply =3D <&vreg_wcn_core_vh_1p95>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; }; =20 &apps_rsc { @@ -415,6 +509,21 @@ &pcie2 { &pcie2_port0 { reset-gpios =3D <&tlmm 8 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 6 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible =3D "pci17cb,1107"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; }; =20 &pcie3 { --=20 2.43.0