From nobody Fri Sep 25 08:47:12 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB11243B3C9 for ; Tue, 15 Sep 2026 06:54:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789455275; cv=none; b=OULnXGefrHS7MtU0foX6STv2kVu/0Ozd6mY4V0CVRtNxWxEMpJUZdbKm8utY+bWKhBfyxh3BISenhKhWmOetQnkR2M84aOVMPS0D5xgjJmcZtrWLa1IfdlsFtp3fUALvMkB8lUmfTi+y1YXfpAfrFRKYx47xRogM6eQFO3q3QC0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789455275; c=relaxed/simple; bh=TcAXQjm3y4bxY72fFI+XTJk2M6ZXHTIsdSnWHX2Ufxk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Wm4GA+yvr23UIBhjERPTL1npHaEnS5Btbhq7Rni2GKjG86mwG7f0VWnFUqaHusuZFwQ2XY3hAX6NoW5/TWXa03yaCzkEJ1WBv18ZF+7OE39tV0BpbE3wyCiK5kiWvgjQuh59ekbohwX6+FTwUE4zRijGQyifp86yyHVvN7Vi1II= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ULeruQoD; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=O71xCPM6; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ULeruQoD"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="O71xCPM6" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68F6Ze3Y3126427 for ; Tue, 15 Sep 2026 06:54:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= VgKDv1xcq0t3CD7zLa+LminS2DbKGmggIsaKAN93+/4=; b=ULeruQoD9wY29BiO WD6/vhW3GyLokxnJHP61EYljQs7Bsh7PXF3KlRCYZJklkUAe5V337F/w0EGNqHZk jux3cM6UI1/BaYKLa28PQzEezEj3I94pd+se1XocZlsNIuDrlwlZc/RDhkc2VZ5F sdCRtPRNhttKoGUx1667Z6rG0MMC3ppzbatFTbroeNJHX0gn4AFV4QL+brugUoI/ 8jIi7OzQnl/d2E8z3xKXhwin1V34vnD1yKkheWe2b9yBl92/yBZMwx3YDYbe/iZf GW9uKjvvzRrvJPK0jOoq1Y38WQuTHV76pR+fevR/Ffkutl/3fHa+vImXxJZSu5Yy nUOGGg== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gpmx9tx6r-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 15 Sep 2026 06:54:32 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-cc42a07d04aso3492476a12.1 for ; Mon, 14 Sep 2026 23:54:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1789455267; x=1790060067; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=VgKDv1xcq0t3CD7zLa+LminS2DbKGmggIsaKAN93+/4=; b=O71xCPM605u9AlOfvbI2HOkH6vOjOZ3ZqA3oJ8HWCobuCRJWJWUzdIjpC05nTQ5FTy Ue/Cs3fAWdQBT7ux2h8GXNHe6pqOV/MlVxqKqORkV1XhIEbSXHD75BnquDjnXSRbmiud MrmqNPJHWP4jMuWxfR4yDGmf7UdSup2jMDVHgdxviQe7Gt3856fCmzEXE6/u2KlTsbnS SO4UdncAr3RpcFcIhgwKy4jn/zmqj70BFt9yfiX8/3q+uV0Jdk2u/ol2XoKQgSbJy1rk 0iTRhQv5Ee/TH9xDrXymHHnaxdW1WMz/o+7UUlAAbp2wMfhKBOJfxvBdSqY3/245Ef8h J3gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1789455267; x=1790060067; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=VgKDv1xcq0t3CD7zLa+LminS2DbKGmggIsaKAN93+/4=; b=Ob84C3DZqwvXYJ9xUJPVCd/8kaWbQAu4adUDcn1591UIUCo++yhamapBrNSL7ZK6gu GZymx8DDcG1tJgJ3oDB6H1OvXi8y7GStdYITICnnl6OuHXnTyD9/KL1t86kkBBt7uHS5 PmrkqfJiwCcw0jj8WeKJlopfIgLY2m0HlkTOMaYN9uzBOC9wjNJtHlsV3LhbLgmk5pBx 1iNP8RArMgzkb+VnpJplCpHXiHDZWlg4tcm1MfIzli99b93j83dbSh171NMdDdyCxhPl oD+h4rJ9HxLNYde7QUsldpxp1vIqVhRKMeVlYjHlK0gD/7ltg80zMGqwLIFjeKqfxHxM aARQ== X-Forwarded-Encrypted: i=1; AKwUvBxW9hXkDocz2PLXlncE8w6NEeA5xTpa4qkMrkPrhFCrdbVnkejY78mcY1KMHxjLUIpWHG8gFmEgS9s0G4Q=@vger.kernel.org X-Gm-Message-State: AFuF++mRptnjYOqzYflvcgHxR4QYJKb7MeGqYz8P4LMGZ92f92nGv4A5 K80l0wa64pGJt1fGLmq0eiPQmhUi7AvI8ycov4w5Cnr32cRpAT8nKhF1e3aW7QHjkt367IBJbF2 biLkHpg5W+iEbanzn1WiefZ4IEf5JxLUmqMZgKGpULhC7h3LfOymfGlGZ8xjorHwvvFM= X-Gm-Gg: AYBFou39QVGfqQilp0RTLua3KFdfNVva8bCW6hQ0IiPuOzriOn6z5+9AZMfoSmTnG/O +pCHj0njqwrEcmxtaxc8Wwc1QHKP0K5TNib2kqw+de04WhIT77YusyKxFStZjDYCVzF3y/KkxKd jyX2q6t96LidIfnZ7pgWtt+bquM8e4uk0bh/93r75335px2IoDzJO/DVrU/lG/W5permhgYjdxO Rxb27nvegPNxjsX368pn5ZluAh5ZtYd29pJw+GYIKKPgVm/xmBAbREs8x0OlAYRrfT1vp3FuStE IQCKykBkcCjRbTgD89plR6SSRuDVAvt1V57US9yb/YRjs3dMsWDfjJuVjHcR9E3IyFMFLjSYWz+ ly4kz4O4HZvHuMbH+aTTqO0/zv59zV6Hl X-Received: by 2002:a17:90b:3bc5:b0:39d:f259:3363 with SMTP id 98e67ed59e1d1-39df25936c1mr10712050a91.12.1789455266947; Mon, 14 Sep 2026 23:54:26 -0700 (PDT) X-Received: by 2002:a17:90b:3bc5:b0:39d:f259:3363 with SMTP id 98e67ed59e1d1-39df25936c1mr10711949a91.12.1789455266021; Mon, 14 Sep 2026 23:54:26 -0700 (PDT) Received: from WENMLIU-LAB01.ap.qualcomm.com ([114.94.8.21]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39dfda39eb4sm3249725a91.8.2026.09.14.23.54.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 23:54:25 -0700 (PDT) From: Wenmeng Liu Date: Tue, 15 Sep 2026 14:54:12 +0800 Subject: [PATCH v7 1/3] dt-bindings: media: i2c: og0ve1b: Add OmniVision OG0VA1B camera sensor Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-og0va1b-v7-1-3a4b6d7360ec@oss.qualcomm.com> References: <20260915-og0va1b-v7-0-3a4b6d7360ec@oss.qualcomm.com> In-Reply-To: <20260915-og0va1b-v7-0-3a4b6d7360ec@oss.qualcomm.com> To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sakari Ailus , Vladimir Zapolskiy Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wenmeng Liu , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789455258; l=2177; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=TcAXQjm3y4bxY72fFI+XTJk2M6ZXHTIsdSnWHX2Ufxk=; b=Gj8CFjJjQ++eeq8C5oAIN/m8Xam3tLFgV29USjOmkdC84ujQ2hXs7aR/MuWjO+zQaL6acipuS w7u+2MsaIHvBpCKgnWUsrq9NBjLYmxFCEQVLrdvS7j0j1N2/zqZ1kJQ X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Authority-Analysis: v=2.4 cv=G+KJgNk5 c=1 sm=1 tr=0 ts=6aa8eba8 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=gEfo2CItAAAA:8 a=XYAwZIGsAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=M65GHGH_L51Dv4RaLaoA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 a=sptkURWiP4Gy88Gu7hUp:22 a=E8ToXWR_bxluHZ7gmE-Z:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDA5NyBTYWx0ZWRfX5/4u1tLwHE9g FePYRnJl/SB+2s2iXv65cc203MRONzprxNfhdq4W/V0FgpLnXTdkAlbLe54/fsIjZdNkLCPk1g1 aVnAGAmPBGfPLXcfxDLwBOmBMy7XI1m89K+ZhZkxIqcVE2pm8jLwh8lsshnSq36BSXxBc1ecmCF zBVQv8UHcX6DODJ6Z3zCTsfUJbTU9XAbVyEMSUIk++XhgIGd/emHqNj3Zuz/c09ATa1GP/od3mF xbZxfPfnmiWBqZ1dbnpnA3X43HKp+kc0BiQdn5/ZRrf0IGae5ZfIrkB58pPgqWgh8by42K++2M7 Pmu30MtyZfXzifr7rEKkaMV2QnPLR+o2sK7lTg4q2R8WcP+2N1IrKnxVGW0URk0BJeXc4Jqh0yJ SSoCq4zSX6B+BPxqbMs7ePU4ZqV2wAXmooIfbDjHN7t83g3+naqBLxRcZ5LWHcPVogUtK/n72Lf 4YhMr75topWTG8gwjvg== X-Proofpoint-GUID: or63nal9Iaz9NviDAx8m6wqf9EWf98io X-Proofpoint-ORIG-GUID: or63nal9Iaz9NviDAx8m6wqf9EWf98io X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDA5NyBTYWx0ZWRfXzKGR+VuUOZY9 WmMnOWy2q8CsCWsBncTFIN7Rvangb6lzwr3LYPimmLktLzfdDsFUVFBF+kTpn20ZTQpOD5seWyw Vx4X4sNUzNR3u1q79HgLgVhok5DLaVs= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_02,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 impostorscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 adultscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150097 The OmniVision OG0VA1B is a monochrome image sensor closely related to the already supported OG0VE1B. It shares the same SCCB control interface, power supplies and MIPI D-PHY description, but differs in its chip ID, register programming and output format. Generalise the binding title and description to cover both sensors. Acked-by: Conor Dooley Reviewed-by: Vladimir Zapolskiy Signed-off-by: Wenmeng Liu --- .../devicetree/bindings/media/i2c/ovti,og0ve1b.yaml | 15 ++++++++---= ---- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml = b/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml index bd2f1ae23e6547032361924a6953000bab1129df..b6fa9645c7c6cb3fa907478684d= 02b01d916fea1 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml @@ -4,14 +4,13 @@ $id: http://devicetree.org/schemas/media/i2c/ovti,og0ve1b.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: OmniVision OG0VE1B Image Sensor +title: OmniVision OG0VA1B and OG0VE1B Image Sensors =20 description: - OmniVision OG0VE1B image sensor is a low power consuming monochrome - image sensor. The sensor is controlled over a serial camera control - bus protocol (SCCB), the widest supported image size is 640x480 at - 120 frames per second rate, data output format is 8/10-bit RAW - transferred over one-lane MIPI D-PHY at up to 800 Mbps. + OmniVision OG0VA1B and OG0VE1B are low power consuming monochrome image + sensors. The sensors are controlled over a serial camera control bus + protocol (SCCB), the widest supported image size is 640x480, data output + format is 8/10-bit RAW transferred over one-lane MIPI D-PHY. =20 maintainers: - Vladimir Zapolskiy @@ -21,7 +20,9 @@ allOf: =20 properties: compatible: - const: ovti,og0ve1b + enum: + - ovti,og0va1b + - ovti,og0ve1b =20 reg: maxItems: 1 --=20 2.34.1 From nobody Fri Sep 25 08:47:12 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 255F13CB569 for ; Tue, 15 Sep 2026 06:54:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789455276; cv=none; b=O779NVIFDmrNOxiO3NcbEniHhj1zee4ifPM+Efdbn7OHovRlruMDEf869XA8aQEFGu08NIbGJYZttFbMqE/TsEQhFGAh4wRIZRajE/7acLyIhwiD0Rjh21T2o8DLpuz9FxtkIwjrGlc6SuZA2Wawd9Ryfsx7FmrRrd4RMrS+PoA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789455276; c=relaxed/simple; bh=mP3bvWznXxIIzJowlzW6vQNAZA58uoi4wI4gneF7fkU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pA8AvwSygjciHAtP1fQp2I/IF/AILVJfUCM5/cuOXWO3lJaswgIh3D3nfGxE5ZpwPyTsfk1VZtwCkWWYlEhjajtsdQ4DIEc/krJpkzJ3pGV5oRcFllBVAXp5KTM3cTE1BXILFmS9NoFXcuqK0VwECZ/BKaJLWb8ejkG9Q/Sebv0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=hIwqDK5D; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=claDr+zW; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="hIwqDK5D"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="claDr+zW" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68F6ZFbO3487022 for ; Tue, 15 Sep 2026 06:54:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= lVpUj42rxzk6HnjxEmo+9uxYZw6TMzwtLr+g/Cafst0=; b=hIwqDK5D28l0hmHL mI9nyrwHLdvrKWvdYt/AVwWwNjSuOlZp40Mu+7hyP0Wl9rLwnJh4Q+hcAFyq0rxu 1UA1kQbNJjp4xnZ1Oqu913QitCWabmN/HzSrQWzAxFlkrU8kZcqaXiFLd+MFh0TU /wbAiWUIbGcNt9HLdsLQFQAkmyMgZEGfCmLE1IOWqqJln1S0nw09q4N0VoWlwlg7 3XgbIgL4gPH0+Nioae1HEcHgPvZ48RGk9LHYwnW5swoWxuNekCXFI0m+dzReGjaD IexrujzREzH4ui8bNCrLwzMDa8mUmKsNCe9GehnnqwKv9uJ4Y7Py66hLEYvB4lAS r/zuyw== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gq0jer52b-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 15 Sep 2026 06:54:31 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-39e087a18deso417233a91.0 for ; Mon, 14 Sep 2026 23:54:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1789455271; x=1790060071; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=lVpUj42rxzk6HnjxEmo+9uxYZw6TMzwtLr+g/Cafst0=; b=claDr+zWqBFQPRxYOPKKc6wsXrrhryMLFdF4+xKMWASdppMnbrrUxbInnUMWKuoopL 3L4kPQ2KDJ2GnYKxKnD5vj7xwoFKCIv0pJUwyXst/3mbactr2kaqIJ4cVPUQ+X0WGx7O oSTKCYqYpb8FbbR57fdySDB2SNeICykbt3rEuRRSJ4wBlGHcPtTVgDgEo0iVLc4ybdmj mrGQRnRWbtC78uhM0IpuXVA62hhb85Mbn34BxYJDOTBQ/zmLAuoJP5BwWymELvEss1vP 18R29Mxjn4rq/lhS6T1ShiO8c3rNR72RHRd6MWy4P1GwVUn3deOGmVFcN0eDKoZpI2Nt P4Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1789455271; x=1790060071; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=lVpUj42rxzk6HnjxEmo+9uxYZw6TMzwtLr+g/Cafst0=; b=WL3deRbDHCrN1pIOQlQxoWd0LQ1uCWcu8FFWvrTqGdQ9rKmLMuPXvbf1DsxlsThXDQ s0mJVYHHX0fw2Uk1aB3Nrp6giBunEi++Ce2D1CAib0FmBIlct+G7HG0nSzojM4Y4xlpn LKbIp6Tbr7gyaLd1gKYpDMM7ZHSLGZR79nIVXLjalg210bYCnSRwOD/WgpVTMmoUYWHB FADW5y9ISYhyxnaBny5U2cIDiaZvGl6WUvgUQn7UCuaPorK7yBCySnBBYfSR/a9EtI37 JvO0FAleX1oeolBfWu7eZaQ+c4ZhBddItHPlIY4cZZ9J9S2pfXidf1Nwic+P7vQtgBUz E5aQ== X-Forwarded-Encrypted: i=1; AKwUvBy2E6CyQKGKBVyZy39P42I/pwyzM0BxlHsJ3Icvj/RyXvJzLqhqzE/APivZ6NiR+RKEJioS9Td4QPD0vE4=@vger.kernel.org X-Gm-Message-State: AFuF++mKInhMq1eo4f2AVuvGAqSCvLrsiuYT2GYm+fABnHJfJYNlmTTJ dNO/ynk3s2hA19MstY2tTNhCiKnmPjF7f8J/IH09yThdAE8B461a5iBVLA2B+UcyUogALE5wtQP 6kMl9OPkfGb6lTFeMz/8guMM9d8wVLJDSOjZeLW/6RcSCIJFbLDYFdd/8GvKqjrDEvdM= X-Gm-Gg: AYBFou0h5W1Vz30bpYfEXInQZaEDOB1dt3iEWizvkdTI7ijlAtmaVSZDgp4yRNTTKak 74/IRf5nbIZhgOTl5qRbXE7slOxUW2Hbr60k+30EnnoBrSeZcbeL1to6BsXgIG2bLOVhZ8xutgV I2+yKCmSUpjd5SYzLdqMoRDZRNd7COl4DA54ojNf2C1P5h642mU9oHU2XTT7yhITkHu0TMHAg5x SjfpkdkTTNpuAJiBf7fvSozaJkplhKokbmxJ0isJYL/7kVyzjh5FugR3H5bkRVg0AJFzMlZLMaZ zawfcxV6tpG9zvIWNDjSXzPeVqGggeWEFLE69xK/7d2lZ9FffrGOrHje+QwS9+nxNEs+oe020GR 0/PLbS11zLfxS+MpQLZPC9sfD70yw8QD3 X-Received: by 2002:a17:90b:4f45:b0:381:1c96:829b with SMTP id 98e67ed59e1d1-39debf6f167mr11325608a91.3.1789455270507; Mon, 14 Sep 2026 23:54:30 -0700 (PDT) X-Received: by 2002:a17:90b:4f45:b0:381:1c96:829b with SMTP id 98e67ed59e1d1-39debf6f167mr11325533a91.3.1789455269485; Mon, 14 Sep 2026 23:54:29 -0700 (PDT) Received: from WENMLIU-LAB01.ap.qualcomm.com ([114.94.8.21]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39dfda39eb4sm3249725a91.8.2026.09.14.23.54.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 23:54:29 -0700 (PDT) From: Wenmeng Liu Date: Tue, 15 Sep 2026 14:54:13 +0800 Subject: [PATCH v7 2/3] media: i2c: og0ve1b: Introduce per-sensor data structure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-og0va1b-v7-2-3a4b6d7360ec@oss.qualcomm.com> References: <20260915-og0va1b-v7-0-3a4b6d7360ec@oss.qualcomm.com> In-Reply-To: <20260915-og0va1b-v7-0-3a4b6d7360ec@oss.qualcomm.com> To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sakari Ailus , Vladimir Zapolskiy Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789455258; l=10306; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=mP3bvWznXxIIzJowlzW6vQNAZA58uoi4wI4gneF7fkU=; b=a6bJ44M/WIph5Z4npnYSmtc02Fks+Mc7zhNhdOQ79+WgGLLN9Z0Mv8wlnnuDQk72lKylcvw/s 315EWsRuFkkCJc8aqEUPHCDimNpY7ttT08fWz3YLVzdQrZGN5XOAz5p X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDA5NyBTYWx0ZWRfX/x/brO3VZ3K1 05vC5R2Ex5p9VqaKBTkcaSKssqeBmHvmVLT7fgDGjyXHGGVwPrxTx3zHQR79rJ6aHCT/UyzguBS p2yy9z6IjMF17/qJSKDq9fEXeN+VOXs= X-Authority-Analysis: v=2.4 cv=Kr/YSmWN c=1 sm=1 tr=0 ts=6aa8eba7 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=aIh3vjFOF9panSEBuokA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: jL-rbQ20M2i15qGjqd9kZU5qXSCj44BG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDA5NyBTYWx0ZWRfX3DBCJdFN1Z4F 2NSmIsV61DjZHagHdby9vSH9Yc+uGj2FfO9rODdDGF4kcPm8SknR/vbS7R94suZ6RVJbTf03VoD K1lLa6VByQLIGt5f8LPK6zzhaa8WPv0YzOiQbBHKr7j2kc3dSMJxeQywqiTQ4mZwNtAQQX64tbq icYjgHoVpcDnEk5OWFNDNIvTkyJ1rGSoEZ59sYrg4Cmc9v1UTYDVeW3WJi+/vMlIrXJFRhbTkja 8pRGPUFH472mN5kvZK5DPH+GTTEjfRGy2v1dSAj+HK2n0TYaZOqvj+AQYIzf5tJgNoiE8bQrYEd dERmk5PtbD9G6FkoFu0VgNAGWyqJ+rpSf19ushxkeQI0fDzVKifGgqNAJj6H5UxWJo33fiGFVjL lU3KpCojxDUdlAevKa+j12BaXC2lesqYsnTDUm6HFNc3zcG9yWYLoF2YjJcPpyRpUw0C4ebHVm9 poXXmvlWwBevTpez0lw== X-Proofpoint-ORIG-GUID: jL-rbQ20M2i15qGjqd9kZU5qXSCj44BG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_02,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150097 Refactor the driver to separate sensor-specific data from the common driver code. Introduce a sensor_data structure, populated through i2c_get_match_data(), to hold the chip ID, MCLK frequency, link frequencies and supported modes. Test pattern programming is described by a per-sensor callback, and each mode stores its media bus format code (rather than a bits-per-pixel value) so that sensors with a different output format can be supported. Reviewed-by: Vladimir Zapolskiy Tested-by: Vladimir Zapolskiy Signed-off-by: Wenmeng Liu --- drivers/media/i2c/og0ve1b.c | 100 +++++++++++++++++++++++++++++++---------= ---- 1 file changed, 72 insertions(+), 28 deletions(-) diff --git a/drivers/media/i2c/og0ve1b.c b/drivers/media/i2c/og0ve1b.c index 84a28cdcade10f8fbcf945999e88f84641b9bc0d..7ab57a3d8d6d0ffabd286cc12fc= bcb17dd56d72f 100644 --- a/drivers/media/i2c/og0ve1b.c +++ b/drivers/media/i2c/og0ve1b.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -65,11 +66,23 @@ struct og0ve1b_mode { u32 height; /* Frame height in pixels */ u32 hts; /* Horizontal timing size */ u32 vts; /* Default vertical timing size */ - u32 bpp; /* Bits per pixel */ + u32 code; /* MEDIA_BUS_FMT code */ =20 const struct og0ve1b_reg_list reg_list; /* Sensor register setting */ }; =20 +struct og0ve1b; + +struct og0ve1b_sensor_data { + u64 chip_id; + unsigned long mclk_freq; + int (*enable_test_pattern)(struct og0ve1b *og0ve1b, u32 pattern); + const s64 *link_freq_menu; + const struct og0ve1b_mode *modes; + int num_link_freqs; + int num_modes; +}; + static const char * const og0ve1b_test_pattern_menu[] =3D { "Disabled", "Vertical Colour Bars", @@ -99,6 +112,8 @@ struct og0ve1b { =20 /* Saved register value */ u64 pre_isp; + + const struct og0ve1b_sensor_data *data; }; =20 static const struct cci_reg_sequence og0ve1b_640x480_120fps_mode[] =3D { @@ -247,13 +262,13 @@ static const struct cci_reg_sequence og0ve1b_640x480_= 120fps_mode[] =3D { { CCI_REG8(0x3f47), 0x35 }, }; =20 -static const struct og0ve1b_mode supported_modes[] =3D { +static const struct og0ve1b_mode og0ve1b_supported_modes[] =3D { { .width =3D 640, .height =3D 480, .hts =3D 792, .vts =3D 568, - .bpp =3D 8, + .code =3D MEDIA_BUS_FMT_Y8_1X8, .reg_list =3D { .regs =3D og0ve1b_640x480_120fps_mode, .num_regs =3D ARRAY_SIZE(og0ve1b_640x480_120fps_mode), @@ -273,11 +288,21 @@ static int og0ve1b_enable_test_pattern(struct og0ve1b= *og0ve1b, u32 pattern) return cci_write(og0ve1b->regmap, OG0VE1B_REG_PRE_ISP, val, NULL); } =20 +static const struct og0ve1b_sensor_data og0ve1b_data =3D { + .chip_id =3D OG0VE1B_CHIP_ID, + .mclk_freq =3D OG0VE1B_MCLK_FREQ_24MHZ, + .enable_test_pattern =3D og0ve1b_enable_test_pattern, + .link_freq_menu =3D og0ve1b_link_freq_menu, + .num_link_freqs =3D ARRAY_SIZE(og0ve1b_link_freq_menu), + .modes =3D og0ve1b_supported_modes, + .num_modes =3D ARRAY_SIZE(og0ve1b_supported_modes), +}; + static int og0ve1b_set_ctrl(struct v4l2_ctrl *ctrl) { struct og0ve1b *og0ve1b =3D container_of(ctrl->handler, struct og0ve1b, ctrl_handler); - const struct og0ve1b_mode *mode =3D &supported_modes[0]; + const struct og0ve1b_mode *mode =3D &og0ve1b->data->modes[0]; s64 exposure_max; int ret; =20 @@ -314,7 +339,7 @@ static int og0ve1b_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + mode->height, NULL); break; case V4L2_CID_TEST_PATTERN: - ret =3D og0ve1b_enable_test_pattern(og0ve1b, ctrl->val); + ret =3D og0ve1b->data->enable_test_pattern(og0ve1b, ctrl->val); break; default: ret =3D -EINVAL; @@ -330,10 +355,19 @@ static const struct v4l2_ctrl_ops og0ve1b_ctrl_ops = =3D { .s_ctrl =3D og0ve1b_set_ctrl, }; =20 +static s64 og0ve1b_pixel_rate(const struct og0ve1b_sensor_data *data) +{ + const struct og0ve1b_mode *mode =3D &data->modes[0]; + unsigned int bpp =3D mode->code =3D=3D MEDIA_BUS_FMT_Y8_1X8 ? 8 : 10; + + return div_u64(data->link_freq_menu[0], bpp); +} + static int og0ve1b_init_controls(struct og0ve1b *og0ve1b) { struct v4l2_ctrl_handler *ctrl_hdlr =3D &og0ve1b->ctrl_handler; - const struct og0ve1b_mode *mode =3D &supported_modes[0]; + const struct og0ve1b_mode *mode =3D &og0ve1b->data->modes[0]; + const struct og0ve1b_sensor_data *data =3D og0ve1b->data; s64 exposure_max, pixel_rate, h_blank, v_blank; struct v4l2_fwnode_device_properties props; struct v4l2_ctrl *ctrl; @@ -343,12 +377,12 @@ static int og0ve1b_init_controls(struct og0ve1b *og0v= e1b) =20 ctrl =3D v4l2_ctrl_new_int_menu(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_LINK_FREQ, - ARRAY_SIZE(og0ve1b_link_freq_menu) - 1, - 0, og0ve1b_link_freq_menu); + data->num_link_freqs - 1, + 0, data->link_freq_menu); if (ctrl) ctrl->flags |=3D V4L2_CTRL_FLAG_READ_ONLY; =20 - pixel_rate =3D og0ve1b_link_freq_menu[0] / mode->bpp; + pixel_rate =3D og0ve1b_pixel_rate(data); v4l2_ctrl_new_std(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1, pixel_rate); =20 @@ -407,7 +441,7 @@ static int og0ve1b_init_controls(struct og0ve1b *og0ve1= b) static void og0ve1b_update_pad_format(const struct og0ve1b_mode *mode, struct v4l2_mbus_framefmt *fmt) { - fmt->code =3D MEDIA_BUS_FMT_Y8_1X8; + fmt->code =3D mode->code; fmt->width =3D mode->width; fmt->height =3D mode->height; fmt->field =3D V4L2_FIELD_NONE; @@ -421,8 +455,8 @@ static int og0ve1b_enable_streams(struct v4l2_subdev *s= d, struct v4l2_subdev_state *state, u32 pad, u64 streams_mask) { - const struct og0ve1b_reg_list *reg_list =3D &supported_modes[0].reg_list; struct og0ve1b *og0ve1b =3D to_og0ve1b(sd); + const struct og0ve1b_reg_list *reg_list =3D &og0ve1b->data->modes[0].reg_= list; int ret; =20 ret =3D pm_runtime_resume_and_get(og0ve1b->dev); @@ -484,13 +518,14 @@ static int og0ve1b_set_pad_format(struct v4l2_subdev = *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_format *fmt) { + struct og0ve1b *og0ve1b =3D to_og0ve1b(sd); struct v4l2_mbus_framefmt *format; const struct og0ve1b_mode *mode; =20 format =3D v4l2_subdev_state_get_format(state, 0); =20 - mode =3D v4l2_find_nearest_size(supported_modes, - ARRAY_SIZE(supported_modes), + mode =3D v4l2_find_nearest_size(og0ve1b->data->modes, + og0ve1b->data->num_modes, width, height, fmt->format.width, fmt->format.height); @@ -505,10 +540,12 @@ static int og0ve1b_enum_mbus_code(struct v4l2_subdev = *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { + struct og0ve1b *og0ve1b =3D to_og0ve1b(sd); + if (code->index > 0) return -EINVAL; =20 - code->code =3D MEDIA_BUS_FMT_Y8_1X8; + code->code =3D og0ve1b->data->modes[0].code; =20 return 0; } @@ -517,15 +554,18 @@ static int og0ve1b_enum_frame_size(struct v4l2_subdev= *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse) { - if (fse->index >=3D ARRAY_SIZE(supported_modes)) + struct og0ve1b *og0ve1b =3D to_og0ve1b(sd); + const struct og0ve1b_sensor_data *data =3D og0ve1b->data; + + if (fse->index >=3D data->num_modes) return -EINVAL; =20 - if (fse->code !=3D MEDIA_BUS_FMT_Y8_1X8) + if (fse->code !=3D data->modes[fse->index].code) return -EINVAL; =20 - fse->min_width =3D supported_modes[fse->index].width; + fse->min_width =3D data->modes[fse->index].width; fse->max_width =3D fse->min_width; - fse->min_height =3D supported_modes[fse->index].height; + fse->min_height =3D data->modes[fse->index].height; fse->max_height =3D fse->min_height; =20 return 0; @@ -534,13 +574,14 @@ static int og0ve1b_enum_frame_size(struct v4l2_subdev= *sd, static int og0ve1b_init_state(struct v4l2_subdev *sd, struct v4l2_subdev_state *state) { + const struct og0ve1b_mode *mode =3D &to_og0ve1b(sd)->data->modes[0]; struct v4l2_subdev_format fmt =3D { .which =3D V4L2_SUBDEV_FORMAT_TRY, .pad =3D 0, .format =3D { - .code =3D MEDIA_BUS_FMT_Y8_1X8, - .width =3D supported_modes[0].width, - .height =3D supported_modes[0].height, + .code =3D mode->code, + .width =3D mode->width, + .height =3D mode->height, }, }; =20 @@ -586,9 +627,9 @@ static int og0ve1b_identify_sensor(struct og0ve1b *og0v= e1b) return ret; } =20 - if (val !=3D OG0VE1B_CHIP_ID) { - dev_err(og0ve1b->dev, "chip id mismatch: %x!=3D%llx\n", - OG0VE1B_CHIP_ID, val); + if (val !=3D og0ve1b->data->chip_id) { + dev_err(og0ve1b->dev, "chip id mismatch: %llx!=3D%llx\n", + og0ve1b->data->chip_id, val); return -ENODEV; } =20 @@ -624,8 +665,8 @@ static int og0ve1b_check_hwcfg(struct og0ve1b *og0ve1b) ret =3D v4l2_link_freq_to_bitmap(og0ve1b->dev, bus_cfg.link_frequencies, bus_cfg.nr_of_link_frequencies, - og0ve1b_link_freq_menu, - ARRAY_SIZE(og0ve1b_link_freq_menu), + og0ve1b->data->link_freq_menu, + og0ve1b->data->num_link_freqs, &freq_bitmap); =20 v4l2_fwnode_endpoint_free(&bus_cfg); @@ -686,6 +727,9 @@ static int og0ve1b_probe(struct i2c_client *client) return -ENOMEM; =20 og0ve1b->dev =3D &client->dev; + og0ve1b->data =3D i2c_get_match_data(client); + if (!og0ve1b->data) + return -ENODEV; =20 v4l2_i2c_subdev_init(&og0ve1b->sd, client, &og0ve1b_subdev_ops); =20 @@ -700,7 +744,7 @@ static int og0ve1b_probe(struct i2c_client *client) "failed to get XVCLK clock\n"); =20 freq =3D clk_get_rate(og0ve1b->xvclk); - if (freq && freq !=3D OG0VE1B_MCLK_FREQ_24MHZ) + if (freq && freq !=3D og0ve1b->data->mclk_freq) return dev_err_probe(og0ve1b->dev, -EINVAL, "XVCLK clock frequency %lu is not supported\n", freq); @@ -819,7 +863,7 @@ static const struct dev_pm_ops og0ve1b_pm_ops =3D { }; =20 static const struct of_device_id og0ve1b_of_match[] =3D { - { .compatible =3D "ovti,og0ve1b" }, + { .compatible =3D "ovti,og0ve1b", .data =3D &og0ve1b_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, og0ve1b_of_match); --=20 2.34.1 From nobody Fri Sep 25 08:47:12 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 934B4446055 for ; Tue, 15 Sep 2026 06:54:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789455279; cv=none; b=icsgViqNvzYd4DLLd8oTUvunOWYpzrVxwPNlK1DD6q+z1d1aVGd9308yq3ijD6uoAfKiPyFmHNYK13p4CxfCXqYWTI90VPNl0uYUTIi9IXTc1t1qTbzB4NpsJKrMHytD/1fvof2XMBj3lwt+5+7Fm8AviBa8JjB7inbvn4QUlks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789455279; c=relaxed/simple; bh=KkOHNN5y6Bw0YBQ9UoQoIgXQ60+QehbpNVxdInDODMo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YkUVwFzWRnY+/K5FvbuJeWKkUeETqJ6Mf/qI9kqsL8Pcv0bYL3are9Dkb1czQrntHPwNi2nmiV77ZLkjfJJSD5S1o+2Cttsw6Sr3Z9yPzijNx2e8/a45YYyZQzCekYY6VEBaRNNVFKXszNO8N3/94j14armNInv7D6olcdFQ+Yc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=PKkgdnQ5; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=MgqWRyUe; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="PKkgdnQ5"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="MgqWRyUe" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68F6Z8hw2892415 for ; Tue, 15 Sep 2026 06:54:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wsYb9rI1fvsJJz9qkf1TUdlooBiRXnlJAMZYQr4RmFE=; b=PKkgdnQ5zhS/4T8L bf64LdE89G+cRWK7BrF7GwyFOGzvRV4Z1ojCkbcHvJ5A97lJ414uGyrLlTUzIGxL XvBTyv/wnTG756PA77W1SBliFHJFg5v04qBmAw17Nv/ySYaYpnrMUWTywGbngf9P nYsCypqYEiGHe33//gCmLPncLABjVHBmZmK2P/P2QB6J7l1fDHyUNBRT47jyVrmz o4sVVBRjfxK2zT6O4F6eVzKoibgcAkq+7MfC6NmjfwOF2HS2+/oUzcQfH2j1zzW6 E1mgjJht1mvI828STGTt4gBRy2q76a58Mr+DTMJu+itT6593klhIlQzR1Eg5oO/Z bXmIVw== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gpg2kv5b1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 15 Sep 2026 06:54:35 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-398dc3d8f0fso707722a91.0 for ; Mon, 14 Sep 2026 23:54:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1789455274; x=1790060074; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=wsYb9rI1fvsJJz9qkf1TUdlooBiRXnlJAMZYQr4RmFE=; b=MgqWRyUeBgcrysUiPWBK8CMRBPmZOLrfnatHY/BRiZJwLlI1aJKVr9jE/MyUlOauZk UFbVuqAl+2Mq6FxFPUiMRqYkxnIqEER50TW63dUK+zJ3mw+sPRdn9mRPa/lxeoAFmLJT w6S2sPo+7ftpCenwyYWUCnjDbqb2B/Qd1byVs1Hn6o+6tbdvG2myZ/CXMZHQHyTGhg1r 3QPRto9RW5VJTquqERqlyhOUVL6TfUU3h2ORqrd8Joxeu7L1E+dNK+fhIlWc5iCxISHk SwShwKe5qaN7LR/irHQVpwKgijLZPsvFea4g29MuEXE77IwYieqyx9tvrMNJTuUD8s4m v+xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1789455274; x=1790060074; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=wsYb9rI1fvsJJz9qkf1TUdlooBiRXnlJAMZYQr4RmFE=; b=mFEeitbMFSxv/YpH5SNevXiV7n/rkNm5pr8BpgS1GTkWVz5xVVO+gZEzDUaFBkztNp W6gSOjrVkLe2CP9U5FIS9bfsPwVeRbNIG/TAkop8gdJRRJ+pg1jF4fIalZZcNwqrQ3Q9 YHF9V6FppbtSHhHqBeMxHPJAxakQNVEJyiGo/jgXaZTxCB2+zoaWm9ALyDlGwfKBuMhY XiODa48mad7QC9qtOjmLInb91vZvXDiF8ZAFdLuLCsOfgZnxyAg02LM9agzFkMKNmJE7 N7K1caXGHFfuiAfD85ZMdS3TUHmvTf8z92cYpcRT1jQVWgRyQGLySFFhCBBPUQPuyTKs hB9A== X-Forwarded-Encrypted: i=1; AKwUvBxSksDM1d8xxF2A/SkMpUPcwLC1SsxQ0auT7EALQKj7J/MYXGUHhcLo/duZZARh0vWqx4cPY1Bzoe5s5LU=@vger.kernel.org X-Gm-Message-State: AFuF++nQeCdJsRV2rmAc092WpDTjVni23dd2G3uLxo67nKTwU5jrP2C0 8z6N+ocenCSrLWPY2ngEB6juGFTcm/AVfSNuIjAuFUCgqdZUWdBvnf3w/7mTrsECokh5BLy0Pr7 NlEd/usSlgHAhIPbWrLbYUuapkbu6K6LsdjfakeMAkAvhJ6y1BAFscVJRBjdJfw+m+b8= X-Gm-Gg: AYBFou0Zcfl8DJdHrMxRsIipp7DF7pIgz/hElTAKTjxa7bm8FDiQnaF7b/BUlaaY/fm HrFIrvJSwHQJJUTsDkysnKF1V2YCN7hcHw1422Jv7qihmBACVOBMuBJGNYi6ckM2sBw8IjTa2mj tKs2JD1vUU9zZIoegFMAgbEjT7MBNzFYjOuooguL4i9t9lQxki9CjPAApDg8foB9Mf+zUY9IwdX Qzt8OptdjxBSOvfhlndQDTfoQ2H0DSLMScvLOHhoHCUxlgdtThcYjU0K9x+Yh4H/sLcnpBucuU6 RxQgoLIaH5qvPDP5i1BYRNHxMF4JhGC4soClKdjeQ2nabSV9a9sdR7Ou/JS7VR/1KvG0H+YuQ5L 0uUsxGza9u22AiMBEpwaj486KQa1fpknF X-Received: by 2002:a17:90b:33c8:b0:398:c6e1:dceb with SMTP id 98e67ed59e1d1-39dfe036433mr3823736a91.9.1789455274095; Mon, 14 Sep 2026 23:54:34 -0700 (PDT) X-Received: by 2002:a17:90b:33c8:b0:398:c6e1:dceb with SMTP id 98e67ed59e1d1-39dfe036433mr3823696a91.9.1789455273427; Mon, 14 Sep 2026 23:54:33 -0700 (PDT) Received: from WENMLIU-LAB01.ap.qualcomm.com ([114.94.8.21]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39dfda39eb4sm3249725a91.8.2026.09.14.23.54.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 23:54:32 -0700 (PDT) From: Wenmeng Liu Date: Tue, 15 Sep 2026 14:54:14 +0800 Subject: [PATCH v7 3/3] media: i2c: og0ve1b: Add support for OmniVision OG0VA1B Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-og0va1b-v7-3-3a4b6d7360ec@oss.qualcomm.com> References: <20260915-og0va1b-v7-0-3a4b6d7360ec@oss.qualcomm.com> In-Reply-To: <20260915-og0va1b-v7-0-3a4b6d7360ec@oss.qualcomm.com> To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sakari Ailus , Vladimir Zapolskiy Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789455258; l=18743; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=KkOHNN5y6Bw0YBQ9UoQoIgXQ60+QehbpNVxdInDODMo=; b=eo8jM45xG+OWLpvc3A0YdOG2XCYE1p9RFjymvYx6vTeL7+8FmSMdcYp0qsE2UvVboHVUy3YqG 74lx2YLy/56A5jpvslObf/iI7gzUl4AMyey4huxxU0axnn0isPqnw3u X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-ORIG-GUID: pZnMymNrvugXZGy4bVanlhvo4XldilZM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDA5NyBTYWx0ZWRfX+m19K+Hx0Ohb 5H8y3+BCY5XrG0WEqC4OYiV4liW37OmwqnARiaV7WFjF8/2QjsOklFBodMyi9yNC3aMHYb4Wa4K aZFoY/jJGcfrothiFHOEhwls0nkWMyradtRD23WYjDd6L5oyooreMIj27wxIuq7lFK3uYXj6BFJ P74ifayPWjWNmSfjzHqpU2iaSrYPVWiqjQASLZVjynt9JuRdHI2yRcGHPI/TYFz2TE9aRFScF/J zB089zLXaBrtGo0R1+Aq0dqOLP9RXw2uRPA+k0XjHp/igRH8sKGR5cqJMVB8rbm4AkmnTW6a1xE HBodCwuWBLRwThGgD8ugtrxBqugjy50T2XGD+DIJaGDbsNnViCIKy3DHXlsmofjLSMFQ5oPrSY1 5LQFrqUg2/zK9RLmzHUWP8oLRfHT1D+HCYVsHRTnfJzXQAet9xBFRT3jOjgvVudbOb7TN7VRDEu jlAqlw1AzEY1TskZw8Q== X-Proofpoint-GUID: pZnMymNrvugXZGy4bVanlhvo4XldilZM X-Authority-Analysis: v=2.4 cv=M7TYuCws c=1 sm=1 tr=0 ts=6aa8ebab cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=pqkbOb-j7vkK_spRw2EA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDA5NyBTYWx0ZWRfX162pfVg4HlQf 0T2Hxsltr1GgdJoxbvgVkZleUQ/mZh1qD/Ul9t+jXBv11WkUH5R9nqet8+3ML9o6UhMEYPDRWup N3lrQma7IJsXNbQj7efVeage5RvX+3U= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_02,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 suspectscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150097 The OmniVision OG0VA1B is a monochrome image sensor closely related to the OG0VE1B. It shares the SCCB control interface, power supplies and the single-lane MIPI D-PHY description, and differs in its chip id, the test pattern register, the register programming and the output format (10-bit RAW instead of 8-bit). Add an og0ve1b_sensor_data entry describing the OG0VA1B together with its 640x480 60fps register sequence. The control registers (mode select, software reset, exposure, analogue gain, vertical timing and the test pattern enable bit) are identical on both parts, so give them a common OG0V_ prefix. Registers that differ between the two sensors keep their part-specific prefix. Reviewed-by: Vladimir Zapolskiy Tested-by: Vladimir Zapolskiy # og0ve1b Signed-off-by: Wenmeng Liu --- drivers/media/i2c/og0ve1b.c | 354 +++++++++++++++++++++++++++++++++++++---= ---- 1 file changed, 304 insertions(+), 50 deletions(-) diff --git a/drivers/media/i2c/og0ve1b.c b/drivers/media/i2c/og0ve1b.c index 7ab57a3d8d6d0ffabd286cc12fcbcb17dd56d72f..45e50469ef42e5f651b3aafd463= 245936028fb84 100644 --- a/drivers/media/i2c/og0ve1b.c +++ b/drivers/media/i2c/og0ve1b.c @@ -15,43 +15,53 @@ #include #include =20 +#define OG0VA1B_LINK_FREQ_480MHZ (480 * HZ_PER_MHZ) +#define OG0VA1B_MCLK_FREQ_19_2MHZ (19200 * HZ_PER_KHZ) + #define OG0VE1B_LINK_FREQ_500MHZ (500 * HZ_PER_MHZ) #define OG0VE1B_MCLK_FREQ_24MHZ (24 * HZ_PER_MHZ) =20 -#define OG0VE1B_REG_CHIP_ID CCI_REG24(0x300a) +#define OG0V_REG_CHIP_ID CCI_REG24(0x300a) +#define OG0VA1B_CHIP_ID 0xc75641 #define OG0VE1B_CHIP_ID 0xc75645 =20 -#define OG0VE1B_REG_MODE_SELECT CCI_REG8(0x0100) -#define OG0VE1B_MODE_STANDBY 0x00 -#define OG0VE1B_MODE_STREAMING BIT(0) +#define OG0V_REG_MODE_SELECT CCI_REG8(0x0100) +#define OG0V_MODE_STANDBY 0x00 +#define OG0V_MODE_STREAMING BIT(0) =20 -#define OG0VE1B_REG_SOFTWARE_RST CCI_REG8(0x0103) -#define OG0VE1B_SOFTWARE_RST BIT(0) +#define OG0V_REG_SOFTWARE_RST CCI_REG8(0x0103) +#define OG0V_SOFTWARE_RST BIT(0) =20 /* Exposure controls from sensor */ -#define OG0VE1B_REG_EXPOSURE CCI_REG24(0x3500) -#define OG0VE1B_EXPOSURE_MIN 1 -#define OG0VE1B_EXPOSURE_MAX_MARGIN 14 -#define OG0VE1B_EXPOSURE_STEP 1 -#define OG0VE1B_EXPOSURE_DEFAULT 554 +#define OG0V_REG_EXPOSURE CCI_REG24(0x3500) +#define OG0V_EXPOSURE_MIN 1 +#define OG0V_EXPOSURE_MAX_MARGIN 14 +#define OG0V_EXPOSURE_STEP 1 +#define OG0V_EXPOSURE_DEFAULT 554 =20 /* Analogue gain controls from sensor */ -#define OG0VE1B_REG_ANALOGUE_GAIN CCI_REG16(0x350a) -#define OG0VE1B_ANALOGUE_GAIN_MIN 1 -#define OG0VE1B_ANALOGUE_GAIN_MAX 0x1ff -#define OG0VE1B_ANALOGUE_GAIN_STEP 1 -#define OG0VE1B_ANALOGUE_GAIN_DEFAULT 16 +#define OG0V_REG_ANALOGUE_GAIN CCI_REG16(0x350a) +#define OG0V_ANALOGUE_GAIN_MIN 1 +#define OG0V_ANALOGUE_GAIN_MAX 0x1ff +#define OG0V_ANALOGUE_GAIN_STEP 1 +#define OG0V_ANALOGUE_GAIN_DEFAULT 16 =20 /* Vertical timing size */ -#define OG0VE1B_REG_VTS CCI_REG16(0x380e) -#define OG0VE1B_VTS_MAX 0xffff +#define OG0V_REG_VTS CCI_REG16(0x380e) +#define OG0V_VTS_MAX 0xffff =20 -/* Test pattern */ +/* Test pattern - OG0VA1B uses 0x5100, OG0VE1B uses 0x5e00 */ +#define OG0VA1B_REG_TEST_PATTERN CCI_REG8(0x5100) +#define OG0VA1B_TEST_PATTERN_BAR_SHIFT 2 #define OG0VE1B_REG_PRE_ISP CCI_REG8(0x5e00) -#define OG0VE1B_TEST_PATTERN_ENABLE BIT(7) +#define OG0V_TEST_PATTERN_ENABLE BIT(7) =20 #define to_og0ve1b(_sd) container_of(_sd, struct og0ve1b, sd) =20 +static const s64 og0va1b_link_freq_menu[] =3D { + OG0VA1B_LINK_FREQ_480MHZ, +}; + static const s64 og0ve1b_link_freq_menu[] =3D { OG0VE1B_LINK_FREQ_500MHZ, }; @@ -74,13 +84,29 @@ struct og0ve1b_mode { struct og0ve1b; =20 struct og0ve1b_sensor_data { + const char *name; u64 chip_id; unsigned long mclk_freq; int (*enable_test_pattern)(struct og0ve1b *og0ve1b, u32 pattern); + const char * const *test_pattern_menu; const s64 *link_freq_menu; const struct og0ve1b_mode *modes; + int num_test_patterns; int num_link_freqs; int num_modes; + /* Exposure register unit: OG0VE1B 1/16 line (4), OG0VA1B whole lines (0)= . */ + unsigned int exposure_shift; + /* Pixel rate multiplier: OG0VA1B uses CSI-2 DDR (2), OG0VE1B keeps 1. */ + unsigned int pixel_rate_mul; + bool cache_test_pattern_reg; +}; + +static const char * const og0va1b_test_pattern_menu[] =3D { + "Disabled", + "Vertical Color Bar", + "Top-Bottom Darker Color Bar", + "Right-Left Darker Color Bar", + "Bottom-Top Darker Color Bar", }; =20 static const char * const og0ve1b_test_pattern_menu[] =3D { @@ -116,6 +142,196 @@ struct og0ve1b { const struct og0ve1b_sensor_data *data; }; =20 +static const struct cci_reg_sequence og0va1b_640x480_60fps_mode[] =3D { + { CCI_REG8(0x0302), 0x31 }, + { CCI_REG8(0x0303), 0x02 }, + { CCI_REG8(0x0304), 0x01 }, + { CCI_REG8(0x0305), 0x90 }, + { CCI_REG8(0x0306), 0x00 }, + { CCI_REG8(0x0323), 0x02 }, + { CCI_REG8(0x0325), 0x68 }, + { CCI_REG8(0x0326), 0xd8 }, + { CCI_REG8(0x3006), 0x0e }, + { CCI_REG8(0x300d), 0x08 }, + { CCI_REG8(0x3018), 0xf0 }, + { CCI_REG8(0x301c), 0xf0 }, + { CCI_REG8(0x3020), 0x20 }, + { CCI_REG8(0x3040), 0x0f }, + { CCI_REG8(0x3022), 0x01 }, + { CCI_REG8(0x3107), 0x40 }, + { CCI_REG8(0x3216), 0x01 }, + { CCI_REG8(0x3217), 0x00 }, + { CCI_REG8(0x3218), 0xc0 }, + { CCI_REG8(0x3219), 0x55 }, + { CCI_REG8(0x3506), 0x01 }, + { CCI_REG8(0x3507), 0x50 }, + { CCI_REG8(0x3508), 0x01 }, + { CCI_REG8(0x3509), 0x00 }, + { CCI_REG8(0x350a), 0x01 }, + { CCI_REG8(0x350b), 0x00 }, + { CCI_REG8(0x350c), 0x00 }, + { CCI_REG8(0x3541), 0x00 }, + { CCI_REG8(0x3542), 0x40 }, + { CCI_REG8(0x3605), 0x90 }, + { CCI_REG8(0x3606), 0x41 }, + { CCI_REG8(0x3612), 0x00 }, + { CCI_REG8(0x3620), 0x08 }, + { CCI_REG8(0x3630), 0x17 }, + { CCI_REG8(0x3631), 0x99 }, + { CCI_REG8(0x3639), 0x88 }, + { CCI_REG8(0x3668), 0x00 }, + { CCI_REG8(0x3674), 0x00 }, + { CCI_REG8(0x3677), 0x3f }, + { CCI_REG8(0x368f), 0x06 }, + { CCI_REG8(0x36a2), 0x19 }, + { CCI_REG8(0x36a4), 0xf1 }, + { CCI_REG8(0x36a5), 0x2d }, + { CCI_REG8(0x3706), 0x30 }, + { CCI_REG8(0x370d), 0x72 }, + { CCI_REG8(0x3713), 0x86 }, + { CCI_REG8(0x3715), 0x03 }, + { CCI_REG8(0x3716), 0x00 }, + { CCI_REG8(0x376d), 0x24 }, + { CCI_REG8(0x3770), 0x3a }, + { CCI_REG8(0x3778), 0x00 }, + { CCI_REG8(0x37a8), 0x03 }, + { CCI_REG8(0x37a9), 0x00 }, + { CCI_REG8(0x37df), 0x7d }, + { CCI_REG8(0x3800), 0x00 }, + { CCI_REG8(0x3801), 0x00 }, + { CCI_REG8(0x3802), 0x00 }, + { CCI_REG8(0x3803), 0x00 }, + { CCI_REG8(0x3804), 0x02 }, + { CCI_REG8(0x3805), 0x8f }, + { CCI_REG8(0x3806), 0x01 }, + { CCI_REG8(0x3807), 0xef }, + { CCI_REG8(0x3808), 0x02 }, + { CCI_REG8(0x3809), 0x80 }, + { CCI_REG8(0x380a), 0x01 }, + { CCI_REG8(0x380b), 0xe0 }, + { CCI_REG8(0x380c), 0x01 }, + { CCI_REG8(0x380d), 0x78 }, + { CCI_REG8(0x380e), 0x08 }, + { CCI_REG8(0x380f), 0x30 }, + { CCI_REG8(0x3810), 0x00 }, + { CCI_REG8(0x3811), 0x08 }, + { CCI_REG8(0x3812), 0x00 }, + { CCI_REG8(0x3813), 0x08 }, + { CCI_REG8(0x3814), 0x11 }, + { CCI_REG8(0x3815), 0x11 }, + { CCI_REG8(0x3816), 0x00 }, + { CCI_REG8(0x3817), 0x01 }, + { CCI_REG8(0x3818), 0x00 }, + { CCI_REG8(0x3819), 0x05 }, + { CCI_REG8(0x3820), 0x40 }, + { CCI_REG8(0x3821), 0x04 }, + { CCI_REG8(0x3823), 0x00 }, + { CCI_REG8(0x3826), 0x00 }, + { CCI_REG8(0x3827), 0x00 }, + { CCI_REG8(0x382b), 0x52 }, + { CCI_REG8(0x384a), 0xa2 }, + { CCI_REG8(0x3858), 0x00 }, + { CCI_REG8(0x3859), 0x00 }, + { CCI_REG8(0x3860), 0x00 }, + { CCI_REG8(0x3861), 0x00 }, + { CCI_REG8(0x3866), 0x0c }, + { CCI_REG8(0x3867), 0x07 }, + { CCI_REG8(0x3884), 0x00 }, + { CCI_REG8(0x3885), 0x08 }, + { CCI_REG8(0x3888), 0x50 }, + { CCI_REG8(0x3893), 0x6c }, + { CCI_REG8(0x3898), 0x00 }, + { CCI_REG8(0x389a), 0x04 }, + { CCI_REG8(0x389b), 0x01 }, + { CCI_REG8(0x389c), 0x0b }, + { CCI_REG8(0x389d), 0xdc }, + { CCI_REG8(0x38b1), 0x04 }, + { CCI_REG8(0x38b2), 0x00 }, + { CCI_REG8(0x38b3), 0x08 }, + { CCI_REG8(0x38c1), 0x46 }, + { CCI_REG8(0x38c9), 0x02 }, + { CCI_REG8(0x38d4), 0x06 }, + { CCI_REG8(0x38d5), 0x5a }, + { CCI_REG8(0x38d6), 0x08 }, + { CCI_REG8(0x38d7), 0x3a }, + { CCI_REG8(0x391f), 0x00 }, + { CCI_REG8(0x3920), 0xaa }, + { CCI_REG8(0x3921), 0x00 }, + { CCI_REG8(0x3922), 0x00 }, + { CCI_REG8(0x3923), 0x00 }, + { CCI_REG8(0x3924), 0x00 }, + { CCI_REG8(0x3925), 0x00 }, + { CCI_REG8(0x3926), 0x00 }, + { CCI_REG8(0x3927), 0x00 }, + { CCI_REG8(0x3928), 0x10 }, + { CCI_REG8(0x3929), 0x01 }, + { CCI_REG8(0x392a), 0xb4 }, + { CCI_REG8(0x392b), 0x00 }, + { CCI_REG8(0x392c), 0x10 }, + { CCI_REG8(0x392d), 0x01 }, + { CCI_REG8(0x392e), 0x78 }, + { CCI_REG8(0x392f), 0x4a }, + { CCI_REG8(0x391e), 0x01 }, + { CCI_REG8(0x389f), 0x08 }, + { CCI_REG8(0x38a0), 0x00 }, + { CCI_REG8(0x38a1), 0x00 }, + { CCI_REG8(0x3a06), 0x06 }, + { CCI_REG8(0x3a07), 0x78 }, + { CCI_REG8(0x3a08), 0x08 }, + { CCI_REG8(0x3a09), 0x80 }, + { CCI_REG8(0x3a52), 0x00 }, + { CCI_REG8(0x3a53), 0x01 }, + { CCI_REG8(0x3a54), 0x0c }, + { CCI_REG8(0x3a55), 0x04 }, + { CCI_REG8(0x3a58), 0x0c }, + { CCI_REG8(0x3a59), 0x04 }, + { CCI_REG8(0x4000), 0xcf }, + { CCI_REG8(0x4003), 0x40 }, + { CCI_REG8(0x4008), 0x04 }, + { CCI_REG8(0x4009), 0x13 }, + { CCI_REG8(0x400a), 0x02 }, + { CCI_REG8(0x400b), 0x34 }, + { CCI_REG8(0x4010), 0x71 }, + { CCI_REG8(0x4042), 0xc3 }, + { CCI_REG8(0x4306), 0x04 }, + { CCI_REG8(0x4307), 0x12 }, + { CCI_REG8(0x4500), 0x70 }, + { CCI_REG8(0x4509), 0x00 }, + { CCI_REG8(0x450b), 0x83 }, + { CCI_REG8(0x4604), 0x68 }, + { CCI_REG8(0x481b), 0x44 }, + { CCI_REG8(0x481f), 0x30 }, + { CCI_REG8(0x4823), 0x44 }, + { CCI_REG8(0x4825), 0x35 }, + { CCI_REG8(0x4837), 0x11 }, + { CCI_REG8(0x4f00), 0x04 }, + { CCI_REG8(0x4f10), 0x04 }, + { CCI_REG8(0x4f21), 0x01 }, + { CCI_REG8(0x4f22), 0x00 }, + { CCI_REG8(0x4f23), 0x54 }, + { CCI_REG8(0x4f24), 0x51 }, + { CCI_REG8(0x4f25), 0x41 }, + { CCI_REG8(0x5000), 0x3f }, + { CCI_REG8(0x5001), 0x80 }, + { CCI_REG8(0x500a), 0x00 }, + { CCI_REG8(0x5100), 0x00 }, + { CCI_REG8(0x5111), 0x20 }, +}; + +static const struct og0ve1b_mode og0va1b_supported_modes[] =3D { + { + .width =3D 640, + .height =3D 480, + .hts =3D 752, + .vts =3D 2096, + .code =3D MEDIA_BUS_FMT_Y10_1X10, + .reg_list =3D { + .regs =3D og0va1b_640x480_60fps_mode, + .num_regs =3D ARRAY_SIZE(og0va1b_640x480_60fps_mode), + }, + }, +}; + static const struct cci_reg_sequence og0ve1b_640x480_120fps_mode[] =3D { { CCI_REG8(0x30a0), 0x02 }, { CCI_REG8(0x30a1), 0x00 }, @@ -276,22 +492,54 @@ static const struct og0ve1b_mode og0ve1b_supported_mo= des[] =3D { }, }; =20 +static int og0va1b_enable_test_pattern(struct og0ve1b *og0ve1b, u32 patter= n) +{ + u64 val =3D 0; + + if (pattern) + val =3D ((pattern - 1) << OG0VA1B_TEST_PATTERN_BAR_SHIFT) | + OG0V_TEST_PATTERN_ENABLE; + + return cci_write(og0ve1b->regmap, OG0VA1B_REG_TEST_PATTERN, val, NULL); +} + static int og0ve1b_enable_test_pattern(struct og0ve1b *og0ve1b, u32 patter= n) { u64 val =3D og0ve1b->pre_isp; =20 if (pattern) - val |=3D OG0VE1B_TEST_PATTERN_ENABLE; + val |=3D OG0V_TEST_PATTERN_ENABLE; else - val &=3D ~OG0VE1B_TEST_PATTERN_ENABLE; + val &=3D ~OG0V_TEST_PATTERN_ENABLE; =20 return cci_write(og0ve1b->regmap, OG0VE1B_REG_PRE_ISP, val, NULL); } =20 +static const struct og0ve1b_sensor_data og0va1b_data =3D { + .name =3D "og0va1b", + .chip_id =3D OG0VA1B_CHIP_ID, + .mclk_freq =3D OG0VA1B_MCLK_FREQ_19_2MHZ, + .enable_test_pattern =3D og0va1b_enable_test_pattern, + .test_pattern_menu =3D og0va1b_test_pattern_menu, + .num_test_patterns =3D ARRAY_SIZE(og0va1b_test_pattern_menu), + .exposure_shift =3D 0, + .pixel_rate_mul =3D 2, + .link_freq_menu =3D og0va1b_link_freq_menu, + .num_link_freqs =3D ARRAY_SIZE(og0va1b_link_freq_menu), + .modes =3D og0va1b_supported_modes, + .num_modes =3D ARRAY_SIZE(og0va1b_supported_modes), +}; + static const struct og0ve1b_sensor_data og0ve1b_data =3D { + .name =3D "og0ve1b", .chip_id =3D OG0VE1B_CHIP_ID, .mclk_freq =3D OG0VE1B_MCLK_FREQ_24MHZ, .enable_test_pattern =3D og0ve1b_enable_test_pattern, + .test_pattern_menu =3D og0ve1b_test_pattern_menu, + .num_test_patterns =3D ARRAY_SIZE(og0ve1b_test_pattern_menu), + .cache_test_pattern_reg =3D true, + .exposure_shift =3D 4, + .pixel_rate_mul =3D 1, .link_freq_menu =3D og0ve1b_link_freq_menu, .num_link_freqs =3D ARRAY_SIZE(og0ve1b_link_freq_menu), .modes =3D og0ve1b_supported_modes, @@ -311,7 +559,7 @@ static int og0ve1b_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_VBLANK: /* Update max exposure while meeting expected vblanking */ exposure_max =3D ctrl->val + mode->height - - OG0VE1B_EXPOSURE_MAX_MARGIN; + OG0V_EXPOSURE_MAX_MARGIN; ret =3D __v4l2_ctrl_modify_range(og0ve1b->exposure, og0ve1b->exposure->minimum, exposure_max, @@ -327,15 +575,16 @@ static int og0ve1b_set_ctrl(struct v4l2_ctrl *ctrl) =20 switch (ctrl->id) { case V4L2_CID_ANALOGUE_GAIN: - ret =3D cci_write(og0ve1b->regmap, OG0VE1B_REG_ANALOGUE_GAIN, + ret =3D cci_write(og0ve1b->regmap, OG0V_REG_ANALOGUE_GAIN, ctrl->val, NULL); break; case V4L2_CID_EXPOSURE: - ret =3D cci_write(og0ve1b->regmap, OG0VE1B_REG_EXPOSURE, - ctrl->val << 4, NULL); + ret =3D cci_write(og0ve1b->regmap, OG0V_REG_EXPOSURE, + ctrl->val << og0ve1b->data->exposure_shift, + NULL); break; case V4L2_CID_VBLANK: - ret =3D cci_write(og0ve1b->regmap, OG0VE1B_REG_VTS, + ret =3D cci_write(og0ve1b->regmap, OG0V_REG_VTS, ctrl->val + mode->height, NULL); break; case V4L2_CID_TEST_PATTERN: @@ -360,7 +609,7 @@ static s64 og0ve1b_pixel_rate(const struct og0ve1b_sens= or_data *data) const struct og0ve1b_mode *mode =3D &data->modes[0]; unsigned int bpp =3D mode->code =3D=3D MEDIA_BUS_FMT_Y8_1X8 ? 8 : 10; =20 - return div_u64(data->link_freq_menu[0], bpp); + return div_u64(data->link_freq_menu[0] * data->pixel_rate_mul, bpp); } =20 static int og0ve1b_init_controls(struct og0ve1b *og0ve1b) @@ -395,26 +644,26 @@ static int og0ve1b_init_controls(struct og0ve1b *og0v= e1b) v_blank =3D mode->vts - mode->height; og0ve1b->vblank =3D v4l2_ctrl_new_std(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_VBLANK, v_blank, - OG0VE1B_VTS_MAX - mode->height, 1, + OG0V_VTS_MAX - mode->height, 1, v_blank); =20 v4l2_ctrl_new_std(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, - OG0VE1B_ANALOGUE_GAIN_MIN, OG0VE1B_ANALOGUE_GAIN_MAX, - OG0VE1B_ANALOGUE_GAIN_STEP, - OG0VE1B_ANALOGUE_GAIN_DEFAULT); + OG0V_ANALOGUE_GAIN_MIN, OG0V_ANALOGUE_GAIN_MAX, + OG0V_ANALOGUE_GAIN_STEP, + OG0V_ANALOGUE_GAIN_DEFAULT); =20 - exposure_max =3D mode->vts - OG0VE1B_EXPOSURE_MAX_MARGIN; + exposure_max =3D mode->vts - OG0V_EXPOSURE_MAX_MARGIN; og0ve1b->exposure =3D v4l2_ctrl_new_std(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_EXPOSURE, - OG0VE1B_EXPOSURE_MIN, + OG0V_EXPOSURE_MIN, exposure_max, - OG0VE1B_EXPOSURE_STEP, - OG0VE1B_EXPOSURE_DEFAULT); + OG0V_EXPOSURE_STEP, + OG0V_EXPOSURE_DEFAULT); =20 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_TEST_PATTERN, - ARRAY_SIZE(og0ve1b_test_pattern_menu) - 1, - 0, 0, og0ve1b_test_pattern_menu); + data->num_test_patterns - 1, + 0, 0, data->test_pattern_menu); =20 if (ctrl_hdlr->error) return ctrl_hdlr->error; @@ -464,8 +713,8 @@ static int og0ve1b_enable_streams(struct v4l2_subdev *s= d, return ret; =20 /* Skip a step of explicit entering into the standby mode */ - ret =3D cci_write(og0ve1b->regmap, OG0VE1B_REG_SOFTWARE_RST, - OG0VE1B_SOFTWARE_RST, NULL); + ret =3D cci_write(og0ve1b->regmap, OG0V_REG_SOFTWARE_RST, + OG0V_SOFTWARE_RST, NULL); if (ret) { dev_err(og0ve1b->dev, "failed to software reset: %d\n", ret); goto error; @@ -482,8 +731,8 @@ static int og0ve1b_enable_streams(struct v4l2_subdev *s= d, if (ret) goto error; =20 - ret =3D cci_write(og0ve1b->regmap, OG0VE1B_REG_MODE_SELECT, - OG0VE1B_MODE_STREAMING, NULL); + ret =3D cci_write(og0ve1b->regmap, OG0V_REG_MODE_SELECT, + OG0V_MODE_STREAMING, NULL); if (ret) { dev_err(og0ve1b->dev, "failed to start streaming: %d\n", ret); goto error; @@ -504,8 +753,8 @@ static int og0ve1b_disable_streams(struct v4l2_subdev *= sd, struct og0ve1b *og0ve1b =3D to_og0ve1b(sd); int ret; =20 - ret =3D cci_write(og0ve1b->regmap, OG0VE1B_REG_MODE_SELECT, - OG0VE1B_MODE_STANDBY, NULL); + ret =3D cci_write(og0ve1b->regmap, OG0V_REG_MODE_SELECT, + OG0V_MODE_STANDBY, NULL); if (ret) dev_err(og0ve1b->dev, "failed to stop streaming: %d\n", ret); =20 @@ -621,7 +870,7 @@ static int og0ve1b_identify_sensor(struct og0ve1b *og0v= e1b) u64 val; int ret; =20 - ret =3D cci_read(og0ve1b->regmap, OG0VE1B_REG_CHIP_ID, &val, NULL); + ret =3D cci_read(og0ve1b->regmap, OG0V_REG_CHIP_ID, &val, NULL); if (ret) { dev_err(og0ve1b->dev, "failed to read chip id: %d\n", ret); return ret; @@ -633,10 +882,12 @@ static int og0ve1b_identify_sensor(struct og0ve1b *og= 0ve1b) return -ENODEV; } =20 - ret =3D cci_read(og0ve1b->regmap, OG0VE1B_REG_PRE_ISP, - &og0ve1b->pre_isp, NULL); - if (ret) - dev_err(og0ve1b->dev, "failed to read pre_isp: %d\n", ret); + if (og0ve1b->data->cache_test_pattern_reg) { + ret =3D cci_read(og0ve1b->regmap, OG0VE1B_REG_PRE_ISP, + &og0ve1b->pre_isp, NULL); + if (ret) + dev_err(og0ve1b->dev, "failed to read pre_isp: %d\n", ret); + } =20 return ret; } @@ -732,6 +983,8 @@ static int og0ve1b_probe(struct i2c_client *client) return -ENODEV; =20 v4l2_i2c_subdev_init(&og0ve1b->sd, client, &og0ve1b_subdev_ops); + v4l2_i2c_subdev_set_name(&og0ve1b->sd, client, + og0ve1b->data->name, NULL); =20 og0ve1b->regmap =3D devm_cci_regmap_init_i2c(client, 16); if (IS_ERR(og0ve1b->regmap)) @@ -863,6 +1116,7 @@ static const struct dev_pm_ops og0ve1b_pm_ops =3D { }; =20 static const struct of_device_id og0ve1b_of_match[] =3D { + { .compatible =3D "ovti,og0va1b", .data =3D &og0va1b_data }, { .compatible =3D "ovti,og0ve1b", .data =3D &og0ve1b_data }, { /* sentinel */ } }; @@ -881,5 +1135,5 @@ static struct i2c_driver og0ve1b_i2c_driver =3D { module_i2c_driver(og0ve1b_i2c_driver); =20 MODULE_AUTHOR("Vladimir Zapolskiy "); -MODULE_DESCRIPTION("OmniVision OG0VE1B sensor driver"); +MODULE_DESCRIPTION("OmniVision OG0VE1B/OG0VA1B sensor driver"); MODULE_LICENSE("GPL"); --=20 2.34.1