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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14382741839sm14244091c88.6.2026.09.15.03.10.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:10:13 -0700 (PDT) From: Hangxiang Ma Date: Tue, 15 Sep 2026 03:09:56 -0700 Subject: [PATCH v16 01/11] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Kaanapali CSI2 PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-kaanapali-camss-v16-1-c9f3f6f4180c@oss.qualcomm.com> References: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> In-Reply-To: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX6tDz5/8a8ZfY CheKyt48Dh98UtAl8AzGMVJzlPp8PqNm70UHLTU+StibBCTKLMxnABhfhOOdQMrxCG2M95xWiMb T2bJANiwB95jS2Q41LCN3D0WBFfnreU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX22Wpu8tN6Gt9 yxCRg2IKum40Durk0TsDZvKaI2OokJQxSSTeGJseBY0pLj4aK4IOBwXj0pdP1rJpNmLF5Ciqxj8 WL8m+WSD0henac6/ulVwv7ZsC2fxXvmhh9RXM3EhcCZh4btbkbppoJHWuNK2SIVzD1Ro8quCq1U bDL1ikypjKPaUgYfs3l/DKkTeyeuS1V22DRCg0amqPWe8t1AMWGd4CblbG8pSYQizfaduzMyx73 /9Jco5741zKJOLzpAyOjbqyUXJ54jDxMrwDpGgOcemsTp1rmapsK8+ag4Po9ExpEXcp9LEwpoFS LFXxaC0eyC4FBMbafjLQu+UywlsnabtlvVPEbjl0Z/zxhgREA0fZSOYoItu3Rjogf5GUuBhCOoV LzoEl0Gr/cUgKDrKdY//Kasy0JKU28GTeYYGNRPYaOneH4J5ySxLho8s8zC3WYIXlu3k3UcGiA2 11X9EZaV9LKXr/M2uTA== X-Authority-Analysis: v=2.4 cv=HsDjiETS c=1 sm=1 tr=0 ts=6aa91986 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=8sc_bQFcTW-iTt5i-CEA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: USZ6fnkSG1vpb-mUBdLJW3f-SP_KU4Qk X-Proofpoint-ORIG-GUID: USZ6fnkSG1vpb-mUBdLJW3f-SP_KU4Qk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_03,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150146 The Kaanapali CSI2 PHY is compatible with the existing x1e80100 CSI2 C-PHY/DPHY binding. Add the "qcom,kaanapali-csi2-phy" compatible. Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma --- Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.y= aml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml index 993271c42fa0..fa56a375e752 100644 --- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml @@ -16,7 +16,9 @@ description: =20 properties: compatible: - const: qcom,x1e80100-csi2-phy + enum: + - qcom,kaanapali-csi2-phy + - qcom,x1e80100-csi2-phy =20 reg: maxItems: 1 --=20 2.34.1 From nobody Fri Sep 25 12:06:09 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ABFE385D99 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14382741839sm14244091c88.6.2026.09.15.03.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:10:14 -0700 (PDT) From: Hangxiang Ma Date: Tue, 15 Sep 2026 03:09:57 -0700 Subject: [PATCH v16 02/11] media: dt-bindings: Add CAMSS device for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-kaanapali-camss-v16-2-c9f3f6f4180c@oss.qualcomm.com> References: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> In-Reply-To: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: D1_bXcxaqwvqufNF1hkS9n_x71Ng_cs1 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX4O3R7isbCq/z 4K9B5AlFMgPCgsEV0YeZdPC/VAtGie42C26sKjIhCO5eV7t6LQJNhD2aL7vZoMUeIeGpW9I6/DO sj8pq2PKfssf90gCzjKf+JwBLUxALJ0= X-Authority-Analysis: v=2.4 cv=dcUVTnXe c=1 sm=1 tr=0 ts=6aa91988 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=P1LTzt_rTVk3HkJ-OnIA:9 a=lP8IeLpE6-iXzjOB:21 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX/Q6SgahlS2Ap vuf2DHFHhB8sLF9fQhoqWySGZ4Z4SXE+R32I2HocCkUlOXGIz4xfSfqtLqpBLOPXATPd8HsK7dV Uu0ruja09HCUXTrMID9/To2X+vELuj6nfEUUXodqNLUK8gNyFFvyPFULk8MA/9NX8/2IfQu1Vgf gQaTUv5FacddV7E8gthW1BXasUkiicUMbcmfyveY4yaJI40t0wwjSJkZO1OQBMtNl5o6kQA4iTH tiXniUi/liT+ZFUhV0t5ZXpE+rgEpnLWQ8vfCaupkwjA5OJiCndsRknbvXRrQQMBE1j2obrOb+T Jdo/dFhr1G9k/DOaNai6Gwhy4ZV0bVQlh0++Lfqw/eCj30hgu2duxyXNfEK8ueFr/9qOtEGbDIm IFZDi0Gpsv02wDT10otKre7uOgv8iBIIvqayr8shOn3+X5IQ9oLjRougya76aC6YlDseSOKFbNO gK0/iE/nfk9XTpT6h0g== X-Proofpoint-GUID: D1_bXcxaqwvqufNF1hkS9n_x71Ng_cs1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_03,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 suspectscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150146 Add bindings for Camera Subsystem (CAMSS) on the Qualcomm Kaanapali platform. The Kaanapali platform provides: - 6 x CSIPHY (CSI Physical Layer) - 3 x TPG (Test Pattern Generator) - 3 x CSID (CSI Decoder) - 2 x CSID Lite - 3 x VFE (Video Front End), 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite Signed-off-by: Hangxiang Ma --- .../bindings/media/qcom,kaanapali-camss.yaml | 375 +++++++++++++++++= ++++ 1 file changed, 375 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.y= aml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml new file mode 100644 index 000000000000..5bbcd35f053c --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml @@ -0,0 +1,375 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Camera Subsystem (CAMSS) + +maintainers: + - Hangxiang Ma + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,kaanapali-camss + + reg: + maxItems: 19 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csitpg0 + - const: csitpg1 + - const: csitpg2 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 35 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe2 + - const: cpas_vfe_lite + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: qdss_debug_xo + + interrupts: + maxItems: 16 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + + iommus: + items: + - description: S1 HLOS IFE non-protected stream + + power-domains: + items: + - description: IFE0 GDSC - Global Distributed Switch Controller for = IFE0. + - description: IFE1 GDSC - Global Distributed Switch Controller for = IFE1. + - description: IFE2 GDSC - Global Distributed Switch Controller for = IFE2. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed = Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports, one per CSID. Each port receives the CSI data + decoded by the matching CSIPHY. + + patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY 0-5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + isp@9253000 { + compatible =3D "qcom,kaanapali-camss"; + + reg =3D <0x0 0x09253000 0x0 0x5e80>, + <0x0 0x09263000 0x0 0x5e80>, + <0x0 0x09273000 0x0 0x5e80>, + <0x0 0x092d3000 0x0 0x3880>, + <0x0 0x092e7000 0x0 0x3880>, + <0x0 0x09523000 0x0 0x2000>, + <0x0 0x09525000 0x0 0x2000>, + <0x0 0x09527000 0x0 0x2000>, + <0x0 0x09529000 0x0 0x2000>, + <0x0 0x0952b000 0x0 0x2000>, + <0x0 0x0952d000 0x0 0x2000>, + <0x0 0x093fd000 0x0 0x400>, + <0x0 0x093fe000 0x0 0x400>, + <0x0 0x093ff000 0x0 0x400>, + <0x0 0x09151000 0x0 0x20000>, + <0x0 0x09171000 0x0 0x20000>, + <0x0 0x09191000 0x0 0x20000>, + <0x0 0x092dc000 0x0 0x1300>, + <0x0 0x092f0000 0x0 0x1300>; + + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks =3D <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACT= IVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACT= IVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 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Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma Reviewed-by: Loic Poulain --- drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 07b3cddca584..2c9f02bca809 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -34,6 +34,20 @@ =20 static const struct parent_dev_ops vfe_parent_dev_ops; =20 +static const struct resources_icc icc_res_kaanapali[] =3D { + { + .name =3D "ahb", + .icc_bw_tbl.avg =3D 150000, + .icc_bw_tbl.peak =3D 300000, + }, + /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */ + { + .name =3D "hf_mnoc", + .icc_bw_tbl.avg =3D 471860, + .icc_bw_tbl.peak =3D 925857, + } +}; + static const struct camss_subdev_resources csiphy_res_8x16[] =3D { /* CSIPHY0 */ { @@ -5596,6 +5610,13 @@ static void camss_remove(struct platform_device *pde= v) camss_genpd_cleanup(camss); } =20 +static const struct camss_resources kaanapali_resources =3D { + .version =3D CAMSS_KAANAPALI, + .pd_name =3D "top", + .icc_res =3D icc_res_kaanapali, + .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), +}; + static const struct camss_resources msm8916_resources =3D { .version =3D CAMSS_8x16, .csiphy_res =3D csiphy_res_8x16, @@ -5829,6 +5850,7 @@ static const struct camss_resources x1e80100_resource= s =3D { }; =20 static const struct of_device_id camss_dt_match[] =3D { + { .compatible =3D "qcom,kaanapali-camss", .data =3D &kaanapali_resources = }, { .compatible =3D "qcom,msm8916-camss", .data =3D &msm8916_resources }, { .compatible =3D "qcom,msm8939-camss", .data =3D &msm8939_resources }, { .compatible =3D "qcom,msm8953-camss", .data =3D &msm8953_resources }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index ba3d51d9c0bf..fadba57c5efa 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -96,6 +96,7 @@ enum camss_version { CAMSS_8550, CAMSS_8650, CAMSS_8775P, + CAMSS_KAANAPALI, CAMSS_X1E80100, }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14382741839sm14244091c88.6.2026.09.15.03.10.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:10:17 -0700 (PDT) From: Hangxiang Ma Date: Tue, 15 Sep 2026 03:09:59 -0700 Subject: [PATCH v16 04/11] phy: qcom-mipi-csi2: Parametrise the common status register offset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-kaanapali-camss-v16-4-c9f3f6f4180c@oss.qualcomm.com> References: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> In-Reply-To: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: wRl4FWXZp0NoDWe_NTZ4eALw_KiNb1l- X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX1hC0KUbSt1oT UNhX0mzDhC1sGyiXlQl30UBQAFdR7tp0L70iDTyYFHNXODNRXcQ8RjsZtyPLu6YiV0uA8X7ELgC L5VFn1IpGww5At5DminAyfAL3JOtAZM= X-Authority-Analysis: v=2.4 cv=dcUVTnXe c=1 sm=1 tr=0 ts=6aa9198a cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=P6Xs4Y00w1yHQXPR5eoA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX10roC2AIo27C FuZjZLnjULvJiKyTcZNKWeIj2Hq9Wc+/RtRLDQRbnNJDNALC8gDkMY51zmSTGXQth1MyoWn2T1l z3UunUJe/5ZOMX38h+qQXQz2KMcPoenBmq2XXkZPAfHN+oH1FM35vvxzV9RVhNTHTCHuJlZWaVO +4Z89qjo7bpPGnsKAqEANIPsM6cUuHEgArDPTayuxNDiYjDrQqD/gymwEHoSjnY4vgNr4faXABr mWVOY+tUYSYDeUZGLmf6g4OAcBglGKNRAilSrUhqabqNbNYYlMHfB9We7Kb3zKcCN6cUaRch9wm eqGl9FhuhEnN0TiRfRFzRjYXAi5BT8OlgJodsqSfr9+S//RxLqFYnEmfsTgw/4co4aijunqF+dV pV7igrST+E1mx214/TIziuB8uCYm/jt+7COLAMvdZqzNmL+D6vXbHf/6htDVZDX2FuEfjeDzmth hmqJRxZoU7/Oz5BnNDg== X-Proofpoint-GUID: wRl4FWXZp0NoDWe_NTZ4eALw_KiNb1l- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_03,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 suspectscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150146 The CSI2 PHY common status registers are not at a fixed offset from the common register block across SoCs: x1e80100 uses 0xb0 while other 3PH v2.4.0 parts differ. Replace the hard-coded 0xb0 in CSIPHY_3PH_CMN_CSI_COMMON_STATUSn() with a per-SoC common_status_offset field in struct mipi_csi2phy_device_regs, initialising x1e80100 to 0xb0 so behaviour is unchanged. This is a no-functional-change preparation for describing other SoC offsets. Signed-off-by: Hangxiang Ma --- drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 16 +++++++++++----- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 1 + 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/p= hy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index 966d79c98f9b..8cd331cfb4b3 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -19,7 +19,8 @@ #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL10_IRQ_CLEAR_CMD BIT(0) -#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x= 4 * (n)) +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, common_status_offset, n)= \ + ((offset) + (common_status_offset) + 0x4 * (n)) =20 #define CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(n) ((0x200 * (n)) + 0x24) =20 @@ -176,19 +177,23 @@ static void phy_qcom_mipi_csi2_hw_version_read(struct= mipi_csi2phy_device *csi2p CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 6)); =20 tmp =3D readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 12)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 12)); csi2phy->hw_version =3D tmp; =20 tmp =3D readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 13)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 13)); csi2phy->hw_version |=3D (tmp << 8) & 0xFF00; =20 tmp =3D readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 14)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 14)); csi2phy->hw_version |=3D (tmp << 16) & 0xFF0000; =20 tmp =3D readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 15)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 15)); csi2phy->hw_version |=3D (tmp << 24) & 0xFF000000; =20 dev_dbg_once(csi2phy->dev, "CSIPHY 3PH HW Version =3D 0x%08x\n", csi2phy-= >hw_version); @@ -375,6 +380,7 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1= e =3D { .init_seq =3D lane_regs_x1e80100, .lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100), .common_regs_offset =3D 0x1000, + .common_status_offset =3D 0xb0, }, .supply_names =3D (const char **)x1e_supplies, .num_supplies =3D ARRAY_SIZE(x1e_supplies), diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualco= mm/phy-qcom-mipi-csi2.h index 7e55ae007370..d6366f809e51 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -51,6 +51,7 @@ struct mipi_csi2phy_device_regs { const struct mipi_csi2phy_lane_regs *init_seq; const int lane_array_size; const u32 common_regs_offset; + const u32 common_status_offset; }; =20 struct mipi_csi2_genpd { --=20 2.34.1 From nobody Fri Sep 25 12:06:09 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5430412BED for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14382741839sm14244091c88.6.2026.09.15.03.10.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:10:18 -0700 (PDT) From: Hangxiang Ma Date: Tue, 15 Sep 2026 03:10:00 -0700 Subject: [PATCH v16 05/11] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-kaanapali-camss-v16-5-c9f3f6f4180c@oss.qualcomm.com> References: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> In-Reply-To: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX15n/cJ6C/bOY fgPG8XQSgX3M63jONMUNkxIceaDJUsz+tXNgPU777uRnmD/zFv7+5zPSPscJCHZ0O78f/a6P90C lWArSp45jAPlH/Gh/BYDaDDDZwc1x50nb+cyl6xdsC9kTP5qwWc5NAkHb7Jwc2xQUd4IhNz17kl 06a0CxxBfR4/uggrnKiDYboMtIAJ9ySOLJAtiAAz+875eh5vIrpQuF3pyeYbx3J3MMhpabsYxBG qJIvFtQjCmiyKE2t57e10FmquB0HAz/acEFgQRDoZQK5z82my3NqUg/88l1bqjRC96kGlWwwkKZ mp/FXloOHRyg30eD1+9JVyOv+p9p97gL3XIDnfl09CWTObYepBa23qItX0LnizR/t9HEfCwOWxx Ll7m7fHYQXCDM6g9jSiNms497J4xIwAtjv0OjbRwKakz/qpCyfujLqTYn+V1VSO04TEiWOMgK5A +OeD9FpyFS/ptBfz9TQ== X-Proofpoint-GUID: 3CUZi9QODatkByFNJjcjh6AqUECVaX6F X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfXwlcda8+Qfed1 2Pq8hhGEtYefGhDDkQBsj5dK5UT6XxvolJ6zkdM0U8tVelvKt3jb320QBv81Xnz31vKWWGNySCo ULaB/O3Wfjj5nlljhhbM+2JICy3r24E= X-Authority-Analysis: v=2.4 cv=fck4WEQF c=1 sm=1 tr=0 ts=6aa9198c cx=c_pps a=z9lCQkyTxNhZyzAvolXo/A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=YI0lirVkik_cQ8OgtUwA:9 a=QEXdDO2ut3YA:10 a=EyFUmsFV_t8cxB2kMr4A:22 X-Proofpoint-ORIG-GUID: 3CUZi9QODatkByFNJjcjh6AqUECVaX6F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_03,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 bulkscore=0 malwarescore=0 phishscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150146 Add support for the v2.4.0 two-phase CSIPHY found on Kaanapali, where the PHY is driven by the standalone phy-qcom-mipi-csi2 DPHY driver rather than by CAMSS. Add the mipi_csi2_dphy_3nm_kaanapali configuration, which reuses the x1e80100 lane sequence, clocks and supplies but selects the v2.4.0 common status offset, adding Kaanapali power domain and register the "qcom,kaanapali-csi2-phy" compatible. Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/camss.c | 53 ++++++++++++++++++= ++++ drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 16 +++++++ drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 1 + drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 1 + 4 files changed, 71 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 2c9f02bca809..0a79484ea1fe 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -34,6 +34,57 @@ =20 static const struct parent_dev_ops vfe_parent_dev_ops; =20 +static const struct camss_subdev_resources csiphy_res_kaanapali[] =3D { + /* CSIPHY0 */ + { + .csiphy =3D { + .id =3D 0, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY1 */ + { + .csiphy =3D { + .id =3D 1, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY2 */ + { + .csiphy =3D { + .id =3D 2, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY3 */ + { + .csiphy =3D { + .id =3D 3, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY4 */ + { + .csiphy =3D { + .id =3D 4, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY5 */ + { + .csiphy =3D { + .id =3D 5, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "ahb", @@ -5613,8 +5664,10 @@ static void camss_remove(struct platform_device *pde= v) static const struct camss_resources kaanapali_resources =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", + .csiphy_res =3D csiphy_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), + .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/p= hy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index 8cd331cfb4b3..658a39463104 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -389,3 +389,19 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x= 1e =3D { .genpds =3D x1e_genpds, .num_genpds =3D ARRAY_SIZE(x1e_genpds), }; + +const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_3nm_kaanapali =3D { + .ops =3D &phy_qcom_mipi_csi2_ops_3ph_1_0, + .reg_info =3D { + .init_seq =3D lane_regs_x1e80100, + .lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100), + .common_regs_offset =3D 0x1000, + .common_status_offset =3D 0x138, + }, + .supply_names =3D (const char **)x1e_supplies, + .num_supplies =3D ARRAY_SIZE(x1e_supplies), + .clk_names =3D (const char **)x1e_clks, + .num_clk =3D ARRAY_SIZE(x1e_clks), + .genpds =3D x1e_genpds, + .num_genpds =3D ARRAY_SIZE(x1e_genpds), +}; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/q= ualcomm/phy-qcom-mipi-csi2-core.c index 4227f29ad1f6..b766e1ece660 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c @@ -441,6 +441,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_dev= ice *pdev) =20 static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] =3D { { .compatible =3D "qcom,x1e80100-csi2-phy", .data =3D &mipi_csi2_dphy_4nm= _x1e }, + { .compatible =3D "qcom,kaanapali-csi2-phy", .data =3D &mipi_csi2_dphy_3n= m_kaanapali }, { } }; MODULE_DEVICE_TABLE(of, phy_qcom_mipi_csi2_of_match_table); diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualco= mm/phy-qcom-mipi-csi2.h index d6366f809e51..2355a1db9b94 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -94,5 +94,6 @@ struct mipi_csi2phy_device { }; =20 extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14382741839sm14244091c88.6.2026.09.15.03.10.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:10:20 -0700 (PDT) From: Hangxiang Ma Date: Tue, 15 Sep 2026 03:10:01 -0700 Subject: [PATCH v16 06/11] media: qcom: camss: csid: Add support for CSID Gen4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-kaanapali-camss-v16-6-c9f3f6f4180c@oss.qualcomm.com> References: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> In-Reply-To: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: aBQgP262k3SKceNk16VEzTDOAnLmfPP1 X-Authority-Analysis: v=2.4 cv=cehHPXDM c=1 sm=1 tr=0 ts=6aa9198e cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=hAI97D9Htgy7VLTQvtAA:9 a=4Q4zU7iZy6iiv8wZ:21 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: aBQgP262k3SKceNk16VEzTDOAnLmfPP1 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX3EZ/WEKmwMe4 Z4OiKRilHPZrbuqqY7BkCiCLn4EaWLpLjkT7TYXGMP2rNityqOeS3Hpw9R2KKZg4y6M2JZoGUqF afaPZ6OKYM5xfn7SQvil3yC6d9YitJ4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX5qXniRiONH2d Zn/ENlT4ccTiGQ+DPGqTp2j3T/gOdINaWnPtGk89I/qNkyvHK2f5VX5nxjUFSAGzbPE+dWhItSh lknqPt3qNEnVDlyGkXhXcAQSgQYQ5lGENULfoKAGcuOzEHkNVOUILLyeRVpaIGlLSAMAPbmjvL8 ElBMUjw2vtZwNYfsSRGggS/u0emn0N4h2jn4oPe5X2aNPXwA9ZyALLTMhN3y14oIddu5SmgxQq6 wq6n4GLZTZ/rFt21xejZSw72onPsaJkj3orFOOaKm02AM/k2irhpLb1W8scKtfR2jW0Qmlfz+xt 1Q7PvNsDkUHdc5o3d/9aK61NXy/ECx0dzZxFpoHngVxHJcqkZ/k9BXi+lK/gNONKDvRq4uXAyeQ z9axXAkVVXsNjZ5Kc7ux1N8s/zX9T9/Z5I8UfWe2P8NDdfWmRgTx785A6637gFd42PDE0lPyPIS 6I4zLic+5ZLjHUzVEcA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_03,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150146 Add support for the CSID Gen4 hardware found on Kaanapali SoC. Introduce Gen4 resource descriptions and implement the hardware-specific register programming, reset sequence, and BUF_DONE interrupt handling. Gen4 splits RUP and AUP updates into separate registers and uses a SET register to commit the updates. Update the CSID interface to support both this scheme and the legacy combined reg_update mechanism. Reviewed-by: Bryan O'Donoghue Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-csid-gen4.c | 380 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-csid.h | 9 +- drivers/media/platform/qcom/camss/camss.c | 75 ++++ 4 files changed, 464 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 27898b3cc7d3..cebfd947f28e 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -10,6 +10,7 @@ qcom-camss-objs +=3D \ camss-csid-680.o \ camss-csid-gen2.o \ camss-csid-gen3.o \ + camss-csid-gen4.o \ camss-csiphy.o \ camss-csiphy-2ph-1-0.o \ camss-csiphy-3ph-1-0.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen4.c b/drivers/= media/platform/qcom/camss/camss-csid-gen4.c new file mode 100644 index 000000000000..4ff2f41f70f7 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-gen4.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-csid-gen4.c + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-gen3.h" + +/* Reset and Command Registers */ +#define CSID_RST_CFG 0x108 +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +/* Reset and Command Registers */ +#define CSID_RST_CMD 0x10C +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) +#define CSID_IRQ_CMD 0x110 +#define IRQ_CMD_CLEAR BIT(0) + +/* Register Update Commands, RUP/AUP */ +#define CSID_RUP_CMD 0x114 +#define CSID_AUP_CMD 0x118 +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) +#define CSID_RUP_AUP_CMD 0x11C +#define RUP_SET BIT(0) +#define MUP BIT(4) + +/* Top level interrupt registers */ +#define CSID_TOP_IRQ_STATUS 0x180 +#define CSID_TOP_IRQ_MASK 0x184 +#define CSID_TOP_IRQ_CLEAR 0x188 +#define INFO_RST_DONE BIT(0) +#define CSI2_RX_IRQ_STATUS BIT(2) +#define BUF_DONE_IRQ_STATUS BIT(3) + +/* Buffer done interrupt registers */ +#define CSID_BUF_DONE_IRQ_STATUS 0x1A0 +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16 +#define CSID_BUF_DONE_IRQ_MASK 0x1A4 +#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8 +#define CSID_BUF_DONE_IRQ_SET 0x1AC + +/* CSI2 RX interrupt registers */ +#define CSID_CSI2_RX_IRQ_STATUS 0x1B0 +#define CSID_CSI2_RX_IRQ_MASK 0x1B4 +#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8 +#define CSID_CSI2_RX_IRQ_SET 0x1BC + +/* CSI2 RX Configuration */ +#define CSID_CSI2_RX_CFG0 0x880 +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 +#define CSID_CSI2_RX_CFG1 0x884 +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define MSM_CSID_MAX_SRC_STREAMS_GEN4 (csid_is_lite(csid) ? 4 : 5) + +/* RDI Configuration */ +#define CSID_RDI_CFG0(rdi) (csid_is_lite(csid) ?\ + (0x3080 + 0x200 * (rdi)) :\ + (0x5480 + 0x200 * (rdi))) +#define RDI_CFG0_RETIME_BS BIT(5) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_EN BIT(31) + +/* RDI Control and Configuration */ +#define CSID_RDI_CTRL(rdi) (csid_is_lite(csid) ?\ + (0x3088 + 0x200 * (rdi)) :\ + (0x5488 + 0x200 * (rdi))) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) (csid_is_lite(csid) ?\ + (0x3094 + 0x200 * (rdi)) :\ + (0x5494 + 0x200 * (rdi))) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +/* RDI Pixel Store Configuration */ +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi)) +#define RDI_PIX_STORE_CFG0_EN BIT(0) +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 + +/* RDI IRQ Status in wrapper */ +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi))) +#define INFO_RUP_DONE BIT(23) + +static void __csid_aup_rup_trigger(struct csid_device *csid) +{ + /* trigger SET in combined register */ + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); +} + +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id) +{ + /* Hardware clears the registers upon consuming the settings */ + csid->aup_update &=3D ~CSID_RUP_AUP_RDI(port_id); + csid->rup_update &=3D ~CSID_RUP_AUP_RDI(port_id); +} + +static void __csid_aup_update(struct csid_device *csid, int port_id) +{ + csid->aup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->aup_update, csid->base + CSID_AUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_reg_update(struct csid_device *csid, int port_id) +{ + csid->rup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->rup_update, csid->base + CSID_RUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy) +{ + int val; + + val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) +{ + int val; + + if (vc > 3) { + val =3D readl(csid->base + CSID_CSI2_RX_CFG1); + val |=3D CSI2_RX_CFG1_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG1); + } +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val =3D 0; + + if (enable) + val =3D RDI_CTRL_START_CMD; + + writel(val, csid->base + CSID_RDI_CTRL(rdi)); +} + +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rd= i) +{ + u32 val; + + /* + * Configure pixel store to allow absorption of hblanking or idle time. + * This helps with horizontal crop and prevents line buffer conflicts. + * Reset state is 0x8 which has MIN_HBI=3D4, we keep the default MIN_HBI + * and just enable the pixel store functionality. + */ + val =3D (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enabl= e, u8 port, u8 vc) +{ + u8 lane_cnt =3D csid->phy.lane_cnt; + u32 val; + + /* Source pads matching RDI channels on hardware. + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. + */ + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST= _SRC + port]; + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res->f= ormats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt =3D 4; + + val =3D RDI_CFG0_TIMESTAMP_EN; + val |=3D RDI_CFG0_TIMESTAMP_STB_SEL; + val |=3D RDI_CFG0_RETIME_BS; + + /* note: for non-RDI path, this should be format->decode_format */ + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |=3D vc << RDI_CFG0_VC; + val |=3D format->data_type << RDI_CFG0_DT; + writel(val, csid->base + CSID_RDI_CFG0(port)); + + val =3D RDI_CFG1_PACKING_FORMAT_MIPI; + writel(val, csid->base + CSID_RDI_CFG1(port)); + + /* Configure pixel store using dedicated register in gen4 */ + if (!csid_is_lite(csid)) + __csid_configure_rdi_pix_store(csid, port); + + val =3D 0; + writel(val, csid->base + CSID_RDI_CTRL(port)); + + val =3D readl(csid->base + CSID_RDI_CFG0(port)); + + if (enable) + val |=3D RDI_CFG0_EN; + + writel(val, csid->base + CSID_RDI_CFG0(port)); +} + +static void csid_configure_stream(struct csid_device *csid, u8 enable) +{ + u8 i, k; + + __csid_configure_rx(csid, &csid->phy); + + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + __csid_configure_rdi_stream(csid, enable, i, 0); + __csid_configure_rx_vc(csid, 0); + + for (k =3D 0; k < CAMSS_INIT_BUF_COUNT; k++) + __csid_aup_update(csid, i); + + __csid_reg_update(csid, i); + + __csid_ctrl_rdi(csid, enable, i); + } + } +} + +static int csid_configure_testgen_pattern(struct csid_device *csid, s32 va= l) +{ + return 0; +} + +static void csid_subdev_reg_update(struct csid_device *csid, int port_id, + bool clear) +{ + if (clear) + __csid_aup_rup_clear(csid, port_id); + else + __csid_aup_update(csid, port_id); +} + +/** + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr(int irq, void *dev) +{ + struct csid_device *csid =3D dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val =3D readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + + reset_done =3D val & INFO_RST_DONE; + + buf_done_val =3D readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + val =3D readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & INFO_RUP_DONE) + csid_subdev_reg_update(csid, i, true); + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) + camss_buf_done(csid->camss, csid->id, i); + } + } + + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/** + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + val =3D INFO_RST_DONE | BUF_DONE_IRQ_STATUS; + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + writel(val, csid->base + CSID_TOP_IRQ_MASK); + + val =3D 0; + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + /* + * Only need to clear buf done IRQ status here, + * RUP done IRQ status will be cleared once isr + * strobe generated by CSID_RST_CMD + */ + val |=3D BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); + } + } + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); + + /* Clear all IRQ status with CLEAR bits set */ + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + val =3D RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val =3D SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time =3D wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -EIO; + } + + return 0; +} + +static void csid_subdev_init(struct csid_device *csid) +{ + csid->testgen.nmodes =3D CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_gen4 =3D { + .configure_stream =3D csid_configure_stream, + .configure_testgen_pattern =3D csid_configure_testgen_pattern, + .hw_version =3D csid_hw_version, + .isr =3D csid_isr, + .reset =3D csid_reset, + .src_pad_code =3D csid_src_pad_code, + .subdev_init =3D csid_subdev_init, + .reg_update =3D csid_subdev_reg_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media= /platform/qcom/camss/camss-csid.h index 5296b10f6bac..4f31ad303c4e 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -154,7 +154,13 @@ struct csid_device { void __iomem *base; u32 irq; char irq_name[30]; - u32 reg_update; + union { + u32 reg_update; + struct { + u32 rup_update; + u32 aup_update; + }; + }; struct camss_clock *clock; int nclocks; struct regulator_bulk_data *supplies; @@ -218,6 +224,7 @@ extern const struct csid_hw_ops csid_ops_340; extern const struct csid_hw_ops csid_ops_680; extern const struct csid_hw_ops csid_ops_gen2; extern const struct csid_hw_ops csid_ops_gen3; +extern const struct csid_hw_ops csid_ops_gen4; =20 /* * csid_is_lite - Check if CSID is CSID lite. diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 0a79484ea1fe..10146c04c6dd 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -85,6 +85,79 @@ static const struct camss_subdev_resources csiphy_res_ka= anapali[] =3D { }, }; =20 +static const struct camss_subdev_resources csid_res_kaanapali[] =3D { + /* CSID0 */ + { + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE0 */ + { + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite0" }, + .interrupt =3D { "csid_lite0" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite1" }, + .interrupt =3D { "csid_lite1" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "ahb", @@ -5665,9 +5738,11 @@ static const struct camss_resources kaanapali_resour= ces =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, + .csid_res =3D csid_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), + .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1 From nobody Fri Sep 25 12:06:09 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACF5848D899 for ; Tue, 15 Sep 2026 10:10:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14382741839sm14244091c88.6.2026.09.15.03.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:10:21 -0700 (PDT) From: Hangxiang Ma Date: Tue, 15 Sep 2026 03:10:02 -0700 Subject: [PATCH v16 07/11] media: qcom: camss: vfe: Add support for VFE Gen4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-kaanapali-camss-v16-7-c9f3f6f4180c@oss.qualcomm.com> References: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> In-Reply-To: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: w_vhbR0Nxvoa-kWMtieHdSfQpZytlltg X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfXyvYQbpIIqUd7 PtVXM6DF3QweJFCYJJVjXrtx0WVCky0pi1pHuF3OcIGS54Stk5jAddDWGTLlpGmuC13mh1bWdyB cP/2N1uiPeOKzyvXQ1FdsC3d1DxsjLA= X-Authority-Analysis: v=2.4 cv=dcUVTnXe c=1 sm=1 tr=0 ts=6aa9198f cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=1ZGTSUkntXfq-hYXLBIA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX6VJdN03oXP5/ a77LvjwzqTenprD03VIykH0FxHD0k2AFU1AWJQI4PBUALNM8tcwr7eCpZqOmmjiBzPDV9N/dR+U C4VPzAFRlPu742o12dJ5HwKhbCY8tmwtFVovIVu6tkTqVpZVKOZ13Sqs3KYz72mdCOMR+hCS+WQ SMIHliYatvQrHQri/QxufmUJ1lJnpwyFoTzzqK6nH94zyzdZK7unu8PdxTd7jcm6lNrccCKe7Wr Ak1JC0nqtHjAW0k99BsT0Sw7okkY1kR9OIkgB2sS5IbhIlzc+XtlvQGXfcvuDCc20gzX6fQN4s3 GsJZSdscS83RVGnlLEOcDxSIvXLu8gwnuPhl/8hDWA4Utau5u7O1Wo38zsehOmTTuXS79Pm+ult NB0gDcDoZDFeTHtoAWHiW3ud7MhW4Qw6OIDJkBZlBdyZP4o1P9tF+i/F6o0H23LmakOEAGLeS3H 2m5/PnyFNTi98+V6QLg== X-Proofpoint-GUID: w_vhbR0Nxvoa-kWMtieHdSfQpZytlltg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_03,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 suspectscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150146 Add support for the VFE (Video Front End) Gen4 found on Kaanapali SoC. In the Kaanapali camera subsystem, the front-end blocks are referred to as TFEs (Thin Front Ends). This driver continues to use the VFE naming in some places to preserve consistency with the existing code and avoid unnecessary renaming. Support is currently limited to three output lines, matching the constraints of the CAMSS framework. Kaanapali requires REG_UPDATE and AUP_UPDATE to be issued only after all CSID configuration has completed. In addition, the number of AUP_UPDATE requests must match the number of buffers queued to the write master while it is being enabled. Although real-time TFE traffic is routed through RT_CAMNOC, both camnoc_rt_axi and camnoc_nrt_axi clocks must be enabled. This ensures that the PDX_NOC, which sits downstream of both RT and NRT NOCs, exits reset in a fully idle state. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-vfe-gen4.c | 197 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-vfe.c | 9 +- drivers/media/platform/qcom/camss/camss-vfe.h | 2 + drivers/media/platform/qcom/camss/camss.c | 153 ++++++++++++++++ 5 files changed, 360 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index cebfd947f28e..b114ca37e36e 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -28,6 +28,7 @@ qcom-camss-objs +=3D \ camss-vfe-680.o \ camss-vfe-gen1.o \ camss-vfe-gen3.o \ + camss-vfe-gen4.o \ camss-vfe-vbif.o \ camss-video.o =20 diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c b/drivers/m= edia/platform/qcom/camss/camss-vfe-gen4.c new file mode 100644 index 000000000000..d73d70898710 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-vfe-gen4.c + * + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen4 + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include + +#include "camss.h" +#include "camss-vfe.h" + +/* VFE-gen4 Bus Register Base Addresses */ +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000) + +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) + +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128) + +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100) +#define WM_CFG_EN BIT(0) +#define WM_VIR_FRM_EN BIT(1) +#define WM_CFG_MODE BIT(16) +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100) +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100) +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50C + (n) * 0x100) +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100) +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100) + +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0= x100) +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * = 0x100) + +/* VFE lite has no such registers */ +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x10= 0) +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53C + (n) * 0x1= 00) + +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x10= 0) +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) = * 0x100) + +/* + * IFE write master client IDs + * + * VIDEO_FULL 0 + * VIDEO_DC4_Y 1 + * VIDEO_DC4_C 2 + * VIDEO_DC16_Y 3 + * VIDEO_DC16_C 4 + * DISPLAY_DS2_Y 5 + * DISPLAY_DS2_C 6 + * FD_Y 7 + * FD_C 8 + * PIXEL_RAW 9 + * STATS_AEC_BG 10 + * STATS_AEC_BHIST 11 + * STATS_TINTLESS_BG 12 + * STATS_AWB_BG 13 + * STATS_AWB_BFW 14 + * STATS_AF_BHIST 15 + * STATS_ALSC_BG 16 + * STATS_FLICKER_BAYERRS 17 + * STATS_TMC_BHIST 18 + * PDAF_0 19 + * PDAF_1 20 + * PDAF_2 21 + * PDAF_3 22 + * RDI0 23 + * RDI1 24 + * RDI2 25 + * RDI3 26 + * RDI4 27 + * + * IFE Lite write master client IDs + * + * RDI0 0 + * RDI1 1 + * RDI2 2 + * RDI3 3 + * GAMMA 4 + * STATES_BE 5 + */ +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) + +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *l= ine) +{ + struct v4l2_pix_format_mplane *pix =3D + &line->video_out.active_fmt.fmt.pix_mp; + + wm =3D RDI_WM(wm); + + /* no clock gating at bus input */ + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); + + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); + + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8, + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF), + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); + + /* no dropped frames, one irq per frame */ + if (!vfe_is_lite(vfe)) { + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); + } + + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); + + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); + + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) +{ + wm =3D RDI_WM(wm); + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, + struct vfe_line *line) +{ + wm =3D RDI_WM(wm); + writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); + + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr); +} + +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_i= d) +{ + int port_id =3D line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, false); +} + +static inline void vfe_reg_update_clear(struct vfe_device *vfe, + enum vfe_line_id line_id) +{ + int port_id =3D line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, true); +} + +static const struct camss_video_ops vfe_video_ops_gen4 =3D { + .queue_buffer =3D vfe_queue_buffer_v2, + .flush_buffers =3D vfe_flush_buffers, +}; + +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) +{ + vfe->video_ops =3D vfe_video_ops_gen4; +} + +static void vfe_global_reset(struct vfe_device *vfe) +{ + vfe_isr_reset_ack(vfe); +} + +static irqreturn_t vfe_isr(int irq, void *dev) +{ + /* nop */ + return IRQ_HANDLED; +} + +static int vfe_halt(struct vfe_device *vfe) +{ + /* rely on vfe_disable_output() to stop the VFE */ + return 0; +} + +const struct vfe_hw_ops vfe_ops_gen4 =3D { + .global_reset =3D vfe_global_reset, + .hw_version =3D vfe_hw_version, + .isr =3D vfe_isr, + .pm_domain_off =3D vfe_pm_domain_off, + .pm_domain_on =3D vfe_pm_domain_on, + .reg_update =3D vfe_reg_update, + .reg_update_clear =3D vfe_reg_update_clear, + .subdev_init =3D vfe_subdev_init, + .vfe_disable =3D vfe_disable, + .vfe_enable =3D vfe_enable_v2, + .vfe_halt =3D vfe_halt, + .vfe_wm_start =3D vfe_wm_start, + .vfe_wm_stop =3D vfe_wm_stop, + .vfe_buf_done =3D vfe_buf_done, + .vfe_wm_update =3D vfe_wm_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index 319d19158988..826ab85a44a1 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -353,6 +353,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, case CAMSS_8550: case CAMSS_8650: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: @@ -525,7 +526,8 @@ int vfe_enable_output_v2(struct vfe_line *line) =20 spin_lock_irqsave(&vfe->output_lock, flags); =20 - ops->reg_update_clear(vfe, line->id); + if (ops->reg_update_clear) + ops->reg_update_clear(vfe, line->id); =20 if (output->state > VFE_OUTPUT_RESERVED) { dev_err(vfe->camss->dev, @@ -552,7 +554,9 @@ int vfe_enable_output_v2(struct vfe_line *line) output->gen2.active_num++; ops->vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); - ops->reg_update(vfe, line->id); + + if (!vfe->res->reg_update_after_csid_config) + ops->reg_update(vfe, line->id); } =20 spin_unlock_irqrestore(&vfe->output_lock, flags); @@ -2013,6 +2017,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe) case CAMSS_8550: case CAMSS_8650: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: ret =3D 16; break; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/= platform/qcom/camss/camss-vfe.h index ae9dad353a37..c402ef170c81 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -133,6 +133,7 @@ struct vfe_isr_ops { =20 struct vfe_subdev_resources { bool is_lite; + bool reg_update_after_csid_config; u8 line_num; bool has_pd; char *pd_name; @@ -249,6 +250,7 @@ extern const struct vfe_hw_ops vfe_ops_340; extern const struct vfe_hw_ops vfe_ops_480; extern const struct vfe_hw_ops vfe_ops_680; extern const struct vfe_hw_ops vfe_ops_gen3; +extern const struct vfe_hw_ops vfe_ops_gen4; =20 int vfe_get(struct vfe_device *vfe); void vfe_put(struct vfe_device *vfe); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 10146c04c6dd..68ddfe911bac 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -158,6 +158,157 @@ static const struct camss_subdev_resources csid_res_k= aanapali[] =3D { } }; =20 +/* In Kaanapali, CAMNOC requires all CPAS_TFEX clocks + * to operate on any TFE Full. + */ +static const struct camss_subdev_resources vfe_res_kaanapali[] =3D { + /* VFE0 - TFE Full */ + { + .clock =3D { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb", + "vfe0_fast_ahb", "vfe0", + "cpas_vfe0", "cpas_vfe1", "cpas_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife0", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE1 - TFE Full */ + { + .clock =3D { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb", + "vfe1_fast_ahb", "vfe1", + "cpas_vfe0", "cpas_vfe1", "cpas_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife1", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE2 - TFE Full */ + { + .clock =3D { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb", + "vfe2_fast_ahb", "vfe2", + "cpas_vfe0", "cpas_vfe1", "cpas_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe2" }, + .interrupt =3D { "vfe2" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife2", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE3 - IFE Lite */ + { + .clock =3D { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb", + "vfe_lite_ahb", "vfe_lite", + "cpas_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite0" }, + .interrupt =3D { "vfe_lite0" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .reg_update_after_csid_config =3D true, + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE4 - IFE Lite */ + { + .clock =3D { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb", + "vfe_lite_ahb", "vfe_lite", + "cpas_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite1" }, + .interrupt =3D { "vfe_lite1" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .reg_update_after_csid_config =3D true, + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "ahb", @@ -5739,10 +5890,12 @@ static const struct camss_resources kaanapali_resou= rces =3D { .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, .csid_res =3D csid_res_kaanapali, + .vfe_res =3D vfe_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), + .vfe_num =3D ARRAY_SIZE(vfe_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1 From nobody Fri Sep 25 12:06:09 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50E6A41D22B for ; Tue, 15 Sep 2026 10:10:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14382741839sm14244091c88.6.2026.09.15.03.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:10:23 -0700 (PDT) From: Hangxiang Ma Date: Tue, 15 Sep 2026 03:10:03 -0700 Subject: [PATCH v16 08/11] media: qcom: camss: tpg: Add support for v2.4.0 TPG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-kaanapali-camss-v16-8-c9f3f6f4180c@oss.qualcomm.com> References: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> In-Reply-To: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: -5EP9BoM3o7tDvajQ1GYAIDJsabR_-b6 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX2ij1IxC++k7g zn7n4M2LkVpS9FboXwKTL5V8RcP0ADheT1o0TU6hYChH4IyGlPXgJjbpsfeYB9V7ZkXrRujnzNm ys70Z141zDPr+KPPPn/MOIUsvYoQOO4= X-Authority-Analysis: v=2.4 cv=dcUVTnXe c=1 sm=1 tr=0 ts=6aa91990 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=zvpRHedlNIWp6186mRgA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfXxSyxa1vqnFKj 5pnIM/YNxorqZJxGHkIls3qLWgVXhSaSSmB8vRru6Wi2vEA5LKKWk71c6bvAvDhl+ggOH9XtM1b HGpi8AfP4zLDCdmdI2uGnbLBMn3Mbi11BjFDxthbdPxo9Rz/tezcT8Ev1k3ejykZS+BUv7m6BZE UNwgN/vyJ+PSpnJhJHqVnh3cPUbsUuea1MfDDZud46jGmrhf2wKOtSYUSklegHf0vqsFM5YxDCs pzDu04Mkzm2XjqiicW/6TkOj/TqkxiXZRQkrh6MmhXqUtgEiwbIeGHuUYN1j9GmUsaOWjaJiASI r9VkRlEIarw3RyOcbVNRk3DFLEt3NCDN5aZp5xO4F2CELbELcsMM6A0tUSR5/WYGU3Z06rqiwxP yc0oMNg+i7O1Mz10QEDSXDz/sFFjCTLKcAP3vD5ES2kDNFHEeqjBr6JrGKW/QfBewHDHYN/ycUn jhepvsyurixT2rkZUkQ== X-Proofpoint-GUID: -5EP9BoM3o7tDvajQ1GYAIDJsabR_-b6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_03,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 suspectscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150146 Add support for the TPG found on Kaanapali. This TPG uses hardware version 2.4.0, which drives test-enable and reset through a separate TPG_CTRL_CMD register instead of TPG_CTRL, and routes its output into the CSID gen4 RX via the CSI2 TPG mux. Signed-off-by: Hangxiang Ma --- .../media/platform/qcom/camss/camss-csid-gen4.c | 15 ++++++++++-- drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 27 +++++++++++++++++-= ---- drivers/media/platform/qcom/camss/camss.c | 2 ++ 3 files changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen4.c b/drivers/= media/platform/qcom/camss/camss-csid-gen4.c index 4ff2f41f70f7..bc52e4a1135c 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen4.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen4.c @@ -63,6 +63,8 @@ #define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_TPG_MUX_EN BIT(27) +#define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28) #define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSID_CSI2_RX_CFG1 0x884 #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) @@ -140,12 +142,21 @@ static void __csid_reg_update(struct csid_device *csi= d, int port_id) static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config *phy) { + struct camss *camss =3D csid->camss; int val; =20 val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; - val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) - << CSI2_RX_CFG0_PHY_NUM_SEL; + + if (camss->tpg && csid->tpg_linked && + camss->tpg[phy->csiphy_id].testgen.mode !=3D TPG_PAYLOAD_MODE_DISABLE= D) { + val |=3D FIELD_PREP(CSI2_RX_CFG0_TPG_MUX_SEL, phy->csiphy_id + 1); + val |=3D CSI2_RX_CFG0_TPG_MUX_EN; + } else { + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + } + writel(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/m= edia/platform/qcom/camss/camss-tpg-gen1.c index d29de5f93c18..770a9e5d5ba5 100644 --- a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c +++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c @@ -22,6 +22,7 @@ =20 #define TPG_HW_VER_2_0_0 TPG_HW_VER(2, 0, 0) #define TPG_HW_VER_2_1_0 TPG_HW_VER(2, 1, 0) +#define TPG_HW_VER_2_4_0 TPG_HW_VER(2, 4, 0) =20 #define TPG_HW_STATUS 0x4 =20 @@ -33,7 +34,9 @@ # define TPG_CTRL_OVERLAP_SHDR_EN BIT(10) # define TPG_CTRL_NUM_ACTIVE_VC GENMASK(31, 30) =20 -#define TPG_CLEAR 0x1F4 +#define TPG_CTRL_CMD 0x1F4 +# define TPG_CTRL_CMD_TEST_EN BIT(4) +# define TPG_CTRL_CMD_HW_RESET BIT(0) =20 /* TPG VC-based registers */ #define TPG_VC_n_GAIN_CFG(n) (0x60 + (n) * 0x60) @@ -164,18 +167,30 @@ static int tpg_stream_on(struct tpg_device *tpg) } =20 /* Global TPG control */ - val =3D FIELD_PREP(TPG_CTRL_TEST_EN, 1) | - FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) | + val =3D FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) | FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, last_vc); - writel(val, tpg->base + TPG_CTRL); + + if (tpg->hw_version >=3D TPG_HW_VER_2_4_0) { + writel(val, tpg->base + TPG_CTRL); + writel(TPG_CTRL_CMD_TEST_EN, tpg->base + TPG_CTRL_CMD); + } else { + val |=3D FIELD_PREP(TPG_CTRL_TEST_EN, 1); + writel(val, tpg->base + TPG_CTRL); + } =20 return 0; } =20 static int tpg_reset(struct tpg_device *tpg) { - writel(0, tpg->base + TPG_CTRL); - writel(1, tpg->base + TPG_CLEAR); + /* + * On TPG older than v2.4.0 test-enable lives in TPG_CTRL, so clear it + * first; v2.4.0+ drives both test-enable and reset through TPG_CTRL_CMD. + */ + if (tpg->hw_version < TPG_HW_VER_2_4_0) + writel(0, tpg->base + TPG_CTRL); + + writel(TPG_CTRL_CMD_HW_RESET, tpg->base + TPG_CTRL_CMD); =20 return 0; } diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 68ddfe911bac..e19f9b54454b 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -5889,11 +5889,13 @@ static const struct camss_resources kaanapali_resou= rces =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, + .tpg_res =3D tpg_res_x1e80100, .csid_res =3D csid_res_kaanapali, .vfe_res =3D vfe_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), + .tpg_num =3D ARRAY_SIZE(tpg_res_x1e80100), .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), .vfe_num =3D ARRAY_SIZE(vfe_res_kaanapali), }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14382741839sm14244091c88.6.2026.09.15.03.10.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:10:24 -0700 (PDT) From: Hangxiang Ma Date: Tue, 15 Sep 2026 03:10:04 -0700 Subject: [PATCH v16 09/11] arm64: dts: qcom: kaanapali: Add CAMSS block definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-kaanapali-camss-v16-9-c9f3f6f4180c@oss.qualcomm.com> References: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> In-Reply-To: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfXyc4DA2UlXwY4 RmPnxzXdgW7MPM9/0z0W9y6Omr4oY87ozUN+MlWU/bxSBngttjf2mqZXewlUnu48OweYkVpJys3 i6o1z3CYHXJCqXM5MFRtAmVZSrRiboU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX+2MWkNLLPHKw ehncH1MOe/Q2W/9MAriDZv4szRIXOHnaIFSgP/mfryFBwDLkNFLiIBL3DQQffpLVySeKZGotUWZ GHEzSn/BxWDcuf7sZ2TB+ifL1PpPzcLH0ORLb/qY+IXus8x+519f6MSXLJWxX7mmNQK7e+DnpQZ qoZTiRt1kzaA2K95qZBr1NX082gV5jKfsKvmDy1wYz/3JoCxvolSPpRi/cUSXAHk5K+prxjFZTB YTl29RJD74bOCYhCQizAZ3Lgv43UYGdmN398oMR+0j4cipdJLdKA+p5UGf+B6uK+KTqiG/iyB1v SSnxa3enjbxB6qYbF8qmjFue2yJom/ZZsqTyYhiDuLDnZJxylVNoSVI2CEvj5tsObEx62MTdz0+ Z6vfxcN2Slx8VYgoTNsI4/ICAOoFXCgnjeCVK6LDrcogmiR+MHpV9O4etSBfoC8onTjl9SmUdmB CW7Lop9IomZd+FBIwKw== X-Authority-Analysis: v=2.4 cv=HsDjiETS c=1 sm=1 tr=0 ts=6aa91992 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=K4jxk-CqiRrnENM1qOEA:9 a=kZHQiraHdqabkTWc:21 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: j7P_XVRdT7Lv4-pWlKYq25E-v6aUD7g2 X-Proofpoint-ORIG-GUID: j7P_XVRdT7Lv4-pWlKYq25E-v6aUD7g2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_03,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150146 Describe the CAMSS and CSI PHY blocks on Kaanapali so that camera pipelines can be enabled by board device trees. The camera subsystem contains: - 6 x CSIPHY (CSI Physical Layer) - 3 x TPG (Test Pattern Generator) - 3 x CSID (CSI Decoder) - 2 x CSID Lite - 3 x VFE (Video Front End), 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite Signed-off-by: Hangxiang Ma --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 372 ++++++++++++++++++++++++++++= ++++ 1 file changed, 372 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 131fd2a16c54..84b93914ad53 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -3314,6 +3315,355 @@ usb_dp_qmpphy_dp_in: endpoint { }; }; =20 + camss: isp@9253000 { + compatible =3D "qcom,kaanapali-camss"; + + reg =3D <0x0 0x09253000 0x0 0x5e80>, + <0x0 0x09263000 0x0 0x5e80>, + <0x0 0x09273000 0x0 0x5e80>, + <0x0 0x092d3000 0x0 0x3880>, + <0x0 0x092e7000 0x0 0x3880>, + <0x0 0x09523000 0x0 0x2000>, + <0x0 0x09525000 0x0 0x2000>, + <0x0 0x09527000 0x0 0x2000>, + <0x0 0x09529000 0x0 0x2000>, + <0x0 0x0952b000 0x0 0x2000>, + <0x0 0x0952d000 0x0 0x2000>, + <0x0 0x093fd000 0x0 0x400>, + <0x0 0x093fe000 0x0 0x400>, + <0x0 0x093ff000 0x0 0x400>, + <0x0 0x09151000 0x0 0x20000>, + <0x0 0x09171000 0x0 0x20000>, + <0x0 0x09191000 0x0 0x20000>, + <0x0 0x092dc000 0x0 0x1300>, + <0x0 0x092f0000 0x0 0x1300>; + + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks =3D <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_mnoc"; + + iommus =3D <&apps_smmu 0x1c00 0x00>; + + power-domains =3D <&camcc CAM_CC_TFE_0_GDSC>, + <&camcc CAM_CC_TFE_1_GDSC>, + <&camcc CAM_CC_TFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names =3D "ife0", + "ife1", + "ife2", + "top"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + + port@3 { + reg =3D <3>; + }; + + port@4 { + reg =3D <4>; + }; + + port@5 { + reg =3D <5>; + }; + }; + }; + + csiphy0: phy@9523000 { + compatible =3D "qcom,kaanapali-csi2-phy"; + reg =3D <0x0 0x09523000 0x0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names =3D "core", + "timer", + "ahb"; + + interrupts =3D ; + + operating-points-v2 =3D <&csiphy_mxc_opp_table>; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names =3D "top", + "mmcx", + "mx"; + + status =3D "disabled"; + }; + + csiphy1: phy@9525000 { + compatible =3D "qcom,kaanapali-csi2-phy"; + reg =3D <0x0 0x09525000 0x0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names =3D "core", + "timer", + "ahb"; + + interrupts =3D ; + + operating-points-v2 =3D <&csiphy_mxc_opp_table>; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names =3D "top", + "mmcx", + "mx"; + + status =3D "disabled"; + }; + + csiphy2: phy@9527000 { + compatible =3D "qcom,kaanapali-csi2-phy"; + reg =3D <0x0 0x09527000 0x0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names =3D "core", + "timer", + "ahb"; + + interrupts =3D ; + + operating-points-v2 =3D <&csiphy_mxc_opp_table>; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names =3D "top", + "mmcx", + "mx"; + + status =3D "disabled"; + }; + + csiphy3: phy@9529000 { + compatible =3D "qcom,kaanapali-csi2-phy"; + reg =3D <0x0 0x09529000 0x0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names =3D "core", + "timer", + "ahb"; + + interrupts =3D ; + + operating-points-v2 =3D <&csiphy_mxc_opp_table>; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names =3D "top", + "mmcx", + "mx"; + + status =3D "disabled"; + }; + + csiphy4: phy@952b000 { + compatible =3D "qcom,kaanapali-csi2-phy"; + reg =3D <0x0 0x0952b000 0x0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names =3D "core", + "timer", + "ahb"; + + interrupts =3D ; + + operating-points-v2 =3D <&csiphy_mxc_opp_table>; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names =3D "top", + "mmcx", + "mx"; + + status =3D "disabled"; + }; + + csiphy5: phy@952d000 { + compatible =3D "qcom,kaanapali-csi2-phy"; + reg =3D <0x0 0x0952d000 0x0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names =3D "core", + "timer", + "ahb"; + + interrupts =3D ; + + operating-points-v2 =3D <&csiphy_mxc_opp_table>; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names =3D "top", + "mmcx", + "mx"; + + status =3D "disabled"; + }; + camcc: clock-controller@956d000 { compatible =3D "qcom,kaanapali-camcc"; reg =3D <0x0 0x0956d000 0x0 0x80000>; @@ -6253,6 +6603,28 @@ pdp_tx: scp-sram-section@100 { }; }; =20 + csiphy_mxc_opp_table: opp-table-mxc { + compatible =3D "operating-points-v2"; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14382741839sm14244091c88.6.2026.09.15.03.10.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:10:25 -0700 (PDT) From: Hangxiang Ma Date: Tue, 15 Sep 2026 03:10:05 -0700 Subject: [PATCH v16 10/11] arm64: dts: qcom: kaanapali: Add CCI controller nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-kaanapali-camss-v16-10-c9f3f6f4180c@oss.qualcomm.com> References: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> In-Reply-To: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: O7J0H1TQC7WEuyFpCmT_SP9SGuHMf4ZR X-Proofpoint-GUID: O7J0H1TQC7WEuyFpCmT_SP9SGuHMf4ZR X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfXzYc03BubOJJn P0LorLV58ZrKOXMmGU6cy+aYnMlf2H5oJf4gW/YUBOUCfO2OsqABQrMRmSw4ppBqaig8ibZE3op qWEUP4WlmEC/vWUXBv+qswS5ESB5uEM= X-Authority-Analysis: v=2.4 cv=As97T+9P c=1 sm=1 tr=0 ts=6aa91993 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=6uyy3mKblwRlHw_pSasA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX6zp5ZYtr7AUE 6ccGxp7eC6ZmQO0f+eLsKxgsjkrkdRyf54rtYvCgJKe0zF6q0yFrdLPgL36zwAehEKQUACESigZ P0VJ1vZpMrfxQoHag2HtRUumC4Df/5fth/sYohiTBpDKnBWqhFNFKricJ4zcGAvwG2+/LblUw7l SqlF6hsnkLsXtRB2K++ZFMYe3Wf2iDr18Rxhne0fol76fBSkZFSvH26sD9i+N/IA6YhoLaAaxel eLC5ukcVZR89PZ6rwVecwp/sPtehOek8Di21KhepqZRKxpoYTf3fhnysBlpdYF/v1H5E2aDaEWn sj7dPCTSEl3YGJA/dwHW///OD5eBNLhfwjdVXfPu8OZg4fZW0eSznghmy/r5O5aozkFbFn+T+24 1urZU/wTaQjAaYSxSH6lOKZFNQ8FPasLM58K+mHME8nfPgAoZxtowUidXuQC6AYJjR0MreuroS4 wO3kYXZBljUjmmDVS3w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_03,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150146 Add the three Camera Control Interface (CCI) controllers present on the Kaanapali SoC. Each controller provides two I2C hosts used for camera sensor control, so define the controller nodes and their pinctrl states. The first bus has two CCI bus master pinouts: cci_i2c_sda0 =3D gpio109 cci_i2c_scl0 =3D gpio110 cci_i2c_sda1 =3D gpio111 cci_i2c_scl1 =3D gpio112 The second bus has two CCI bus master pinouts: cci_i2c_sda3 =3D gpio113 cci_i2c_scl3 =3D gpio114 cci_i2c_sda4 =3D gpio107 cci_i2c_scl4 =3D gpio160 The third bus has two CCI bus master pinouts: cci_i2c_sda5 =3D gpio108 cci_i2c_scl5 =3D gpio149 cci_i2c_sda6 =3D gpio115 cci_i2c_scl6 =3D gpio116 Reviewed-by: Vladimir Zapolskiy Signed-off-by: Hangxiang Ma --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 303 ++++++++++++++++++++++++++++= ++++ 1 file changed, 303 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 84b93914ad53..02f8dab30b91 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3514,6 +3514,117 @@ port@5 { }; }; =20 + cci0: cci@941b000 { + compatible =3D "qcom,kaanapali-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0941b000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci0_i2c0_default &cci0_i2c1_default>; + pinctrl-1 =3D <&cci0_i2c0_sleep &cci0_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@941c000 { + compatible =3D "qcom,kaanapali-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0941c000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci1_i2c0_default &cci1_i2c1_default>; + pinctrl-1 =3D <&cci1_i2c0_sleep &cci1_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@941d000 { + compatible =3D "qcom,kaanapali-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0941d000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names =3D "ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci2_i2c0_default &cci2_i2c1_default>; + pinctrl-1 =3D <&cci2_i2c0_sleep &cci2_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + csiphy0: phy@9523000 { compatible =3D "qcom,kaanapali-csi2-phy"; reg =3D <0x0 0x09523000 0x0 0x2000>; @@ -4224,6 +4335,198 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + cci0_i2c0_default: cci0-i2c0-default-state { + scl-pins { + pins =3D "gpio110"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sda-pins { + pins =3D "gpio109"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci0_i2c0_sleep: cci0-i2c0-sleep-state { + scl-pins { + pins =3D "gpio110"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sda-pins { + pins =3D "gpio109"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci0_i2c1_default: cci0-i2c1-default-state { + scl-pins { + pins =3D "gpio112"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sda-pins { + pins =3D "gpio111"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-state { + scl-pins { + pins =3D "gpio112"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sda-pins { + pins =3D "gpio111"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_i2c0_default: cci1-i2c0-default-state { + scl-pins { + pins =3D "gpio114"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sda-pins { + pins =3D "gpio113"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci1_i2c0_sleep: cci1-i2c0-sleep-state { + scl-pins { + pins =3D "gpio114"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sda-pins { + pins =3D "gpio113"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_i2c1_default: cci1-i2c1-default-state { + scl-pins { + pins =3D "gpio160"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sda-pins { + pins =3D "gpio107"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-state { + scl-pins { + pins =3D "gpio160"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sda-pins { + pins =3D "gpio107"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_i2c0_default: cci2-i2c0-default-state { + scl-pins { + pins =3D "gpio149"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sda-pins { + pins =3D "gpio108"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci2_i2c0_sleep: cci2-i2c0-sleep-state { + scl-pins { + pins =3D "gpio149"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14382741839sm14244091c88.6.2026.09.15.03.10.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:10:26 -0700 (PDT) From: Hangxiang Ma Date: Tue, 15 Sep 2026 03:10:06 -0700 Subject: [PATCH v16 11/11] arm64: dts: qcom: kaanapali: Add camera MCLK pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-kaanapali-camss-v16-11-c9f3f6f4180c@oss.qualcomm.com> References: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> In-Reply-To: <20260915-kaanapali-camss-v16-0-c9f3f6f4180c@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma , Konrad Dybcio X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: 9xMMfD8Q3n6zbNCAh9NbuhlOIQaLm_bM X-Authority-Analysis: v=2.4 cv=cehHPXDM c=1 sm=1 tr=0 ts=6aa91994 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=4Dwyees-64n8yO_2jeYA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: 9xMMfD8Q3n6zbNCAh9NbuhlOIQaLm_bM X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX/acUEjX55jl5 sqMpvfwJsa3HN3MQZ8f4JoBPcVln8Cy9n5ma1mC4E25JToe94fVRVr23YavuQVKvtSosjrl7wnI E+6upNfgHEqWx1mwuE2FUJKfbr13e/k= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDE0NiBTYWx0ZWRfX2u4V5GiWWR9I pNU7xxEcbLp85tPQx4oO0yQNs9sG7akPhUdDXTQwJJVxLo3+jpHv9BY1FFidWXE0NsXYe+Oa/e8 t+lVET7kcjjPpcHsFURO2kzfRR64QQssNDPrUfXzFvvXQMdb8PEN+67Y2BGwHXoQtdpH0SUoOz7 f2GNJa5aGmDVrGC7Zv+bJGgICaJapq68zPbpUSZITfhU8B2vAnmaBUAZwpqUj/BPv4x3xfL2NFV dYUKKgEb7dXUUsrK4U+z6327xZGD4T16igRDPv8otRFvNUPe1Th6yGFeVUJ25qFO3p/SLuFiyUS 5eRLErOTY9wLeEFow3SY9+BnqE37xQE/2t94H6J4zZf8tvKrzv6K6ybpNYC5RFA+1dm6jAbvrbl 83Mpij/rJALJVm2/A6NnKRb+9YeISuf3p9+c/e/2mOZzLKr/ZzQxZr/aon8hkScALZY62u2u2yO 9ycWZvNUFFJ35Mquwgg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_03,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150146 Add TLMM pinctrl states for the camera master clock GPIOs on Kaanapali so camera sensor nodes can select the proper MCLK pin functions when enabled. Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Hangxiang Ma --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 56 +++++++++++++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 02f8dab30b91..44fb673185cd 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -4335,6 +4335,62 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + cam_mclk0_default: cam-mclk0-default-state { + pins =3D "gpio89"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_mclk1_default: cam-mclk1-default-state { + pins =3D "gpio90"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_mclk2_default: cam-mclk2-default-state { + pins =3D "gpio91"; + function =3D "cam_asc_mclk2"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_mclk3_default: cam_mclk3-default-state { + pins =3D "gpio92"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_mclk4_default: cam_mclk4-default-state { + pins =3D "gpio93"; + function =3D "cam_asc_mclk4"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_mclk5_default: cam_mclk5-default-state { + pins =3D "gpio94"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_mclk6_default: cam_mclk6-default-state { + pins =3D "gpio95"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam_mclk7_default: cam_mclk7-default-state { + pins =3D "gpio96"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + cci0_i2c0_default: cci0-i2c0-default-state { scl-pins { pins =3D "gpio110"; --=20 2.34.1