From nobody Fri Sep 25 07:23:40 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EE4B4AA41F; Tue, 15 Sep 2026 15:32:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789486340; cv=none; b=OG/6fuBWlf0AeVr/7Mcp4YEwYE4ctI1GX2YlEDPdG5eylekNuvGOvxni9PeqbvoBxFePTZf1MClwDORomAaBORfc3i5NH64Zp7jCVOl0yh6AkzIMoyu9cGE1QDKJlVIsDwSUak6NXYaoW7WORkkUxb8EryPhiA7yJ0JY0PAs4iA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789486340; c=relaxed/simple; bh=lovxw8H+zQOBVogPQi/dk3jsKeTgYnEiAzmlGOktMoc=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=dRhvG1SheNgXOQfhBNVTSFAB3IWseo3e/DbtxHe18oMj9xCGVopZ8fq0sNT2mui9xxh/hjiezU4byiVqZpCzFUmxpfry+KMidSmGfnkHNOV6GFEOmESe8enibeNl5Hmqi/vTFGeh59RLpYV4DIxh/hMZByrv0fDr5vyl4PMxrpE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=W53K8ELK; arc=none smtp.client-ip=210.118.77.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="W53K8ELK" Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20260915153215euoutp01f6a41b1c13a34f9a2128aa823aa5ebb6~ViFdSE2CA0097300973euoutp01c; Tue, 15 Sep 2026 15:32:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20260915153215euoutp01f6a41b1c13a34f9a2128aa823aa5ebb6~ViFdSE2CA0097300973euoutp01c DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1789486335; bh=krjhFSRUjjcodVOjvmoECQPfmzBFrbf2f9ZT/pSJOz8=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=W53K8ELKFpEAxnCP1RILam1PxVQ2gEEA+7eKnxtYbc7sX9T5MUJkJTSO+un9vBInQ zpOKLHFKU/nfy7ckAnG0F/bdt3z6LoS+0mIOY1185dkqX2l+0P1qhcL1Jawf3fVeBV 9MNEP2PKXh2SjuGmIsaZdfYv/uaWF/6UQ7z+NqO8= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20260915153214eucas1p2b548f3236ef98fb0cbf320e397420125~ViFctveW01216312163eucas1p2Q; Tue, 15 Sep 2026 15:32:14 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153213eusmtip1506e9aac16998b42934c3838840ebe79~ViFbDT1fr0419704197eusmtip1z; Tue, 15 Sep 2026 15:32:13 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:09 +0200 Subject: [PATCH v4 01/20] dt-bindings: phy: Add starfive,jh7110-inno-hdmi-phy Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-1-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153214eucas1p2b548f3236ef98fb0cbf320e397420125 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153214eucas1p2b548f3236ef98fb0cbf320e397420125 X-EPHeader: CA X-CMS-RootMailID: 20260915153214eucas1p2b548f3236ef98fb0cbf320e397420125 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> Add the dt-binding for the StarFive JH7110 Innosilicon HDMI PHY. This device is a child of the starfive,jh7110-hdmi-subsystem node. It functions as both a PHY provider for the controller and as a clock provider for the variable pixel clock (hdmi_pclk), which it generates from its refoclk. Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- .../phy/starfive,jh7110-inno-hdmi-phy.yaml | 49 ++++++++++++++++++= ++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdm= i-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdm= i-phy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..f838fcc238ec7db0a8e794234bd= ceec36cb6d9e7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.y= aml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-inno-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Innosilicon INNO HDMI PHY + +maintainers: + - Michal Wilczynski + +description: + The PHY portion of the StarFive JH7110 INNO HDMI IP. + +properties: + compatible: + const: starfive,jh7110-inno-hdmi-phy + + clocks: + maxItems: 1 + description: Reference oscillator. + + '#clock-cells': + const: 0 + + '#phy-cells': + const: 0 + +required: + - compatible + - clocks + - '#clock-cells' + - '#phy-cells' + +additionalProperties: false + +examples: + # Shown as a child of the HDMI subsystem node; see + # Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.y= aml + # for the full node. + - | + phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + #clock-cells =3D <0>; + clocks =3D <&xin24m>; + #phy-cells =3D <0>; + }; + +... --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F9864A482F; Tue, 15 Sep 2026 15:32:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789486350; cv=none; b=pfccqlUBIgJhU04n59rWRorYgqYtBKs2iRGMn/Gj8nHB+elePNhcBigoa0U0nVcnKdcqeZRlyW9gRUnMbTsQQc9LLUnlZrMZDyKAnjpiXK+G/HvJ/F2/jMqTwTQ2bcy+6ER74m3vVJ4FBhaDZNt4rjyhtXmYradjL2eLt5p7e6w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 15 Sep 2026 15:32:14 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:10 +0200 Subject: [PATCH v4 02/20] dt-bindings: display: bridge: Add starfive,jh7110-inno-hdmi-controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-2-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153216eucas1p2388b49e6b4c064ea49639d21f987e05e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153216eucas1p2388b49e6b4c064ea49639d21f987e05e X-EPHeader: CA X-CMS-RootMailID: 20260915153216eucas1p2388b49e6b4c064ea49639d21f987e05e References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> Add the dt-binding for the StarFive JH7110 Innosilicon HDMI controller (DRM bridge). This device is the second child of the starfive,jh7110-hdmi-subsystem node. It consumes its register access, audio master and audio bit clocks (pclk, mclk, bclk) from voutcrg, and both the pixel clock (pixel) and the PHY from its hdmi_phy sibling. Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- .../starfive,jh7110-inno-hdmi-controller.yaml | 121 +++++++++++++++++= ++++ 1 file changed, 121 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/starfive,jh71= 10-inno-hdmi-controller.yaml b/Documentation/devicetree/bindings/display/br= idge/starfive,jh7110-inno-hdmi-controller.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ea489a7722d0279b3ed67bc2576= ec144e31bd05d --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno= -hdmi-controller.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/starfive,jh7110-inno-hdm= i-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Innosilicon HDMI Controller + +maintainers: + - Michal Wilczynski + +description: + The controller portion of the StarFive JH7110 INNO HDMI IP. + +properties: + compatible: + const: starfive,jh7110-inno-hdmi-controller + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The HDMI controller main clock + - description: Audio master clock + - description: Audio bit clock, from the I2S transmitter + - description: The pixel clock, generated by the PHY + + clock-names: + items: + - const: pclk + - const: mclk + - const: bclk + - const: pixel + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + starfive,vout-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the dom_vout_syscon system controller, which holds the mux + selecting the DC8200 output that drives the HDMI transmitter. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Input from the DC8200. The remote port number selects the DC8200 + panel and the remote endpoint number the interface on that panel, + 0 for DPI and 1 for DP. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output to the HDMI connector. + + required: + - port@0 + - port@1 + +required: + - compatible + - interrupts + - clocks + - clock-names + - resets + - phys + - starfive,vout-syscon + - ports + +additionalProperties: false + +examples: + # Shown as a child of the HDMI subsystem node; see + # Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.y= aml + # for the full node. + - | + #include + #include + + controller { + compatible =3D "starfive,jh7110-inno-hdmi-controller"; + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "pclk", "mclk", "bclk", "pixel"; + interrupts =3D <99>; + phys =3D <&hdmi_phy>; + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + starfive,vout-syscon =3D <&vout_syscon>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + endpoint { + remote-endpoint =3D <&dpu_out_dpi0>; + }; + }; + + port@1 { + reg =3D <1>; + + endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + }; + }; + }; + +... --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B8502BD00C; Tue, 15 Sep 2026 15:32:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789486353; cv=none; b=FGleX0N/qXN+5D/C3G9KnavmngpaBcfBEqS7LETc9tbLCgWT2GoJCNLOf417xJhDHtJg69+bX4xuEYB2guun34g/nMwZJ46ostHx2gUy9c95HqLOUXEc80WMgGdW13vPPgCFZmpVUrRfUgXf84Km+rlknRNUJCR1nAZSbK4MeZM= ARC-Message-Signature: i=1; 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Tue, 15 Sep 2026 15:32:16 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:11 +0200 Subject: [PATCH v4 03/20] dt-bindings: mfd: Add starfive,jh7110-hdmi-subsystem Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-3-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153218eucas1p278c4870936afe1aaa52438660418f8c8 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153218eucas1p278c4870936afe1aaa52438660418f8c8 X-EPHeader: CA X-CMS-RootMailID: 20260915153218eucas1p278c4870936afe1aaa52438660418f8c8 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> Add the dt-binding for the StarFive JH7110 HDMI subsystem. The JH7110 HDMI IP is a monolithic block containing both the digital controller and analog PHY in a single register space. This binding defines the parent device, which holds the shared register map and populates its two children: the PHY and the controller. This is necessary to resolve a circular clock dependency between the HDMI block and the VOUT clock generator. Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- .../mfd/starfive,jh7110-hdmi-subsystem.yaml | 95 ++++++++++++++++++= ++++ 1 file changed, 95 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-sub= system.yaml b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-su= bsystem.yaml new file mode 100644 index 0000000000000000000000000000000000000000..18034d8273b860b71d386cfc63a= 125f21b20a6b1 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.= yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/starfive,jh7110-hdmi-subsystem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 HDMI subsystem + +maintainers: + - Michal Wilczynski + +description: + The StarFive JH7110 HDMI block is a monolithic IP containing both + the digital controller logic and the analog PHY logic in a single + register space. It sits inside the video output subsystem, which owns + the NoC bus clock and reset gating this region and the power domain it + belongs to. + +properties: + compatible: + const: starfive,jh7110-hdmi-subsystem + + reg: + maxItems: 1 + + phy: + $ref: /schemas/phy/starfive,jh7110-inno-hdmi-phy.yaml# + + controller: + $ref: /schemas/display/bridge/starfive,jh7110-inno-hdmi-controller.yam= l# + +required: + - compatible + - reg + - phy + - controller + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi-subsystem"; + reg =3D <0x29590000 0x4000>; + + controller { + compatible =3D "starfive,jh7110-inno-hdmi-controller"; + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "pclk", "mclk", "bclk", "pixel"; + interrupts =3D <99>; + phys =3D <&hdmi_phy>; + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + starfive,vout-syscon =3D <&vout_syscon>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + endpoint { + remote-endpoint =3D <&dpu_out_dpi0>; + }; + }; + + port@1 { + reg =3D <1>; + + endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + }; + }; + }; + + hdmi_phy: phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + #clock-cells =3D <0>; + clocks =3D <&xin24m>; + #phy-cells =3D <0>; + }; + }; + }; +... --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 039594AA586; Tue, 15 Sep 2026 15:32:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 15 Sep 2026 15:32:20 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153218eusmtip1a67d7df51779cea51b9ccba9edfd3c9d~ViFgQLW9c0616306163eusmtip1b; Tue, 15 Sep 2026 15:32:18 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:12 +0200 Subject: [PATCH v4 04/20] dt-bindings: soc: starfive: Add starfive,jh7110-vout-syscon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-4-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153220eucas1p1f5b0e03015500d9d66db8993426c8734 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153220eucas1p1f5b0e03015500d9d66db8993426c8734 X-EPHeader: CA X-CMS-RootMailID: 20260915153220eucas1p1f5b0e03015500d9d66db8993426c8734 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> The video output subsystem has its own system controller, documented as dom_vout_syscon. Among other things it holds the mux that selects which DC8200 output drives the HDMI transmitter, so the HDMI controller needs to reach it. Signed-off-by: Michal Wilczynski Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110= -syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh71= 10-syscon.yaml index 0039319e91fe6e6aadc4300114626348e4dfb7ce..cf9b657d0e8a3ed5c5688336fee= 4123e14a2ac58 100644 --- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon= .yaml +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon= .yaml @@ -24,6 +24,7 @@ properties: - enum: - starfive,jh7110-aon-syscon - starfive,jh7110-stg-syscon + - starfive,jh7110-vout-syscon - const: syscon =20 reg: --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6B154AC167; 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Tue, 15 Sep 2026 15:32:22 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153220eusmtip1597ba736145d4647dfcd6e0d88695ed1~ViFh_H60p0424304243eusmtip1w; Tue, 15 Sep 2026 15:32:20 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:13 +0200 Subject: [PATCH v4 05/20] dt-bindings: display: verisilicon: Add starfive,jh7110-dc8200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-5-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153222eucas1p213b95b05ea7eb9a18700af8888ef5a44 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153222eucas1p213b95b05ea7eb9a18700af8888ef5a44 X-EPHeader: CA X-CMS-RootMailID: 20260915153222eucas1p213b95b05ea7eb9a18700af8888ef5a44 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> The JH7110 embeds a DC8200. The binding requires an SoC specific compatible ahead of the generic one, so add the JH7110 to the enum. Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/display/verisilicon,dc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml = b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml index 919a9001220120054cb62d1d01b7293367266f95..05a202633cd273fec358c095c64= 584d959d96d90 100644 --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml @@ -16,6 +16,7 @@ properties: compatible: items: - enum: + - starfive,jh7110-dc8200 - thead,th1520-dc8200 - const: verisilicon,dc # DC IPs have discoverable ID/revision regis= ters =20 --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31E634AA567; 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Tue, 15 Sep 2026 15:32:24 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153222eusmtip1871deee67ee9100e2f92688386019ecf~ViFjsh48Q0604306043eusmtip1i; Tue, 15 Sep 2026 15:32:22 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:14 +0200 Subject: [PATCH v4 06/20] dt-bindings: soc: starfive: Add starfive,jh7110-vout-subsystem Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-6-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153224eucas1p1c19b20f6af600b1c3228a9a8f4bb4490 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153224eucas1p1c19b20f6af600b1c3228a9a8f4bb4490 X-EPHeader: CA X-CMS-RootMailID: 20260915153224eucas1p1c19b20f6af600b1c3228a9a8f4bb4490 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> The JH7110 groups its display hardware into a video output subsystem, dom_vout_top, covering the DC8200, the HDMI transmitter, the video output clock generator and the video output system controller. They share one NoC port whose clock and reset gate access to every register in the region, and the region sits in the PD_VOUT power domain. Describe the subsystem as a bus node so those resources are owned by the block that shares them, rather than by whichever consumer happens to probe first. Signed-off-by: Michal Wilczynski Reviewed-by: Rob Herring (Arm) --- .../starfive/starfive,jh7110-vout-subsystem.yaml | 218 +++++++++++++++++= ++++ 1 file changed, 218 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110= -vout-subsystem.yaml b/Documentation/devicetree/bindings/soc/starfive/starf= ive,jh7110-vout-subsystem.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3306c4068493ec30b3863db6ff7= eb47b13d55240 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-s= ubsystem.yaml @@ -0,0 +1,218 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-vout-subsy= stem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 video output subsystem + +maintainers: + - Michal Wilczynski + +description: + The JH7110 groups its display hardware into a video output subsystem, na= med + dom_vout_top in the documentation. It covers the DC8200 display controll= er, + the HDMI transmitter, the video output clock generator and the video out= put + system controller, all behind one NoC port. That port's clock and reset = gate + access to every register in the region, and the region sits in the PD_VO= UT + power domain, so this node owns those resources on behalf of its childre= n. + +properties: + compatible: + const: starfive,jh7110-vout-subsystem + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: NoC display bus clock. + + resets: + maxItems: 1 + description: NoC display bus reset. + + power-domains: + maxItems: 1 + + dma-noncoherent: true + + ranges: true + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + +patternProperties: + "^display@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: starfive,jh7110-dc8200 + + "^hdmi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: starfive,jh7110-hdmi-subsystem + + "^syscon@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: starfive,jh7110-vout-syscon + + "^clock-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: starfive,jh7110-voutcrg + +required: + - compatible + - reg + - clocks + - resets + - power-domains + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + display-subsystem@29400000 { + compatible =3D "starfive,jh7110-vout-subsystem"; + reg =3D <0x0 0x29400000 0x0 0x200000>; + ranges; + #address-cells =3D <2>; + clocks =3D <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>; + dma-noncoherent; + power-domains =3D <&pwrc JH7110_PD_VOUT>; + resets =3D <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>; + #size-cells =3D <2>; + + display@29400000 { + compatible =3D "starfive,jh7110-dc8200", "verisilicon,dc"; + reg =3D <0x0 0x29400000 0x0 0x2800>; + clocks =3D <&voutcrg JH7110_VOUTCLK_DC8200_CORE>, + <&voutcrg JH7110_VOUTCLK_DC8200_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_AHB>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>; + clock-names =3D "core", "axi", "ahb", "pix0", "pix1"; + interrupts =3D <95>; + resets =3D <&voutcrg JH7110_VOUTRST_DC8200_CORE>, + <&voutcrg JH7110_VOUTRST_DC8200_AXI>, + <&voutcrg JH7110_VOUTRST_DC8200_AHB>; + reset-names =3D "core", "axi", "ahb"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_out_dpi0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_in>; + }; + }; + + port@1 { + reg =3D <1>; + }; + }; + }; + + hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi-subsystem"; + reg =3D <0x0 0x29590000 0x0 0x4000>; + + controller { + compatible =3D "starfive,jh7110-inno-hdmi-controller"; + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "pclk", "mclk", "bclk", "pixel"; + interrupts =3D <99>; + phys =3D <&hdmi_phy>; + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + starfive,vout-syscon =3D <&vout_syscon>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi_in: endpoint { + remote-endpoint =3D <&dpu_out_dpi0>; + }; + }; + + port@1 { + reg =3D <1>; + + endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + }; + }; + }; + + hdmi_phy: phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + #clock-cells =3D <0>; + clocks =3D <&xin24m>; + #phy-cells =3D <0>; + }; + }; + + vout_syscon: syscon@295b0000 { + compatible =3D "starfive,jh7110-vout-syscon", "syscon"; + reg =3D <0x0 0x295b0000 0x0 0x10000>; + }; + + voutcrg: clock-controller@295c0000 { + compatible =3D "starfive,jh7110-voutcrg"; + reg =3D <0x0 0x295c0000 0x0 0x10000>; + #clock-cells =3D <1>; + clocks =3D <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmi_phy>; + clock-names =3D "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + power-domains =3D <&pwrc JH7110_PD_VOUT>; + #reset-cells =3D <1>; + resets =3D <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + }; + }; + }; +... --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0695E4ACC7D; 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Tue, 15 Sep 2026 15:32:26 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153224eusmtip1f47b9d063d7792081016464514cb6a81~ViFlavdY-0419804198eusmtip12; Tue, 15 Sep 2026 15:32:24 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:15 +0200 Subject: [PATCH v4 07/20] drm/bridge: inno-hdmi: Split probe out of bind Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-7-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153226eucas1p1d69e9e853b4b5cfb1d42c2c585b57f95 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153226eucas1p1d69e9e853b4b5cfb1d42c2c585b57f95 X-EPHeader: CA X-CMS-RootMailID: 20260915153226eucas1p1d69e9e853b4b5cfb1d42c2c585b57f95 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> inno_hdmi_bind() both sets up the bridge and attaches it to a DRM encoder. A platform whose HDMI controller is a child of a larger device needs the first half without the second, since it registers as its own platform driver and lets the DRM core bind the bridge later. Move the setup into a new exported inno_hdmi_probe(), with a matching inno_hdmi_remove(), and reduce inno_hdmi_bind() to a wrapper around it. No functional change intended. Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 49 +++++++++++++++++++++++++++++++++-= ---- include/drm/bridge/inno_hdmi.h | 4 ++++ 2 files changed, 47 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index dd35f5a875d3d842fee6d2ead0de88503f9914e1..840f1c7bc202951d3dfee3711f6= 1105f328c3326 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -929,7 +929,14 @@ static irqreturn_t inno_hdmi_irq(int irq, void *dev_id) { struct inno_hdmi *hdmi =3D dev_id; =20 - drm_helper_hpd_irq_event(hdmi->bridge.dev); + /* + * The interrupt is requested in probe, but bridge.dev is only set once + * the DRM master binds and attaches the bridge, which may never happen. + * Drop hotplug events that arrive before then rather than dereference a + * NULL drm_device. + */ + if (hdmi->bridge.dev) + drm_helper_hpd_irq_event(hdmi->bridge.dev); =20 return IRQ_HANDLED; } @@ -1061,11 +1068,24 @@ static struct i2c_adapter *inno_hdmi_i2c_adapter(st= ruct inno_hdmi *hdmi) return adap; } =20 -struct inno_hdmi *inno_hdmi_bind(struct device *dev, - struct drm_encoder *encoder, - const struct inno_hdmi_plat_data *plat_data) +/** + * inno_hdmi_probe - Internal helper to perform common setup + * @pdev: platform device + * @plat_data: SoC-specific platform data + * + * This function handles all the common hardware setup: allocating the main + * struct, mapping registers, getting clocks, initializing the hardware, + * setting up the IRQ, and initializing the DDC adapter and bridge struct. + * It returns a pointer to the inno_hdmi struct on success, or an ERR_PTR + * on failure. + * + * This function is used by modern, decoupled MFD/glue drivers. It registe= rs + * the bridge but does not attach it. + */ +struct inno_hdmi *inno_hdmi_probe(struct platform_device *pdev, + const struct inno_hdmi_plat_data *plat_data) { - struct platform_device *pdev =3D to_platform_device(dev); + struct device *dev =3D &pdev->dev; struct inno_hdmi *hdmi; int irq; int ret; @@ -1128,7 +1148,24 @@ struct inno_hdmi *inno_hdmi_bind(struct device *dev, if (ret) return ERR_PTR(ret); =20 - ret =3D drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH= _NO_CONNECTOR); + return hdmi; +} +EXPORT_SYMBOL_GPL(inno_hdmi_probe); + +struct inno_hdmi *inno_hdmi_bind(struct device *dev, + struct drm_encoder *encoder, + const struct inno_hdmi_plat_data *plat_data) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct inno_hdmi *hdmi; + int ret; + + hdmi =3D inno_hdmi_probe(pdev, plat_data); + if (IS_ERR(hdmi)) + return hdmi; + + ret =3D drm_bridge_attach(encoder, &hdmi->bridge, NULL, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret) return ERR_PTR(ret); =20 diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h index 5bbcaeea94e2a20fd0dc0ae0c6946eb5604bbaf6..81da9d9bcd79db8fe26c6dff456= 9371e484df608 100644 --- a/include/drm/bridge/inno_hdmi.h +++ b/include/drm/bridge/inno_hdmi.h @@ -12,6 +12,7 @@ struct device; struct drm_encoder; struct drm_display_mode; struct inno_hdmi; +struct platform_device; =20 struct inno_hdmi_plat_ops { void (*enable)(struct device *pdev, struct drm_display_mode *mode); @@ -32,4 +33,7 @@ struct inno_hdmi_plat_data { struct inno_hdmi *inno_hdmi_bind(struct device *pdev, struct drm_encoder *encoder, const struct inno_hdmi_plat_data *plat_data); + +struct inno_hdmi *inno_hdmi_probe(struct platform_device *pdev, + const struct inno_hdmi_plat_data *plat_data); #endif /* __INNO_HDMI__ */ --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C3814ACC7F; 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Tue, 15 Sep 2026 15:32:27 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153226eusmtip1b8862067e39eb9b8c67522b01c52aff8~ViFnFT_Cd0424304243eusmtip1x; Tue, 15 Sep 2026 15:32:26 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:16 +0200 Subject: [PATCH v4 08/20] drm/bridge: inno-hdmi: Allow the register map to come from a parent Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-8-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153227eucas1p2c51b87dc8da5d9dfacd6db6bb7d6774e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153227eucas1p2c51b87dc8da5d9dfacd6db6bb7d6774e X-EPHeader: CA X-CMS-RootMailID: 20260915153227eucas1p2c51b87dc8da5d9dfacd6db6bb7d6774e References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> On some SoCs the HDMI controller does not own its register window. The StarFive JH7110 documents one 64 KB block, u0_hdmitx, that holds both the controller and the PHY, so the parent device maps it and owns the regmap while the two children share it. Use a regmap supplied by the parent device when there is one, and keep mapping our own resource when there is not, so platforms that own their register window are unaffected. Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index 840f1c7bc202951d3dfee3711f61105f328c3326..1264152fb1434acda584e4af3d5= 4e4986b57aa3e 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -397,6 +397,7 @@ struct inno_hdmi { struct clk *pclk; struct clk *refclk; void __iomem *regs; + struct regmap *regmap; struct regmap *grf; =20 struct inno_hdmi_i2c *i2c; @@ -470,11 +471,25 @@ static int inno_hdmi_find_phy_config(struct inno_hdmi= *hdmi, =20 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset) { + u32 val; + + if (hdmi->regmap) { + if (regmap_read(hdmi->regmap, offset * 4, &val)) + return 0; + + return val; + } + return readl_relaxed(hdmi->regs + (offset) * 0x04); } =20 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) { + if (hdmi->regmap) { + regmap_write(hdmi->regmap, offset * 4, val); + return; + } + writel_relaxed(val, hdmi->regs + (offset) * 0x04); } =20 @@ -1102,9 +1117,19 @@ struct inno_hdmi *inno_hdmi_probe(struct platform_de= vice *pdev, hdmi->dev =3D dev; hdmi->plat_data =3D plat_data; =20 - hdmi->regs =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(hdmi->regs)) - return ERR_CAST(hdmi->regs); + /* + * On platforms where the controller shares a register space with + * other blocks, the parent owns the regmap. Fall back to mapping + * our own resource where it does not. + */ + if (dev->parent) + hdmi->regmap =3D dev_get_regmap(dev->parent, NULL); + + if (!hdmi->regmap) { + hdmi->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(hdmi->regs)) + return ERR_CAST(hdmi->regs); + } =20 hdmi->pclk =3D devm_clk_get_enabled(hdmi->dev, "pclk"); if (IS_ERR(hdmi->pclk)) { --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D13804ACC8C; Tue, 15 Sep 2026 15:32:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789486358; cv=none; b=XtLd7emMJJPfaCT4ENYQjqAMn3dfqHuRM9jZ6/e0zaszbIVLHoiiRtmC4x2PxIPplRX8TG6jn5Nr1lDtsTfLDDzeggVmR0Lh6bzh/Rn1ukk+c3HfDL2HsODLzxgZmxHC8UbHsbcUYoL3vIRhGxWCKDhkbvljha6ziSerXiBYBAM= ARC-Message-Signature: i=1; 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Tue, 15 Sep 2026 15:32:27 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:17 +0200 Subject: [PATCH v4 09/20] drm/bridge: inno-hdmi: Add .disable platform operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-9-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153229eucas1p2d1b02b6f3871d6b536f678b9ea293c1c X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153229eucas1p2d1b02b6f3871d6b536f678b9ea293c1c X-EPHeader: CA X-CMS-RootMailID: 20260915153229eucas1p2d1b02b6f3871d6b536f678b9ea293c1c References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> The Innosilicon HDMI driver supports platform-specific behavior through the `inno_hdmi_plat_ops`. While it provides an `.enable` hook for platform-specific power up sequences (like enabling PHYs), it lacks a corresponding hook for power down. This patch adds a new `.disable` op to the `inno_hdmi_plat_ops` struct and calls it at the beginning of `inno_hdmi_bridge_atomic_disable()`. This allows platform specific drivers, such as the StarFive JH7110, to implement their own power down sequence (e.g., calling phy_power_off() and clk_disable_unprepare()). Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 4 ++++ include/drm/bridge/inno_hdmi.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index 1264152fb1434acda584e4af3d54e4986b57aa3e..06917e83c5e530d158a06ae2a87= 7e78e22ed842d 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -886,6 +886,10 @@ static void inno_hdmi_bridge_atomic_disable(struct drm= _bridge *bridge, struct drm_atomic_commit *state) { struct inno_hdmi *hdmi =3D bridge_to_inno_hdmi(bridge); + const struct inno_hdmi_plat_ops *plat_ops =3D hdmi->plat_data->ops; + + if (plat_ops && plat_ops->disable) + plat_ops->disable(hdmi->dev); =20 inno_hdmi_standby(hdmi); } diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h index 81da9d9bcd79db8fe26c6dff4569371e484df608..5fca651c56b056d814124aa9c7e= 91aa7fd7ed1cd 100644 --- a/include/drm/bridge/inno_hdmi.h +++ b/include/drm/bridge/inno_hdmi.h @@ -16,6 +16,7 @@ struct platform_device; =20 struct inno_hdmi_plat_ops { void (*enable)(struct device *pdev, struct drm_display_mode *mode); + void (*disable)(struct device *pdev); }; =20 struct inno_hdmi_phy_config { --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 253AC4A6CE0; Tue, 15 Sep 2026 15:32:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789486359; cv=none; b=XiuAHTKNKBX1C/lIjV1SIk6rI37G3sybK5L9VhCWe77pnAeUmASdQ5s/nl8EvkR9tpYzwXjhLeXmqQGrfC2dCypb+gpFU9BNf47W0mvZoJ5J9UrVfC5vNNQFbipDKxo/w+A1GmwcQdQqR4EefMyGWY+SY9lgLg6VFIBPzaj5LF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789486359; c=relaxed/simple; bh=MEnEtnu4r3f08PY63sNQ09Ef8G5IuAgz2nwPcTFzWNM=; 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Tue, 15 Sep 2026 15:32:29 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:18 +0200 Subject: [PATCH v4 10/20] drm/bridge: inno-hdmi: Add .mode_valid platform operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-10-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153231eucas1p1e106fee2d6f7db2aa8bb93d18d0f5dc1 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153231eucas1p1e106fee2d6f7db2aa8bb93d18d0f5dc1 X-EPHeader: CA X-CMS-RootMailID: 20260915153231eucas1p1e106fee2d6f7db2aa8bb93d18d0f5dc1 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> inno_hdmi_bridge_mode_valid() validates the pixel clock against hdmi->refclk, but that clock is optional and is only present on platforms that describe a "ref" clock. Platforms where the pixel clock is produced by a separate device - such as the StarFive JH7110, whose PHY is both the clock and the PHY provider - have no "ref" clock, so the check is skipped entirely and every mode is reported as valid. A mode the platform cannot generate is then advertised to userspace. The subsequent modeset appears to succeed, since the atomic enable path cannot fail, and the display silently stays blank. Add a .mode_valid platform operation so platforms can reject modes they are unable to drive. Platforms that do not implement it are unaffected. Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 9 +++++++++ include/drm/bridge/inno_hdmi.h | 5 ++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index 06917e83c5e530d158a06ae2a877e78e22ed842d..00450250336adb9530894af7670= 34572d775a8df 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -823,6 +823,7 @@ static enum drm_mode_status inno_hdmi_bridge_mode_valid= (struct drm_bridge *bridg const struct drm_display_mode *mode) { struct inno_hdmi *hdmi =3D bridge_to_inno_hdmi(bridge); + const struct inno_hdmi_plat_ops *plat_ops =3D hdmi->plat_data->ops; unsigned long mpixelclk, max_tolerance; long rounded_refclk; =20 @@ -838,6 +839,14 @@ static enum drm_mode_status inno_hdmi_bridge_mode_vali= d(struct drm_bridge *bridg if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0) return MODE_CLOCK_HIGH; =20 + if (plat_ops && plat_ops->mode_valid) { + enum drm_mode_status status; + + status =3D plat_ops->mode_valid(hdmi->dev, mode); + if (status !=3D MODE_OK) + return status; + } + if (hdmi->refclk) { rounded_refclk =3D clk_round_rate(hdmi->refclk, mpixelclk); if (rounded_refclk < 0) diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h index 5fca651c56b056d814124aa9c7e91aa7fd7ed1cd..1e9974401c39e3773bb339eaec0= b45ff1dd9c975 100644 --- a/include/drm/bridge/inno_hdmi.h +++ b/include/drm/bridge/inno_hdmi.h @@ -8,15 +8,18 @@ =20 #include =20 +#include + struct device; struct drm_encoder; -struct drm_display_mode; struct inno_hdmi; struct platform_device; =20 struct inno_hdmi_plat_ops { void (*enable)(struct device *pdev, struct drm_display_mode *mode); void (*disable)(struct device *pdev); + enum drm_mode_status (*mode_valid)(struct device *pdev, + const struct drm_display_mode *mode); }; =20 struct inno_hdmi_phy_config { --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37E254AA408; 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Tue, 15 Sep 2026 15:32:33 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153231eusmtip19a6ca86b35c8d62c1324b24637525198~ViFr-1w1n0336503365eusmtip1x; Tue, 15 Sep 2026 15:32:31 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:19 +0200 Subject: [PATCH v4 11/20] drm/bridge: inno-hdmi: Make the PHY configuration table optional Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-11-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153233eucas1p2e26a6953a31c5f836aeaed03a4ae325e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153233eucas1p2e26a6953a31c5f836aeaed03a4ae325e X-EPHeader: CA X-CMS-RootMailID: 20260915153233eucas1p2e26a6953a31c5f836aeaed03a4ae325e References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> The pre-emphasis and drive-strength values in inno_hdmi_phy_config, and the registers they are written to, belong to the PHY integrated into the controller. A platform whose PHY is a separate device has neither, and its own .mode_valid already validates the pixel clock against the real PHY, so the table only bounds the generic check. Let such a platform omit the table: skip the integrated-PHY register writes in the power-up path and the table lookup in .mode_valid when it is absent. Platforms that supply one are unaffected. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index 00450250336adb9530894af767034572d775a8df..0988775e7e4881a84f59efda846= 5ad4d5e61b4cd 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -538,8 +538,14 @@ static void inno_hdmi_power_up(struct inno_hdmi *hdmi, unsigned long mpixelclock) { struct inno_hdmi_phy_config *phy_config; - int ret =3D inno_hdmi_find_phy_config(hdmi, mpixelclock); + int ret; + + inno_hdmi_sys_power(hdmi, false); + + if (!hdmi->plat_data->phy_configs) + goto out; =20 + ret =3D inno_hdmi_find_phy_config(hdmi, mpixelclock); if (ret < 0) { phy_config =3D hdmi->plat_data->default_phy_config; DRM_DEV_ERROR(hdmi->dev, @@ -549,8 +555,6 @@ static void inno_hdmi_power_up(struct inno_hdmi *hdmi, phy_config =3D &hdmi->plat_data->phy_configs[ret]; } =20 - inno_hdmi_sys_power(hdmi, false); - hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis); hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control); hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); @@ -560,6 +564,7 @@ static void inno_hdmi_power_up(struct inno_hdmi *hdmi, hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00); hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01); =20 +out: inno_hdmi_sys_power(hdmi, true); }; =20 @@ -836,7 +841,8 @@ static enum drm_mode_status inno_hdmi_bridge_mode_valid= (struct drm_bridge *bridg if (mpixelclk < HDMI_TMDS_CHAR_RATE_MIN_HZ) return MODE_CLOCK_LOW; =20 - if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0) + if (hdmi->plat_data->phy_configs && + inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0) return MODE_CLOCK_HIGH; =20 if (plat_ops && plat_ops->mode_valid) { @@ -1118,11 +1124,6 @@ struct inno_hdmi *inno_hdmi_probe(struct platform_de= vice *pdev, int irq; int ret; =20 - if (!plat_data->phy_configs || !plat_data->default_phy_config) { - dev_err(dev, "Missing platform PHY ops\n"); - return ERR_PTR(-ENODEV); - } - hdmi =3D devm_drm_bridge_alloc(dev, struct inno_hdmi, bridge, &inno_hdmi_= bridge_funcs); if (IS_ERR(hdmi)) return ERR_CAST(hdmi); --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A8474AE133; Tue, 15 Sep 2026 15:32:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789486362; cv=none; b=bm6j5dchZy/hrmKSPHZnzAoKLGQ1NjuiwtoX5NOSv35vwTBe4eNmZm4UVSbblVY6/EmtdVevqHTj61pZkdrg51HOErhxJwjjsJUkwHA9GcFukIpnGJkmoj1qXMh9XGQjYj+F8bp+OFfJFPgOT81OF/dxbBIlW/EkmCnf/+W7sqU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789486362; c=relaxed/simple; bh=qKymp8E8uxrxGbeQzNIcrweTllWhBN6YKPt0/xuWMNs=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; 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a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1789486355; bh=sH+xZkZrlWCLVn5PSU/HsI1mSFzFtZNw1J3UtaFtBck=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=kqKPeHRF5yePqxPIuK6+gdKzJtT615Mg4WBfQgoClJYIyVITWHhQJRe0geV1/3Gme ul0hz5bpi7t/9IoC9vdt9Hr2zoh4FLHq0AvoIxuY4FpsDtGuHL8vBrO9ia/tICwm8k 9yTPSpzuUCaKG58VDEFrxgyx5fK3lZHars1KnJHE= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20260915153234eucas1p221dd53b5f1bccb6228c0a5a7d0be8394~ViFvOwGKD1216312163eucas1p2Z; Tue, 15 Sep 2026 15:32:34 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153233eusmtip1b6ab608f7a1bbd071a84d43106b84560~ViFtoQCVP0419704197eusmtip12; Tue, 15 Sep 2026 15:32:33 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:20 +0200 Subject: [PATCH v4 12/20] soc: starfive: Add jh7110-hdmi-subsystem driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-12-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153234eucas1p221dd53b5f1bccb6228c0a5a7d0be8394 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153234eucas1p221dd53b5f1bccb6228c0a5a7d0be8394 X-EPHeader: CA X-CMS-RootMailID: 20260915153234eucas1p221dd53b5f1bccb6228c0a5a7d0be8394 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> Add the parent driver for the monolithic JH7110 HDMI IP block. This driver binds to the starfive,jh7110-hdmi-subsystem node. It maps the shared register block, creates a regmap, and calls devm_of_platform_populate() to create its hdmi_phy and hdmi_controller child devices, which retrieve the shared regmap from this parent. The NoC display bus clock and reset that gate access to this region, and the PD_VOUT power domain it sits in, are held by the video output subsystem parent for as long as this device exists, so there is nothing for this driver to bring up itself. Co-developed-by: Dominique Belhachemi Signed-off-by: Dominique Belhachemi Signed-off-by: Michal Wilczynski --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/starfive/Kconfig | 28 +++++++++++ drivers/soc/starfive/Makefile | 2 + drivers/soc/starfive/jh7110-hdmi-subsystem.c | 73 ++++++++++++++++++++++++= ++++ 5 files changed, 105 insertions(+) diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index a2d65adffb8052c0ac5a6b60bf33fa9c644701bb..b3b01fc38139d98076c14f626a4= 2ae3b7ef7c5d6 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -24,6 +24,7 @@ source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" source "drivers/soc/sophgo/Kconfig" +source "drivers/soc/starfive/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index c9e689080ceb759384f690c2b65a82b3cb451c74..009f85ff891a15e0455f92c5d5a= 4059d8b1fcd3f 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -30,6 +30,7 @@ obj-y +=3D renesas/ obj-y +=3D rockchip/ obj-$(CONFIG_SOC_SAMSUNG) +=3D samsung/ obj-y +=3D sophgo/ +obj-y +=3D starfive/ obj-y +=3D sunxi/ obj-$(CONFIG_ARCH_TEGRA) +=3D tegra/ obj-y +=3D ti/ diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..e738638ab0f755fbbabca259264= abb56f3b6101f --- /dev/null +++ b/drivers/soc/starfive/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Starfive SoC drivers +# + +if ARCH_STARFIVE || COMPILE_TEST +menu "Starfive SoC drivers" + +config SOC_STARFIVE_JH7110_HDMI_SUBSYSTEM + tristate "StarFive JH7110 HDMI subsystem driver" + depends on OF + select REGMAP_MMIO + help + This option enables the parent driver + for the monolithic StarFive JH7110 HDMI peripheral. + + The JH7110 HDMI IP block contains both the digital controller + (DRM bridge) and the analog PHY (clock/phy provider) logic within + a single shared register space. + + This driver acts as a wrapper. Its only job is to map the + shared registers and create separate logical child devices + for the "PHY" and the "controller". This is required to + correctly manage resources and break a circular clock dependency + between the PHY and the VOUT clock generator at probe time. + +endmenu +endif diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..be89d8119212b7a7038817c2f0e= 8eac1984ada88 --- /dev/null +++ b/drivers/soc/starfive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_SOC_STARFIVE_JH7110_HDMI_SUBSYSTEM) +=3D jh7110-hdmi-subsyste= m.o diff --git a/drivers/soc/starfive/jh7110-hdmi-subsystem.c b/drivers/soc/sta= rfive/jh7110-hdmi-subsystem.c new file mode 100644 index 0000000000000000000000000000000000000000..e64a22263045935ae69541cf8a1= 44f6128170c11 --- /dev/null +++ b/drivers/soc/starfive/jh7110-hdmi-subsystem.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for the StarFive JH7110 HDMI subsystem + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * This driver binds to the monolithic HDMI block and creates separate + * logical platform devices for the HDMI Controller (bridge) and the + * HDMI PHY (clock/phy provider), allowing them to share a single regmap + * and breaking the probing circular dependency. + */ + +#include +#include +#include +#include +#include + +static const struct regmap_config starfive_hdmi_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 8, + .max_register =3D 0x3fff, +}; + +static int starfive_hdmi_subsys_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *regs; + int ret; + + /* + * The NoC display bus clock and reset that gate access to this region, + * and the PD_VOUT power domain it sits in, are held by the video + * output subsystem parent for as long as this device exists. + */ + regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + regmap =3D devm_regmap_init_mmio(dev, regs, + &starfive_hdmi_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "Failed to init shared regmap\n"); + + ret =3D devm_of_platform_populate(dev); + if (ret) + return dev_err_probe(dev, ret, + "Failed to populate child devices\n"); + + return 0; +} + +static const struct of_device_id starfive_hdmi_subsys_of_match[] =3D { + { .compatible =3D "starfive,jh7110-hdmi-subsystem", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_hdmi_subsys_of_match); + +static struct platform_driver starfive_hdmi_subsys_driver =3D { + .probe =3D starfive_hdmi_subsys_probe, + .driver =3D { + .name =3D "starfive-hdmi-subsystem", + .of_match_table =3D starfive_hdmi_subsys_of_match, + }, +}; +module_platform_driver(starfive_hdmi_subsys_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("StarFive JH7110 HDMI subsystem Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E7804AE8B6; Tue, 15 Sep 2026 15:32:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789486365; cv=none; b=ZOyAN/mQl2Xo3lvfBbtzJlASzgdq1jrTN5sWJrPpU2lN+PaovIwdaT78PksNqrq6zgVCERLSOPiAbxULkZY1fgZ0zH5flvzsEXm0FJez/q2tDtg1oa9cOrnhtFHU1i6T25oZc00t0/AwKfPEtQ+yI3XkB/OHXCknjjXur47pI5U= ARC-Message-Signature: i=1; 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Tue, 15 Sep 2026 15:32:34 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:21 +0200 Subject: [PATCH v4 13/20] soc: starfive: Add jh7110-vout-subsystem driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-13-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153236eucas1p1712930425e569f894c870299f245e99f X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153236eucas1p1712930425e569f894c870299f245e99f X-EPHeader: CA X-CMS-RootMailID: 20260915153236eucas1p1712930425e569f894c870299f245e99f References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> Nothing in the video output subsystem can reach its own registers until the NoC display bus clock and reset are up and PD_VOUT is powered, and those are shared by every device in the region. Leaving them to whichever consumer probes first works by accident and stops working as soon as the probe order changes. Add a driver for the subsystem node that takes the bus clock and reset, holds a runtime PM reference so genpd keeps PD_VOUT powered, and then populates its children. All three are released only once the last child is gone. Signed-off-by: Michal Wilczynski --- drivers/soc/starfive/Kconfig | 15 +++++ drivers/soc/starfive/Makefile | 1 + drivers/soc/starfive/jh7110-vout-subsystem.c | 82 ++++++++++++++++++++++++= ++++ 3 files changed, 98 insertions(+) diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig index e738638ab0f755fbbabca259264abb56f3b6101f..cf5e626b8a39a75768917eee188= a79256b36f1aa 100644 --- a/drivers/soc/starfive/Kconfig +++ b/drivers/soc/starfive/Kconfig @@ -6,6 +6,21 @@ if ARCH_STARFIVE || COMPILE_TEST menu "Starfive SoC drivers" =20 +config SOC_STARFIVE_JH7110_VOUT_SUBSYSTEM + tristate "StarFive JH7110 video output subsystem driver" + depends on OF + select PM + help + This option enables the parent driver for the StarFive JH7110 + video output subsystem, which the documentation calls dom_vout_top. + + The subsystem covers the DC8200 display controller, the HDMI + transmitter, the video output clock generator and the video output + system controller. They share one NoC port whose clock and reset + gate access to the whole register region, and the region sits in + the PD_VOUT power domain. This driver owns those resources and + holds them for as long as any of its children exist. + config SOC_STARFIVE_JH7110_HDMI_SUBSYSTEM tristate "StarFive JH7110 HDMI subsystem driver" depends on OF diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile index be89d8119212b7a7038817c2f0e8eac1984ada88..6c229020c1e563b37df43f6ac16= 65465a11333cc 100644 --- a/drivers/soc/starfive/Makefile +++ b/drivers/soc/starfive/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_SOC_STARFIVE_JH7110_HDMI_SUBSYSTEM) +=3D jh7110-hdmi-subsyste= m.o +obj-$(CONFIG_SOC_STARFIVE_JH7110_VOUT_SUBSYSTEM) +=3D jh7110-vout-subsyste= m.o diff --git a/drivers/soc/starfive/jh7110-vout-subsystem.c b/drivers/soc/sta= rfive/jh7110-vout-subsystem.c new file mode 100644 index 0000000000000000000000000000000000000000..af632692e2139d9d07edd478a29= 9b170ad1b7104 --- /dev/null +++ b/drivers/soc/starfive/jh7110-vout-subsystem.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for the StarFive JH7110 video output subsystem + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * The display hardware sits behind a single NoC port whose clock and reset + * gate access to every register in the region, inside the PD_VOUT power + * domain. Nothing below this node can reach its own registers until all t= hree + * are up, so bring them up here and hold them for as long as any child de= vice + * exists, rather than leaving them to whichever consumer happens to probe + * first. + */ + +#include +#include +#include +#include +#include +#include + +static void jh7110_vout_subsys_pm_put(void *data) +{ + pm_runtime_put_sync(data); +} + +static int jh7110_vout_subsys_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct reset_control *bus_rst; + struct clk *bus_clk; + int ret; + + /* + * Take a runtime PM reference for the lifetime of this device. genpd + * only keeps PD_VOUT powered while something actually holds it, and + * an unclocked or unpowered access to this region wedges the bus. + */ + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to power on PD_VOUT\n"); + + ret =3D devm_add_action_or_reset(dev, jh7110_vout_subsys_pm_put, dev); + if (ret) + return ret; + + bus_clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(bus_clk)) + return dev_err_probe(dev, PTR_ERR(bus_clk), + "Failed to enable NoC bus clock\n"); + + bus_rst =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(bus_rst)) + return dev_err_probe(dev, PTR_ERR(bus_rst), + "Failed to deassert NoC bus reset\n"); + + return devm_of_platform_populate(dev); +} + +static const struct of_device_id jh7110_vout_subsys_of_match[] =3D { + { .compatible =3D "starfive,jh7110-vout-subsystem", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_vout_subsys_of_match); + +static struct platform_driver jh7110_vout_subsys_driver =3D { + .probe =3D jh7110_vout_subsys_probe, + .driver =3D { + .name =3D "jh7110-vout-subsystem", + .of_match_table =3D jh7110_vout_subsys_of_match, + }, +}; +module_platform_driver(jh7110_vout_subsys_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("StarFive JH7110 video output subsystem driver"); +MODULE_LICENSE("GPL"); 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d=samsung.com; s=mail20170921; t=1789486359; bh=JcSXHVMDqv6KSfxLj3MK5INKK9EFwX8I0N6g2xkU6Kk=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=MgUE7O//cUy4rTHrEiCnRpYaxzokcH6wvdIzFDm/DphRUPTBDU+0DSYinsYpDvIVq GgU5c1ARllh0Ti83WtCJJ/DgOSxbV12xBQW1ApiKL6yOoU37+AMBOIhu5JmJY8Lozp yfB22pDmUmtqz//XMd/IzixnyYrc4XjJY6ga/ArA= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20260915153238eucas1p29917a31d10ce1aa55c1dcb44b62180f9~ViFylzEdz1456714567eucas1p2W; Tue, 15 Sep 2026 15:32:38 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153236eusmtip152220ca6bbe3751e6dc90fe7c7a6eff2~ViFw96L6d0616606166eusmtip1V; Tue, 15 Sep 2026 15:32:36 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:22 +0200 Subject: [PATCH v4 14/20] clk: starfive: jh7110-vout: Allow pixel clock rate propagation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-14-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153238eucas1p29917a31d10ce1aa55c1dcb44b62180f9 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153238eucas1p29917a31d10ce1aa55c1dcb44b62180f9 X-EPHeader: CA X-CMS-RootMailID: 20260915153238eucas1p29917a31d10ce1aa55c1dcb44b62180f9 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> The dc8200_pix0 and dc8200_pix1 MUXes feed the display controller, and the rate they carry is ultimately produced by the HDMI PHY, which registers hdmitx0_pixelclk as a clock provider. Add CLK_SET_RATE_PARENT to both MUXes so a rate requested on them reaches that parent, instead of being clamped to whatever rate the parent already happens to run at. Co-developed-by: Dominique Belhachemi Signed-off-by: Dominique Belhachemi Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- drivers/clk/starfive/clk-starfive-jh7110-vout.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/= starfive/clk-starfive-jh7110-vout.c index bad20d5d794a72f071b4d547b7304786a8ba9afa..aeba42cd3c44ba205ced52b1826= d2d2de82ad78f 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c @@ -40,10 +40,12 @@ static const struct jh71x0_clk_data jh7110_voutclk_data= [] =3D { JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VO= UT_TOP_AXI), JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_= VOUT_TOP_AXI), JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VO= UT_TOP_AHB), - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, JH7110_VOUTCLK_DC8200_PIX, JH7110_VOUTCLK_HDMITX0_PIXELCLK), - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, JH7110_VOUTCLK_DC8200_PIX, JH7110_VOUTCLK_HDMITX0_PIXELCLK), /* LCD */ --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A1564AD4C4; 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Tue, 15 Sep 2026 15:32:41 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153238eusmtip197fbcf8485a837a60ae232d052f7f39c~ViFyp3p_w0555305553eusmtip1x; Tue, 15 Sep 2026 15:32:38 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:23 +0200 Subject: [PATCH v4 15/20] drm/bridge: starfive: Add JH7110 HDMI controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-15-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153241eucas1p292a3312a0ca8aed99cc416c0e01c3b66 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153241eucas1p292a3312a0ca8aed99cc416c0e01c3b66 X-EPHeader: CA X-CMS-RootMailID: 20260915153241eucas1p292a3312a0ca8aed99cc416c0e01c3b66 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> Add the HDMI controller (bridge) driver for the StarFive JH7110. This driver binds to the starfive,jh7110-inno-hdmi-controller node. It gets its register access, module and bus clocks from voutcrg, and consumes the pixel clock and the PHY from its hdmi_phy sibling. The driver calls the generic inno_hdmi_probe function, which picks up the regmap shared with the PHY from the parent device and registers a DRM bridge. The .enable hook is responsible for setting the PHY's pixel clock rate via clk_set_rate() and powering on the PHY via phy_power_on(). The DC8200 has two panels, each exposing a DP and a DPI interface, and a mux in the video output system controller picks which of them drives the HDMI transmitter. It comes out of reset on panel 0 / DPI, which happens to be what the default wiring needs, so nothing has had to program it so far. Derive it from the port graph instead, taking the panel from the remote port number and the interface from the remote endpoint number, so that a board describing a different output is honoured. The generic driver holds the clock it looks up as the register access clock enabled for its lifetime, and derives the DDC divider from that clock's rate, so point it at the system clock. Naming the pixel clock there instead would keep the PHY pre-PLL powered from probe onwards and size the divider from the wrong rate. The PHY can only generate the discrete set of pixel clocks described by its pre-PLL table, so .mode_valid rejects any mode clk_round_rate() cannot satisfy. Without it such a mode would be advertised to userspace and the modeset would appear to succeed while the display stayed blank. .enable returns early when the rate is unsupported or the PHY fails to power on, so track whether the pixel clock was actually enabled and let .disable tear down only what was brought up, otherwise the clock refcount underflows. The clocks and the reset are torn down through devm rather than from .remove, so that they outlive the bridge that inno_hdmi_probe() adds with devm_drm_bridge_add(). Releasing them in .remove runs before devres unwinds and would leave the bridge registered with its clocks already gated. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/Kconfig | 11 ++ drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/jh7110-inno-hdmi.c | 297 ++++++++++++++++++++++++++= ++++ 3 files changed, 309 insertions(+) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 4a57d49b4c6d3ab4b965228835b372d191647197..75b1cf6727d5a32310dcf9fe573= 4d95e14eea8fe 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -359,6 +359,17 @@ config DRM_SOLOMON_SSD2825 Say M here if you want to support this hardware as a module. The module will be named "ssd2825". =20 +config DRM_STARFIVE_JH7110_INNO_HDMI + tristate "Starfive JH7110 Innosilicon HDMI bridge" + depends on OF + depends on ARCH_STARFIVE || COMPILE_TEST + select DRM_INNO_HDMI + help + Enable support for the StarFive JH7110 specific implementation + of the Innosilicon HDMI controller. + This driver acts as a glue layer between the JH7110 HDMI subsystem + parent driver and the generic Innosilicon HDMI bridge driver. + config DRM_THINE_THC63LVD1024 tristate "Thine THC63LVD1024 LVDS decoder bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makef= ile index 15cc821d85b7ea6f3cdc313f3e521b028de567d7..5d843f4ad7ed50b28cb75286c5e= 22789d91a0836 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_DRM_SIL_SII8620) +=3D sil-sii8620.o obj-$(CONFIG_DRM_SII902X) +=3D sii902x.o obj-$(CONFIG_DRM_SII9234) +=3D sii9234.o obj-$(CONFIG_DRM_SIMPLE_BRIDGE) +=3D simple-bridge.o +obj-$(CONFIG_DRM_STARFIVE_JH7110_INNO_HDMI) +=3D jh7110-inno-hdmi.o obj-$(CONFIG_DRM_SOLOMON_SSD2825) +=3D ssd2825.o obj-$(CONFIG_DRM_THEAD_TH1520_DW_HDMI) +=3D th1520-dw-hdmi.o obj-$(CONFIG_DRM_THINE_THC63LVD1024) +=3D thc63lvd1024.o diff --git a/drivers/gpu/drm/bridge/jh7110-inno-hdmi.c b/drivers/gpu/drm/br= idge/jh7110-inno-hdmi.c new file mode 100644 index 0000000000000000000000000000000000000000..e9b91787330d7b65558868017bc= 36ca8f4535998 --- /dev/null +++ b/drivers/gpu/drm/bridge/jh7110-inno-hdmi.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) StarFive Technology Co., Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * HDMI controller (bridge) driver for the StarFive JH7110 HDMI subsystem. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* dom_vout_syscon: HDMI pixel data mapping */ +#define VOUT_SYSCFG_4 0x4 +#define VOUT_HDMI_DP_BIT_DEPTH BIT(25) +#define VOUT_HDMI_DP_YUV_MODE GENMASK(27, 26) +#define VOUT_HDMI_DP_YUV_MODE_RGB 3 +#define VOUT_HDMI_DPI_BIT_DEPTH GENMASK(29, 28) +#define VOUT_HDMI_DPI_BIT_DEPTH_8BIT 0 +#define VOUT_HDMI_DPI_DP_SEL BIT(30) + +/* u2_display_panel_mux feeds HDMI_Ctrl, see the block diagram in 5.1 */ +#define VOUT_SYSCFG_8 0x8 +#define VOUT_HDMI_PANEL_SEL BIT(4) + +enum stf_hdmi_ctrl_clocks { CLK_SYS =3D 0, CLK_M, CLK_B, CLK_PCLK, CLK_CTR= L_NUM }; + +struct stf_inno_hdmi_controller { + struct device *dev; + struct clk_bulk_data clks[CLK_CTRL_NUM]; + struct reset_control *tx_rst; + struct phy *phy; + bool enabled; +}; + +static enum drm_mode_status +inno_hdmi_starfive_mode_valid(struct device *dev, + const struct drm_display_mode *mode) +{ + struct stf_inno_hdmi_controller *ctrl =3D dev_get_drvdata(dev); + unsigned long pixelclk =3D mode->clock * 1000; + long rounded; + + /* + * The PHY can only generate the discrete set of pixel clocks described + * by its pre-PLL table, and clk_round_rate() fails for anything else. + * Reject those modes here: without this the modeset would appear to + * succeed while the PHY never produces a signal. + */ + rounded =3D clk_round_rate(ctrl->clks[CLK_PCLK].clk, pixelclk); + if (rounded !=3D pixelclk) + return MODE_NOCLOCK; + + return MODE_OK; +} + +static void inno_hdmi_starfive_enable(struct device *dev, + struct drm_display_mode *mode) +{ + struct stf_inno_hdmi_controller *ctrl =3D dev_get_drvdata(dev); + int ret; + + /* + * 1. Set the pixel clock rate. This calls the PHY driver's .set_rate op. + */ + ret =3D clk_set_rate(ctrl->clks[CLK_PCLK].clk, mode->clock * 1000); + if (ret) { + dev_err(dev, "Failed to set pclk rate %d: %d\n", + mode->clock * 1000, ret); + return; + } + + /* + * 2. Enable the pixel clock. This calls the PHY driver's .prepare op. + */ + ret =3D clk_prepare_enable(ctrl->clks[CLK_PCLK].clk); + if (ret) { + dev_err(dev, "Failed to enable pclk: %d\n", ret); + return; + } + + /* + * 3. Power on the PHY. This calls the PHY driver's .power_on op, + * which configures the Post-PLL and analog blocks. + */ + ret =3D phy_power_on(ctrl->phy); + if (ret) { + dev_err(dev, "Failed to power on PHY: %d\n", ret); + clk_disable_unprepare(ctrl->clks[CLK_PCLK].clk); + return; + } + + ctrl->enabled =3D true; +} + +static void inno_hdmi_starfive_disable(struct device *dev) +{ + struct stf_inno_hdmi_controller *ctrl =3D dev_get_drvdata(dev); + + /* + * .enable bails out early if the pixel clock rate is unsupported or + * the PHY fails to power on, leaving pclk and the PHY untouched. + * Only tear down what was actually brought up, otherwise the clock + * refcount underflows. + */ + if (!ctrl->enabled) + return; + + phy_power_off(ctrl->phy); + clk_disable_unprepare(ctrl->clks[CLK_PCLK].clk); + ctrl->enabled =3D false; +} + +/* + * The DC8200 has two panels, each exposing a DP and a DPI interface, and = a mux + * in dom_vout_syscon picks which of them drives the HDMI transmitter. Der= ive + * the mux setting from the port graph: the remote port number selects the + * DC8200 panel, and the remote endpoint number the interface on that panel + * (0 for DPI, 1 for DP). Both drive 8-bit RGB, the only format this driver + * currently produces. + */ +static int stf_inno_hdmi_setup_mux(struct device *dev) +{ + struct of_endpoint endpoint; + struct regmap *syscon; + u32 mask, val; + int ret; + + syscon =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "starfive,vout-syscon"); + if (IS_ERR(syscon)) + return dev_err_probe(dev, PTR_ERR(syscon), + "Failed to get vout syscon\n"); + + struct device_node *ep __free(device_node) =3D + of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); + if (!ep) + return dev_err_probe(dev, -ENODEV, "No input endpoint\n"); + + struct device_node *remote __free(device_node) =3D + of_graph_get_remote_endpoint(ep); + if (!remote) + return dev_err_probe(dev, -ENODEV, + "Input endpoint is not connected\n"); + + ret =3D of_graph_parse_endpoint(remote, &endpoint); + if (ret) + return dev_err_probe(dev, ret, + "Failed to parse the remote endpoint\n"); + + if (endpoint.port > 1 || endpoint.id > 1) + return dev_err_probe(dev, -EINVAL, + "Unsupported DC8200 output %u/%u\n", + endpoint.port, endpoint.id); + + /* Data mapping: 8-bit RGB on whichever interface is in use. */ + mask =3D VOUT_HDMI_DPI_DP_SEL | VOUT_HDMI_DP_BIT_DEPTH | + VOUT_HDMI_DP_YUV_MODE | VOUT_HDMI_DPI_BIT_DEPTH; + val =3D FIELD_PREP(VOUT_HDMI_DPI_DP_SEL, endpoint.id) | + FIELD_PREP(VOUT_HDMI_DP_YUV_MODE, VOUT_HDMI_DP_YUV_MODE_RGB) | + FIELD_PREP(VOUT_HDMI_DPI_BIT_DEPTH, VOUT_HDMI_DPI_BIT_DEPTH_8BIT); + + ret =3D regmap_update_bits(syscon, VOUT_SYSCFG_4, mask, val); + if (ret) + return ret; + + /* Which DC8200 panel drives the HDMI transmitter. */ + return regmap_update_bits(syscon, VOUT_SYSCFG_8, VOUT_HDMI_PANEL_SEL, + FIELD_PREP(VOUT_HDMI_PANEL_SEL, + endpoint.port)); +} + +static void stf_inno_hdmi_clk_disable(void *data) +{ + struct stf_inno_hdmi_controller *ctrl =3D data; + + clk_bulk_disable_unprepare(CLK_CTRL_NUM - 1, ctrl->clks); +} + +static void stf_inno_hdmi_rst_assert(void *data) +{ + reset_control_assert(data); +} + +static int starfive_inno_hdmi_controller_probe(struct platform_device *pde= v) +{ + struct device *dev =3D &pdev->dev; + struct stf_inno_hdmi_controller *ctrl; + const struct inno_hdmi_plat_data *plat_data; + struct inno_hdmi *inno; + int ret; + + ctrl =3D devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + ctrl->dev =3D dev; + platform_set_drvdata(pdev, ctrl); + + ctrl->phy =3D devm_phy_get(dev, NULL); + if (IS_ERR(ctrl->phy)) + return dev_err_probe(dev, PTR_ERR(ctrl->phy), "Failed to get PHY\n"); + + ctrl->tx_rst =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(ctrl->tx_rst)) + return dev_err_probe(dev, PTR_ERR(ctrl->tx_rst), "failed to get tx reset= \n"); + + /* Populate the clock names this controller *consumes* */ + ctrl->clks[CLK_SYS].id =3D "pclk"; + ctrl->clks[CLK_M].id =3D "mclk"; + ctrl->clks[CLK_B].id =3D "bclk"; + ctrl->clks[CLK_PCLK].id =3D "pixel"; /* Generated by the PHY */ + + ret =3D devm_clk_bulk_get(dev, CLK_CTRL_NUM, ctrl->clks); + if (ret) + return dev_err_probe(dev, ret, "Unable to get controller clocks\n"); + + /* + * Tear the clocks and the reset down through devm, so that they outlive + * everything registered after them. The bridge is added with + * devm_drm_bridge_add(), and unwinding in the wrong order would leave it + * registered while its clocks are already gated. + * + * The pixel clock is enabled on demand during modeset. + */ + ret =3D clk_bulk_prepare_enable(CLK_CTRL_NUM - 1, ctrl->clks); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, stf_inno_hdmi_clk_disable, ctrl); + if (ret) + return ret; + + ret =3D reset_control_deassert(ctrl->tx_rst); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, stf_inno_hdmi_rst_assert, + ctrl->tx_rst); + if (ret) + return ret; + + ret =3D stf_inno_hdmi_setup_mux(dev); + if (ret) + return ret; + + plat_data =3D of_device_get_match_data(dev); + + /* Hand off to the generic library to create the bridge. */ + inno =3D inno_hdmi_probe(pdev, plat_data); + if (IS_ERR(inno)) + return PTR_ERR(inno); + + return 0; +} + +static const struct inno_hdmi_plat_ops stf_inno_hdmi_plat_ops =3D { + .enable =3D inno_hdmi_starfive_enable, + .disable =3D inno_hdmi_starfive_disable, + .mode_valid =3D inno_hdmi_starfive_mode_valid, +}; + +static const struct inno_hdmi_plat_data stf_inno_hdmi_plat_data =3D { + .ops =3D &stf_inno_hdmi_plat_ops, +}; + +static const struct of_device_id starfive_hdmi_controller_dt_ids[] =3D { + { .compatible =3D "starfive,jh7110-inno-hdmi-controller", + .data =3D &stf_inno_hdmi_plat_data }, + {} +}; +MODULE_DEVICE_TABLE(of, starfive_hdmi_controller_dt_ids); + +struct platform_driver starfive_inno_hdmi_controller_driver =3D { + .probe =3D starfive_inno_hdmi_controller_probe, + .driver =3D { + .name =3D "starfive-inno-hdmi-controller", + .of_match_table =3D starfive_hdmi_controller_dt_ids, + }, +}; +module_platform_driver(starfive_inno_hdmi_controller_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("StarFive INNO HDMI Controller Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A486F4AF9C2; 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Tue, 15 Sep 2026 15:32:42 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153241eusmtip136721d290a695f65d862da5909921a00~ViF1NFQUt0441604416eusmtip1q; Tue, 15 Sep 2026 15:32:41 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:24 +0200 Subject: [PATCH v4 16/20] phy: Add common Innosilicon HDMI PHY helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-16-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153242eucas1p1394a6a5e272f106b9cab2a0f709ddeb8 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153242eucas1p1394a6a5e272f106b9cab2a0f709ddeb8 X-EPHeader: CA X-CMS-RootMailID: 20260915153242eucas1p1394a6a5e272f106b9cab2a0f709ddeb8 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> The Innosilicon HDMI PHY IP is used by several SoCs. They differ in where the PHY register block sits in the register space and in which pixel clocks they support, but the pre-PLL programming sequence and the layout of its registers are the same. Add a small library holding that shared part: the pre-PLL configuration table format, a lookup, clk_ops determine_rate and recalc_rate helpers, and the pre-PLL register programming. Callers pass a regmap, a register offset for the PHY block, and their own pixel clock table. No driver uses it yet; the users are converted separately. Reviewed-by: Chaoyi Chen Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/phy-inno-hdmi.c | 298 ++++++++++++++++++++++++++++++++++= ++++ include/linux/phy/inno-hdmi-phy.h | 85 +++++++++++ 4 files changed, 392 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 19f3b7d12b7d492d16000fa52483dc5002590d7a..0e973b3b02a30704d339db9f15d= 4695bcbec1c75 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -168,6 +168,14 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. =20 +config PHY_INNO_HDMI + tristate + depends on GENERIC_PHY + select REGMAP + help + Common helpers for the Innosilicon HDMI PHY, shared by the SoC + drivers that instantiate it. Selected by those drivers. + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/apple/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d7aa516bcc49e7662c9c9db421833fe591dfbc05..e93c473dfc6d837ed6ba540f0b0= 204a0d68d25bf 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_COMMON_PROPS) +=3D phy-common-props.o obj-$(CONFIG_PHY_COMMON_PROPS_TEST) +=3D phy-common-props-test.o obj-$(CONFIG_GENERIC_PHY) +=3D phy-core.o obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) +=3D phy-core-mipi-dphy.o +obj-$(CONFIG_PHY_INNO_HDMI) +=3D phy-inno-hdmi.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_CAN_TRANSCEIVER) +=3D phy-can-transceiver.o obj-$(CONFIG_PHY_ECONET_PCIE) +=3D phy-econet-pcie.o diff --git a/drivers/phy/phy-inno-hdmi.c b/drivers/phy/phy-inno-hdmi.c new file mode 100644 index 0000000000000000000000000000000000000000..77e745a87d22b5f3776593e642a= f1f03305bb67e --- /dev/null +++ b/drivers/phy/phy-inno-hdmi.c @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Common helpers for the Innosilicon HDMI PHY. + * + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * + * Author: Zheng Yang + * Author: Michal Wilczynski + * + * Derived from drivers/phy/rockchip/phy-rockchip-inno-hdmi.c. + * + * The same PHY IP is used by several SoCs, which differ in where the PHY + * register block sits and in the pixel clock table they support, but share + * the pre-PLL programming sequence. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define INNO_PRE_PLL_CONTROL 0xa0 +#define INNO_PRE_PLL_POWER_DOWN BIT(0) +#define INNO_PCLK_VCO_DIV_5_MASK BIT(1) +#define INNO_PCLK_VCO_DIV_5(x) FIELD_PREP(BIT(1), x) + +#define INNO_PRE_PLL_DIV_1 0xa1 +#define INNO_PRE_PLL_PRE_DIV_MASK GENMASK(5, 0) +#define INNO_PRE_PLL_PRE_DIV(x) FIELD_PREP(GENMASK(5, 0), x) + +#define INNO_PRE_PLL_DIV_2 0xa2 +#define INNO_SPREAD_SPECTRUM_MOD_DISABLE BIT(6) +#define INNO_PRE_PLL_FRAC_DIV_DISABLE FIELD_PREP(GENMASK(5, 4), 3) +#define INNO_PRE_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define INNO_PRE_PLL_FB_DIV_11_8(x) FIELD_PREP(GENMASK(3, 0), (x) >> 8) + +#define INNO_PRE_PLL_DIV_3 0xa3 +#define INNO_PRE_PLL_FB_DIV_7_0(x) FIELD_PREP(GENMASK(7, 0), x) + +#define INNO_PRE_PLL_TMDSCLK_DIV 0xa4 +#define INNO_PRE_PLL_TMDSCLK_DIV_C(x) FIELD_PREP(GENMASK(1, 0), x) +#define INNO_PRE_PLL_TMDSCLK_DIV_B(x) FIELD_PREP(GENMASK(3, 2), x) +#define INNO_PRE_PLL_TMDSCLK_DIV_A(x) FIELD_PREP(GENMASK(5, 4), x) + +#define INNO_PCLK_DIV_AB 0xa5 +#define INNO_PCLK_DIV_B_MASK GENMASK(6, 5) +#define INNO_PCLK_DIV_B(x) FIELD_PREP(GENMASK(6, 5), x) +#define INNO_PCLK_DIV_A_MASK GENMASK(4, 0) +#define INNO_PCLK_DIV_A(x) FIELD_PREP(GENMASK(4, 0), x) + +#define INNO_PCLK_DIV_CD 0xa6 +#define INNO_PCLK_DIV_C(x) FIELD_PREP(GENMASK(6, 5), x) +#define INNO_PCLK_DIV_D_MASK GENMASK(4, 0) +#define INNO_PCLK_DIV_D(x) FIELD_PREP(GENMASK(4, 0), x) + +#define INNO_PRE_PLL_LOCK_STATUS 0xa9 +#define INNO_PRE_PLL_LOCK BIT(0) + +#define INNO_PRE_PLL_FRAC_DIV_23_16 0xd1 +#define INNO_PRE_PLL_FRAC_DIV_15_8 0xd2 +#define INNO_PRE_PLL_FRAC_DIV_7_0 0xd3 +#define INNO_PRE_PLL_FRAC_DIV(x) FIELD_PREP(GENMASK(7, 0), x) + +#define INNO_FRAC_DIV_WIDTH 24 + +static unsigned int inno_reg(const struct inno_hdmi_phy_pre_pll *pll, + unsigned int reg) +{ + return (pll->offset + reg) * 4; +} + +static void inno_write(const struct inno_hdmi_phy_pre_pll *pll, + unsigned int reg, u8 val) +{ + regmap_write(pll->regmap, inno_reg(pll, reg), val); +} + +static u8 inno_read(const struct inno_hdmi_phy_pre_pll *pll, unsigned int = reg) +{ + unsigned int val; + int ret; + + ret =3D regmap_read(pll->regmap, inno_reg(pll, reg), &val); + if (ret) + return 0; + + return val; +} + +static void inno_update_bits(const struct inno_hdmi_phy_pre_pll *pll, + unsigned int reg, u8 mask, u8 val) +{ + regmap_update_bits(pll->regmap, inno_reg(pll, reg), mask, val); +} + +/** + * inno_hdmi_phy_pre_pll_lookup - find the settings for a pixel clock + * @pll: pre-PLL instance + * @pixclock: requested pixel clock, in Hz + * @tmdsclock: requested TMDS clock, in Hz + * + * Return: the matching table entry, or an ERR_PTR if the PHY cannot gener= ate + * the requested combination. + */ +const struct inno_hdmi_phy_pre_pll_config * +inno_hdmi_phy_pre_pll_lookup(const struct inno_hdmi_phy_pre_pll *pll, + unsigned long pixclock, unsigned long tmdsclock) +{ + const struct inno_hdmi_phy_pre_pll_config *cfg; + + for (cfg =3D pll->table; cfg->pixclock !=3D 0; cfg++) + if (cfg->pixclock =3D=3D pixclock && cfg->tmdsclock =3D=3D tmdsclock) + return cfg; + + return ERR_PTR(-EINVAL); +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_lookup); + +/** + * inno_hdmi_phy_pre_pll_determine_rate - clk_ops.determine_rate helper + * @pll: pre-PLL instance + * @req: rate request, updated with the rate the PHY would produce + * + * The PHY can only generate the pixel clocks described by its table, so a + * request that does not appear there is rejected rather than rounded. + * + * Return: 0 on success, -EINVAL if the rate is not supported. + */ +int inno_hdmi_phy_pre_pll_determine_rate(const struct inno_hdmi_phy_pre_pl= l *pll, + struct clk_rate_request *req) +{ + const struct inno_hdmi_phy_pre_pll_config *cfg; + unsigned long rate =3D rounddown(req->rate, 1000); + + for (cfg =3D pll->table; cfg->pixclock !=3D 0; cfg++) { + if (cfg->pixclock =3D=3D rate) { + req->rate =3D cfg->pixclock; + return 0; + } + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_determine_rate); + +/** + * inno_hdmi_phy_pre_pll_recalc_rate - clk_ops.recalc_rate helper + * @pll: pre-PLL instance + * @parent_rate: rate of the reference clock, in Hz + * + * Return: the pixel clock the pre-PLL is currently programmed for, in Hz. + */ +unsigned long +inno_hdmi_phy_pre_pll_recalc_rate(const struct inno_hdmi_phy_pre_pll *pll, + unsigned long parent_rate) +{ + u8 nd, no_a, no_b, no_d; + unsigned long frac, rate; + u64 vco, vco_rate; + u16 nf; + + nd =3D inno_read(pll, INNO_PRE_PLL_DIV_1) & INNO_PRE_PLL_PRE_DIV_MASK; + nf =3D (inno_read(pll, INNO_PRE_PLL_DIV_2) & + INNO_PRE_PLL_FB_DIV_11_8_MASK) << 8; + nf |=3D inno_read(pll, INNO_PRE_PLL_DIV_3); + vco =3D parent_rate * nf; + + if (!(inno_read(pll, INNO_PRE_PLL_DIV_2) & + INNO_PRE_PLL_FRAC_DIV_DISABLE)) { + frac =3D inno_read(pll, INNO_PRE_PLL_FRAC_DIV_7_0) | + (inno_read(pll, INNO_PRE_PLL_FRAC_DIV_15_8) << 8) | + (inno_read(pll, INNO_PRE_PLL_FRAC_DIV_23_16) << 16); + vco +=3D DIV_ROUND_CLOSEST(parent_rate * frac, + BIT(INNO_FRAC_DIV_WIDTH)); + } + + vco_rate =3D vco; + + if (inno_read(pll, INNO_PRE_PLL_CONTROL) & INNO_PCLK_VCO_DIV_5_MASK) { + do_div(vco, nd * 5); + } else { + no_a =3D inno_read(pll, INNO_PCLK_DIV_AB) & INNO_PCLK_DIV_A_MASK; + no_b =3D FIELD_GET(INNO_PCLK_DIV_B_MASK, + inno_read(pll, INNO_PCLK_DIV_AB)) + 2; + no_d =3D inno_read(pll, INNO_PCLK_DIV_CD) & INNO_PCLK_DIV_D_MASK; + + do_div(vco, nd * (no_a =3D=3D 1 ? no_b : no_a) * no_d * 2); + } + + rate =3D DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; + + /* The VCO is only in spec between 1.4 and 3.2 GHz, so log it. */ + dev_dbg(pll->dev, "%s rate %lu vco %llu\n", __func__, rate, vco_rate); + + return rate; +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_recalc_rate); + +/** + * inno_hdmi_phy_pre_pll_configure - program the pre-PLL dividers + * @pll: pre-PLL instance + * @cfg: settings to program + * + * The caller is responsible for powering the pre-PLL down beforehand and = back + * up afterwards, and for waiting for it to lock. + */ +void inno_hdmi_phy_pre_pll_configure(const struct inno_hdmi_phy_pre_pll *p= ll, + const struct inno_hdmi_phy_pre_pll_config *cfg) +{ + u8 val; + + inno_update_bits(pll, INNO_PRE_PLL_CONTROL, INNO_PCLK_VCO_DIV_5_MASK, + INNO_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); + inno_write(pll, INNO_PRE_PLL_DIV_1, INNO_PRE_PLL_PRE_DIV(cfg->prediv)); + + val =3D INNO_SPREAD_SPECTRUM_MOD_DISABLE; + if (!cfg->fracdiv) + val |=3D INNO_PRE_PLL_FRAC_DIV_DISABLE; + + inno_write(pll, INNO_PRE_PLL_DIV_2, + INNO_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); + inno_write(pll, INNO_PRE_PLL_DIV_3, + INNO_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); + + inno_write(pll, INNO_PCLK_DIV_AB, + INNO_PCLK_DIV_A(cfg->pclk_div_a) | + INNO_PCLK_DIV_B(cfg->pclk_div_b)); + inno_write(pll, INNO_PCLK_DIV_CD, + INNO_PCLK_DIV_C(cfg->pclk_div_c) | + INNO_PCLK_DIV_D(cfg->pclk_div_d)); + + inno_write(pll, INNO_PRE_PLL_TMDSCLK_DIV, + INNO_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | + INNO_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b) | + INNO_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c)); + + inno_write(pll, INNO_PRE_PLL_FRAC_DIV_7_0, + INNO_PRE_PLL_FRAC_DIV(cfg->fracdiv)); + inno_write(pll, INNO_PRE_PLL_FRAC_DIV_15_8, + INNO_PRE_PLL_FRAC_DIV(cfg->fracdiv >> 8)); + inno_write(pll, INNO_PRE_PLL_FRAC_DIV_23_16, + INNO_PRE_PLL_FRAC_DIV(cfg->fracdiv >> 16)); +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_configure); + +/** + * inno_hdmi_phy_pre_pll_power_down - power the pre-PLL down or up + * @pll: pre-PLL instance + * @power_down: true to power down, false to power up + */ +void inno_hdmi_phy_pre_pll_power_down(const struct inno_hdmi_phy_pre_pll *= pll, + bool power_down) +{ + inno_update_bits(pll, INNO_PRE_PLL_CONTROL, INNO_PRE_PLL_POWER_DOWN, + power_down ? INNO_PRE_PLL_POWER_DOWN : 0); +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_power_down); + +/** + * inno_hdmi_phy_pre_pll_is_locked - report whether the pre-PLL has locked + * @pll: pre-PLL instance + */ +bool inno_hdmi_phy_pre_pll_is_locked(const struct inno_hdmi_phy_pre_pll *p= ll) +{ + return inno_read(pll, INNO_PRE_PLL_LOCK_STATUS) & INNO_PRE_PLL_LOCK; +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_is_locked); + +/** + * inno_hdmi_phy_pre_pll_wait_locked - wait for the pre-PLL to lock + * @pll: pre-PLL instance + * @timeout_us: how long to wait, in microseconds + * + * Return: 0 once locked, -ETIMEDOUT otherwise. + */ +int inno_hdmi_phy_pre_pll_wait_locked(const struct inno_hdmi_phy_pre_pll *= pll, + unsigned int timeout_us) +{ + unsigned int val; + + return regmap_read_poll_timeout(pll->regmap, + inno_reg(pll, INNO_PRE_PLL_LOCK_STATUS), + val, val & INNO_PRE_PLL_LOCK, + 1000, timeout_us); +} +EXPORT_SYMBOL_GPL(inno_hdmi_phy_pre_pll_wait_locked); + +MODULE_DESCRIPTION("Innosilicon HDMI PHY common helpers"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/phy/inno-hdmi-phy.h b/include/linux/phy/inno-hdm= i-phy.h new file mode 100644 index 0000000000000000000000000000000000000000..4f243d883ea94f385b167fffd60= 2e70d3e1a3759 --- /dev/null +++ b/include/linux/phy/inno-hdmi-phy.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Common helpers for the Innosilicon HDMI PHY. + * + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * + * Author: Zheng Yang + * Author: Michal Wilczynski + * + * Derived from drivers/phy/rockchip/phy-rockchip-inno-hdmi.c. + */ + +#ifndef __PHY_INNO_HDMI_H__ +#define __PHY_INNO_HDMI_H__ + +#include + +struct clk_rate_request; +struct regmap; + +/** + * struct inno_hdmi_phy_pre_pll_config - pre-PLL settings for one pixel cl= ock + * @pixclock: pixel clock this entry describes, in Hz + * @tmdsclock: TMDS clock this entry describes, in Hz + * @prediv: pre-PLL reference divider + * @fbdiv: pre-PLL feedback divider + * @tmds_div_a: TMDS clock divider A + * @tmds_div_b: TMDS clock divider B + * @tmds_div_c: TMDS clock divider C + * @pclk_div_a: pixel clock divider A + * @pclk_div_b: pixel clock divider B + * @pclk_div_c: pixel clock divider C + * @pclk_div_d: pixel clock divider D + * @vco_div_5_en: divide the VCO output by five + * @fracdiv: pre-PLL fractional divider, zero to use integer mode + */ +struct inno_hdmi_phy_pre_pll_config { + unsigned long pixclock; + unsigned long tmdsclock; + u8 prediv; + u16 fbdiv; + u8 tmds_div_a; + u8 tmds_div_b; + u8 tmds_div_c; + u8 pclk_div_a; + u8 pclk_div_b; + u8 pclk_div_c; + u8 pclk_div_d; + u8 vco_div_5_en; + u32 fracdiv; +}; + +/** + * struct inno_hdmi_phy_pre_pll - a pre-PLL instance + * @regmap: register map covering the PHY registers + * @offset: offset of the PHY register block, in units of the register ind= ex. + * Zero where the PHY block starts the register space, 0x100 on the + * StarFive JH7110 where it is preceded by the HDMI controller. + * @table: pixel clock table, terminated by an entry with a zero pixclock + */ +struct inno_hdmi_phy_pre_pll { + struct device *dev; + struct regmap *regmap; + unsigned int offset; + const struct inno_hdmi_phy_pre_pll_config *table; +}; + +const struct inno_hdmi_phy_pre_pll_config * +inno_hdmi_phy_pre_pll_lookup(const struct inno_hdmi_phy_pre_pll *pll, + unsigned long pixclock, unsigned long tmdsclock); +int inno_hdmi_phy_pre_pll_determine_rate(const struct inno_hdmi_phy_pre_pl= l *pll, + struct clk_rate_request *req); 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Tue, 15 Sep 2026 15:32:44 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153243eusmtip1fdf9330043c1df7d97815c6e678a48ff~ViF24GFUg0616306163eusmtip1d; Tue, 15 Sep 2026 15:32:43 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:25 +0200 Subject: [PATCH v4 17/20] phy: rockchip: inno-hdmi: Use the common Innosilicon PHY helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-17-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153244eucas1p180f69e8f957a5c615d3c6a59a1c205b2 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153244eucas1p180f69e8f957a5c615d3c6a59a1c205b2 X-EPHeader: CA X-CMS-RootMailID: 20260915153244eucas1p180f69e8f957a5c615d3c6a59a1c205b2 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> The RK3328 pre-PLL programming, its table lookup and its recalc_rate and determine_rate implementations are the generic Innosilicon ones, so drop the local copies and use the shared helpers instead. The RK3228 pre-PLL sits at different register addresses, so it keeps its own register level code and only shares the table lookup. The now unused RK3328 pre-PLL register macros go with it, as does the local pre-PLL config lookup wrapper; both call sites already have the TMDS clock to hand and call inno_hdmi_phy_pre_pll_lookup() directly. The RK3328 recalc_rate used to log the pre-PLL output as "vco". The shared helper logs it too, and reports the actual VCO frequency alongside the rate, which is the value with the 1.4-3.2 GHz constraint. The register writes, their order and the values written are unchanged. No functional change intended. Signed-off-by: Michal Wilczynski Reviewed-by: Chaoyi Chen --- drivers/phy/rockchip/Kconfig | 1 + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 168 ++++------------------= ---- 2 files changed, 25 insertions(+), 144 deletions(-) diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 14698571b607590dc0e7a29f3b39eb9a5d4e3d25..9732c5be87717dc3ddbea1c6008= 0952336a07af9 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -34,6 +34,7 @@ config PHY_ROCKCHIP_INNO_HDMI depends on COMMON_CLK depends on HAS_IOMEM select GENERIC_PHY + select PHY_INNO_HDMI help Enable this to support the Rockchip Innosilicon HDMI PHY. =20 diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/ro= ckchip/phy-rockchip-inno-hdmi.c index c3d257a0f4a65b4c475ed7246568dd463b46ed86..ddd6d6858a46a77de9816d1223b= 8bfdb3f82778e 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include =20 @@ -130,42 +131,14 @@ #define RK3328_INT_VSS_AGND_ESD_DET BIT(1) #define RK3328_INT_AGND_VSS_ESD_DET BIT(0) /* REG: 0xa0 */ -#define RK3328_PCLK_VCO_DIV_5_MASK BIT(1) -#define RK3328_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1) #define RK3328_PRE_PLL_POWER_DOWN BIT(0) /* REG: 0xa1 */ -#define RK3328_PRE_PLL_PRE_DIV_MASK GENMASK(5, 0) -#define RK3328_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0) /* REG: 0xa2 */ -/* unset means center spread */ -#define RK3328_SPREAD_SPECTRUM_MOD_DOWN BIT(7) -#define RK3328_SPREAD_SPECTRUM_MOD_DISABLE BIT(6) -#define RK3328_PRE_PLL_FRAC_DIV_DISABLE UPDATE(3, 5, 4) -#define RK3328_PRE_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) -#define RK3328_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0) /* REG: 0xa3 */ -#define RK3328_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) /* REG: 0xa4*/ -#define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(1, 0) -#define RK3328_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 1, 0) -#define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2) -#define RK3328_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 3, 2) -#define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(5, 4) -#define RK3328_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 5, 4) /* REG: 0xa5 */ -#define RK3328_PRE_PLL_PCLK_DIV_B_SHIFT 5 -#define RK3328_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5) -#define RK3328_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) -#define RK3328_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0) -#define RK3328_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0) /* REG: 0xa6 */ -#define RK3328_PRE_PLL_PCLK_DIV_C_SHIFT 5 -#define RK3328_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5) -#define RK3328_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5) -#define RK3328_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0) -#define RK3328_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0) /* REG: 0xa9 */ -#define RK3328_PRE_PLL_LOCK_STATUS BIT(0) /* REG: 0xaa */ #define RK3328_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2) #define RK3328_POST_PLL_REFCLK_SEL_TMDS BIT(1) @@ -218,11 +191,8 @@ #define RK3328_TMDS_TERM_RESIST_1000 BIT(1) #define RK3328_TMDS_TERM_RESIST_2000 BIT(0) /* REG: 0xd1 */ -#define RK3328_PRE_PLL_FRAC_DIV_23_16(x) UPDATE((x) >> 16, 7, 0) /* REG: 0xd2 */ -#define RK3328_PRE_PLL_FRAC_DIV_15_8(x) UPDATE((x) >> 8, 7, 0) /* REG: 0xd3 */ -#define RK3328_PRE_PLL_FRAC_DIV_7_0(x) UPDATE(x, 7, 0) =20 struct inno_hdmi_phy_drv_data; =20 @@ -240,6 +210,8 @@ struct inno_hdmi_phy { const struct inno_hdmi_phy_drv_data *plat_data; int chip_version; =20 + struct inno_hdmi_phy_pre_pll pre_pll; + /* clk provider */ struct clk_hw hw; struct clk *phyclk; @@ -248,21 +220,6 @@ struct inno_hdmi_phy { unsigned long opts_tmds_char_rate; }; =20 -struct pre_pll_config { - unsigned long pixclock; - unsigned long tmdsclock; - u8 prediv; - u16 fbdiv; - u8 tmds_div_a; - u8 tmds_div_b; - u8 tmds_div_c; - u8 pclk_div_a; - u8 pclk_div_b; - u8 pclk_div_c; - u8 pclk_div_d; - u8 vco_div_5_en; - u32 fracdiv; -}; =20 struct post_pll_config { unsigned long tmdsclock; @@ -291,7 +248,7 @@ struct inno_hdmi_phy_drv_data { const struct phy_config *phy_cfg_table; }; =20 -static const struct pre_pll_config pre_pll_cfg_table[] =3D { +static const struct inno_hdmi_phy_pre_pll_config pre_pll_cfg_table[] =3D { { 25175000, 25175000, 3, 125, 3, 1, 1, 1, 3, 3, 4, 0, 0xe00000}, { 25175000, 31468750, 1, 41, 0, 3, 3, 1, 3, 3, 4, 0, 0xf5554f}, { 27000000, 27000000, 1, 36, 0, 3, 3, 1, 2, 3, 4, 0, 0x0}, @@ -603,7 +560,7 @@ static irqreturn_t inno_hdmi_phy_rk3328_irq(int irq, vo= id *dev_id) static int inno_hdmi_phy_validate(struct phy *phy, enum phy_mode mode, int submode, union phy_configure_opts *opts) { - const struct pre_pll_config *cfg =3D pre_pll_cfg_table; + const struct inno_hdmi_phy_pre_pll_config *cfg =3D pre_pll_cfg_table; unsigned long tmdsclock; =20 if (!(mode =3D=3D PHY_MODE_HDMI && submode =3D=3D PHY_HDMI_MODE_TMDS)) @@ -717,23 +674,6 @@ static const struct phy_ops inno_hdmi_phy_ops =3D { .validate =3D inno_hdmi_phy_validate, }; =20 -static const -struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy = *inno, - unsigned long rate) -{ - const struct pre_pll_config *cfg =3D pre_pll_cfg_table; - unsigned long tmdsclock =3D inno_hdmi_phy_get_tmdsclk(inno, rate); - - for (; cfg->pixclock !=3D 0; cfg++) - if (cfg->pixclock =3D=3D rate && cfg->tmdsclock =3D=3D tmdsclock) - break; - - if (cfg->pixclock =3D=3D 0) - return ERR_PTR(-EINVAL); - - return cfg; -} - static int inno_hdmi_phy_rk3228_clk_is_prepared(struct clk_hw *hw) { struct inno_hdmi_phy *inno =3D to_inno_hdmi_phy(hw); @@ -797,7 +737,7 @@ unsigned long inno_hdmi_phy_rk3228_clk_recalc_rate(stru= ct clk_hw *hw, static int inno_hdmi_phy_rk3228_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - const struct pre_pll_config *cfg =3D pre_pll_cfg_table; + const struct inno_hdmi_phy_pre_pll_config *cfg =3D pre_pll_cfg_table; =20 req->rate =3D (req->rate / 1000) * 1000; =20 @@ -818,7 +758,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk= _hw *hw, unsigned long parent_rate) { struct inno_hdmi_phy *inno =3D to_inno_hdmi_phy(hw); - const struct pre_pll_config *cfg; + const struct inno_hdmi_phy_pre_pll_config *cfg; unsigned long tmdsclock =3D inno_hdmi_phy_get_tmdsclk(inno, rate); u32 v; int ret; @@ -829,7 +769,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk= _hw *hw, if (inno->pixclock =3D=3D rate && inno->tmdsclock =3D=3D tmdsclock) return 0; =20 - cfg =3D inno_hdmi_phy_get_pre_pll_cfg(inno, rate); + cfg =3D inno_hdmi_phy_pre_pll_lookup(&inno->pre_pll, rate, tmdsclock); if (IS_ERR(cfg)) return PTR_ERR(cfg); =20 @@ -915,39 +855,9 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(str= uct clk_hw *hw, unsigned long parent_rate) { struct inno_hdmi_phy *inno =3D to_inno_hdmi_phy(hw); - unsigned long frac; - u8 nd, no_a, no_b, no_d; - u64 vco; - u16 nf; - - nd =3D inno_read(inno, 0xa1) & RK3328_PRE_PLL_PRE_DIV_MASK; - nf =3D ((inno_read(inno, 0xa2) & RK3328_PRE_PLL_FB_DIV_11_8_MASK) << 8); - nf |=3D inno_read(inno, 0xa3); - vco =3D parent_rate * nf; - - if (!(inno_read(inno, 0xa2) & RK3328_PRE_PLL_FRAC_DIV_DISABLE)) { - frac =3D inno_read(inno, 0xd3) | - (inno_read(inno, 0xd2) << 8) | - (inno_read(inno, 0xd1) << 16); - vco +=3D DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); - } - - if (inno_read(inno, 0xa0) & RK3328_PCLK_VCO_DIV_5_MASK) { - do_div(vco, nd * 5); - } else { - no_a =3D inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_A_MASK; - no_b =3D inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK; - no_b >>=3D RK3328_PRE_PLL_PCLK_DIV_B_SHIFT; - no_b +=3D 2; - no_d =3D inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK; - - do_div(vco, (nd * (no_a =3D=3D 1 ? no_b : no_a) * no_d * 2)); - } =20 - inno->pixclock =3D DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; - - dev_dbg(inno->dev, "%s rate %lu vco %llu\n", - __func__, inno->pixclock, vco); + inno->pixclock =3D inno_hdmi_phy_pre_pll_recalc_rate(&inno->pre_pll, + parent_rate); =20 return inno->pixclock; } @@ -955,20 +865,9 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(str= uct clk_hw *hw, static int inno_hdmi_phy_rk3328_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - const struct pre_pll_config *cfg =3D pre_pll_cfg_table; - - req->rate =3D (req->rate / 1000) * 1000; - - for (; cfg->pixclock !=3D 0; cfg++) - if (cfg->pixclock =3D=3D req->rate) - break; - - if (cfg->pixclock =3D=3D 0) - return -EINVAL; - - req->rate =3D cfg->pixclock; + struct inno_hdmi_phy *inno =3D to_inno_hdmi_phy(hw); =20 - return 0; + return inno_hdmi_phy_pre_pll_determine_rate(&inno->pre_pll, req); } =20 static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, @@ -976,9 +875,8 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk= _hw *hw, unsigned long parent_rate) { struct inno_hdmi_phy *inno =3D to_inno_hdmi_phy(hw); - const struct pre_pll_config *cfg; + const struct inno_hdmi_phy_pre_pll_config *cfg; unsigned long tmdsclock =3D inno_hdmi_phy_get_tmdsclk(inno, rate); - u32 val; int ret; =20 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", @@ -987,39 +885,15 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct c= lk_hw *hw, if (inno->pixclock =3D=3D rate && inno->tmdsclock =3D=3D tmdsclock) return 0; =20 - cfg =3D inno_hdmi_phy_get_pre_pll_cfg(inno, rate); + cfg =3D inno_hdmi_phy_pre_pll_lookup(&inno->pre_pll, rate, tmdsclock); if (IS_ERR(cfg)) return PTR_ERR(cfg); =20 - inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, - RK3328_PRE_PLL_POWER_DOWN); + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); + inno_hdmi_phy_pre_pll_configure(&inno->pre_pll, cfg); + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, false); =20 - /* Configure pre-pll */ - inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK, - RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); - inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); - - val =3D RK3328_SPREAD_SPECTRUM_MOD_DISABLE; - if (!cfg->fracdiv) - val |=3D RK3328_PRE_PLL_FRAC_DIV_DISABLE; - inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); - inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); - inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) | - RK3328_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b)); - inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | - RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d)); - inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | - RK3328_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | - RK3328_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b)); - inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv)); - inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv)); - inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv)); - - inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0); - - /* Wait for Pre-PLL lock */ - ret =3D inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS, - 1000, 10000); + ret =3D inno_hdmi_phy_pre_pll_wait_locked(&inno->pre_pll, 10000); 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Tue, 15 Sep 2026 15:32:46 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153244eusmtip158e2b395c869d805da213fe3dbd3a489~ViF4jklDo0604306043eusmtip1l; Tue, 15 Sep 2026 15:32:44 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:26 +0200 Subject: [PATCH v4 18/20] phy: starfive: Add jh7110-inno-hdmi-phy driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-18-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153246eucas1p289987fd8757c89ff865c99b6465708a8 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153246eucas1p289987fd8757c89ff865c99b6465708a8 X-EPHeader: CA X-CMS-RootMailID: 20260915153246eucas1p289987fd8757c89ff865c99b6465708a8 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> Add the HDMI PHY driver for the StarFive JH7110. This driver binds to the starfive,jh7110-inno-hdmi-phy node and gets its regmap from the parent. It has no dependencies on voutcrg, only on its reference oscillator (xin24m), which breaks the probe-time circular dependency. This driver provides two main functions: - Clock Provider: It registers clk_ops to provide the variable pixel clock. The .set_rate operation configures the Pre-PLL registers (0x1a0+) based on the requested rate. - PHY Provider: It registers phy_ops for the controller. The .power_on op configures and enables the Post-PLL and other analog blocks (BIAS, LDO, Serializer, etc.). The clock ops reach registers in the window shared with the HDMI controller, and access to that window is gated by the controller's system clock, which only the sibling controller driver holds. The clock framework walks every registered clock regardless of which drivers have bound, so deliberately do not implement .is_prepared, which lets the framework fall back to the software prepare count, and return the cached rate from .recalc_rate whenever the clock is not prepared. Without this, clk_disable_unused() reads a PHY register with that clock gated and the resulting stalled bus transaction wedges the CPU hard enough that it stops responding to NMIs. It is reproducible by building the bridge driver as a module so that the controller has not bound by then. The JH7110 instantiates the same Innosilicon IP as the Rockchip RK3328, with the PHY register block shifted by 0x100 because it sits behind the HDMI controller in the shared register space. The pre-PLL programming therefore comes from the common Innosilicon helpers; this driver adds the JH7110 pixel clock table, the post-PLL and the analog configuration. Co-developed-by: Dominique Belhachemi Signed-off-by: Dominique Belhachemi Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- drivers/phy/starfive/Kconfig | 20 + drivers/phy/starfive/Makefile | 1 + drivers/phy/starfive/phy-jh7110-inno-hdmi.c | 579 ++++++++++++++++++++++++= ++++ 3 files changed, 600 insertions(+) diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig index d0cdd7cb4a13de22ff643c89a79d99cce57284d7..1da417ffbf224c13224e42a3ce3= 22e3d0c272824 100644 --- a/drivers/phy/starfive/Kconfig +++ b/drivers/phy/starfive/Kconfig @@ -25,6 +25,26 @@ config PHY_STARFIVE_JH7110_DPHY_TX system. If M is selected, the module will be called phy-jh7110-dphy-tx.ko. =20 +config PHY_STARFIVE_JH7110_INNO_HDMI + tristate "Starfive JH7110 INNO HDMI PHY" + select PHY_INNO_HDMI + depends on COMMON_CLK + select GENERIC_PHY + help + This option enables the driver for the analog HDMI PHY (Physical + Layer) on the StarFive JH7110 SoC. + + This driver binds to a child node of the 'starfive,jh7110-hdmi-subsyste= m' + parent driver and gets its register map from that parent. + + It is responsible for two main functions: + 1. PHY Provider: It provides standard PHY operations (.power_on, + .power_off) for the HDMI controller (bridge) driver. This + involves configuring the Post-PLL and analog TMDS blocks. + 2. Clock Provider: It registers as a clock provider to supply the + variable pixel clock (hdmi_pclk) to the HDMI controller and + the VOUT subsystem, which it generates using the Pre-PLL. + config PHY_STARFIVE_JH7110_PCIE tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support" depends on HAS_IOMEM diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile index eedc4a6fec156320c99ac0a0da609083b6a6a695..e7b13f00880b500f933f21b6037= 384d5c6884e3e 100644 --- a/drivers/phy/starfive/Makefile +++ b/drivers/phy/starfive/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_RX) +=3D phy-jh7110-dphy-rx.o obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_TX) +=3D phy-jh7110-dphy-tx.o +obj-$(CONFIG_PHY_STARFIVE_JH7110_INNO_HDMI) +=3D phy-jh7110-inno-hdmi.o obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) +=3D phy-jh7110-pcie.o obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) +=3D phy-jh7110-usb.o diff --git a/drivers/phy/starfive/phy-jh7110-inno-hdmi.c b/drivers/phy/star= five/phy-jh7110-inno-hdmi.c new file mode 100644 index 0000000000000000000000000000000000000000..2575cb5ed624a82dddd485d3ebd= 83c846b6a3602 --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-inno-hdmi.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * + * Author: Zheng Yang + * Author: Michal Wilczynski + * + * The register layout and programming sequence derive from + * drivers/phy/rockchip/phy-rockchip-inno-hdmi.c; the JH7110 places the + * same Innosilicon PHY block at a 0x100 register offset. + * + * This driver handles the PHY portion of the StarFive Innosilicon HDMI IP, + * which is part of a monolithic HDMI block. It provides the variable pixel + * clock (from the Pre-PLL) and the PHY operations (for the Post-PLL/analo= g). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * StarFive (JH7110) Innosilicon HDMI PHY Register Definitions + */ + +/* REG: 0x1aa */ +#define STF_INNO_POST_PLL_DIV_1 0x1aa +#define STF_INNO_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2) +#define STF_INNO_POST_PLL_REFCLK_SEL_TMDS BIT(1) +#define STF_INNO_POST_PLL_POWER_DOWN BIT(0) + +/* REG: 0x1ab */ +#define STF_INNO_POST_PLL_DIV_2 0x1ab +#define STF_INNO_POST_PLL_PRE_DIV(x) FIELD_PREP(GENMASK(5, 0), x) +#define STF_INNO_POST_PLL_FB_DIV_8(x) FIELD_PREP(BIT(7), (x) >> 8) + +/* REG: 0x1ac */ +#define STF_INNO_POST_PLL_DIV_3 0x1ac +#define STF_INNO_POST_PLL_FB_DIV_7_0(x) FIELD_PREP(GENMASK(7, 0), x) + +/* REG: 0x1ad */ +#define STF_INNO_POST_PLL_DIV_4 0x1ad +#define STF_INNO_POST_PLL_POST_DIV_MASK GENMASK(1, 0) + +/* REG: 0x1af */ +#define STF_INNO_POST_PLL_LOCK_STATUS 0x1af +#define STF_INNO_POST_PLL_LOCK BIT(0) + +/* REG: 0x1b0 */ +#define STF_INNO_BIAS_CONTROL 0x1b0 +#define STF_INNO_BIAS_ENABLE BIT(2) + +/* REG: 0x1b2 */ +#define STF_INNO_TMDS_CONTROL 0x1b2 +#define STF_INNO_TMDS_CLK_DRIVER_EN BIT(3) +#define STF_INNO_TMDS_D2_DRIVER_EN BIT(2) +#define STF_INNO_TMDS_D1_DRIVER_EN BIT(1) +#define STF_INNO_TMDS_D0_DRIVER_EN BIT(0) +#define STF_INNO_TMDS_DRIVER_ENABLE (STF_INNO_TMDS_CLK_DRIVER_EN | \ + STF_INNO_TMDS_D2_DRIVER_EN | \ + STF_INNO_TMDS_D1_DRIVER_EN | \ + STF_INNO_TMDS_D0_DRIVER_EN) + +/* REG: 0x1b4 */ +#define STF_INNO_LDO_CONTROL 0x1b4 +#define STF_INNO_LDO_ENABLE (BIT(2) | BIT(1) | BIT(0)) + +/* REG: 0x1be */ +#define STF_INNO_SERIALIER_CONTROL 0x1be +#define STF_INNO_SERIALIER_ENABLE (BIT(6) | BIT(5) | BIT(4) | BIT(0)) + +/* REG: 0x1cc */ +#define STF_INNO_RX_CONTROL 0x1cc +#define STF_INNO_RX_ENABLE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) + +/* + * These tables are copied from the monolithic driver. + * They match the Rockchip PHY driver tables. + */ + +struct post_pll_config { + unsigned long tmdsclock; + u8 prediv; + u16 fbdiv; + u8 postdiv; + u8 post_div_en; +}; + +static const struct inno_hdmi_phy_pre_pll_config pre_pll_cfg_table[] =3D { + { 25175000, 25175000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0xF55555 }, + { 25200000, 25200000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0 }, + { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0 }, + { 27027000, 27027000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0x170A3D }, + { 28320000, 28320000, 1, 28, 2, 1, 1, 3, 0, 3, 4, 0, 0x51EB85 }, + { 30240000, 30240000, 1, 30, 2, 1, 1, 3, 0, 3, 4, 0, 0x3D70A3 }, + { 31500000, 31500000, 1, 31, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 33750000, 33750000, 1, 33, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 36000000, 36000000, 1, 36, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0 }, + { 46970000, 46970000, 1, 46, 2, 1, 1, 3, 0, 3, 4, 0, 0xF851EB }, + { 49500000, 49500000, 1, 49, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 49000000, 49000000, 1, 49, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 50000000, 50000000, 1, 50, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 54000000, 54000000, 1, 54, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 54054000, 54054000, 1, 54, 2, 1, 1, 3, 0, 3, 4, 0, 0x0DD2F1 }, + { 57284000, 57284000, 1, 57, 2, 1, 1, 3, 0, 3, 4, 0, 0x48B439 }, + { 58230000, 58230000, 1, 58, 2, 1, 1, 3, 0, 3, 4, 0, 0x3AE147 }, + { 59341000, 59341000, 1, 59, 2, 1, 1, 3, 0, 3, 4, 0, 0x574BC6 }, + { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0 }, + { 65000000, 65000000, 1, 130, 2, 2, 2, 12, 0, 2, 2, 0, 0 }, + { 68250000, 68250000, 1, 68, 2, 1, 1, 3, 0, 3, 4, 0, 0x3FFFFF }, + { 71000000, 71000000, 1, 71, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B }, + { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0 }, + { 75000000, 75000000, 1, 75, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 78750000, 78750000, 1, 78, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 79500000, 79500000, 1, 79, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0 }, + { 83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000 }, + { 85500000, 85500000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 85750000, 85750000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 85800000, 85800000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xCCCCCC }, + { 88750000, 88750000, 1, 88, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 89910000, 89910000, 1, 89, 2, 1, 1, 3, 0, 3, 4, 0, 0xE8F5C1 }, + { 90000000, 90000000, 1, 90, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 101000000, 101000000, 1, 101, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 102250000, 102250000, 1, 102, 2, 1, 1, 3, 0, 3, 4, 0, 0x3FFFFF }, + { 106500000, 106500000, 1, 106, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 108000000, 108000000, 1, 90, 3, 0, 0, 5, 0, 2, 2, 0, 0 }, + { 119000000, 119000000, 1, 119, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 131481000, 131481000, 1, 131, 2, 1, 1, 3, 0, 3, 4, 0, 0x7B22D1 }, + { 135000000, 135000000, 1, 135, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 136750000, 136750000, 1, 136, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 147180000, 147180000, 1, 147, 2, 1, 1, 3, 0, 3, 4, 0, 0x2E147A }, + { 148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B }, + { 148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0 }, + { 154000000, 154000000, 1, 154, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 156000000, 156000000, 1, 156, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 157000000, 157000000, 1, 157, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 162000000, 162000000, 1, 162, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 174250000, 174250000, 1, 145, 3, 0, 0, 5, 0, 2, 2, 0, 0x355555 }, + { 174500000, 174500000, 1, 174, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 174570000, 174570000, 1, 174, 2, 1, 1, 3, 0, 3, 4, 0, 0x91EB84 }, + { 175500000, 175500000, 1, 175, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 185590000, 185590000, 1, 185, 2, 1, 1, 3, 0, 3, 4, 0, 0x970A3C }, + { 187000000, 187000000, 1, 187, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 235690000, 235690000, 1, 235, 2, 1, 1, 3, 0, 3, 4, 0, 0xB0A3D6 }, + { 241500000, 241500000, 1, 161, 1, 1, 1, 4, 0, 2, 2, 0, 0 }, + { 241700000, 241700000, 1, 241, 2, 1, 1, 3, 0, 3, 4, 0, 0xB33332 }, + { 262750000, 262750000, 1, 262, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 296500000, 296500000, 1, 296, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B }, + { 297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0 }, + { 594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +}; + +static const struct post_pll_config post_pll_cfg_table[] =3D { + { 25200000, 1, 80, 13, 3 }, + { 27000000, 1, 40, 11, 3 }, + { 27027000, 1, 40, 11, 3 }, + { 33750000, 1, 40, 11, 3 }, + { 49000000, 1, 20, 1, 3 }, + { 65000000, 1, 20, 1, 3 }, + { 74250000, 1, 20, 1, 3 }, + { 88750000, 1, 20, 1, 3 }, + { 108000000, 1, 20, 1, 3 }, + { 148500000, 1, 20, 1, 3 }, + { 162000000, 1, 20, 1, 3 }, + { 174250000, 1, 20, 1, 3 }, + { 187000000, 1, 20, 1, 3 }, + { 241700000, 1, 20, 1, 3 }, + { 297000000, 4, 20, 0, 0 }, + { 594000000, 4, 20, 0, 0 }, /* postpll_postdiv_en =3D 0 */ + { /* sentinel */ } +}; + +struct starfive_hdmi_phy { + struct device *dev; + struct regmap *regmap; + struct phy *phy; + struct clk *refoclk; + + struct inno_hdmi_phy_pre_pll pre_pll; + + struct clk_hw hw; + struct clk *phyclk; + unsigned long pixclock; + unsigned long tmdsclock; +}; + +static inline void inno_write(struct starfive_hdmi_phy *inno, u32 reg, u8 = val) +{ + regmap_write(inno->regmap, reg * 4, val); +} + +static inline u8 inno_read(struct starfive_hdmi_phy *inno, u32 reg) +{ + u32 val; + + regmap_read(inno->regmap, reg * 4, &val); + return val; +} + +static inline void inno_update_bits(struct starfive_hdmi_phy *inno, u16 re= g, + u8 mask, u8 val) +{ + regmap_update_bits(inno->regmap, reg * 4, mask, val); +} + +#define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \ + regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \ + sleep_us, timeout_us) + +static inline struct starfive_hdmi_phy *to_starfive_hdmi_phy(struct clk_hw= *hw) +{ + return container_of(hw, struct starfive_hdmi_phy, hw); +} + +static int starfive_hdmi_phy_clk_prepare(struct clk_hw *hw) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + int ret; + + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, false); + + if (inno_hdmi_phy_pre_pll_is_locked(&inno->pre_pll)) + return 0; + + ret =3D inno_hdmi_phy_pre_pll_wait_locked(&inno->pre_pll, 100000); + if (ret) { + dev_err(inno->dev, "Timeout waiting for pre-PLL lock\n"); + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); + return ret; + } + + return 0; +} + +static void starfive_hdmi_phy_clk_unprepare(struct clk_hw *hw) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); + inno->pixclock =3D 0; /* Invalidate cached rate */ +} + +static unsigned long starfive_hdmi_phy_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + + /* + * Reading the PLL back requires the HDMI controller's system clock, + * which the sibling controller driver holds and this driver cannot + * request without creating a probe cycle with voutcrg. The clock + * framework walks every registered clock regardless of which drivers + * have bound, so fall back to the cached rate whenever this clock is + * not prepared; an unclocked access to the shared register window + * wedges the bus hard enough that the CPU stops taking NMIs. + */ + if (!clk_hw_is_prepared(hw)) + return inno->pixclock; + + inno->pixclock =3D inno_hdmi_phy_pre_pll_recalc_rate(&inno->pre_pll, + parent_rate); + + return inno->pixclock; +} + +static int starfive_hdmi_phy_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + + return inno_hdmi_phy_pre_pll_determine_rate(&inno->pre_pll, req); +} + +static int starfive_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long= rate, + unsigned long parent_rate) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + const struct inno_hdmi_phy_pre_pll_config *cfg; + + /* + * The JH7110 only drives 8bpc, so the TMDS clock always matches the + * pixel clock. + */ + cfg =3D inno_hdmi_phy_pre_pll_lookup(&inno->pre_pll, rate, rate); + if (IS_ERR(cfg)) + return PTR_ERR(cfg); + + dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", + __func__, rate, cfg->tmdsclock); + + if (inno->pixclock =3D=3D rate && inno->tmdsclock =3D=3D cfg->tmdsclock) + return 0; + + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, + STF_INNO_BIAS_ENABLE, STF_INNO_BIAS_ENABLE); + inno_write(inno, STF_INNO_RX_CONTROL, STF_INNO_RX_ENABLE); + + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); + inno_hdmi_phy_pre_pll_configure(&inno->pre_pll, cfg); + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, false); + + inno->pixclock =3D rate; + inno->tmdsclock =3D cfg->tmdsclock; + + return 0; +} + +static const struct clk_ops starfive_hdmi_phy_clk_ops =3D { + .prepare =3D starfive_hdmi_phy_clk_prepare, + .unprepare =3D starfive_hdmi_phy_clk_unprepare, + .recalc_rate =3D starfive_hdmi_phy_clk_recalc_rate, + .determine_rate =3D starfive_hdmi_phy_clk_determine_rate, + .set_rate =3D starfive_hdmi_phy_clk_set_rate, +}; + +static void starfive_hdmi_phy_power_down(struct starfive_hdmi_phy *inno) +{ + inno_write(inno, STF_INNO_TMDS_CONTROL, 0x00); + inno_write(inno, STF_INNO_SERIALIER_CONTROL, 0x00); + inno_write(inno, STF_INNO_LDO_CONTROL, 0x00); + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, + STF_INNO_BIAS_ENABLE, 0x00); + inno_write(inno, STF_INNO_RX_CONTROL, 0x00); + + /* Power down Post-PLL */ + inno_update_bits(inno, STF_INNO_POST_PLL_DIV_1, + STF_INNO_POST_PLL_POWER_DOWN, + STF_INNO_POST_PLL_POWER_DOWN); + + inno->tmdsclock =3D 0; + inno->pixclock =3D 0; +} + +static int starfive_hdmi_phy_power_on(struct phy *phy) +{ + struct starfive_hdmi_phy *inno =3D phy_get_drvdata(phy); + const struct post_pll_config *cfg =3D post_pll_cfg_table; + const struct inno_hdmi_phy_pre_pll_config *pre_cfg; + unsigned long tmdsclock; + u8 reg_1ad_value; + u8 reg_1aa_value; + + u32 v; + int ret; + + tmdsclock =3D clk_get_rate(inno->phyclk); + pre_cfg =3D inno_hdmi_phy_pre_pll_lookup(&inno->pre_pll, tmdsclock, + tmdsclock); + if (IS_ERR(pre_cfg)) { + dev_err(inno->dev, "no pre-PLL config for current pixel clock\n"); + return PTR_ERR(pre_cfg); + } + tmdsclock =3D pre_cfg->tmdsclock; + inno->tmdsclock =3D tmdsclock; + + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, + STF_INNO_BIAS_ENABLE, STF_INNO_BIAS_ENABLE); + inno_write(inno, STF_INNO_RX_CONTROL, STF_INNO_RX_ENABLE); + + /* Find Post-PLL config */ + for (; cfg->tmdsclock !=3D 0; cfg++) + if (tmdsclock <=3D cfg->tmdsclock) + break; + + if (cfg->tmdsclock =3D=3D 0) { + dev_err(inno->dev, "Failed to find Post-PLL config\n"); + ret =3D -EINVAL; + goto err_power_down; + } + dev_dbg(inno->dev, "Inno HDMI PHY Power On: pixclk %lu, tmdsclk %lu\n", + inno->pixclock, tmdsclock); + + reg_1ad_value =3D cfg->post_div_en ? cfg->postdiv : 0x00; + reg_1aa_value =3D cfg->post_div_en ? 0x0e : 0x02; + + /* + * Pre-PLL is already prepared and running at inno->pixclock + * via the clk_set_rate and prepare calls from the controller/bridge. + * Now, configure and enable the Post-PLL and TMDS outputs. + */ + + inno_write(inno, STF_INNO_POST_PLL_DIV_2, + STF_INNO_POST_PLL_PRE_DIV(cfg->prediv)); + inno_write(inno, STF_INNO_POST_PLL_DIV_3, cfg->fbdiv & 0xff); + inno_write(inno, STF_INNO_POST_PLL_DIV_4, reg_1ad_value); + + /* Power up Post-PLL */ + inno_write(inno, STF_INNO_POST_PLL_DIV_1, reg_1aa_value); + + /* Wait for post PLL lock */ + ret =3D inno_poll(inno, STF_INNO_POST_PLL_LOCK_STATUS, v, + v & STF_INNO_POST_PLL_LOCK, 1000, 100000); + if (ret) { + dev_err(inno->dev, "Post-PLL locking failed\n"); + goto err_power_down; + } + + inno_write(inno, STF_INNO_LDO_CONTROL, STF_INNO_LDO_ENABLE); + inno_write(inno, STF_INNO_SERIALIER_CONTROL, + STF_INNO_SERIALIER_ENABLE); + inno_write(inno, STF_INNO_TMDS_CONTROL, 0x8f); + + return 0; + + /* + * The PHY core leaves power_count at zero when .power_on fails and + * never calls .power_off, so undo the blocks enabled above here. + */ +err_power_down: + starfive_hdmi_phy_power_down(inno); + return ret; +} + +static int starfive_hdmi_phy_power_off(struct phy *phy) +{ + struct starfive_hdmi_phy *inno =3D phy_get_drvdata(phy); + + dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); + + starfive_hdmi_phy_power_down(inno); + + return 0; +} + +static const struct phy_ops starfive_hdmi_phy_ops =3D { + .owner =3D THIS_MODULE, + .power_on =3D starfive_hdmi_phy_power_on, + .power_off =3D starfive_hdmi_phy_power_off, +}; + +static int starfive_hdmi_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device *parent =3D dev->parent; + struct starfive_hdmi_phy *inno; + struct phy_provider *phy_provider; + struct regmap *regmap; + struct clk_init_data init =3D {}; + const char *refoclk_name; + int ret; + + inno =3D devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL); + if (!inno) + return -ENOMEM; + + inno->dev =3D dev; + + /* Get the regmap from the parent device */ + regmap =3D dev_get_regmap(parent, NULL); + if (!regmap) { + dev_err(dev, "Failed to get parent regmap\n"); + return -ENODEV; + } + inno->regmap =3D regmap; + + /* + * The PHY block sits behind the HDMI controller in the shared register + * space, so the common pre-PLL helpers need a 0x100 register offset. + */ + inno->pre_pll.dev =3D dev; + inno->pre_pll.regmap =3D regmap; + inno->pre_pll.offset =3D 0x100; + inno->pre_pll.table =3D pre_pll_cfg_table; + + /* Get the input reference clock */ + inno->refoclk =3D devm_clk_get(inno->dev, NULL); + if (IS_ERR(inno->refoclk)) { + ret =3D PTR_ERR(inno->refoclk); + dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n", + ret); + return ret; + } + + /* We must prepare/enable refoclk here so .set_rate/.recalc_rate work */ + ret =3D clk_prepare_enable(inno->refoclk); + if (ret) { + dev_err(dev, "Failed to enable refoclk: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, inno); + + /* Initialize and register the clock provider */ + refoclk_name =3D __clk_get_name(inno->refoclk); + init.parent_names =3D &refoclk_name; + init.num_parents =3D 1; + init.flags =3D 0; + init.name =3D "hdmi_pclk"; + init.ops =3D &starfive_hdmi_phy_clk_ops; + + inno->hw.init =3D &init; + inno->phyclk =3D devm_clk_register(dev, &inno->hw); + if (IS_ERR(inno->phyclk)) { + ret =3D PTR_ERR(inno->phyclk); + dev_err(dev, "Failed to register clock provider: %d\n", ret); + goto err_disable_refoclk; + } + + ret =3D of_clk_add_provider(dev->of_node, of_clk_src_simple_get, inno->ph= yclk); + if (ret) { + dev_err(dev, "Failed to add clock provider: %d\n", ret); + goto err_disable_refoclk; + } + + ret =3D clk_set_rate(inno->phyclk, 297000000); + if (ret) { + dev_err(dev, "Failed to set default rate: %d\n", ret); + goto err_del_clk_provider; + } + + /* Create and register the PHY provider */ + inno->phy =3D devm_phy_create(inno->dev, NULL, &starfive_hdmi_phy_ops); + if (IS_ERR(inno->phy)) { + ret =3D PTR_ERR(inno->phy); + dev_err(inno->dev, "failed to create HDMI PHY: %d\n", ret); + goto err_del_clk_provider; + } + + phy_set_drvdata(inno->phy, inno); + + phy_provider =3D devm_of_phy_provider_register(inno->dev, + of_phy_simple_xlate); + ret =3D PTR_ERR_OR_ZERO(phy_provider); + if (ret) + goto err_del_clk_provider; + + return 0; + +err_del_clk_provider: + of_clk_del_provider(dev->of_node); +err_disable_refoclk: + clk_disable_unprepare(inno->refoclk); + return ret; +} + +static void starfive_hdmi_phy_remove(struct platform_device *pdev) +{ + struct starfive_hdmi_phy *inno =3D platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + clk_disable_unprepare(inno->refoclk); +} + +static const struct of_device_id starfive_hdmi_phy_of_match[] =3D { + { .compatible =3D "starfive,jh7110-inno-hdmi-phy", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_hdmi_phy_of_match); + +static struct platform_driver starfive_hdmi_phy_driver =3D { + .probe =3D starfive_hdmi_phy_probe, + .remove =3D starfive_hdmi_phy_remove, + .driver =3D { + .name =3D "starfive-inno-hdmi-phy", + .of_match_table =3D starfive_hdmi_phy_of_match, + }, +}; +module_platform_driver(starfive_hdmi_phy_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("StarFive JH7110 Innosilicon HDMI PHY Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Sep 25 07:23:40 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ED304AFE17; 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Tue, 15 Sep 2026 15:32:48 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153246eusmtip15edfba0ffcf3bb630f485eee3d586fff~ViF6Obsuy0441604416eusmtip1t; Tue, 15 Sep 2026 15:32:46 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:27 +0200 Subject: [PATCH v4 19/20] riscv: dts: starfive: jh7110: Update DT for display subsystem Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-19-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153248eucas1p27d8d2c9fa536bbd951e0102b04416dad X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153248eucas1p27d8d2c9fa536bbd951e0102b04416dad X-EPHeader: CA X-CMS-RootMailID: 20260915153248eucas1p27d8d2c9fa536bbd951e0102b04416dad References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> Activate the display subsystem by describing the video output subsystem, which the documentation calls dom_vout_top, as a bus node covering the whole 0x29400000 region, with dc8200, the HDMI block, the video output system controller and voutcrg as its children. The subsystem node owns the resources its children share: the NoC display bus clock and reset that gate access to every register in the region, and the PD_VOUT power domain. Modelling it this way keeps a shared gate owned by the block that shares it rather than by whichever consumer happens to probe first, and lets dc8200 inherit dma-noncoherent for framebuffer DMA from the bus it sits on. The monolithic hdmi node is in turn modelled as a container with hdmi_phy and hdmi_controller children. This lets the PHY (clock provider, depending only on xin24m) and the controller (clock consumer) probe independently, breaking the circular clock dependency with voutcrg. voutcrg consumes the pixel clock from the &hdmi_phy node instead of the old fixed-clock, and dc8200 gets its pixel clocks from voutcrg's MUXes. The old, incorrect hdmitx0-pixel-clock fixed-clock node is removed. The HDMI controller gets a phandle to the video output system controller, which holds the mux selecting the DC8200 output that drives the HDMI transmitter. CMA is enlarged and constrained to memory the display controller can address, because the default pool is too small for its framebuffers. Co-developed-by: Dominique Belhachemi Signed-off-by: Dominique Belhachemi Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 121 ++++++++++++++++++++= +++- arch/riscv/boot/dts/starfive/jh7110.dtsi | 105 ++++++++++++++++---- 2 files changed, 203 insertions(+), 23 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7110-common.dtsi index a7a1c09a2c9075711f3a214a49618911fdc7b421..a4c3daf712a63b177f744e8c613= 416d22e0c9dbd 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -33,6 +33,27 @@ memory@40000000 { bootph-pre-ram; }; =20 + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * The display controller allocates its framebuffers from CMA, + * and the default pool is too small for them. Keep the pool + * inside the range the controller can address; it fits in the + * memory every VisionFive 2 variant has. + */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x0 0x20000000>; + alignment =3D <0x0 0x1000>; + alloc-ranges =3D <0x0 0x70000000 0x0 0x20000000>; + linux,cma-default; + }; + }; + gpio-restart { compatible =3D "gpio-restart"; gpios =3D <&sysgpio 35 GPIO_ACTIVE_HIGH>; @@ -73,12 +94,47 @@ codec { }; }; }; + + hdmi-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; }; =20 &cpus { timebase-frequency =3D <4000000>; }; =20 +&dc8200 { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_port0: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_out_dpi0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_in>; + }; + }; + + dpu_port1: port@1 { + reg =3D <1>; + }; + }; +}; + &dvp_clk { clock-frequency =3D <74250000>; }; @@ -99,8 +155,31 @@ &gmac1_rmii_refin { clock-frequency =3D <50000000>; }; =20 -&hdmitx0_pixelclk { - clock-frequency =3D <297000000>; +&hdmi_controller { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_pins>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi_in: endpoint { + remote-endpoint =3D <&dpu_out_dpi0>; + }; + }; + + hdmi_out_port: port@1 { + reg =3D <1>; + + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + }; + }; }; =20 &i2srx_bclk_ext { @@ -351,6 +430,40 @@ &syscrg { }; =20 &sysgpio { + hdmi_pins: hdmi-0 { + hdmi-cec-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + hdmi-hpd-pins { + pinmux =3D ; + input-enable; + bias-disable; /* external pull-up */ + }; + + hdmi-scl-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + hdmi-sda-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-0 { i2c-pins { pinmux =3D ; }; + +&voutcrg { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 9c3e4598747eb5541effe697044484715569a285..bc2470963520eef30d7524370fc= b013f0631f509 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -290,12 +290,6 @@ gmac1_rmii_refin: gmac1-rmii-refin-clock { #clock-cells =3D <0>; }; =20 - hdmitx0_pixelclk: hdmitx0-pixel-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "hdmitx0_pixelclk"; - #clock-cells =3D <0>; - }; - i2srx_bclk_ext: i2srx-bclk-ext-clock { compatible =3D "fixed-clock"; clock-output-names =3D "i2srx_bclk_ext"; @@ -352,6 +346,13 @@ tdm_ext: tdm-ext-clock { #clock-cells =3D <0>; }; =20 + xin24m: xin24m-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "xin24m"; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -1199,22 +1200,84 @@ csi_phy: phy@19820000 { #phy-cells =3D <0>; }; =20 - voutcrg: clock-controller@295c0000 { - compatible =3D "starfive,jh7110-voutcrg"; - reg =3D <0x0 0x295c0000 0x0 0x10000>; - clocks =3D <&syscrg JH7110_SYSCLK_VOUT_SRC>, - <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, - <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, - <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, - <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, - <&hdmitx0_pixelclk>; - clock-names =3D "vout_src", "vout_top_ahb", - "vout_top_axi", "vout_top_hdmitx0_mclk", - "i2stx0_bclk", "hdmitx0_pixelclk"; - resets =3D <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; + vout_subsystem: display-subsystem@29400000 { + compatible =3D "starfive,jh7110-vout-subsystem"; + reg =3D <0x0 0x29400000 0x0 0x200000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + clocks =3D <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>; + dma-noncoherent; power-domains =3D <&pwrc JH7110_PD_VOUT>; + resets =3D <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>; + + dc8200: display@29400000 { + compatible =3D "starfive,jh7110-dc8200", "verisilicon,dc"; + reg =3D <0x0 0x29400000 0x0 0x2800>; + clocks =3D <&voutcrg JH7110_VOUTCLK_DC8200_CORE>, + <&voutcrg JH7110_VOUTCLK_DC8200_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_AHB>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>; + clock-names =3D "core", "axi", "ahb", "pix0", "pix1"; + assigned-clocks =3D <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>; + assigned-clock-parents =3D <&hdmi_phy>, <&hdmi_phy>; + interrupts =3D <95>; + resets =3D <&voutcrg JH7110_VOUTRST_DC8200_CORE>, + <&voutcrg JH7110_VOUTRST_DC8200_AXI>, + <&voutcrg JH7110_VOUTRST_DC8200_AHB>; + reset-names =3D "core", "axi", "ahb"; + }; + + hdmi_subsystem: hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi-subsystem"; + reg =3D <0x0 0x29590000 0x0 0x4000>; + + hdmi_controller: controller { + compatible =3D + "starfive,jh7110-inno-hdmi-controller"; + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "pclk", "mclk", "bclk", "pixel"; + interrupts =3D <99>; + phys =3D <&hdmi_phy>; + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + starfive,vout-syscon =3D <&vout_syscon>; + }; + + hdmi_phy: phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + clocks =3D <&xin24m>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + }; + }; + + vout_syscon: syscon@295b0000 { + compatible =3D "starfive,jh7110-vout-syscon", "syscon"; + reg =3D <0x0 0x295b0000 0x0 0x10000>; + }; + + voutcrg: clock-controller@295c0000 { + compatible =3D "starfive,jh7110-voutcrg"; + reg =3D <0x0 0x295c0000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmi_phy>; + clock-names =3D "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + power-domains =3D <&pwrc JH7110_PD_VOUT>; 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a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1789486371; bh=5VJr9vBmbACanL0MeXx4ma5BlMfN70MxN8Z8af1jAN8=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=TbL4tjHB3FlMrYe92qC+NybVosVgaDcvWJfq2ZNFthYqUgBvSrdrWpSttXsWTIAiN jj9qXzq5SaDUQy/UITupzA5ZlwmNWj9+fHFBeoSIer90sZgh2kCWvy2Da3l93Wi3wT 7gI0Zkmzo2ogOIboFW6nnJiI7BIfKnAdBQ/CpQsQ= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20260915153250eucas1p2132ca4040b3c35a3aed471cb816b7857~ViF9fvU4I1454914549eucas1p2X; Tue, 15 Sep 2026 15:32:50 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260915153248eusmtip1ff29e81b00d983d86a6897dddbc876f8~ViF74X4zS0616306163eusmtip1e; Tue, 15 Sep 2026 15:32:48 +0000 (GMT) From: Michal Wilczynski Date: Tue, 15 Sep 2026 17:32:28 +0200 Subject: [PATCH v4 20/20] MAINTAINERS: Add StarFive JH7110 display subsystem entry Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-jh7110-clean-send-v4-20-f0e4fd6f2cc8@samsung.com> In-Reply-To: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michal Wilczynski X-Mailer: b4 0.15-dev X-CMS-MailID: 20260915153250eucas1p2132ca4040b3c35a3aed471cb816b7857 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260915153250eucas1p2132ca4040b3c35a3aed471cb816b7857 X-EPHeader: CA X-CMS-RootMailID: 20260915153250eucas1p2132ca4040b3c35a3aed471cb816b7857 References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> The JH7110 display subsystem spans a PHY driver, a DRM bridge driver, a parent device and their bindings, and has no existing maintainer entry. Add an entry covering them so patches reach someone who can review them. Reviewed-by: Joshua Peisach Signed-off-by: Michal Wilczynski --- MAINTAINERS | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c2414447892c24d58595059ca27b18775919ac12..3706b5787a25de7acba023bc404= 9f0fcdd078672 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26072,6 +26072,19 @@ S: Maintained F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c =20 +STARFIVE JH7110 DISPLAY SUBSYSTEM +M: Michal Wilczynski +R: Icenowy Zheng +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-h= dmi-controller.yaml +F: Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.ya= ml +F: Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml +F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-sub= system.yaml +F: drivers/gpu/drm/bridge/jh7110-inno-hdmi.c +F: drivers/phy/starfive/phy-jh7110-inno-hdmi.c +F: drivers/soc/starfive/jh7110-hdmi-subsystem.c +F: drivers/soc/starfive/jh7110-vout-subsystem.c + STARFIVE JH7110 DPHY RX DRIVER M: Jack Zhu M: Changhuang Liang --=20 2.34.1