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Tue, 15 Sep 2026 05:44:53 -0700 (PDT) From: Abel Vesa Date: Tue, 15 Sep 2026 15:44:50 +0300 Subject: [PATCH] Revert "interconnect: qcom: x1e80100: enable QoS configuration" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-icc-qcom-x1e80100-revert-qos-enabling-v1-1-cc4ba943bd9d@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAME9qWoC/yXNwQ6CMBCE4Vche3aTXQwEfRXjgdYR12grLRgSw rtb9fgd5p+VMpIh07FaKeFt2WIo0F1F/taHAWyXYqqlbuWgDZv3PPr45EXRiYpwmSFNPMbMCL1 7WBgYjXQq2jq3B5XWK+Fqy+/ndP47z+4OP33jtG0fcz2O94kAAAA= X-Change-ID: 20260915-icc-qcom-x1e80100-revert-qos-enabling-e5081016bb3e To: Georgi Djakov Cc: Mostafa Saleh , Marc Zyngier , Thorsten Leemhuis , Konrad Dybcio , Raviteja Laggyshetty , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.16-dev-0e65f X-Developer-Signature: v=1; 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Some Hamoa- and Purwa-based machines fail to boot after this change. Attempts to resolve the issue have not been successful, so revert the change for now. Reported-by: Mostafa Saleh Link: https://lore.kernel.org/all/apgeBNSiP01YfNcs@google.com/ Signed-off-by: Abel Vesa --- drivers/interconnect/qcom/x1e80100.c | 485 -------------------------------= ---- 1 file changed, 485 deletions(-) diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qc= om/x1e80100.c index 8075e0ff2059..2ba2823c7860 100644 --- a/drivers/interconnect/qcom/x1e80100.c +++ b/drivers/interconnect/qcom/x1e80100.c @@ -173,13 +173,6 @@ static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", .channels =3D 1, .buswidth =3D 4, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xb000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -188,13 +181,6 @@ static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", .channels =3D 1, .buswidth =3D 4, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xc000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -203,13 +189,6 @@ static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xd000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -218,13 +197,6 @@ static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 16, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xe000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -233,13 +205,6 @@ static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", .channels =3D 1, .buswidth =3D 4, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x16000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -248,13 +213,6 @@ static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", .channels =3D 1, .buswidth =3D 4, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x11000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -263,13 +221,6 @@ static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x12000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -286,13 +237,6 @@ static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x13000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -301,13 +245,6 @@ static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x14000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -316,13 +253,6 @@ static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x15000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -407,13 +337,6 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x271000 }, - .prio =3D 1, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -422,13 +345,6 @@ static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x27d000 }, - .prio =3D 3, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -437,13 +353,6 @@ static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x273000 }, - .prio =3D 6, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -461,13 +370,6 @@ static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", .channels =3D 4, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 4, - .port_offsets =3D { 0x51000, 0x58000, 0xd1000, 0xd8000 }, - .prio =3D 0, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -476,13 +378,6 @@ static struct qcom_icc_node qnm_lpass =3D { .name =3D "qnm_lpass", .channels =3D 1, .buswidth =3D 16, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x275000 }, - .prio =3D 0, - .urg_fwd =3D 1, - .prio_fwd_disable =3D 0, - }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -492,13 +387,6 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 2, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 2, - .port_offsets =3D { 0x53000, 0xd3000 }, - .prio =3D 0, - .urg_fwd =3D 1, - .prio_fwd_disable =3D 0, - }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -507,13 +395,6 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 2, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 2, - .port_offsets =3D { 0x55000, 0xd5000 }, - .prio =3D 0, - .urg_fwd =3D 1, - .prio_fwd_disable =3D 0, - }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -522,13 +403,6 @@ static struct qcom_icc_node qnm_nsp_noc =3D { .name =3D "qnm_nsp_noc", .channels =3D 2, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 2, - .port_offsets =3D { 0x57000, 0xd7000 }, - .prio =3D 0, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -538,13 +412,6 @@ static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", .channels =3D 1, .buswidth =3D 64, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x277000 }, - .prio =3D 0, - .urg_fwd =3D 1, - .prio_fwd_disable =3D 0, - }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -553,13 +420,6 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 64, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x27b000 }, - .prio =3D 2, - .urg_fwd =3D 1, - .prio_fwd_disable =3D 0, - }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -569,13 +429,6 @@ static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x27f000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; @@ -616,13 +469,6 @@ static struct qcom_icc_node qnm_av1_enc =3D { .name =3D "qnm_av1_enc", .channels =3D 1, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x2f000 }, - .prio =3D 4, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -631,13 +477,6 @@ static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", .channels =3D 2, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 2, - .port_offsets =3D { 0x28000, 0x29000 }, - .prio =3D 0, - .urg_fwd =3D 1, - .prio_fwd_disable =3D 0, - }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -646,13 +485,6 @@ static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x2a000 }, - .prio =3D 4, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -661,13 +493,6 @@ static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", .channels =3D 2, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 2, - .port_offsets =3D { 0x2b000, 0x2c000 }, - .prio =3D 0, - .urg_fwd =3D 1, - .prio_fwd_disable =3D 0, - }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -676,13 +501,6 @@ static struct qcom_icc_node qnm_eva =3D { .name =3D "qnm_eva", .channels =3D 1, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x33000 }, - .prio =3D 0, - .urg_fwd =3D 1, - .prio_fwd_disable =3D 0, - }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -691,13 +509,6 @@ static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", .channels =3D 2, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 2, - .port_offsets =3D { 0x2d000, 0x2e000 }, - .prio =3D 0, - .urg_fwd =3D 1, - .prio_fwd_disable =3D 0, - }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -706,13 +517,6 @@ static struct qcom_icc_node qnm_video =3D { .name =3D "qnm_video", .channels =3D 2, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 2, - .port_offsets =3D { 0x30000, 0x31000 }, - .prio =3D 0, - .urg_fwd =3D 1, - .prio_fwd_disable =3D 0, - }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -721,13 +525,6 @@ static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x32000 }, - .prio =3D 4, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -736,13 +533,6 @@ static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x34000 }, - .prio =3D 4, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -783,13 +573,6 @@ static struct qcom_icc_node xm_pcie_3 =3D { .name =3D "xm_pcie_3", .channels =3D 1, .buswidth =3D 64, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x7000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_north_gem_noc }, }; @@ -798,13 +581,6 @@ static struct qcom_icc_node xm_pcie_4 =3D { .name =3D "xm_pcie_4", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x8000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_north_gem_noc }, }; @@ -813,13 +589,6 @@ static struct qcom_icc_node xm_pcie_5 =3D { .name =3D "xm_pcie_5", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x9000 }, - .prio =3D 3, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_north_gem_noc }, }; @@ -828,13 +597,6 @@ static struct qcom_icc_node xm_pcie_0 =3D { .name =3D "xm_pcie_0", .channels =3D 1, .buswidth =3D 16, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x9000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_south_gem_noc }, }; @@ -843,13 +605,6 @@ static struct qcom_icc_node xm_pcie_1 =3D { .name =3D "xm_pcie_1", .channels =3D 1, .buswidth =3D 16, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xa000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_south_gem_noc }, }; @@ -858,13 +613,6 @@ static struct qcom_icc_node xm_pcie_2 =3D { .name =3D "xm_pcie_2", .channels =3D 1, .buswidth =3D 16, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xb000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_south_gem_noc }, }; @@ -873,13 +621,6 @@ static struct qcom_icc_node xm_pcie_6a =3D { .name =3D "xm_pcie_6a", .channels =3D 1, .buswidth =3D 32, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xc000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_south_gem_noc }, }; @@ -888,13 +629,6 @@ static struct qcom_icc_node xm_pcie_6b =3D { .name =3D "xm_pcie_6b", .channels =3D 1, .buswidth =3D 16, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xd000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_south_gem_noc }, }; @@ -919,13 +653,6 @@ static struct qcom_icc_node qnm_gic =3D { .name =3D "qnm_gic", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x1c000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_sf }, }; @@ -958,13 +685,6 @@ static struct qcom_icc_node xm_usb2_0 =3D { .name =3D "xm_usb2_0", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x6000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_north_snoc }, }; @@ -973,13 +693,6 @@ static struct qcom_icc_node xm_usb3_mp =3D { .name =3D "xm_usb3_mp", .channels =3D 1, .buswidth =3D 16, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0x7000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_north_snoc }, }; @@ -988,13 +701,6 @@ static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xa000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -1003,13 +709,6 @@ static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xb000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -1018,13 +717,6 @@ static struct qcom_icc_node xm_usb3_2 =3D { .name =3D "xm_usb3_2", .channels =3D 1, .buswidth =3D 8, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xc000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -1033,13 +725,6 @@ static struct qcom_icc_node xm_usb4_0 =3D { .name =3D "xm_usb4_0", .channels =3D 1, .buswidth =3D 16, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xd000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -1048,13 +733,6 @@ static struct qcom_icc_node xm_usb4_1 =3D { .name =3D "xm_usb4_1", .channels =3D 1, .buswidth =3D 16, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xe000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -1063,13 +741,6 @@ static struct qcom_icc_node xm_usb4_2 =3D { .name =3D "xm_usb4_2", .channels =3D 1, .buswidth =3D 16, - .qosbox =3D &(const struct qcom_icc_qosbox) { - .num_ports =3D 1, - .port_offsets =3D { 0xf000 }, - .prio =3D 2, - .urg_fwd =3D 0, - .prio_fwd_disable =3D 1, - }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -1795,21 +1466,11 @@ static struct qcom_icc_node * const aggre1_noc_node= s[] =3D { [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, }; =20 -static const struct regmap_config x1e80100_aggre1_noc_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x14400, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_aggre1_noc =3D { - .config =3D &x1e80100_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), - .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -1827,16 +1488,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes= [] =3D { [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, }; =20 -static const struct regmap_config x1e80100_aggre2_noc_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x1c400, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_aggre2_noc =3D { - .config =3D &x1e80100_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1921,16 +1573,7 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[]= =3D { [SLAVE_TCU] =3D &xs_sys_tcu_cfg, }; =20 -static const struct regmap_config x1e80100_cnoc_cfg_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x6600, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_cnoc_cfg =3D { - .config =3D &x1e80100_cnoc_cfg_regmap_config, .nodes =3D cnoc_cfg_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), .bcms =3D cnoc_cfg_bcms, @@ -1960,16 +1603,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[= ] =3D { [SLAVE_PCIE_6B] =3D &xs_pcie_6b, }; =20 -static const struct regmap_config x1e80100_cnoc_main_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x14400, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_cnoc_main =3D { - .config =3D &x1e80100_cnoc_main_regmap_config, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, @@ -1999,16 +1633,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { [SLAVE_MEM_NOC_PCIE_SNOC] =3D &qns_pcie, }; =20 -static const struct regmap_config x1e80100_gem_noc_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x311200, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_gem_noc =3D { - .config =3D &x1e80100_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -2023,16 +1648,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nod= es[] =3D { [SLAVE_LPASS_GEM_NOC] =3D &qns_lpass_ag_noc_gemnoc, }; =20 -static const struct regmap_config x1e80100_lpass_ag_noc_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0xe080, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_lpass_ag_noc =3D { - .config =3D &x1e80100_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -2048,16 +1664,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc= _nodes[] =3D { [SLAVE_LPIAON_NOC_LPASS_AG_NOC] =3D &qns_lpass_aggnoc, }; =20 -static const struct regmap_config x1e80100_lpass_lpiaon_noc_regmap_config = =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x19080, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc =3D { - .config =3D &x1e80100_lpass_lpiaon_noc_regmap_config, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, @@ -2072,16 +1679,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_= nodes[] =3D { [SLAVE_LPICX_NOC_LPIAON_NOC] =3D &qns_lpi_aon_noc, }; =20 -static const struct regmap_config x1e80100_lpass_lpicx_noc_regmap_config = =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x3a200, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc =3D { - .config =3D &x1e80100_lpass_lpicx_noc_regmap_config, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), .bcms =3D lpass_lpicx_noc_bcms, @@ -2126,16 +1724,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[]= =3D { [SLAVE_SERVICE_MNOC] =3D &srvc_mnoc, }; =20 -static const struct regmap_config x1e80100_mmss_noc_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x5b800, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_mmss_noc =3D { - .config =3D &x1e80100_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -2151,16 +1740,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { [SLAVE_CDSP_MEM_NOC] =3D &qns_nsp_gemnoc, }; =20 -static const struct regmap_config x1e80100_nsp_noc_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0xe080, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_nsp_noc =3D { - .config =3D &x1e80100_nsp_noc_regmap_config, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -2177,16 +1757,7 @@ static struct qcom_icc_node * const pcie_center_anoc= _nodes[] =3D { [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_mem_noc, }; =20 -static const struct regmap_config x1e80100_pcie_center_anoc_regmap_config = =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x7000, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_pcie_center_anoc =3D { - .config =3D &x1e80100_pcie_center_anoc_regmap_config, .nodes =3D pcie_center_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_center_anoc_nodes), .bcms =3D pcie_center_anoc_bcms, @@ -2203,16 +1774,7 @@ static struct qcom_icc_node * const pcie_north_anoc_= nodes[] =3D { [SLAVE_PCIE_NORTH] =3D &qns_pcie_north_gem_noc, }; =20 -static const struct regmap_config x1e80100_pcie_north_anoc_regmap_config = =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x9080, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_pcie_north_anoc =3D { - .config =3D &x1e80100_pcie_north_anoc_regmap_config, .nodes =3D pcie_north_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_north_anoc_nodes), .bcms =3D pcie_north_anoc_bcms, @@ -2231,16 +1793,7 @@ static struct qcom_icc_node * const pcie_south_anoc_= nodes[] =3D { [SLAVE_PCIE_SOUTH] =3D &qns_pcie_south_gem_noc, }; =20 -static const struct regmap_config x1e80100_pcie_south_anoc_regmap_config = =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0xd080, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_pcie_south_anoc =3D { - .config =3D &x1e80100_pcie_south_anoc_regmap_config, .nodes =3D pcie_south_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_south_anoc_nodes), .bcms =3D pcie_south_anoc_bcms, @@ -2262,16 +1815,7 @@ static struct qcom_icc_node * const system_noc_nodes= [] =3D { [SLAVE_SNOC_GEM_NOC_SF] =3D &qns_gemnoc_sf, }; =20 -static const struct regmap_config x1e80100_system_noc_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x1c080, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_system_noc =3D { - .config =3D &x1e80100_system_noc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, @@ -2287,16 +1831,7 @@ static struct qcom_icc_node * const usb_center_anoc_= nodes[] =3D { [SLAVE_USB_NOC_SNOC] =3D &qns_aggre_usb_snoc, }; =20 -static const struct regmap_config x1e80100_usb_center_anoc_regmap_config = =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x8800, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_usb_center_anoc =3D { - .config =3D &x1e80100_usb_center_anoc_regmap_config, .nodes =3D usb_center_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_center_anoc_nodes), .bcms =3D usb_center_anoc_bcms, @@ -2312,21 +1847,11 @@ static struct qcom_icc_node * const usb_north_anoc_= nodes[] =3D { [SLAVE_AGGRE_USB_NORTH] =3D &qns_aggre_usb_north_snoc, }; =20 -static const struct regmap_config x1e80100_usb_north_anoc_regmap_config = =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x7080, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_usb_north_anoc =3D { - .config =3D &x1e80100_usb_north_anoc_regmap_config, .nodes =3D usb_north_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_north_anoc_nodes), .bcms =3D usb_north_anoc_bcms, .num_bcms =3D ARRAY_SIZE(usb_north_anoc_bcms), - .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const usb_south_anoc_bcms[] =3D { @@ -2342,21 +1867,11 @@ static struct qcom_icc_node * const usb_south_anoc_= nodes[] =3D { [SLAVE_AGGRE_USB_SOUTH] =3D &qns_aggre_usb_south_snoc, }; =20 -static const struct regmap_config x1e80100_usb_south_anoc_regmap_config = =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0xf080, - .fast_io =3D true, -}; - static const struct qcom_icc_desc x1e80100_usb_south_anoc =3D { - .config =3D &x1e80100_usb_south_anoc_regmap_config, .nodes =3D usb_south_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_south_anoc_nodes), .bcms =3D usb_south_anoc_bcms, .num_bcms =3D ARRAY_SIZE(usb_south_anoc_bcms), - .qos_requires_clocks =3D true, }; =20 static const struct of_device_id qnoc_of_match[] =3D { --- base-commit: 1a1de54f7369cd2b5bac0f265910e60ad3a6b4c3 change-id: 20260915-icc-qcom-x1e80100-revert-qos-enabling-e5081016bb3e Best regards, -- =20 Abel Vesa