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Mon, 14 Sep 2026 16:05:53 -0700 (PDT) From: Alexey Klimov Date: Tue, 15 Sep 2026 00:05:43 +0100 Subject: [PATCH v2 1/2] clk: samsung: acpm: introduce driver data for SoC-specific clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-exynos850-acpm-clk-v2-1-ffad4a6b3fb1@linaro.org> References: <20260915-exynos850-acpm-clk-v2-0-ffad4a6b3fb1@linaro.org> In-Reply-To: <20260915-exynos850-acpm-clk-v2-0-ffad4a6b3fb1@linaro.org> To: Sam Protsenko , Tudor Ambarus , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Brian Masney , Peter Griffin , Brian Masney , Jerome Brunet Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 Currently, the ACPM clock driver hardcodes the GS101 clock variant arrays and counts directly in probe() routine. To support additional other SoCs (for instance Exynos850 SoC) that use the same ACPM protocol but have different clock trees, the driver needs to be more flexible. Introduce driver data attached to the platform_device_id table. Update the probe function to dynamically extract the clock lists, number of clocks, its names and mailbox channel id based on the matching device ID. Reviewed-by: Tudor Ambarus Signed-off-by: Alexey Klimov --- drivers/clk/samsung/clk-acpm.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-acpm.c b/drivers/clk/samsung/clk-acpm.c index 7680bc8c5275..4b68b44fe615 100644 --- a/drivers/clk/samsung/clk-acpm.c +++ b/drivers/clk/samsung/clk-acpm.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -101,6 +102,8 @@ static int acpm_clk_register(struct device *dev, struct= acpm_clk *aclk, =20 static int acpm_clk_probe(struct platform_device *pdev) { + const struct acpm_clk_driver_data *drv_data; + const struct platform_device_id *id; struct acpm_handle *acpm_handle; struct clk_hw_onecell_data *clk_data; struct clk_hw **hws; @@ -114,8 +117,14 @@ static int acpm_clk_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(acpm_handle), "Failed to get acpm handle\n"); =20 - count =3D acpm_clk_gs101.nr_clks; - mbox_chan_id =3D acpm_clk_gs101.mbox_chan_id; + id =3D platform_get_device_id(pdev); + if (!id || !id->driver_data) + return -ENODEV; + + drv_data =3D (const struct acpm_clk_driver_data *)id->driver_data; + + count =3D drv_data->nr_clks; + mbox_chan_id =3D drv_data->mbox_chan_id; =20 clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, count), GFP_KERNEL); @@ -142,8 +151,7 @@ static int acpm_clk_probe(struct platform_device *pdev) =20 hws[i] =3D &aclk->hw; =20 - err =3D acpm_clk_register(dev, aclk, - acpm_clk_gs101.clks[i].name); + err =3D acpm_clk_register(dev, aclk, drv_data->clks[i].name); if (err) return dev_err_probe(dev, err, "Failed to register clock\n"); @@ -154,7 +162,7 @@ static int acpm_clk_probe(struct platform_device *pdev) } =20 static const struct platform_device_id acpm_clk_id[] =3D { - { .name =3D "gs101-acpm-clk" }, + { .name =3D "gs101-acpm-clk", (kernel_ulong_t)&acpm_clk_gs101 }, { } }; MODULE_DEVICE_TABLE(platform, acpm_clk_id); --=20 2.51.0 From nobody Fri Sep 25 09:22:43 2026 Received: from mail-wr2-f12.google.com (mail-wr2-f12.google.com [74.125.225.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD9F242902E for ; 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Mon, 14 Sep 2026 16:05:55 -0700 (PDT) Received: from [127.0.1.1] ([94.4.85.166]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-486eb32d5f1sm32098817f8f.12.2026.09.14.16.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 16:05:54 -0700 (PDT) From: Alexey Klimov Date: Tue, 15 Sep 2026 00:05:44 +0100 Subject: [PATCH v2 2/2] clk: samsung: acpm: add Exynos850 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-exynos850-acpm-clk-v2-2-ffad4a6b3fb1@linaro.org> References: <20260915-exynos850-acpm-clk-v2-0-ffad4a6b3fb1@linaro.org> In-Reply-To: <20260915-exynos850-acpm-clk-v2-0-ffad4a6b3fb1@linaro.org> To: Sam Protsenko , Tudor Ambarus , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Brian Masney , Peter Griffin , Brian Masney , Jerome Brunet Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 The Exynos850 SoC utilizes the APM co-processor for clock management via ACPM, similar to the GS101 SoC. Add the Exynos850-specific clock variant array (including mif, int, cpucl0, cpucl1, g3d, aud, cam, disp, and cp) and wire it up to the driver data infrastructure. Add the "exynos850-acpm-clk" device ID to enable dynamic instantiation of these clocks during probe(). Unlike GS101, the ACPM firmware on Exynos850 does not implement a dynamic rate read call over ACPM IPC. To return sane clock rate in ->recalc_rate introduce a SoC-specific ->get_rate() driver data callback. For Exynos850, this falls back to reading the upstream parent CMU clock rate. When ->get_rate() is set, populate pdata.fw_name during clock registration to let clock framework to link the parent clock. Signed-off-by: Alexey Klimov --- drivers/clk/samsung/clk-acpm.c | 46 ++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-acpm.c b/drivers/clk/samsung/clk-acpm.c index 4b68b44fe615..9f46fbdd999d 100644 --- a/drivers/clk/samsung/clk-acpm.c +++ b/drivers/clk/samsung/clk-acpm.c @@ -22,6 +22,7 @@ struct acpm_clk { struct clk_hw hw; unsigned int mbox_chan_id; struct acpm_handle *handle; + const struct acpm_clk_driver_data *drv_data; }; =20 struct acpm_clk_variant { @@ -32,6 +33,8 @@ struct acpm_clk_driver_data { const struct acpm_clk_variant *clks; unsigned int nr_clks; unsigned int mbox_chan_id; + /* For SoCs where ACPM firmware doesn't implement get_rate call */ + unsigned long (*get_rate)(struct clk_hw *clk, unsigned long parent_rate); }; =20 #define to_acpm_clk(clk) container_of(clk, struct acpm_clk, hw) @@ -41,6 +44,18 @@ struct acpm_clk_driver_data { .name =3D cname, \ } =20 +static const struct acpm_clk_variant exynos850_acpm_clks[] =3D { + ACPM_CLK("mif"), + ACPM_CLK("int"), + ACPM_CLK("cpucl0"), + ACPM_CLK("cpucl1"), + ACPM_CLK("g3d"), + ACPM_CLK("aud"), + ACPM_CLK("cam"), + ACPM_CLK("disp"), + ACPM_CLK("cp"), +}; + static const struct acpm_clk_variant gs101_acpm_clks[] =3D { ACPM_CLK("mif"), ACPM_CLK("int"), @@ -58,6 +73,19 @@ static const struct acpm_clk_variant gs101_acpm_clks[] = =3D { ACPM_CLK("bo"), }; =20 +static unsigned long bypass_acpm_exynos850_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate; +} + +static const struct acpm_clk_driver_data acpm_clk_exynos850 =3D { + .clks =3D exynos850_acpm_clks, + .nr_clks =3D ARRAY_SIZE(exynos850_acpm_clks), + .mbox_chan_id =3D 0, + .get_rate =3D bypass_acpm_exynos850_get_rate, +}; + static const struct acpm_clk_driver_data acpm_clk_gs101 =3D { .clks =3D gs101_acpm_clks, .nr_clks =3D ARRAY_SIZE(gs101_acpm_clks), @@ -69,6 +97,9 @@ static unsigned long acpm_clk_recalc_rate(struct clk_hw *= hw, { struct acpm_clk *clk =3D to_acpm_clk(hw); =20 + if (clk->drv_data->get_rate) + return clk->drv_data->get_rate(hw, parent_rate); + return clk->handle->ops->dvfs.get_rate(clk->handle, clk->mbox_chan_id, clk->id); } @@ -89,14 +120,23 @@ static const struct clk_ops acpm_clk_ops =3D { }; =20 static int acpm_clk_register(struct device *dev, struct acpm_clk *aclk, - const char *name) + const char *name, const struct acpm_clk_driver_data *drv_data) { struct clk_init_data init =3D {}; + struct clk_parent_data pdata =3D {}; =20 init.name =3D name; init.ops =3D &acpm_clk_ops; aclk->hw.init =3D &init; =20 + /* If get_rate is set, the SoC relies on parent topology */ + if (drv_data->get_rate) { + pdata.fw_name =3D name; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.flags =3D CLK_GET_RATE_NOCACHE; + } + return devm_clk_hw_register(dev, &aclk->hw); } =20 @@ -145,13 +185,14 @@ static int acpm_clk_probe(struct platform_device *pde= v) * The code assumes the clock IDs start from zero, * are sequential and do not have gaps. */ + aclk->drv_data =3D drv_data; aclk->id =3D i; aclk->handle =3D acpm_handle; aclk->mbox_chan_id =3D mbox_chan_id; =20 hws[i] =3D &aclk->hw; =20 - err =3D acpm_clk_register(dev, aclk, drv_data->clks[i].name); + err =3D acpm_clk_register(dev, aclk, drv_data->clks[i].name, drv_data); if (err) return dev_err_probe(dev, err, "Failed to register clock\n"); @@ -162,6 +203,7 @@ static int acpm_clk_probe(struct platform_device *pdev) } =20 static const struct platform_device_id acpm_clk_id[] =3D { + { .name =3D "exynos850-acpm-clk", (kernel_ulong_t)&acpm_clk_exynos850 }, { .name =3D "gs101-acpm-clk", (kernel_ulong_t)&acpm_clk_gs101 }, { } }; --=20 2.51.0