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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2dd2cfd8c84sm71567305ad.62.2026.09.15.10.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 10:33:08 -0700 (PDT) From: Vivek Aknurwar Date: Tue, 15 Sep 2026 10:33:01 -0700 Subject: [PATCH v3 1/2] dt-bindings: clock: qcom: Add Hawi CAMCC compatible strings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-camcc-hawi-v3-1-5b57f45477f1@oss.qualcomm.com> References: <20260915-camcc-hawi-v3-0-5b57f45477f1@oss.qualcomm.com> In-Reply-To: <20260915-camcc-hawi-v3-0-5b57f45477f1@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vladimir Zapolskiy , Jagadeesh Kona , Taniya Das , Brian Masney , Jerome Brunet , Jagadeesh Kona , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vivek Aknurwar , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789493584; l=10553; i=vivek.aknurwar@oss.qualcomm.com; s=20260311; h=from:subject:message-id; bh=I5v3k4KuCQbDP/nwqPNIehICVFA4lqZJpL+PQlwxs+k=; b=mycYEnsHOhRmgEZhUAQqkXpOO8whLASG7FbRTznuGuW0GpgeqQ3Qg/giRRsCXDOUv4jhmE7oU d+Nkq5+j/mfDFUrrLktpxjLLCwO5TfYaMgvYcM+PnhejN/kyn5fDVN3 X-Developer-Key: i=vivek.aknurwar@oss.qualcomm.com; a=ed25519; pk=WIVIbn3nJR9YRWNRyJiEbvpgoHhNyYrmVqMUXWqAIC0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDI1NSBTYWx0ZWRfXzYlzO8ZIb0F/ IWJljAzfp7xL5p0+L3jW0vqUamiILyraCyZUqMYlD7qQCmLiCbcNXyU9B6vWfT+r2wvQhE90hcM ZwGVdzQ2INWe1QOarb9rGeW5NrBVnunDQHAX4zoxXVMBXvxwedOwiBU9j/s5VpZkESH067JHad5 pRqtL4tJoN+2ZoA0FhYiWZyMJzls/wxTNadFliGXh5vI2/vCoGM9or9Iba5Ak/RNdfeRW6eVXjB q5KIWDYpMoyaFgVS7Xi58Nv/xtUMSQRZ8dPMb5tZek4bpJYMtKlNn2xFpLGPjtwP3njxTeeMqGg vee9x5hyhAJFqALK+tc72rVmXWfrCbtpft7VjujBTRwyHZmxhEVkz9Ub8eifEfQESdc5epQmkRQ hCou+B5HKgfdUFe7qTMuzXve+qQGEZT4o2MTxlnmociJuG6kb+iydfL/F6pRoGCHGy9FLLD1Q8r ByYI2+ldaduzC+mHIwQ== X-Proofpoint-ORIG-GUID: -otG9HbXW3waC_gVyGW9WjfaJ4kJrbt_ X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDI1NSBTYWx0ZWRfX82Dji8b79MWU MjW7yt1zTUjb6DSofo25pGwndRVwZUAjwj272+8LuFbqb6wcrm5xwy1MkkmSgWNLr+fGpsq1gQB 08WO7Zn6+omdB50LCdxJ1FPDqi41SLU= X-Proofpoint-GUID: -otG9HbXW3waC_gVyGW9WjfaJ4kJrbt_ X-Authority-Analysis: v=2.4 cv=QYLzLcbv c=1 sm=1 tr=0 ts=6aa98157 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=RNlHf_2cRKinjC6Nl1QA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_04,2026-09-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150255 The Hawi SoC is a derivative of Kaanapali with an updated camera clock controller (CAMCC). While the overall block structure is similar, Hawi's CAMCC differs from Kaanapali in the following ways: - Uses Taycan EHA-T PLLs instead of Taycan EKO-T PLLs, with an additional ninth PLL (PLL8) - Adds a SQPF block with its own GDSC, AHB clock, and BCR reset - Adds a CX GDSC (CAM_CC_TITAN_TOP_CX_GDSC) for the camera subsystem - Expands ICP from one to two instances (ICP_0 and ICP_1) Due to these differences, Hawi requires its own 'qcom,hawi-camcc' compatible string and a dedicated driver. The BIST MCLK clock controller (CAMBISTMCLKCC) is unchanged between Hawi and Kaanapali, allowing the existing Kaanapali CAMBISTMCLKCC driver to support both SoCs without modification. Add the 'qcom,hawi-camcc' and 'qcom,hawi-cambistmclkcc' compatible strings to the binding, along with the corresponding clock ID header. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vivek Aknurwar --- .../bindings/clock/qcom,sm8450-camcc.yaml | 43 ++++-- include/dt-bindings/clock/qcom,hawi-camcc.h | 165 +++++++++++++++++= ++++ 2 files changed, 198 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index f65380747220..e2a126925e9d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -16,6 +16,7 @@ description: | domains on SM8450. =20 See also: + include/dt-bindings/clock/qcom,hawi-camcc.h include/dt-bindings/clock/qcom,kaanapali-camcc.h include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h include/dt-bindings/clock/qcom,nord-camcc.h @@ -27,16 +28,22 @@ description: | =20 properties: compatible: - enum: - - qcom,kaanapali-cambistmclkcc - - qcom,kaanapali-camcc - - qcom,nord-camcc - - qcom,sm8450-camcc - - qcom,sm8475-camcc - - qcom,sm8550-camcc - - qcom,sm8650-camcc - - qcom,sm8750-cambistmclkcc - - qcom,sm8750-camcc + oneOf: + - enum: + - qcom,hawi-camcc + - qcom,kaanapali-cambistmclkcc + - qcom,kaanapali-camcc + - qcom,nord-camcc + - qcom,sm8450-camcc + - qcom,sm8475-camcc + - qcom,sm8550-camcc + - qcom,sm8650-camcc + - qcom,sm8750-cambistmclkcc + - qcom,sm8750-camcc + - items: + - enum: + - qcom,hawi-cambistmclkcc + - const: qcom,kaanapali-cambistmclkcc =20 clocks: items: @@ -45,6 +52,10 @@ properties: - description: Board active XO source - description: Sleep clock source =20 + interconnects: + items: + - description: Interconnect path to enable the MultiMedia NoC + power-domains: description: Power domains required for the clock controller to operate @@ -80,12 +91,22 @@ allOf: then: required: - required-opps + - if: + properties: + compatible: + contains: + const: qcom,hawi-camcc + then: + required: + - interconnects =20 unevaluatedProperties: false =20 examples: - | #include + #include + #include #include #include clock-controller@ade0000 { @@ -99,6 +120,8 @@ examples: <&rpmhpd RPMHPD_MXC>; required-opps =3D <&rpmhpd_opp_low_svs>, <&rpmhpd_opp_low_svs>; + interconnects =3D <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; diff --git a/include/dt-bindings/clock/qcom,hawi-camcc.h b/include/dt-bindi= ngs/clock/qcom,hawi-camcc.h new file mode 100644 index 000000000000..6ef731738e6e --- /dev/null +++ b/include/dt-bindings/clock/qcom,hawi-camcc.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_HAWI_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_HAWI_H + +/* CAM_CC clocks */ +#define CAM_CC_CAM_TOP_AHB_CLK 0 +#define CAM_CC_CAM_TOP_FAST_AHB_CLK 1 +#define CAM_CC_CAMNOC_DCD_XO_CLK 2 +#define CAM_CC_CAMNOC_NRT_AXI_CLK 3 +#define CAM_CC_CAMNOC_NRT_CRE_CLK 4 +#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK 5 +#define CAM_CC_CAMNOC_NRT_IPE_SCALERS_CLK 6 +#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK 7 +#define CAM_CC_CAMNOC_NRT_SQPF_CLK 8 +#define CAM_CC_CAMNOC_RT_AXI_CLK 9 +#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 10 +#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK 11 +#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK 12 +#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK 13 +#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK 14 +#define CAM_CC_CCI_0_CLK 15 +#define CAM_CC_CCI_0_CLK_SRC 16 +#define CAM_CC_CCI_1_CLK 17 +#define CAM_CC_CCI_1_CLK_SRC 18 +#define CAM_CC_CCI_2_CLK 19 +#define CAM_CC_CCI_2_CLK_SRC 20 +#define CAM_CC_CORE_AHB_CLK 21 +#define CAM_CC_CPHY_RX_CLK_SRC 22 +#define CAM_CC_CRE_AHB_CLK 23 +#define CAM_CC_CRE_CLK 24 +#define CAM_CC_CRE_CLK_SRC 25 +#define CAM_CC_CSI0PHYTIMER_CLK 26 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSI1PHYTIMER_CLK 28 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 29 +#define CAM_CC_CSI2PHYTIMER_CLK 30 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 31 +#define CAM_CC_CSI3PHYTIMER_CLK 32 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 33 +#define CAM_CC_CSI4PHYTIMER_CLK 34 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSI5PHYTIMER_CLK 36 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 37 +#define CAM_CC_CSID_CLK 38 +#define CAM_CC_CSID_CLK_SRC 39 +#define CAM_CC_CSID_CSIPHY_RX_CLK 40 +#define CAM_CC_CSIPHY0_CLK 41 +#define CAM_CC_CSIPHY1_CLK 42 +#define CAM_CC_CSIPHY2_CLK 43 +#define CAM_CC_CSIPHY3_CLK 44 +#define CAM_CC_CSIPHY4_CLK 45 +#define CAM_CC_CSIPHY5_CLK 46 +#define CAM_CC_CX_GDSC_CLK 47 +#define CAM_CC_DRV_AHB_CLK 48 +#define CAM_CC_DRV_XO_CLK 49 +#define CAM_CC_FAST_AHB_CLK_SRC 50 +#define CAM_CC_GDSC_CLK 51 +#define CAM_CC_ICP_0_AHB_CLK 52 +#define CAM_CC_ICP_0_CLK 53 +#define CAM_CC_ICP_0_CLK_SRC 54 +#define CAM_CC_ICP_1_AHB_CLK 55 +#define CAM_CC_ICP_1_CLK 56 +#define CAM_CC_ICP_1_CLK_SRC 57 +#define CAM_CC_IFE_LITE_AHB_CLK 58 +#define CAM_CC_IFE_LITE_CLK 59 +#define CAM_CC_IFE_LITE_CLK_SRC 60 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 61 +#define CAM_CC_IFE_LITE_CSID_CLK 62 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 63 +#define CAM_CC_IPE_NPS_AHB_CLK 64 +#define CAM_CC_IPE_NPS_CLK 65 +#define CAM_CC_IPE_NPS_CLK_SRC 66 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 67 +#define CAM_CC_IPE_PPS_CLK 68 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 69 +#define CAM_CC_IPE_SCALERS_CLK 70 +#define CAM_CC_IPE_SCALERS_FAST_AHB_CLK 71 +#define CAM_CC_JPEG_CLK 72 +#define CAM_CC_JPEG_CLK_SRC 73 +#define CAM_CC_MMSS_AHB_CLK 74 +#define CAM_CC_OFE_AHB_CLK 75 +#define CAM_CC_OFE_ANCHOR_CLK 76 +#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK 77 +#define CAM_CC_OFE_CLK_SRC 78 +#define CAM_CC_OFE_HDR_CLK 79 +#define CAM_CC_OFE_HDR_FAST_AHB_CLK 80 +#define CAM_CC_OFE_MAIN_CLK 81 +#define CAM_CC_OFE_MAIN_FAST_AHB_CLK 82 +#define CAM_CC_OFE_MP_CLK 83 +#define CAM_CC_OFE_MP_FAST_AHB_CLK 84 +#define CAM_CC_PLL0 85 +#define CAM_CC_PLL0_OUT_EVEN 86 +#define CAM_CC_PLL0_OUT_ODD 87 +#define CAM_CC_PLL1 88 +#define CAM_CC_PLL1_OUT_EVEN 89 +#define CAM_CC_PLL2 90 +#define CAM_CC_PLL2_OUT_EVEN 91 +#define CAM_CC_PLL3 92 +#define CAM_CC_PLL3_OUT_EVEN 93 +#define CAM_CC_PLL4 94 +#define CAM_CC_PLL4_OUT_EVEN 95 +#define CAM_CC_PLL5 96 +#define CAM_CC_PLL5_OUT_EVEN 97 +#define CAM_CC_PLL6 98 +#define CAM_CC_PLL6_OUT_EVEN 99 +#define CAM_CC_PLL6_OUT_ODD 100 +#define CAM_CC_PLL7 101 +#define CAM_CC_PLL8 102 +#define CAM_CC_PLL8_OUT_EVEN 103 +#define CAM_CC_QDSS_DEBUG_CLK 104 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 105 +#define CAM_CC_QDSS_DEBUG_XO_CLK 106 +#define CAM_CC_SLEEP_CLK 107 +#define CAM_CC_SLOW_AHB_CLK_SRC 108 +#define CAM_CC_SQPF_AHB_CLK 109 +#define CAM_CC_SQPF_CLK 110 +#define CAM_CC_SQPF_CLK_SRC 111 +#define CAM_CC_SQPF_FAST_AHB_CLK 112 +#define CAM_CC_TFE_0_BAYER_CLK 113 +#define CAM_CC_TFE_0_BAYER_FAST_AHB_CLK 114 +#define CAM_CC_TFE_0_CLK_SRC 115 +#define CAM_CC_TFE_0_MAIN_CLK 116 +#define CAM_CC_TFE_0_MAIN_FAST_AHB_CLK 117 +#define CAM_CC_TFE_1_BAYER_CLK 118 +#define CAM_CC_TFE_1_BAYER_FAST_AHB_CLK 119 +#define CAM_CC_TFE_1_CLK_SRC 120 +#define CAM_CC_TFE_1_MAIN_CLK 121 +#define CAM_CC_TFE_1_MAIN_FAST_AHB_CLK 122 +#define CAM_CC_TFE_2_BAYER_CLK 123 +#define CAM_CC_TFE_2_BAYER_FAST_AHB_CLK 124 +#define CAM_CC_TFE_2_CLK_SRC 125 +#define CAM_CC_TFE_2_MAIN_CLK 126 +#define CAM_CC_TFE_2_MAIN_FAST_AHB_CLK 127 +#define CAM_CC_TITAN_CAMNOC_XO_CLK 128 +#define CAM_CC_TITAN_MNOC_HF_CLK 129 +#define CAM_CC_TITAN_MNOC_SF_CLK 130 +#define CAM_CC_TRACENOC_TPDM_1_CMB_CLK 131 +#define CAM_CC_XO_CLK_SRC 132 + +/* CAM_CC power domains */ +#define CAM_CC_IPE_0_GDSC 0 +#define CAM_CC_OFE_GDSC 1 +#define CAM_CC_SQPF_GDSC 2 +#define CAM_CC_TFE_0_GDSC 3 +#define CAM_CC_TFE_1_GDSC 4 +#define CAM_CC_TFE_2_GDSC 5 +#define CAM_CC_TITAN_TOP_CX_GDSC 6 +#define CAM_CC_TITAN_TOP_GDSC 7 + +/* CAM_CC resets */ +#define CAM_CC_DRV_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IPE_0_BCR 2 +#define CAM_CC_OFE_BCR 3 +#define CAM_CC_QDSS_DEBUG_BCR 4 +#define CAM_CC_SQPF_BCR 5 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2dd2cfd8c84sm71567305ad.62.2026.09.15.10.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 10:33:11 -0700 (PDT) From: Vivek Aknurwar Date: Tue, 15 Sep 2026 10:33:02 -0700 Subject: [PATCH v3 2/2] clk: qcom: Add support for the camera clock controller (CAMCC) on Hawi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-camcc-hawi-v3-2-5b57f45477f1@oss.qualcomm.com> References: <20260915-camcc-hawi-v3-0-5b57f45477f1@oss.qualcomm.com> In-Reply-To: <20260915-camcc-hawi-v3-0-5b57f45477f1@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vladimir Zapolskiy , Jagadeesh Kona , Taniya Das , Brian Masney , Jerome Brunet , Jagadeesh Kona , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vivek Aknurwar , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789493584; l=89455; i=vivek.aknurwar@oss.qualcomm.com; s=20260311; h=from:subject:message-id; bh=YBfu6N6V1jMYconJYGn+dslKjmhWBHduBYJR1ga2I/I=; b=dd+WgT/2/j7jDIFJcZKdpZgrdWtof6kEs5+m8gNBaX5acpChpyfAsxYanBThK+RwGiI15Siwr HbmItR1llq5BNuRRarqObEAvWwjxnR8Mdfd2JppQhfuOiVyK0blEVqQ X-Developer-Key: i=vivek.aknurwar@oss.qualcomm.com; a=ed25519; pk=WIVIbn3nJR9YRWNRyJiEbvpgoHhNyYrmVqMUXWqAIC0= X-Proofpoint-ORIG-GUID: yrxy0XRScThAr_94-K3akEnRVRHuMdNK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDI1NSBTYWx0ZWRfX2buL0ON54FDX +x1NvaHd4rL56iPD3VqcHX6EeWWaSW+asPvwfLSnR4/Rd7vbjzdY3Ohin4nkAlx4Ec1SwsGZXgE wgtOrgr6N0Kx9Yu5IWUKxk88hb2tApiUgEi18nP+Esnej0mCc0k+G9KNKi0wwtYUqatSSVTA2eH +d6F7toqXv6aSXWdxfE7V13qcPVH3Qyb5weJ1FW/XhQFfb1+nQdlMiUVdod5hhARfwEn5WezElc 1HmA874WrRZ/ccUlAKXgrM8KuhQIC1ltcpmpKHf5B8WditMcO5G+7VBMBfj/8I1SUHd/ZWWbPKT dcuMwD2nk4tzHkDCrRenSPPLepRhYSXj7XRa/FRGp8CAKy/+oINHLHQ7EBFAy4pjpRlpbo9dYjw kRNJs95TttFb3NOfJ2gQ+knZVUrD7Epx/59a3ffVCE5Ali4nzCT2NzM3ySHKF2C64n8sp0rqCF2 nrQJYPbYJYQcVROj3ew== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDI1NSBTYWx0ZWRfX6AK2Vmv/ETL0 qwV7KUS1T80klKJepbc/9qREudXCiddktbN6Lg0DNSNHVSfCqq/0vP7VgZfd7eJBQTb2a+tqfXh 3ETtDAqoGAJcdC85hKV0ncj7kW9t0oo= X-Proofpoint-GUID: yrxy0XRScThAr_94-K3akEnRVRHuMdNK X-Authority-Analysis: v=2.4 cv=IcISymqa c=1 sm=1 tr=0 ts=6aa9815c cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=DNZtTDGKgN8HDTSViz0A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_04,2026-09-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 clxscore=1015 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150255 The CAMCC block on the Qualcomm Hawi SoC provides the primary camera clocks. The Camera BIST MCLK clock controller is identical to Kaanapali's and hence reuses the cambistmclkcc-kaanapali driver to provide the functional MCLK required for camera operations. Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Taniya Das Signed-off-by: Vivek Aknurwar --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-hawi.c | 2993 +++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 3005 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6ef083f5d9e2..6b8e8da4e4ee 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -495,6 +495,17 @@ config QCOM_CLK_RPMH Say Y if you want to support the clocks exposed by RPMh on platforms such as SDM845. =20 +config CLK_HAWI_CAMCC + tristate "Hawi Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_HAWI_GCC + default m if ARCH_QCOM + help + Support for the camera clock controller on Qualcomm Technologies, Inc + Hawi devices. + Say Y if you want to support camera devices and functionality such as + capturing pictures. + config CLK_HAWI_GCC tristate "Hawi Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index a6c676f68b79..bd70e18a7118 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GPUCC) +=3D gpucc-glymur.o gxclkctl-kaanapali.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) +=3D videocc-glymur.o +obj-$(CONFIG_CLK_HAWI_CAMCC) +=3D cambistmclkcc-kaanapali.o camcc-hawi.o obj-$(CONFIG_CLK_HAWI_GCC) +=3D gcc-hawi.o obj-$(CONFIG_CLK_HAWI_GPUCC) +=3D gpucc-hawi.o gxclkctl-kaanapali.o obj-$(CONFIG_CLK_HAWI_TCSRCC) +=3D tcsrcc-hawi.o diff --git a/drivers/clk/qcom/camcc-hawi.c b/drivers/clk/qcom/camcc-hawi.c new file mode 100644 index 000000000000..aa52b99aec00 --- /dev/null +++ b/drivers/clk/qcom/camcc-hawi.c @@ -0,0 +1,2993 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_AHB_CLK, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +/* Need to match the order of interconnects in DT binding */ +enum { + DT_ICC_TOP_GDSC, +}; + +enum { + P_BI_TCXO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL1_OUT_EVEN, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_CAM_CC_PLL6_OUT_EVEN, + P_CAM_CC_PLL6_OUT_MAIN, + P_CAM_CC_PLL6_OUT_ODD, + P_CAM_CC_PLL7_OUT_EVEN, + P_CAM_CC_PLL7_OUT_MAIN, + P_CAM_CC_PLL8_OUT_EVEN, +}; + +static const struct pll_vco taycan_eha_t_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +/* 1200.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll0_config =3D { + .l =3D 0x3e, + .alpha =3D 0x8000, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00008400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eha_t_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] =3D= { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd =3D { + .offset =3D 0x0, + .post_div_shift =3D 14, + .post_div_table =3D post_div_table_cam_cc_pll0_out_odd, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0_out_odd", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eha_t_ops, + }, +}; + +/* 493.2 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll1_config =3D { + .l =3D 0x19, + .alpha =3D 0xb000, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even =3D { + .offset =3D 0x1000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll1_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll1_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eha_t_ops, + }, +}; + +/* 451.2 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll2_config =3D { + .l =3D 0x17, + .alpha =3D 0x8000, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even =3D { + .offset =3D 0x2000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll2_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll2.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eha_t_ops, + }, +}; + +/* 476.4 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll3_config =3D { + .l =3D 0x18, + .alpha =3D 0xd000, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll3 =3D { + .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even =3D { + .offset =3D 0x3000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll3_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eha_t_ops, + }, +}; + +/* 476.4 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll4_config =3D { + .l =3D 0x18, + .alpha =3D 0xd000, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll4 =3D { + .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even =3D { + .offset =3D 0x4000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll4_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll4_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eha_t_ops, + }, +}; + +/* 476.4 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll5_config =3D { + .l =3D 0x18, + .alpha =3D 0xd000, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll5 =3D { + .offset =3D 0x5000, + .config =3D &cam_cc_pll5_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll5", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even =3D { + .offset =3D 0x5000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll5_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll5_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eha_t_ops, + }, +}; + +/* 960.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll6_config =3D { + .l =3D 0x32, + .alpha =3D 0x0, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00008400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll6 =3D { + .offset =3D 0x6000, + .config =3D &cam_cc_pll6_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even =3D { + .offset =3D 0x6000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll6_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eha_t_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] =3D= { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd =3D { + .offset =3D 0x6000, + .post_div_shift =3D 14, + .post_div_table =3D post_div_table_cam_cc_pll6_out_odd, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6_out_odd", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eha_t_ops, + }, +}; + +/* 345.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll7_config =3D { + .l =3D 0x11, + .alpha =3D 0xf800, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll7 =3D { + .offset =3D 0x7000, + .config =3D &cam_cc_pll7_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll7", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +/* 493.2 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll8_config =3D { + .l =3D 0x19, + .alpha =3D 0xb000, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll cam_cc_pll8 =3D { + .offset =3D 0x8000, + .config =3D &cam_cc_pll8_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll8", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even =3D { + .offset =3D 0x8000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll8_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll8_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll8.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_eha_t_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL6_OUT_ODD, 4 }, + { P_CAM_CC_PLL6_OUT_EVEN, 5 }, + { P_CAM_CC_PLL6_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll6.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL6_OUT_ODD, 4 }, + { P_CAM_CC_PLL6_OUT_EVEN, 5 }, + { P_CAM_CC_PLL6_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll6.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL7_OUT_EVEN, 5 }, + { P_CAM_CC_PLL7_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll7.clkr.hw }, + { .hw =3D &cam_cc_pll7.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll1_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll2_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL8_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll8_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_7[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_7[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_8[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_8[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_9[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_9[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(120000000, P_CAM_CC_PLL6_OUT_EVEN, 4, 0, 0), + F(160000000, P_CAM_CC_PLL6_OUT_EVEN, 3, 0, 0), + F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0), + F(320000000, P_CAM_CC_PLL6_OUT_EVEN, 1.5, 0, 0), + F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src =3D { + .cmd_rcgr =3D 0x212cc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_camnoc_rt_axi_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_axi_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] =3D { + F(37500000, P_CAM_CC_PLL0_OUT_ODD, 1, 3, 32), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src =3D { + .cmd_rcgr =3D 0x21250, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_0_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src =3D { + .cmd_rcgr =3D 0x2126c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_1_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_2_clk_src =3D { + .cmd_rcgr =3D 0x21288, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_2_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] =3D { + F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src =3D { + .cmd_rcgr =3D 0x21064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cphy_rx_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] =3D { + F(80000000, P_CAM_CC_PLL6_OUT_EVEN, 6, 0, 0), + F(137142857, P_CAM_CC_PLL6_OUT_EVEN, 3.5, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cre_clk_src =3D { + .cmd_rcgr =3D 0x211a0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cre_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cre_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] =3D { + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src =3D { + .cmd_rcgr =3D 0x20000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src =3D { + .cmd_rcgr =3D 0x20024, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src =3D { + .cmd_rcgr =3D 0x20044, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src =3D { + .cmd_rcgr =3D 0x20064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi3phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src =3D { + .cmd_rcgr =3D 0x20084, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi4phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi5phytimer_clk_src =3D { + .cmd_rcgr =3D 0x200a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi5phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csid_clk_src =3D { + .cmd_rcgr =3D 0x212a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] =3D { + F(128000000, P_CAM_CC_PLL6_OUT_ODD, 2.5, 0, 0), + F(213333333, P_CAM_CC_PLL6_OUT_ODD, 1.5, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src =3D { + .cmd_rcgr =3D 0x200dc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_fast_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_fast_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_0_clk_src[] =3D { + F(345000000, P_CAM_CC_PLL7_OUT_MAIN, 1, 0, 0), + F(500000000, P_CAM_CC_PLL7_OUT_MAIN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL7_OUT_MAIN, 1, 0, 0), + F(770000000, P_CAM_CC_PLL7_OUT_MAIN, 1, 0, 0), + F(900000000, P_CAM_CC_PLL7_OUT_MAIN, 1, 0, 0), + F(1150000000, P_CAM_CC_PLL7_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_0_clk_src =3D { + .cmd_rcgr =3D 0x211f8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_icp_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_icp_1_clk_src =3D { + .cmd_rcgr =3D 0x21220, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_icp_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] =3D { + F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src =3D { + .cmd_rcgr =3D 0x21144, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_ife_lite_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src =3D { + .cmd_rcgr =3D 0x21170, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] =3D { + F(246600000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(411000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_nps_clk_src =3D { + .cmd_rcgr =3D 0x2019c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_3, + .freq_tbl =3D ftbl_cam_cc_ipe_nps_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_clk_src", + .parent_data =3D cam_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src =3D { + .cmd_rcgr =3D 0x211c4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cre_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_jpeg_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ofe_clk_src[] =3D { + F(225600000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(300000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(376000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(445000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(500000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(609000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(688000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(841000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ofe_clk_src =3D { + .cmd_rcgr =3D 0x20120, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_4, + .freq_tbl =3D ftbl_cam_cc_ofe_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_clk_src", + .parent_data =3D cam_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] =3D { + F(40000000, P_CAM_CC_PLL6_OUT_ODD, 8, 0, 0), + F(60000000, P_CAM_CC_PLL0_OUT_EVEN, 10, 0, 0), + F(120000000, P_CAM_CC_PLL0_OUT_EVEN, 5, 0, 0), + F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src =3D { + .cmd_rcgr =3D 0x21310, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_qdss_debug_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] =3D { + F(56470588, P_CAM_CC_PLL6_OUT_EVEN, 8.5, 0, 0), + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src =3D { + .cmd_rcgr =3D 0x20104, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_slow_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_slow_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sqpf_clk_src[] =3D { + F(246600000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(411000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(475000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(575000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(825000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sqpf_clk_src =3D { + .cmd_rcgr =3D 0x2021c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_5, + .freq_tbl =3D ftbl_cam_cc_sqpf_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sqpf_clk_src", + .parent_data =3D cam_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] =3D { + F(238200000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(397000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(440000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(630000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(750000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(833000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_tfe_0_clk_src =3D { + .cmd_rcgr =3D 0x21018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_6, + .freq_tbl =3D ftbl_cam_cc_tfe_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_clk_src", + .parent_data =3D cam_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_tfe_1_clk_src[] =3D { + F(238200000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(397000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(440000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(750000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(833000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_tfe_1_clk_src =3D { + .cmd_rcgr =3D 0x21094, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_7, + .freq_tbl =3D ftbl_cam_cc_tfe_1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_clk_src", + .parent_data =3D cam_cc_parent_data_7, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_7), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_tfe_2_clk_src[] =3D { + F(238200000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(397000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(440000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(630000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(750000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(833000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_tfe_2_clk_src =3D { + .cmd_rcgr =3D 0x210f8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_8, + .freq_tbl =3D ftbl_cam_cc_tfe_2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_clk_src", + .parent_data =3D cam_cc_parent_data_8, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_8), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x21348, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_9, + .freq_tbl =3D ftbl_cam_cc_xo_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_xo_clk_src", + .parent_data =3D cam_cc_parent_data_9, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_9), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch cam_cc_cam_top_ahb_clk =3D { + .halt_reg =3D 0x21378, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21378, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cam_top_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cam_top_fast_ahb_clk =3D { + .halt_reg =3D 0x21368, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21368, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cam_top_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_axi_clk =3D { + .halt_reg =3D 0x212f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x212f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_cre_clk =3D { + .halt_reg =3D 0x211bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x211bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_cre_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_ipe_nps_clk =3D { + .halt_reg =3D 0x201c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_ipe_nps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_ipe_scalers_clk =3D { + .halt_reg =3D 0x201e8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_ipe_scalers_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_ofe_main_clk =3D { + .halt_reg =3D 0x20148, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20148, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_ofe_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_sqpf_clk =3D { + .halt_reg =3D 0x20244, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20244, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_sqpf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_sqpf_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_axi_clk =3D { + .halt_reg =3D 0x212e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x212e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_ife_lite_clk =3D { + .halt_reg =3D 0x2116c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2116c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_0_main_clk =3D { + .halt_reg =3D 0x21040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_0_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_1_main_clk =3D { + .halt_reg =3D 0x210bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x210bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_1_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_2_main_clk =3D { + .halt_reg =3D 0x21120, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21120, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_2_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk =3D { + .halt_reg =3D 0x21268, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21268, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk =3D { + .halt_reg =3D 0x21284, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21284, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_2_clk =3D { + .halt_reg =3D 0x212a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x212a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk =3D { + .halt_reg =3D 0x21344, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x21344, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_core_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_ahb_clk =3D { + .halt_reg =3D 0x211c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x211c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cre_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_clk =3D { + .halt_reg =3D 0x211b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x211b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cre_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk =3D { + .halt_reg =3D 0x20018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk =3D { + .halt_reg =3D 0x2003c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2003c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk =3D { + .halt_reg =3D 0x2005c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2005c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk =3D { + .halt_reg =3D 0x2007c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2007c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi3phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk =3D { + .halt_reg =3D 0x2009c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2009c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi4phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi5phytimer_clk =3D { + .halt_reg =3D 0x200bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi5phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi5phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk =3D { + .halt_reg =3D 0x212bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x212bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk =3D { + .halt_reg =3D 0x20020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_csiphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk =3D { + .halt_reg =3D 0x2001c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2001c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk =3D { + .halt_reg =3D 0x20040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk =3D { + .halt_reg =3D 0x20060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk =3D { + .halt_reg =3D 0x20080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk =3D { + .halt_reg =3D 0x200a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy5_clk =3D { + .halt_reg =3D 0x200c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_0_ahb_clk =3D { + .halt_reg =3D 0x21248, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21248, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_0_clk =3D { + .halt_reg =3D 0x21210, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21210, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_icp_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_1_ahb_clk =3D { + .halt_reg =3D 0x2124c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2124c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_1_clk =3D { + .halt_reg =3D 0x21238, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21238, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_icp_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk =3D { + .halt_reg =3D 0x2119c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2119c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk =3D { + .halt_reg =3D 0x2115c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2115c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk =3D { + .halt_reg =3D 0x21198, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21198, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk =3D { + .halt_reg =3D 0x21188, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21188, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_ahb_clk =3D { + .halt_reg =3D 0x201f4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_clk =3D { + .halt_reg =3D 0x201b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk =3D { + .halt_reg =3D 0x201f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_clk =3D { + .halt_reg =3D 0x201c8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201c8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_pps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk =3D { + .halt_reg =3D 0x201fc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201fc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_pps_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_scalers_clk =3D { + .halt_reg =3D 0x201d8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_scalers_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_scalers_fast_ahb_clk =3D { + .halt_reg =3D 0x20200, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20200, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_scalers_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_clk =3D { + .halt_reg =3D 0x211dc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x211dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_jpeg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_ahb_clk =3D { + .halt_reg =3D 0x2011c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2011c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_anchor_clk =3D { + .halt_reg =3D 0x2014c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2014c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_anchor_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_anchor_fast_ahb_clk =3D { + .halt_reg =3D 0x200f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_anchor_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_hdr_clk =3D { + .halt_reg =3D 0x2015c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2015c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_hdr_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_hdr_fast_ahb_clk =3D { + .halt_reg =3D 0x200fc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200fc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_hdr_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_main_clk =3D { + .halt_reg =3D 0x20138, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20138, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_main_fast_ahb_clk =3D { + .halt_reg =3D 0x200f4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_mp_clk =3D { + .halt_reg =3D 0x2016c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2016c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_mp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_mp_fast_ahb_clk =3D { + .halt_reg =3D 0x20100, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20100, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_mp_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk =3D { + .halt_reg =3D 0x21328, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21328, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk =3D { + .halt_reg =3D 0x2132c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2132c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sqpf_ahb_clk =3D { + .halt_reg =3D 0x20250, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20250, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sqpf_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sqpf_clk =3D { + .halt_reg =3D 0x20234, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20234, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sqpf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_sqpf_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sqpf_fast_ahb_clk =3D { + .halt_reg =3D 0x20254, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20254, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sqpf_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_bayer_clk =3D { + .halt_reg =3D 0x21044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_bayer_fast_ahb_clk =3D { + .halt_reg =3D 0x21060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_bayer_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_main_clk =3D { + .halt_reg =3D 0x21030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_main_fast_ahb_clk =3D { + .halt_reg =3D 0x2105c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2105c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_bayer_clk =3D { + .halt_reg =3D 0x210c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x210c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_bayer_fast_ahb_clk =3D { + .halt_reg =3D 0x210dc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x210dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_bayer_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_main_clk =3D { + .halt_reg =3D 0x210ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x210ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_main_fast_ahb_clk =3D { + .halt_reg =3D 0x210d8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x210d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_bayer_clk =3D { + .halt_reg =3D 0x21124, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21124, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_bayer_fast_ahb_clk =3D { + .halt_reg =3D 0x21140, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21140, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_bayer_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_main_clk =3D { + .halt_reg =3D 0x21110, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21110, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_main_fast_ahb_clk =3D { + .halt_reg =3D 0x2113c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2113c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_titan_mnoc_hf_clk =3D { + .halt_reg =3D 0x213a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x213a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_titan_mnoc_hf_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_titan_mnoc_sf_clk =3D { + .halt_reg =3D 0x213b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x213b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_titan_mnoc_sf_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tracenoc_tpdm_1_cmb_clk =3D { + .halt_reg =3D 0x213dc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x213dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tracenoc_tpdm_1_cmb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_cx_gdsc =3D { + .gdscr =3D 0x21388, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_titan_top_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .needs_icc =3D true, + .icc_path_index =3D DT_ICC_TOP_GDSC, +}; + +static struct gdsc cam_cc_titan_top_gdsc =3D { + .gdscr =3D 0x21330, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_titan_top_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .needs_icc =3D true, + .icc_path_index =3D DT_ICC_TOP_GDSC, + .parent =3D &cam_cc_titan_top_cx_gdsc.pd, +}; + +static struct gdsc cam_cc_ipe_0_gdsc =3D { + .gdscr =3D 0x20188, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ipe_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &cam_cc_titan_top_gdsc.pd, +}; + +static struct gdsc cam_cc_ofe_gdsc =3D { + .gdscr =3D 0x200c8, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ofe_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &cam_cc_titan_top_gdsc.pd, +}; + +static struct gdsc cam_cc_sqpf_gdsc =3D { + .gdscr =3D 0x20208, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_sqpf_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &cam_cc_titan_top_gdsc.pd, +}; + +static struct gdsc cam_cc_tfe_0_gdsc =3D { + .gdscr =3D 0x21004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_tfe_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &cam_cc_titan_top_gdsc.pd, +}; + +static struct gdsc cam_cc_tfe_1_gdsc =3D { + .gdscr =3D 0x21080, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_tfe_1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &cam_cc_titan_top_gdsc.pd, +}; + +static struct gdsc cam_cc_tfe_2_gdsc =3D { + .gdscr =3D 0x210e4, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_tfe_2_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &cam_cc_titan_top_gdsc.pd, +}; + +static struct clk_regmap *cam_cc_hawi_clocks[] =3D { + [CAM_CC_CAM_TOP_AHB_CLK] =3D &cam_cc_cam_top_ahb_clk.clkr, + [CAM_CC_CAM_TOP_FAST_AHB_CLK] =3D &cam_cc_cam_top_fast_ahb_clk.clkr, + [CAM_CC_CAMNOC_NRT_AXI_CLK] =3D &cam_cc_camnoc_nrt_axi_clk.clkr, + [CAM_CC_CAMNOC_NRT_CRE_CLK] =3D &cam_cc_camnoc_nrt_cre_clk.clkr, + [CAM_CC_CAMNOC_NRT_IPE_NPS_CLK] =3D &cam_cc_camnoc_nrt_ipe_nps_clk.clkr, + [CAM_CC_CAMNOC_NRT_IPE_SCALERS_CLK] =3D &cam_cc_camnoc_nrt_ipe_scalers_cl= k.clkr, + [CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK] =3D &cam_cc_camnoc_nrt_ofe_main_clk.clkr, + [CAM_CC_CAMNOC_NRT_SQPF_CLK] =3D &cam_cc_camnoc_nrt_sqpf_clk.clkr, + [CAM_CC_CAMNOC_RT_AXI_CLK] =3D &cam_cc_camnoc_rt_axi_clk.clkr, + [CAM_CC_CAMNOC_RT_AXI_CLK_SRC] =3D &cam_cc_camnoc_rt_axi_clk_src.clkr, + [CAM_CC_CAMNOC_RT_IFE_LITE_CLK] =3D &cam_cc_camnoc_rt_ife_lite_clk.clkr, + [CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK] =3D &cam_cc_camnoc_rt_tfe_0_main_clk.cl= kr, + [CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK] =3D &cam_cc_camnoc_rt_tfe_1_main_clk.cl= kr, + [CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK] =3D &cam_cc_camnoc_rt_tfe_2_main_clk.cl= kr, + [CAM_CC_CCI_0_CLK] =3D &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] =3D &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] =3D &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] =3D &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CCI_2_CLK] =3D &cam_cc_cci_2_clk.clkr, + [CAM_CC_CCI_2_CLK_SRC] =3D &cam_cc_cci_2_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] =3D &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] =3D &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CRE_AHB_CLK] =3D &cam_cc_cre_ahb_clk.clkr, + [CAM_CC_CRE_CLK] =3D &cam_cc_cre_clk.clkr, + [CAM_CC_CRE_CLK_SRC] =3D &cam_cc_cre_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] =3D &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] =3D &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] =3D &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] =3D &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] =3D &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] =3D &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] =3D &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] =3D &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] =3D &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] =3D &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSI5PHYTIMER_CLK] =3D &cam_cc_csi5phytimer_clk.clkr, + [CAM_CC_CSI5PHYTIMER_CLK_SRC] =3D &cam_cc_csi5phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] =3D &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] =3D &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] =3D &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] =3D &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] =3D &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] =3D &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] =3D &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] =3D &cam_cc_csiphy4_clk.clkr, + [CAM_CC_CSIPHY5_CLK] =3D &cam_cc_csiphy5_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] =3D &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_0_AHB_CLK] =3D &cam_cc_icp_0_ahb_clk.clkr, + [CAM_CC_ICP_0_CLK] =3D &cam_cc_icp_0_clk.clkr, + [CAM_CC_ICP_0_CLK_SRC] =3D &cam_cc_icp_0_clk_src.clkr, + [CAM_CC_ICP_1_AHB_CLK] =3D &cam_cc_icp_1_ahb_clk.clkr, + [CAM_CC_ICP_1_CLK] =3D &cam_cc_icp_1_clk.clkr, + [CAM_CC_ICP_1_CLK_SRC] =3D &cam_cc_icp_1_clk_src.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] =3D &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] =3D &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] =3D &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] =3D &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] =3D &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] =3D &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_NPS_AHB_CLK] =3D &cam_cc_ipe_nps_ahb_clk.clkr, + [CAM_CC_IPE_NPS_CLK] =3D &cam_cc_ipe_nps_clk.clkr, + [CAM_CC_IPE_NPS_CLK_SRC] =3D &cam_cc_ipe_nps_clk_src.clkr, + [CAM_CC_IPE_NPS_FAST_AHB_CLK] =3D &cam_cc_ipe_nps_fast_ahb_clk.clkr, + [CAM_CC_IPE_PPS_CLK] =3D &cam_cc_ipe_pps_clk.clkr, + [CAM_CC_IPE_PPS_FAST_AHB_CLK] =3D &cam_cc_ipe_pps_fast_ahb_clk.clkr, + [CAM_CC_IPE_SCALERS_CLK] =3D &cam_cc_ipe_scalers_clk.clkr, + [CAM_CC_IPE_SCALERS_FAST_AHB_CLK] =3D &cam_cc_ipe_scalers_fast_ahb_clk.cl= kr, + [CAM_CC_JPEG_CLK] =3D &cam_cc_jpeg_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] =3D &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_OFE_AHB_CLK] =3D &cam_cc_ofe_ahb_clk.clkr, + [CAM_CC_OFE_ANCHOR_CLK] =3D &cam_cc_ofe_anchor_clk.clkr, + [CAM_CC_OFE_ANCHOR_FAST_AHB_CLK] =3D &cam_cc_ofe_anchor_fast_ahb_clk.clkr, + [CAM_CC_OFE_CLK_SRC] =3D &cam_cc_ofe_clk_src.clkr, + [CAM_CC_OFE_HDR_CLK] =3D &cam_cc_ofe_hdr_clk.clkr, + [CAM_CC_OFE_HDR_FAST_AHB_CLK] =3D &cam_cc_ofe_hdr_fast_ahb_clk.clkr, + [CAM_CC_OFE_MAIN_CLK] =3D &cam_cc_ofe_main_clk.clkr, + [CAM_CC_OFE_MAIN_FAST_AHB_CLK] =3D &cam_cc_ofe_main_fast_ahb_clk.clkr, + [CAM_CC_OFE_MP_CLK] =3D &cam_cc_ofe_mp_clk.clkr, + [CAM_CC_OFE_MP_FAST_AHB_CLK] =3D &cam_cc_ofe_mp_fast_ahb_clk.clkr, + [CAM_CC_PLL0] =3D &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] =3D &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] =3D &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL1] =3D &cam_cc_pll1.clkr, + [CAM_CC_PLL1_OUT_EVEN] =3D &cam_cc_pll1_out_even.clkr, + [CAM_CC_PLL2] =3D &cam_cc_pll2.clkr, + [CAM_CC_PLL2_OUT_EVEN] =3D &cam_cc_pll2_out_even.clkr, + [CAM_CC_PLL3] =3D &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] =3D &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] =3D &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] =3D &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] =3D &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] =3D &cam_cc_pll5_out_even.clkr, + [CAM_CC_PLL6] =3D &cam_cc_pll6.clkr, + [CAM_CC_PLL6_OUT_EVEN] =3D &cam_cc_pll6_out_even.clkr, + [CAM_CC_PLL6_OUT_ODD] =3D &cam_cc_pll6_out_odd.clkr, + [CAM_CC_PLL7] =3D &cam_cc_pll7.clkr, + [CAM_CC_PLL8] =3D &cam_cc_pll8.clkr, + [CAM_CC_PLL8_OUT_EVEN] =3D &cam_cc_pll8_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] =3D &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] =3D &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] =3D &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] =3D &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_SQPF_AHB_CLK] =3D &cam_cc_sqpf_ahb_clk.clkr, + [CAM_CC_SQPF_CLK] =3D &cam_cc_sqpf_clk.clkr, + [CAM_CC_SQPF_CLK_SRC] =3D &cam_cc_sqpf_clk_src.clkr, + [CAM_CC_SQPF_FAST_AHB_CLK] =3D &cam_cc_sqpf_fast_ahb_clk.clkr, + [CAM_CC_TFE_0_BAYER_CLK] =3D &cam_cc_tfe_0_bayer_clk.clkr, + [CAM_CC_TFE_0_BAYER_FAST_AHB_CLK] =3D &cam_cc_tfe_0_bayer_fast_ahb_clk.cl= kr, + [CAM_CC_TFE_0_CLK_SRC] =3D &cam_cc_tfe_0_clk_src.clkr, + [CAM_CC_TFE_0_MAIN_CLK] =3D &cam_cc_tfe_0_main_clk.clkr, + [CAM_CC_TFE_0_MAIN_FAST_AHB_CLK] =3D &cam_cc_tfe_0_main_fast_ahb_clk.clkr, + [CAM_CC_TFE_1_BAYER_CLK] =3D &cam_cc_tfe_1_bayer_clk.clkr, + [CAM_CC_TFE_1_BAYER_FAST_AHB_CLK] =3D &cam_cc_tfe_1_bayer_fast_ahb_clk.cl= kr, + [CAM_CC_TFE_1_CLK_SRC] =3D &cam_cc_tfe_1_clk_src.clkr, + [CAM_CC_TFE_1_MAIN_CLK] =3D &cam_cc_tfe_1_main_clk.clkr, + [CAM_CC_TFE_1_MAIN_FAST_AHB_CLK] =3D &cam_cc_tfe_1_main_fast_ahb_clk.clkr, + [CAM_CC_TFE_2_BAYER_CLK] =3D &cam_cc_tfe_2_bayer_clk.clkr, + [CAM_CC_TFE_2_BAYER_FAST_AHB_CLK] =3D &cam_cc_tfe_2_bayer_fast_ahb_clk.cl= kr, + [CAM_CC_TFE_2_CLK_SRC] =3D &cam_cc_tfe_2_clk_src.clkr, + [CAM_CC_TFE_2_MAIN_CLK] =3D &cam_cc_tfe_2_main_clk.clkr, + [CAM_CC_TFE_2_MAIN_FAST_AHB_CLK] =3D &cam_cc_tfe_2_main_fast_ahb_clk.clkr, + [CAM_CC_TITAN_MNOC_HF_CLK] =3D &cam_cc_titan_mnoc_hf_clk.clkr, + [CAM_CC_TITAN_MNOC_SF_CLK] =3D &cam_cc_titan_mnoc_sf_clk.clkr, + [CAM_CC_TRACENOC_TPDM_1_CMB_CLK] =3D &cam_cc_tracenoc_tpdm_1_cmb_clk.clkr, + [CAM_CC_XO_CLK_SRC] =3D &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_hawi_gdscs[] =3D { + [CAM_CC_IPE_0_GDSC] =3D &cam_cc_ipe_0_gdsc, + [CAM_CC_OFE_GDSC] =3D &cam_cc_ofe_gdsc, + [CAM_CC_SQPF_GDSC] =3D &cam_cc_sqpf_gdsc, + [CAM_CC_TFE_0_GDSC] =3D &cam_cc_tfe_0_gdsc, + [CAM_CC_TFE_1_GDSC] =3D &cam_cc_tfe_1_gdsc, + [CAM_CC_TFE_2_GDSC] =3D &cam_cc_tfe_2_gdsc, + [CAM_CC_TITAN_TOP_CX_GDSC] =3D &cam_cc_titan_top_cx_gdsc, + [CAM_CC_TITAN_TOP_GDSC] =3D &cam_cc_titan_top_gdsc, +}; + +static const struct qcom_reset_map cam_cc_hawi_resets[] =3D { + [CAM_CC_DRV_BCR] =3D { 0x213d4 }, + [CAM_CC_ICP_BCR] =3D { 0x211f4 }, + [CAM_CC_IPE_0_BCR] =3D { 0x20184 }, + [CAM_CC_OFE_BCR] =3D { 0x200c4 }, + [CAM_CC_QDSS_DEBUG_BCR] =3D { 0x2130c }, + [CAM_CC_SQPF_BCR] =3D { 0x20204 }, + [CAM_CC_TFE_0_BCR] =3D { 0x21000 }, + [CAM_CC_TFE_1_BCR] =3D { 0x2107c }, + [CAM_CC_TFE_2_BCR] =3D { 0x210e0 }, +}; + +static struct clk_alpha_pll *cam_cc_hawi_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, + &cam_cc_pll7, + &cam_cc_pll8, +}; + +static const u32 cam_cc_hawi_critical_cbcrs[] =3D { + 0x21308, /* CAM_CC_CAMNOC_DCD_XO_CLK */ + 0x2139c, /* CAM_CC_CX_GDSC_CLK */ + 0x213e0, /* CAM_CC_DRV_AHB_CLK */ + 0x213d8, /* CAM_CC_DRV_XO_CLK */ + 0x21360, /* CAM_CC_GDSC_CLK */ + 0x213d0, /* CAM_CC_MMSS_AHB_CLK */ + 0x21364, /* CAM_CC_SLEEP_CLK */ + 0x213a0, /* CAM_CC_TITAN_CAMNOC_XO_CLK */ +}; + +static const struct regmap_config cam_cc_hawi_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x26024, + .fast_io =3D true, +}; + +static const struct qcom_cc_driver_data cam_cc_hawi_driver_data =3D { + .alpha_plls =3D cam_cc_hawi_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_hawi_plls), + .clk_cbcrs =3D cam_cc_hawi_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_hawi_critical_cbcrs), +}; + +static const struct qcom_cc_desc cam_cc_hawi_desc =3D { + .config =3D &cam_cc_hawi_regmap_config, + .clks =3D cam_cc_hawi_clocks, + .num_clks =3D ARRAY_SIZE(cam_cc_hawi_clocks), + .resets =3D cam_cc_hawi_resets, + .num_resets =3D ARRAY_SIZE(cam_cc_hawi_resets), + .gdscs =3D cam_cc_hawi_gdscs, + .num_gdscs =3D ARRAY_SIZE(cam_cc_hawi_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_hawi_driver_data, +}; + +static const struct of_device_id cam_cc_hawi_match_table[] =3D { + { .compatible =3D "qcom,hawi-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_hawi_match_table); + +static int cam_cc_hawi_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &cam_cc_hawi_desc); +} + +static struct platform_driver cam_cc_hawi_driver =3D { + .probe =3D cam_cc_hawi_probe, + .driver =3D { + .name =3D "camcc-hawi", + .of_match_table =3D cam_cc_hawi_match_table, + }, +}; + +module_platform_driver(cam_cc_hawi_driver); + +MODULE_DESCRIPTION("QTI CAMCC Hawi Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1