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Tue, 15 Sep 2026 17:32:59 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 68E3D480029; Tue, 15 Sep 2026 17:32:59 +0200 (CEST) From: Sebastian Reichel Date: Tue, 15 Sep 2026 17:32:48 +0200 Subject: [PATCH v15 1/6] phy: rockchip: usbdp: Add phy reset notification support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-1-9ad90a456953@collabora.com> References: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-0-9ad90a456953@collabora.com> In-Reply-To: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-0-9ad90a456953@collabora.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Heiko Stuebner , Zhang Yubing , Frank Wang Cc: linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel , Igor Paunovic X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A To resolve issues with running into permanent "cmn ana lcpll lock timeout" errors after a few device replugs, add support for reset notifications, which will be handled by the DWC3 driver to gracefully handle the PHY being disabled. This avoids corrupting the controller's internal state and the PIPE interface between the USB3 controller and the PHY, thus fixing the issue. Tested-by: Igor Paunovic # Orange Pi 5 Plus Signed-off-by: Sebastian Reichel --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockch= ip/phy-rockchip-usbdp.c index e748acdd2d31..0f39982c70b1 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -1004,24 +1004,39 @@ static int rk_udphy_power_on(struct rk_udphy *udphy= , u8 mode) } =20 if (udphy->status =3D=3D UDPHY_MODE_NONE) { + phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_PRE_RESET); + + rk_udphy_u3_port_disable(udphy, true); + udelay(10); + ret =3D rk_udphy_setup(udphy); - if (ret) + if (ret) { + phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_POST_RESET); return ret; + } =20 if (!udphy->hs && udphy->mode & UDPHY_MODE_USB) rk_udphy_u3_port_disable(udphy, false); udphy->phy_needs_reinit =3D false; + + phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_POST_RESET); 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Tue, 15 Sep 2026 17:32:59 +0200 (CEST) From: Sebastian Reichel Date: Tue, 15 Sep 2026 17:32:49 +0200 Subject: [PATCH v15 2/6] phy: rockchip: usbdp: Drop -EPROBE_DEFER hack Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-2-9ad90a456953@collabora.com> References: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-0-9ad90a456953@collabora.com> In-Reply-To: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-0-9ad90a456953@collabora.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Heiko Stuebner , Zhang Yubing , Frank Wang Cc: linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel , Igor Paunovic X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A The hack to return -EPROBE_DEFER when the lcpll lock timeouts is no longer needed. The driver now does a reset during its PHY init, which avoids the problem. Since rk_udphy_status_check() is called after the probe, it should not return -EPROBE_DEFER. Tested-by: Igor Paunovic # Orange Pi 5 Plus Signed-off-by: Sebastian Reichel --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockch= ip/phy-rockchip-usbdp.c index 0f39982c70b1..144d83997a79 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -749,17 +749,7 @@ static int rk_udphy_status_check(struct rk_udphy *udph= y) (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000); if (ret) { dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); - /* - * If earlier software (U-Boot) enabled USB once already - * the PLL may have problems locking on the first try. - * It will be successful on the second try, so for the - * time being a -EPROBE_DEFER will solve the issue. - * - * This requires further investigation to understand the - * root cause, especially considering that the driver is - * asserting all reset lines at probe time. - */ - return -EPROBE_DEFER; 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Tue, 15 Sep 2026 17:32:59 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 6BB89480030; Tue, 15 Sep 2026 17:32:59 +0200 (CEST) From: Sebastian Reichel Date: Tue, 15 Sep 2026 17:32:50 +0200 Subject: [PATCH v15 3/6] phy: rockchip: usbdp: Rename mode to hw_mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-3-9ad90a456953@collabora.com> References: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-0-9ad90a456953@collabora.com> In-Reply-To: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-0-9ad90a456953@collabora.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Heiko Stuebner , Zhang Yubing , Frank Wang Cc: linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel , Igor Paunovic X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Rename mode field to hw_mode to make clear that this is the modes currently supported by the hardware, but not necessarily requested by software. I.e. it is only set by either the USB-C state machine or device-tree if the PHY is used in a fixed routing setup. Tested-by: Igor Paunovic # Orange Pi 5 Plus Signed-off-by: Sebastian Reichel --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 48 +++++++++++++++------------= ---- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockch= ip/phy-rockchip-usbdp.c index 144d83997a79..b06d94db42ea 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -173,7 +173,7 @@ struct rk_udphy { /* PHY status management */ bool flip; bool phy_needs_reinit; - u8 mode; + u8 hw_mode; /* modes currently supported by hardware */ u8 status; =20 /* utilized for USB */ @@ -578,18 +578,18 @@ static void rk_udphy_dp_lane_enable(struct rk_udphy *= udphy, int dp_lanes) CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); } =20 -static void rk_udphy_mode_set(struct rk_udphy *udphy, u8 mode) +static void rk_udphy_mode_set(struct rk_udphy *udphy, u8 hw_mode) { - if (udphy->mode =3D=3D mode) + if (udphy->hw_mode =3D=3D hw_mode) return; =20 udphy->phy_needs_reinit =3D true; - udphy->mode =3D mode; + udphy->hw_mode =3D hw_mode; } =20 static void rk_udphy_set_typec_state(struct rk_udphy *udphy, unsigned long= state) { - u8 mode; + u8 hw_mode; =20 switch (state) { case TYPEC_DP_STATE_C: @@ -598,7 +598,7 @@ static void rk_udphy_set_typec_state(struct rk_udphy *u= dphy, unsigned long state udphy->lane_mux_sel[1] =3D PHY_LANE_MUX_DP; udphy->lane_mux_sel[2] =3D PHY_LANE_MUX_DP; udphy->lane_mux_sel[3] =3D PHY_LANE_MUX_DP; - mode =3D UDPHY_MODE_DP; + hw_mode =3D UDPHY_MODE_DP; udphy->dp_lanes =3D 4; break; =20 @@ -615,12 +615,12 @@ static void rk_udphy_set_typec_state(struct rk_udphy = *udphy, unsigned long state udphy->lane_mux_sel[2] =3D PHY_LANE_MUX_DP; udphy->lane_mux_sel[3] =3D PHY_LANE_MUX_DP; } - mode =3D UDPHY_MODE_DP_USB; + hw_mode =3D UDPHY_MODE_DP_USB; udphy->dp_lanes =3D 2; break; } =20 - rk_udphy_mode_set(udphy, mode); + rk_udphy_mode_set(udphy, hw_mode); } =20 static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy) @@ -743,7 +743,7 @@ static int rk_udphy_status_check(struct rk_udphy *udphy) int ret; =20 /* LCPLL check */ - if (udphy->mode & UDPHY_MODE_USB) { + if (udphy->hw_mode & UDPHY_MODE_USB) { ret =3D regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_O= FFSET, val, (val & CMN_ANA_LCPLL_AFC_DONE) && (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000); @@ -778,15 +778,15 @@ static int rk_udphy_init(struct rk_udphy *udphy) int ret; =20 dev_dbg(udphy->dev, "reinit PHY with USB3=3D%s and DP=3D%s (%u lanes) fli= pped=3D%s\n", - str_on_off(udphy->mode & UDPHY_MODE_USB), - str_on_off(udphy->mode & UDPHY_MODE_DP), + str_on_off(udphy->hw_mode & UDPHY_MODE_USB), + str_on_off(udphy->hw_mode & UDPHY_MODE_DP), udphy->dp_lanes, str_yes_no(udphy->flip)); =20 rk_udphy_reset_assert_all(udphy); usleep_range(10000, 11000); =20 /* enable rx lfps for usb */ - if (udphy->mode & UDPHY_MODE_USB) + if (udphy->hw_mode & UDPHY_MODE_USB) rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); =20 /* Step 1: power on pma and deassert apb rstn */ @@ -823,13 +823,13 @@ static int rk_udphy_init(struct rk_udphy *udphy) FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); =20 /* Step 4: deassert init rstn and wait for 200ns from datasheet */ - if (udphy->mode & UDPHY_MODE_USB) { + if (udphy->hw_mode & UDPHY_MODE_USB) { ret =3D rk_udphy_reset_deassert(udphy, "init"); if (ret) goto assert_resets; } =20 - if (udphy->mode & UDPHY_MODE_DP) { + if (udphy->hw_mode & UDPHY_MODE_DP) { regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_INIT_RSTN, FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); @@ -838,7 +838,7 @@ static int rk_udphy_init(struct rk_udphy *udphy) udelay(1); =20 /* Step 5: deassert cmn/lane rstn */ - if (udphy->mode & UDPHY_MODE_USB) { + if (udphy->hw_mode & UDPHY_MODE_USB) { ret =3D rk_udphy_reset_deassert(udphy, "cmn"); if (ret) goto assert_resets; @@ -897,7 +897,7 @@ static int rk_udphy_parse_lane_mux_data(struct rk_udphy= *udphy) num_lanes =3D device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux= "); if (num_lanes < 0) { dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n"); - udphy->mode =3D UDPHY_MODE_USB; + udphy->hw_mode =3D UDPHY_MODE_USB; return 0; } =20 @@ -926,10 +926,10 @@ static int rk_udphy_parse_lane_mux_data(struct rk_udp= hy *udphy) } } =20 - udphy->mode =3D UDPHY_MODE_DP; + udphy->hw_mode =3D UDPHY_MODE_DP; udphy->dp_lanes =3D num_lanes; if (num_lanes =3D=3D 1 || num_lanes =3D=3D 2) { - udphy->mode |=3D UDPHY_MODE_USB; + udphy->hw_mode |=3D UDPHY_MODE_USB; udphy->flip =3D (udphy->lane_mux_sel[0] =3D=3D PHY_LANE_MUX_DP) || (udphy->lane_mux_sel[1] =3D=3D PHY_LANE_MUX_DP); } @@ -988,7 +988,7 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, u8= mode) { int ret; =20 - if (!(udphy->mode & mode)) { + if (!(udphy->hw_mode & mode)) { dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); return 0; } @@ -1005,7 +1005,7 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, = u8 mode) return ret; } =20 - if (!udphy->hs && udphy->mode & UDPHY_MODE_USB) + if (!udphy->hs && udphy->hw_mode & UDPHY_MODE_USB) rk_udphy_u3_port_disable(udphy, false); udphy->phy_needs_reinit =3D false; =20 @@ -1022,7 +1022,7 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, = u8 mode) return ret; } =20 - if (!udphy->hs && udphy->mode & UDPHY_MODE_USB) + if (!udphy->hs && udphy->hw_mode & UDPHY_MODE_USB) rk_udphy_u3_port_disable(udphy, false); udphy->phy_needs_reinit =3D false; =20 @@ -1036,7 +1036,7 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, = u8 mode) =20 static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode) { - if (!(udphy->mode & mode)) { + if (!(udphy->hw_mode & mode)) { dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); return; } @@ -1295,7 +1295,7 @@ static int rk_udphy_usb3_phy_init(struct phy *phy) guard(mutex)(&udphy->mutex); =20 /* DP only or high-speed, disable U3 port */ - if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { + if (!(udphy->hw_mode & UDPHY_MODE_USB) || udphy->hs) { rk_udphy_u3_port_disable(udphy, true); return 0; } @@ -1310,7 +1310,7 @@ static int rk_udphy_usb3_phy_exit(struct phy *phy) guard(mutex)(&udphy->mutex); =20 /* DP only or high-speed */ - if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) + if (!(udphy->hw_mode & UDPHY_MODE_USB) || udphy->hs) return 0; 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Tue, 15 Sep 2026 17:32:59 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 6D6A7480031; Tue, 15 Sep 2026 17:32:59 +0200 (CEST) From: Sebastian Reichel Date: Tue, 15 Sep 2026 17:32:51 +0200 Subject: [PATCH v15 4/6] phy: rockchip: usbdp: Fix power state handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-4-9ad90a456953@collabora.com> References: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-0-9ad90a456953@collabora.com> In-Reply-To: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-0-9ad90a456953@collabora.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Heiko Stuebner , Zhang Yubing , Frank Wang Cc: linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel , Igor Paunovic X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Restructure power state handling by introducing sw_mode in addition to the hw_mode field, so that the PHY knows about the currently supported modes from the hardware perspective, the current modes requested by software and the actual hardware status. Now anything updating either the hardware or software state can simply update the status field and call rk_udphy_update_power_state(). This makes it a lot more obvious what is going on and also fixes a few potential resource leaks identified by Sashiko as a side-effect. For example if USB3 is requested by software while the USB-C is in DP-only mode, things are decently handled after this. Tested-by: Igor Paunovic # Orange Pi 5 Plus Signed-off-by: Sebastian Reichel --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 143 +++++++++++++++++++-------= ---- 1 file changed, 90 insertions(+), 53 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockch= ip/phy-rockchip-usbdp.c index b06d94db42ea..867f356f394d 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -172,9 +172,10 @@ struct rk_udphy { =20 /* PHY status management */ bool flip; - bool phy_needs_reinit; + bool phy_needs_reinit; /* lane mux changed */ u8 hw_mode; /* modes currently supported by hardware */ - u8 status; + u8 sw_mode; /* modes currently requested */ + u8 status; /* current PHY power state */ =20 /* utilized for USB */ bool hs; /* flag for high-speed */ @@ -984,70 +985,95 @@ static int rk_udphy_parse_dt(struct rk_udphy *udphy) return rk_udphy_reset_init(udphy, dev); } =20 -static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode) +static int rk_udphy_update_power_state(struct rk_udphy *udphy) { + bool usb3_port_enable; + u8 target_mode; int ret; =20 - if (!(udphy->hw_mode & mode)) { - dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); + /* + * Initialize PHY mode according to the hardware setup (either described + * in DT or negotiated via the Type-C controller) instead of requesting + * only the needed PHY side, because that would break the USB/DP data + * streams when the other PHY is being requested. This is not an issue + * during the Type-C negotiation as that happens during the hotplug phase + * and not during normal operation. Also disable everything if the + * software has not requested anything, as there shouldn't be any active + * data streams in that case. + */ + target_mode =3D udphy->hw_mode; + if (udphy->sw_mode =3D=3D UDPHY_MODE_NONE) + target_mode =3D UDPHY_MODE_NONE; + + usb3_port_enable =3D !udphy->hs && (target_mode & UDPHY_MODE_USB); + + if (!udphy->phy_needs_reinit && udphy->status =3D=3D target_mode) { + if (udphy->sw_mode & UDPHY_MODE_USB) + rk_udphy_u3_port_disable(udphy, !usb3_port_enable); return 0; } =20 - if (udphy->status =3D=3D UDPHY_MODE_NONE) { - phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_PRE_RESET); + /* Avoid to re-init disabled PHY */ + if (udphy->status =3D=3D target_mode && target_mode =3D=3D UDPHY_MODE_NON= E) + return 0; =20 + /* + * Inform DWC3 driver, that we are about to reset the PHY, so that it can + * assert its PIPE reset lines and avoid DWC3 getting into a buggy state. + * This is intentionally done for a PHY disable, since that also changes + * the clocks routed to the PHY. + */ + ret =3D phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_PRE_RESET); + if (ret) + return ret; + + /* + * Disable USB3 port, which among other things re-routes a DWC3 clock to + * avoid SErrors when the DWC3 registers are accessed while the PHY is + * disabled. This is only done, when the DWC3 is running as the accessed + * GRF registers and in PD_USB. + */ + if (udphy->sw_mode & UDPHY_MODE_USB) { rk_udphy_u3_port_disable(udphy, true); udelay(10); + } =20 + if (udphy->status =3D=3D UDPHY_MODE_NONE) { + /* Power up (incl. clocks) */ ret =3D rk_udphy_setup(udphy); if (ret) { phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_POST_RESET); return ret; } - - if (!udphy->hs && udphy->hw_mode & UDPHY_MODE_USB) - rk_udphy_u3_port_disable(udphy, false); - udphy->phy_needs_reinit =3D false; - - phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_POST_RESET); - } else if (udphy->phy_needs_reinit) { - phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_PRE_RESET); - - rk_udphy_u3_port_disable(udphy, true); - udelay(10); - + } else if (target_mode =3D=3D UDPHY_MODE_NONE) { + /* Power down (incl. clocks) */ + rk_udphy_disable(udphy); + } else { + /* Mode change =3D> re-init */ ret =3D rk_udphy_init(udphy); if (ret) { phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_POST_RESET); return ret; } - - if (!udphy->hs && udphy->hw_mode & UDPHY_MODE_USB) - rk_udphy_u3_port_disable(udphy, false); - udphy->phy_needs_reinit =3D false; - - phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_POST_RESET); } =20 - udphy->status |=3D mode; - - return 0; -} + /* Ensure USB3 support is enabled when supported */ + if (udphy->sw_mode & UDPHY_MODE_USB) + rk_udphy_u3_port_disable(udphy, !usb3_port_enable); =20 -static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode) -{ - if (!(udphy->hw_mode & mode)) { - dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); - return; - } - - if (!udphy->status) - return; + /* + * Inform DWC3, that we are done with the reset, so that it can deassert + * its PIPE reset line. This is sent in pair with a PRE_RESET allowing + * consumer driver to do paired resource requests (e.g. clocks) in their + * notification handlers. As we reroute the clocks, its also fine to + * send this after completely disabling the PHY. + */ + phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_POST_RESET); =20 - udphy->status &=3D ~mode; + udphy->status =3D target_mode; + udphy->phy_needs_reinit =3D false; =20 - if (udphy->status =3D=3D UDPHY_MODE_NONE) - rk_udphy_disable(udphy); + return 0; } =20 static int rk_udphy_dp_phy_power_on(struct phy *phy) @@ -1056,11 +1082,15 @@ static int rk_udphy_dp_phy_power_on(struct phy *phy) int ret; =20 scoped_guard(mutex, &udphy->mutex) { + udphy->sw_mode |=3D UDPHY_MODE_DP; + phy_set_bus_width(phy, udphy->dp_lanes); =20 - ret =3D rk_udphy_power_on(udphy, UDPHY_MODE_DP); - if (ret) + ret =3D rk_udphy_update_power_state(udphy); + if (ret) { + udphy->sw_mode &=3D ~UDPHY_MODE_DP; return ret; + } =20 rk_udphy_dp_lane_enable(udphy, udphy->dp_lanes); =20 @@ -1083,10 +1113,10 @@ static int rk_udphy_dp_phy_power_off(struct phy *ph= y) =20 guard(mutex)(&udphy->mutex); =20 - rk_udphy_dp_lane_enable(udphy, 0); - rk_udphy_power_off(udphy, UDPHY_MODE_DP); + udphy->sw_mode &=3D ~UDPHY_MODE_DP; =20 - return 0; + rk_udphy_dp_lane_enable(udphy, 0); + return rk_udphy_update_power_state(udphy); } =20 /* @@ -1291,16 +1321,24 @@ static const struct phy_ops rk_udphy_dp_phy_ops =3D= { static int rk_udphy_usb3_phy_init(struct phy *phy) { struct rk_udphy *udphy =3D phy_get_drvdata(phy); + int ret; =20 guard(mutex)(&udphy->mutex); =20 - /* DP only or high-speed, disable U3 port */ - if (!(udphy->hw_mode & UDPHY_MODE_USB) || udphy->hs) { + if (udphy->hs) { rk_udphy_u3_port_disable(udphy, true); return 0; } =20 - return rk_udphy_power_on(udphy, UDPHY_MODE_USB); + udphy->sw_mode |=3D UDPHY_MODE_USB; + + ret =3D rk_udphy_update_power_state(udphy); + if (ret) { + udphy->sw_mode &=3D ~UDPHY_MODE_USB; + return ret; + } + + return 0; } =20 static int rk_udphy_usb3_phy_exit(struct phy *phy) @@ -1309,13 +1347,12 @@ static int rk_udphy_usb3_phy_exit(struct phy *phy) =20 guard(mutex)(&udphy->mutex); =20 - /* DP only or high-speed */ - if (!(udphy->hw_mode & UDPHY_MODE_USB) || udphy->hs) + if (udphy->hs) return 0; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Ensure that the right part of the PHY are powered up when the mode changes. This ensures the PHY is re-initialized in the following two scenarios, which are currently broken: - cable orientation changes without DP being involved - switching from DP-only into a mode with USB support Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver") Tested-by: Igor Paunovic # Orange Pi 5 Plus Signed-off-by: Sebastian Reichel --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockch= ip/phy-rockchip-usbdp.c index 867f356f394d..ca01c1112c0f 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -1391,7 +1391,7 @@ static int rk_udphy_typec_mux_set(struct typec_mux_de= v *mux, =20 rk_udphy_set_typec_state(udphy, state->mode); =20 - return 0; + return rk_udphy_update_power_state(udphy); } =20 static void rk_udphy_typec_mux_unregister(void *data) --=20 2.53.0 From nobody Fri Sep 25 07:23:45 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 537514BA1E8 for ; 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Tue, 15 Sep 2026 17:33:00 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 711C9480038; Tue, 15 Sep 2026 17:32:59 +0200 (CEST) From: Sebastian Reichel Date: Tue, 15 Sep 2026 17:32:53 +0200 Subject: [PATCH v15 6/6] phy: rockchip: usbdp: Add USB-C state without DP enabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-6-9ad90a456953@collabora.com> References: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-0-9ad90a456953@collabora.com> In-Reply-To: <20260915-b4-rockchip-usbdp-cleanup-part3-v15-0-9ad90a456953@collabora.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Heiko Stuebner , Zhang Yubing , Frank Wang Cc: linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel , Igor Paunovic X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A The driver currently only differs between 4 lanes DP mode or combined DP + USB3 mode. This makes sense from a lane routing point of view, as the hardware only has 2 lanes of USB3. But adding a separate state for USB-only helps with power management, since we always power up all PHY parts according to the current hardware setup to avoid data stream interruptions. Even if some lanes are muxed to the DP controller there is no need to keep the DP side enabled if something without DP AltMode is plugged into USB-C. This potentially triggers some more USB reconnections during the PD AltMode negotiation when switching from USB-only to combined USB+DP mode. This should be fine, as the cable is freshly plugged at this point. Tested-by: Igor Paunovic # Orange Pi 5 Plus Signed-off-by: Sebastian Reichel --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 57 ++++++++++++++++++---------= ---- 1 file changed, 33 insertions(+), 24 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockch= ip/phy-rockchip-usbdp.c index ca01c1112c0f..f95c3216364f 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -579,32 +579,14 @@ static void rk_udphy_dp_lane_enable(struct rk_udphy *= udphy, int dp_lanes) CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); } =20 -static void rk_udphy_mode_set(struct rk_udphy *udphy, u8 hw_mode) +static void rk_udphy_set_lane_mux(struct rk_udphy *udphy) { - if (udphy->hw_mode =3D=3D hw_mode) - return; - - udphy->phy_needs_reinit =3D true; - udphy->hw_mode =3D hw_mode; -} - -static void rk_udphy_set_typec_state(struct rk_udphy *udphy, unsigned long= state) -{ - u8 hw_mode; - - switch (state) { - case TYPEC_DP_STATE_C: - case TYPEC_DP_STATE_E: + if (udphy->dp_lanes =3D=3D 4) { udphy->lane_mux_sel[0] =3D PHY_LANE_MUX_DP; udphy->lane_mux_sel[1] =3D PHY_LANE_MUX_DP; udphy->lane_mux_sel[2] =3D PHY_LANE_MUX_DP; udphy->lane_mux_sel[3] =3D PHY_LANE_MUX_DP; - hw_mode =3D UDPHY_MODE_DP; - udphy->dp_lanes =3D 4; - break; - - case TYPEC_DP_STATE_D: - default: + } else { if (udphy->flip) { udphy->lane_mux_sel[0] =3D PHY_LANE_MUX_DP; udphy->lane_mux_sel[1] =3D PHY_LANE_MUX_DP; @@ -616,12 +598,39 @@ static void rk_udphy_set_typec_state(struct rk_udphy = *udphy, unsigned long state udphy->lane_mux_sel[2] =3D PHY_LANE_MUX_DP; udphy->lane_mux_sel[3] =3D PHY_LANE_MUX_DP; } - hw_mode =3D UDPHY_MODE_DP_USB; - udphy->dp_lanes =3D 2; + } +} + +static void rk_udphy_mode_set(struct rk_udphy *udphy, u8 hw_mode, u8 dp_la= nes) +{ + if (udphy->hw_mode =3D=3D hw_mode && udphy->dp_lanes =3D=3D dp_lanes) + return; + + udphy->phy_needs_reinit =3D true; + udphy->hw_mode =3D hw_mode; + udphy->dp_lanes =3D dp_lanes; +} + +static void rk_udphy_set_typec_state(struct rk_udphy *udphy, unsigned long= state) +{ + switch (state) { + case TYPEC_DP_STATE_C: + case TYPEC_DP_STATE_E: + rk_udphy_mode_set(udphy, UDPHY_MODE_DP, 4); + break; + + case TYPEC_DP_STATE_D: + rk_udphy_mode_set(udphy, UDPHY_MODE_DP_USB, 2); + break; + + case TYPEC_STATE_SAFE: + case TYPEC_STATE_USB: + default: + rk_udphy_mode_set(udphy, UDPHY_MODE_USB, 0); break; } =20 - rk_udphy_mode_set(udphy, hw_mode); + rk_udphy_set_lane_mux(udphy); } =20 static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy) --=20 2.53.0