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Currently this teardown is open-coded in iommu_deinit_device; however when 32-bit ARM gains a parallel implementation of iommu_setup_dma_ops it becomes nicer to have a matching parallel iommu_teardown_dma_ops as well. Signed-off-by: Mikko Perttunen --- drivers/iommu/dma-iommu.c | 5 +++++ drivers/iommu/dma-iommu.h | 5 +++++ drivers/iommu/iommu.c | 3 +-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9abaec0703ef..26674eec5996 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -2166,6 +2166,11 @@ void iommu_setup_dma_ops(struct device *dev, struct = iommu_domain *domain) dev_clear_dma_iommu(dev); } =20 +void iommu_teardown_dma_ops(struct device *dev) +{ + dev_clear_dma_iommu(dev); +} + static bool has_msi_cookie(const struct iommu_domain *domain) { return domain && (domain->cookie_type =3D=3D IOMMU_COOKIE_DMA_IOVA || diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index 040d00252563..349d6a57e5a0 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -10,6 +10,7 @@ #ifdef CONFIG_IOMMU_DMA =20 void iommu_setup_dma_ops(struct device *dev, struct iommu_domain *domain); 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Currently that struct owns an IOMMU domain -- to allow inverting that relation, add a cookie type pointing to a struct dma_iommu_mapping, more in line with how other architectures work. Signed-off-by: Mikko Perttunen --- drivers/iommu/iommu.c | 1 + include/linux/iommu.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 75687d1aafe9..43dd69662fac 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2127,6 +2127,7 @@ void iommu_domain_free(struct iommu_domain *domain) { switch (domain->cookie_type) { case IOMMU_COOKIE_DMA_IOVA: + case IOMMU_COOKIE_ARM_DMA: iommu_put_dma_cookie(domain); break; case IOMMU_COOKIE_DMA_MSI: diff --git a/include/linux/iommu.h b/include/linux/iommu.h index d20aa6f6863a..e2f8513d2067 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -43,6 +43,7 @@ struct notifier_block; struct iommu_sva; struct iommu_dma_cookie; struct iommu_dma_msi_cookie; +struct dma_iommu_mapping; struct iommu_fault_param; struct iommufd_ctx; struct iommufd_viommu; @@ -174,6 +175,7 @@ enum iommu_domain_cookie_type { IOMMU_COOKIE_FAULT_HANDLER, IOMMU_COOKIE_SVA, IOMMU_COOKIE_IOMMUFD, + IOMMU_COOKIE_ARM_DMA, }; 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and the corresponding IOMMU domain. Split out the former into __arm_iommu_alloc_mapping(), with a matching __arm_iommu_free_mapping(), so that the bookkeeping can be created independently when a domain is allocated outside the ARM dma-mapping code. A later patch uses this to turn struct dma_iommu_mapping into an IOMMU domain cookie. No functional change. Signed-off-by: Mikko Perttunen --- arch/arm/mm/dma-mapping.c | 76 +++++++++++++++++++++++++++++--------------= ---- 1 file changed, 47 insertions(+), 29 deletions(-) diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index f9bc53b60f99..a7ad194960ce 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -1470,21 +1470,8 @@ static const struct dma_map_ops iommu_ops =3D { .sync_sg_for_device =3D arm_iommu_sync_sg_for_device, }; =20 -/** - * arm_iommu_create_mapping - * @dev: pointer to the client device (for IOMMU calls) - * @base: start address of the valid IO address space - * @size: maximum size of the valid IO address space - * - * Creates a mapping structure which holds information about used/unused - * IO address ranges, which is required to perform memory allocation and - * mapping with IOMMU aware functions. - * - * The client device need to be attached to the mapping with - * arm_iommu_attach_device function. - */ -struct dma_iommu_mapping * -arm_iommu_create_mapping(struct device *dev, dma_addr_t base, u64 size) +static struct dma_iommu_mapping * +__arm_iommu_alloc_mapping(dma_addr_t base, u64 size) { unsigned int bits =3D size >> PAGE_SHIFT; unsigned int bitmap_size =3D BITS_TO_LONGS(bits) * sizeof(long); @@ -1525,16 +1512,7 @@ arm_iommu_create_mapping(struct device *dev, dma_add= r_t base, u64 size) =20 spin_lock_init(&mapping->lock); =20 - mapping->domain =3D iommu_paging_domain_alloc(dev); - if (IS_ERR(mapping->domain)) { - err =3D PTR_ERR(mapping->domain); - goto err4; - } - - kref_init(&mapping->kref); return mapping; -err4: - kfree(mapping->bitmaps[0]); err3: kfree(mapping->bitmaps); err2: @@ -1542,21 +1520,61 @@ arm_iommu_create_mapping(struct device *dev, dma_ad= dr_t base, u64 size) err: return ERR_PTR(err); } -EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); =20 -static void release_iommu_mapping(struct kref *kref) +static void __arm_iommu_free_mapping(struct dma_iommu_mapping *mapping) { int i; - struct dma_iommu_mapping *mapping =3D - container_of(kref, struct dma_iommu_mapping, kref); =20 - iommu_domain_free(mapping->domain); for (i =3D 0; i < mapping->nr_bitmaps; i++) kfree(mapping->bitmaps[i]); kfree(mapping->bitmaps); kfree(mapping); } =20 +/** + * arm_iommu_create_mapping + * @dev: pointer to the client device (for IOMMU calls) + * @base: start address of the valid IO address space + * @size: maximum size of the valid IO address space + * + * Creates a mapping structure which holds information about used/unused + * IO address ranges, which is required to perform memory allocation and + * mapping with IOMMU aware functions. + * + * The client device need to be attached to the mapping with + * arm_iommu_attach_device function. + */ +struct dma_iommu_mapping * +arm_iommu_create_mapping(struct device *dev, dma_addr_t base, u64 size) +{ + struct dma_iommu_mapping *mapping; + + mapping =3D __arm_iommu_alloc_mapping(base, size); + if (IS_ERR(mapping)) + return mapping; + + mapping->domain =3D iommu_paging_domain_alloc(dev); + if (IS_ERR(mapping->domain)) { + int err =3D PTR_ERR(mapping->domain); + + __arm_iommu_free_mapping(mapping); + return ERR_PTR(err); + } + + kref_init(&mapping->kref); + return mapping; +} +EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); + +static void release_iommu_mapping(struct kref *kref) +{ + struct dma_iommu_mapping *mapping =3D + container_of(kref, struct dma_iommu_mapping, kref); + + iommu_domain_free(mapping->domain); + __arm_iommu_free_mapping(mapping); +} + static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) { int next_bitmap; --=20 2.55.0 From nobody Fri Sep 25 08:47:51 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010047.outbound.protection.outlook.com [40.93.198.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 926873D332C; Tue, 15 Sep 2026 02:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.198.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789438565; cv=fail; b=DoWmjtVmC8/4Yes/21SgK7oIhkf/A40zreIGjVS8by8N8xnlhOvUGgu6QfL354wUwnP1ktOGzuctBU3MzZPUC6UgVuvBPnzD7ajNNdjYovPQA6lZAjgYG/CXPL04OydEXROui7lkES0tYuEkW8GDf4MJjlJFqmqqFKlDrTwFH0M= ARC-Message-Signature: i=2; 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To allow the IOMMU core to own DMA domains as is the case with other architectures, we have to allow that code to allocate the domain and get the cookie from the ARM DMA code. Implement ARM versions of iommu_get/put_dma_cookie that create a struct dma_iommu_mapping that doesn't have its own domain, as well as iommu_setup/teardown_dma_ops that set the device's archdata.mapping, allowing ARM DMA ops to seamlessly work on these devices. The code is protected by CONFIG_ARM_DMA_USE_IOMMU and mutually exclusive with the same-named functions in the dma-iommu code; and not reachable yet. Signed-off-by: Mikko Perttunen --- arch/arm/include/asm/dma-iommu.h | 17 ++++++ arch/arm/mm/dma-mapping.c | 118 ++++++++++++++++++++++++++++++++++-= ---- drivers/iommu/dma-iommu.h | 50 +++++++++++------ 3 files changed, 154 insertions(+), 31 deletions(-) diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-io= mmu.h index 2ce4c5683e6d..85cf9b05faab 100644 --- a/arch/arm/include/asm/dma-iommu.h +++ b/arch/arm/include/asm/dma-iommu.h @@ -19,6 +19,14 @@ struct dma_iommu_mapping { size_t bits; /* per bitmap */ dma_addr_t base; =20 + /* + * Set for mappings created by arm_iommu_create_mapping(), where + * @domain is owned by the mapping. + * Clear for mappings that are a cookie of a domain owned by the IOMMU + * core. + */ + bool owns_domain; + spinlock_t lock; struct kref kref; }; @@ -32,5 +40,14 @@ int arm_iommu_attach_device(struct device *dev, struct dma_iommu_mapping *mapping); void arm_iommu_detach_device(struct device *dev); =20 +#ifdef CONFIG_ARM_DMA_USE_IOMMU +struct iommu_domain; + +void iommu_setup_dma_ops(struct device *dev, struct iommu_domain *domain); +void iommu_teardown_dma_ops(struct device *dev); +int iommu_get_dma_cookie(struct iommu_domain *domain); +void iommu_put_dma_cookie(struct iommu_domain *domain); +#endif + #endif /* __KERNEL__ */ #endif diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index a7ad194960ce..e0d58778c5f5 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -1531,6 +1531,79 @@ static void __arm_iommu_free_mapping(struct dma_iomm= u_mapping *mapping) kfree(mapping); } =20 +static int __arm_iommu_init_cookie(struct iommu_domain *domain, + dma_addr_t base, u64 size) +{ + struct dma_iommu_mapping *mapping; + + if (domain->cookie_type !=3D IOMMU_COOKIE_NONE) + return -EEXIST; + + mapping =3D __arm_iommu_alloc_mapping(base, size); + if (IS_ERR(mapping)) + return PTR_ERR(mapping); + + mapping->domain =3D domain; + domain->cookie_type =3D IOMMU_COOKIE_ARM_DMA; + domain->arm_cookie =3D mapping; + + return 0; +} + +/** + * iommu_get_dma_cookie - Set up a domain cookie for ARM IOMMU-based DMA A= PI + * @domain: IOMMU_DOMAIN_DMA domain being configured + * + * Allocates IOVA bookkeeping for the domain based on the domain's specifi= ed + * geometry. The aperture can currently be at most 4GB in size, otherwise + * fails with -ERANGE. + */ +int iommu_get_dma_cookie(struct iommu_domain *domain) +{ + dma_addr_t base =3D domain->geometry.aperture_start; + u64 size; + + if (base > domain->geometry.aperture_end) + return -EINVAL; + + size =3D (u64)domain->geometry.aperture_end - base + 1; + + return __arm_iommu_init_cookie(domain, base, size); +} + +/** + * iommu_put_dma_cookie - Free domain cookie for ARM IOMMU-based DMA API + * @domain: the domain being freed + */ +void iommu_put_dma_cookie(struct iommu_domain *domain) +{ + __arm_iommu_free_mapping(domain->arm_cookie); +} + +/** + * iommu_setup_dma_ops - Record a device's DMA API domain cookie + * @dev: the device + * @domain: the group's new default domain + * + * Records the cookie of @domain on @dev, or clears it if @domain is not a= DMA + * API domain. The DMA ops themselves are per driver binding and are insta= lled + * by arch_setup_dma_ops(). + */ +void iommu_setup_dma_ops(struct device *dev, struct iommu_domain *domain) +{ + to_dma_iommu_mapping(dev) =3D iommu_is_dma_domain(domain) ? + domain->arm_cookie : NULL; +} + +/** + * iommu_teardown_dma_ops - Clear a device's DMA API domain cookie + * @dev: the device + */ +void iommu_teardown_dma_ops(struct device *dev) +{ + to_dma_iommu_mapping(dev) =3D NULL; +} + /** * arm_iommu_create_mapping * @dev: pointer to the client device (for IOMMU calls) @@ -1541,28 +1614,32 @@ static void __arm_iommu_free_mapping(struct dma_iom= mu_mapping *mapping) * IO address ranges, which is required to perform memory allocation and * mapping with IOMMU aware functions. * + * Unlike a default domain set up by the IOMMU core, the returned mapping = owns + * the domain it describes and releases it along with the last reference. + * * The client device need to be attached to the mapping with * arm_iommu_attach_device function. */ struct dma_iommu_mapping * arm_iommu_create_mapping(struct device *dev, dma_addr_t base, u64 size) { - struct dma_iommu_mapping *mapping; - - mapping =3D __arm_iommu_alloc_mapping(base, size); - if (IS_ERR(mapping)) - return mapping; + struct iommu_domain *domain; + int err; =20 - mapping->domain =3D iommu_paging_domain_alloc(dev); - if (IS_ERR(mapping->domain)) { - int err =3D PTR_ERR(mapping->domain); + domain =3D iommu_paging_domain_alloc(dev); + if (IS_ERR(domain)) + return ERR_CAST(domain); =20 - __arm_iommu_free_mapping(mapping); + err =3D __arm_iommu_init_cookie(domain, base, size); + if (err) { + iommu_domain_free(domain); return ERR_PTR(err); } =20 - kref_init(&mapping->kref); - return mapping; + domain->arm_cookie->owns_domain =3D true; + kref_init(&domain->arm_cookie->kref); + + return domain->arm_cookie; } EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); =20 @@ -1571,8 +1648,8 @@ static void release_iommu_mapping(struct kref *kref) struct dma_iommu_mapping *mapping =3D container_of(kref, struct dma_iommu_mapping, kref); =20 + /* Frees mapping too, via iommu_put_dma_cookie(). */ iommu_domain_free(mapping->domain); - __arm_iommu_free_mapping(mapping); } =20 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) @@ -1595,8 +1672,13 @@ static int extend_iommu_mapping(struct dma_iommu_map= ping *mapping) =20 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) { - if (mapping) - kref_put(&mapping->kref, release_iommu_mapping); + if (!mapping) + return; + + if (WARN_ON(!mapping->owns_domain)) + return; + + kref_put(&mapping->kref, release_iommu_mapping); } EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); =20 @@ -1660,6 +1742,14 @@ void arm_iommu_detach_device(struct device *dev) return; } =20 + /* + * This pairs with arm_iommu_attach_device() on a driver-owned mapping. + * A mapping which is merely the cookie of a core-owned default domain + * must not be torn down from here. + */ + if (WARN_ON(!mapping->owns_domain)) + return; + iommu_detach_device(mapping->domain, dev); kref_put(&mapping->kref, release_iommu_mapping); to_dma_iommu_mapping(dev) =3D NULL; diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index 349d6a57e5a0..71b23cb698c0 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -7,25 +7,24 @@ =20 #include =20 -#ifdef CONFIG_IOMMU_DMA +/* + * Both dma-iommu.c and arch/arm/mm/dma-mapping.c implement functions to s= et up + * IOMMU_DOMAIN_DMA default domains. Only one provider can be compiled in = at a + * time. + */ +#if defined(CONFIG_ARM_DMA_USE_IOMMU) + +#include + +#elif defined(CONFIG_IOMMU_DMA) =20 void iommu_setup_dma_ops(struct device *dev, struct iommu_domain *domain); void iommu_teardown_dma_ops(struct device *dev); =20 int iommu_get_dma_cookie(struct iommu_domain *domain); void iommu_put_dma_cookie(struct iommu_domain *domain); -void iommu_put_msi_cookie(struct iommu_domain *domain); =20 -int iommu_dma_init_fq(struct iommu_domain *domain); - -void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list= ); - -int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr); - -extern bool iommu_dma_forcedac; - -#else /* CONFIG_IOMMU_DMA */ +#else =20 static inline void iommu_setup_dma_ops(struct device *dev, struct iommu_domain *domain) @@ -36,11 +35,6 @@ static inline void iommu_teardown_dma_ops(struct device = *dev) { } =20 -static inline int iommu_dma_init_fq(struct iommu_domain *domain) -{ - return -EINVAL; -} - static inline int iommu_get_dma_cookie(struct iommu_domain *domain) { return -ENODEV; @@ -50,6 +44,28 @@ static inline void iommu_put_dma_cookie(struct iommu_dom= ain *domain) { } =20 +#endif + +#ifdef CONFIG_IOMMU_DMA + +void iommu_put_msi_cookie(struct iommu_domain *domain); + +int iommu_dma_init_fq(struct iommu_domain *domain); + +void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list= ); + +int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, + phys_addr_t msi_addr); + +extern bool iommu_dma_forcedac; + +#else /* CONFIG_IOMMU_DMA */ + +static inline int iommu_dma_init_fq(struct iommu_domain *domain) +{ + return -EINVAL; +} + static inline void iommu_put_msi_cookie(struct iommu_domain *domain) { } --=20 2.55.0 From nobody Fri Sep 25 08:47:51 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010047.outbound.protection.outlook.com [40.93.198.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 234123D1CCA; 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When, however, that DMA default domain is requested and the core owns the domain, we need to skip our own domain management. Add checks to arm_setup/teardown_iommu_dma_ops for these cases. Signed-off-by: Mikko Perttunen --- arch/arm/mm/dma-mapping.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index e0d58778c5f5..91f12fb91509 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -1761,9 +1761,18 @@ EXPORT_SYMBOL_GPL(arm_iommu_detach_device); =20 static void arm_setup_iommu_dma_ops(struct device *dev) { - struct dma_iommu_mapping *mapping; + struct dma_iommu_mapping *mapping =3D to_dma_iommu_mapping(dev); u64 dma_base =3D 0, size =3D 1ULL << 32; =20 + /* + * An existing cookie means the core owns the domain. Only set the + * per-binding DMA ops. + */ + if (mapping) { + set_dma_ops(dev, &iommu_ops); + return; + } + if (dev->dma_range_map) { dma_base =3D dma_range_map_min(dev->dma_range_map); size =3D dma_range_map_max(dev->dma_range_map) - dma_base; @@ -1792,6 +1801,9 @@ static void arm_teardown_iommu_dma_ops(struct device = *dev) if (!mapping) return; =20 + if (!mapping->owns_domain) + return; + arm_iommu_detach_device(dev); arm_iommu_release_mapping(mapping); } --=20 2.55.0 From nobody Fri Sep 25 08:47:51 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010047.outbound.protection.outlook.com [40.93.198.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D2943D34A8; Tue, 15 Sep 2026 02:16:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.198.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; 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This is stricter than iommu_dma_get_sgtable(), which falls back to describing the buffer as a single chunk. The difference shows up when a buffer is allocated for one device and mapped for another, as TegraDRM does. Buffers are allocated on the host1x logical device, which has no dma_configure and therefore uses direct DMA ops, and are then mapped for a display controller behind the SMMU. Add the same fallback as iommu_dma_get_sgtable(). Signed-off-by: Mikko Perttunen --- arch/arm/mm/dma-mapping.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 91f12fb91509..22bde6acd1d3 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -1169,12 +1169,29 @@ static int arm_iommu_get_sgtable(struct device *dev= , struct sg_table *sgt, { unsigned int count =3D PAGE_ALIGN(size) >> PAGE_SHIFT; struct page **pages =3D __iommu_get_pages(cpu_addr, attrs); + struct page *page; + int ret; =20 - if (!pages) - return -ENXIO; + if (pages) + return sg_alloc_table_from_pages(sgt, pages, count, 0, size, + GFP_KERNEL); =20 - return sg_alloc_table_from_pages(sgt, pages, count, 0, size, - GFP_KERNEL); + /* + * The buffer was not allocated through these DMA ops. It may belong to + * a device which is not behind an IOMMU at all, which can happen when a + * buffer is allocated on one device and mapped for another. Describe it + * as a single chunk, as iommu_dma_get_sgtable() does. + */ + if (is_vmalloc_addr(cpu_addr)) + page =3D vmalloc_to_page(cpu_addr); + else + page =3D virt_to_page(cpu_addr); + + ret =3D sg_alloc_table(sgt, 1, GFP_KERNEL); + if (!ret) + sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); + + return ret; } =20 /* --=20 2.55.0 From nobody Fri Sep 25 08:47:51 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010047.outbound.protection.outlook.com [40.93.198.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A1621E0DD8; Tue, 15 Sep 2026 02:16:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.198.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789438573; cv=fail; b=BejN1Z7MULnhfQRaGa67myqPgr4+Vcw7MLMST+vBxhM40Nf5W7U39j9Y0gE/Tpi7RmRJnROCUMnAIn0r4K3JZgH+G/6iYBCWgWmnCk6RMMNi2UEReOrSqo0uLfdZvbE+3COGQIcyRHMutZLNA/imAQEEj8TQCyvirh/MLyVILl0= ARC-Message-Signature: i=2; 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Now that the ARM DMA API state is an ordinary domain cookie, IOMMU drivers can ask for a real IOMMU_DOMAIN_DMA default domain instead. Drop the override so that ->def_domain_type is honoured, and let a driver-requested DMA domain through the !CONFIG_IOMMU_DMA guard when ARM_DMA_USE_IOMMU can back it. IOMMU_DOMAIN_DMA stays strictly opt-in on 32-bit ARM and is never the fallback to avoid unexpected changes, as drivers today return 0 from ->def_domain_type while expecting the legacy behaviour. Behaviour is therefore unchanged for every existing 32-bit ARM IOMMU driver: - exynos-iommu, omap-iommu, rockchip-iommu, msm_iommu, ipmmu-vmsa, mtk_iommu*, sun50i-iommu and qcom_iommu have no ->def_domain_type, so iommu_get_def_domain_type() returns the unchanged cur_type of 0, which is forced to IDENTITY as before. - arm-smmu returns IDENTITY for legacy bindings and 0 otherwise, which ends up in the same place. - tegra-smmu returns IDENTITY explicitly, and keeps doing so until a later patch. Also move the static_assert on the two DMA API implementations being mutually exclusive to drivers/iommu/dma-iommu.h, next to the declarations that depend on it. Signed-off-by: Mikko Perttunen --- drivers/iommu/dma-iommu.h | 3 +++ drivers/iommu/iommu.c | 20 +++++--------------- 2 files changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index 71b23cb698c0..24fa4165450f 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -12,6 +12,9 @@ * IOMMU_DOMAIN_DMA default domains. Only one provider can be compiled in = at a * time. */ +static_assert(!(IS_ENABLED(CONFIG_IOMMU_DMA) && + IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU))); + #if defined(CONFIG_ARM_DMA_USE_IOMMU) =20 #include diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 43dd69662fac..6b4c328852db 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1884,18 +1884,6 @@ static int iommu_get_default_domain_type(struct iomm= u_group *group, =20 lockdep_assert_held(&group->mutex); =20 - /* - * ARM32 drivers supporting CONFIG_ARM_DMA_USE_IOMMU can declare an - * identity_domain and it will automatically become their default - * domain. Later on ARM_DMA_USE_IOMMU will install its UNMANAGED domain. - * Override the selection to IDENTITY. - */ - if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)) { - static_assert(!(IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) && - IS_ENABLED(CONFIG_IOMMU_DMA))); - driver_type =3D IOMMU_DOMAIN_IDENTITY; - } - for_each_group_device(group, gdev) { driver_type =3D iommu_get_def_domain_type(group, gdev->dev, driver_type); @@ -1913,11 +1901,13 @@ static int iommu_get_default_domain_type(struct iom= mu_group *group, =20 /* * If the common dma ops are not selected in kconfig then we cannot use - * IOMMU_DOMAIN_DMA at all. Force IDENTITY if nothing else has been - * selected. + * IOMMU_DOMAIN_DMA at all, unless this is ARM32 and the driver asked + * for it explicitly, where CONFIG_ARM_DMA_USE_IOMMU provides the + * implementation. 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Enabling translation for them without special care during that time would cause translation faults. Because of this, tegra_smmu_def_domain_type has kept every device on an identity domain at boot, and TegraDRM has parallel custom IOMMU domain management code paths for these clients. Mark the dc and dcb swgroups on Tegra30, Tegra114, Tegra124 and Tegra210 with a new defer_enable flag. tegra_smmu_enable() sets those swgroups up as usual, ASID and per-client enables and all, but leaves SMMU_ASID_ENABLE clear, so the clients stay in bypass. tegra_dc_probe() then calls tegra_smmu_enable_translation() once it has asserted the display controller's reset (and set up its final IOMMU domain), at which point the hardware is guaranteed not to be fetching and translation can be turned on. If the display driver never probes, the clients simply stay in bypass, which is what they do today. Signed-off-by: Mikko Perttunen --- drivers/gpu/drm/tegra/dc.c | 8 +++++++ drivers/iommu/tegra-smmu.c | 51 +++++++++++++++++++++++++++++++++++++= +++- drivers/memory/tegra/tegra114.c | 6 +++-- drivers/memory/tegra/tegra124.c | 6 +++-- drivers/memory/tegra/tegra210.c | 6 +++-- drivers/memory/tegra/tegra30.c | 6 +++-- include/soc/tegra/mc.h | 13 +++++++++++ 7 files changed, 87 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 0b3fcc7011b3..2ae4da07bbc9 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -19,6 +19,7 @@ #include =20 #include +#include #include =20 #include @@ -2751,6 +2752,13 @@ static int tegra_dc_init(struct host1x_client *clien= t) return err; } =20 + /* + * Enable translation now that the final domain is attached. + * The hardware was reset at probe and has not been programmed + * since. + */ + tegra_smmu_enable_translation(client->dev); + if (dc->soc->wgrps) primary =3D tegra_dc_add_shared_planes(drm, dc); else diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 67e7a7b925f0..6636a044905f 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -368,7 +368,13 @@ static void tegra_smmu_enable(struct tegra_smmu *smmu,= unsigned int swgroup, value =3D smmu_readl(smmu, group->reg); value &=3D ~SMMU_ASID_MASK; value |=3D SMMU_ASID_VALUE(asid); - value |=3D SMMU_ASID_ENABLE; + /* + * A deferred client is set up completely, but with translation + * gated off, so it stays in bypass until its driver calls + * tegra_smmu_enable_translation(). + */ + if (!group->defer_enable) + value |=3D SMMU_ASID_ENABLE; smmu_writel(smmu, value, group->reg); } else { pr_warn("%s group from swgroup %u not found\n", __func__, @@ -417,6 +423,49 @@ static void tegra_smmu_disable(struct tegra_smmu *smmu= , unsigned int swgroup, } } =20 +/** + * tegra_smmu_enable_translation - Release a client's swgroups to translat= ion + * @dev: memory client device, already quiesced by its driver + * + * Enables translation for swgroups which were left in bypass at attach ti= me + * because the client could still have been running from a pre-kernel + * configuration. Must be called after @dev has been attached to the domai= n it + * will use. Safe to call for any device; clients which were not deferred = are + * unaffected. + */ +void tegra_smmu_enable_translation(struct device *dev) +{ + struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); + struct tegra_smmu *smmu =3D dev_iommu_priv_get(dev); + struct iommu_domain *domain; + unsigned int i; + + if (!fwspec || !smmu) + return; + + domain =3D iommu_get_domain_for_dev(dev); + if (!domain || !(domain->type & __IOMMU_DOMAIN_PAGING)) + return; + + mutex_lock(&smmu->lock); + + for (i =3D 0; i < fwspec->num_ids; i++) { + const struct tegra_smmu_swgroup *group; + u32 value; + + group =3D tegra_smmu_find_swgroup(smmu, fwspec->ids[i]); + if (!group || !group->defer_enable) + continue; + + value =3D smmu_readl(smmu, group->reg); + value |=3D SMMU_ASID_ENABLE; + smmu_writel(smmu, value, group->reg); + } + + mutex_unlock(&smmu->lock); +} +EXPORT_SYMBOL_GPL(tegra_smmu_enable_translation); + static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, struct tegra_smmu_as *as) { diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra11= 4.c index 2cb153091228..2883c4f91144 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -1028,8 +1028,10 @@ static const struct tegra_mc_client tegra114_mc_clie= nts[] =3D { }; =20 static const struct tegra_smmu_swgroup tegra114_swgroups[] =3D { - { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0= x240 }, - { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0= x244 }, + { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0= x240, + .defer_enable =3D true }, + { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0= x244, + .defer_enable =3D true }, { .name =3D "epp", .swgroup =3D TEGRA_SWGROUP_EPP, .reg =3D 0= x248 }, { .name =3D "g2", .swgroup =3D TEGRA_SWGROUP_G2, .reg =3D 0= x24c }, { .name =3D "avpc", .swgroup =3D TEGRA_SWGROUP_AVPC, .reg =3D 0= x23c }, diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra12= 4.c index df87c5038625..a38fbf2baf6c 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -1070,8 +1070,10 @@ static const struct tegra_mc_client tegra124_mc_clie= nts[] =3D { }; =20 static const struct tegra_smmu_swgroup tegra124_swgroups[] =3D { - { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0= x240 }, - { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0= x244 }, + { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0= x240, + .defer_enable =3D true }, + { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0= x244, + .defer_enable =3D true }, { .name =3D "afi", .swgroup =3D TEGRA_SWGROUP_AFI, .reg =3D 0= x238 }, { .name =3D "avpc", .swgroup =3D TEGRA_SWGROUP_AVPC, .reg =3D 0= x23c }, { .name =3D "hda", .swgroup =3D TEGRA_SWGROUP_HDA, .reg =3D 0= x254 }, diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra21= 0.c index f58f3ef6f681..92e809cd7c26 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1166,8 +1166,10 @@ static const struct tegra_mc_client tegra210_mc_clie= nts[] =3D { static const struct tegra_smmu_swgroup tegra210_swgroups[] =3D { { .name =3D "afi", .swgroup =3D TEGRA_SWGROUP_AFI, .reg =3D 0= x238 }, { .name =3D "avpc", .swgroup =3D TEGRA_SWGROUP_AVPC, .reg =3D 0= x23c }, - { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0= x240 }, - { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0= x244 }, + { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0= x240, + .defer_enable =3D true }, + { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0= x244, + .defer_enable =3D true }, { .name =3D "hc", .swgroup =3D TEGRA_SWGROUP_HC, .reg =3D 0= x250 }, { .name =3D "hda", .swgroup =3D TEGRA_SWGROUP_HDA, .reg =3D 0= x254 }, { .name =3D "isp2", .swgroup =3D TEGRA_SWGROUP_ISP2, .reg =3D 0= x258 }, diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 8389e3af0121..0ee4715413ba 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -1139,8 +1139,10 @@ static const struct tegra_mc_client tegra30_mc_clien= ts[] =3D { }; =20 static const struct tegra_smmu_swgroup tegra30_swgroups[] =3D { - { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0x240 }, - { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0x244 }, + { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0x240, + .defer_enable =3D true }, + { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0x244, + .defer_enable =3D true }, { .name =3D "epp", .swgroup =3D TEGRA_SWGROUP_EPP, .reg =3D 0x248 }, { .name =3D "g2", .swgroup =3D TEGRA_SWGROUP_G2, .reg =3D 0x24c }, { .name =3D "mpe", .swgroup =3D TEGRA_SWGROUP_MPE, .reg =3D 0x264 }, diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 25d465d70493..ea67972fd585 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -70,6 +70,14 @@ struct tegra_smmu_swgroup { const char *name; unsigned int swgroup; unsigned int reg; + + /* + * Set for clients which may already be running when the kernel takes + * over, e.g. display controllers scanning out a boot splash. They are + * left in bypass until their driver calls + * tegra_smmu_enable_translation(). + */ + bool defer_enable; }; =20 struct tegra_smmu_group_soc { @@ -103,6 +111,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc, struct tegra_mc *mc); void tegra_smmu_remove(struct tegra_smmu *smmu); +void tegra_smmu_enable_translation(struct device *dev); #else static inline struct tegra_smmu * tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc, @@ -114,6 +123,10 @@ tegra_smmu_probe(struct device *dev, const struct tegr= a_smmu_soc *soc, static inline void tegra_smmu_remove(struct tegra_smmu *smmu) { } + +static inline void tegra_smmu_enable_translation(struct device *dev) +{ +} #endif =20 struct tegra_mc_reset { --=20 2.55.0 From nobody Fri Sep 25 08:47:51 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010029.outbound.protection.outlook.com [52.101.85.29]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B2AE4BEE38; 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We are about to enable default domain based DMA domains for Host1x and TegraDRM devices. These will take the same path as on 64-bit ARM, but we need to avoid trying to detach the now perfectly functional mapping on the device, so get rid of that code. Strictly speaking, the code removed here would not be harmful but would cause WARNs to happen. nouveau and tegra-vde have the same construct, but their clients stay on identity domains for now, so those copies are left alone. Signed-off-by: Mikko Perttunen --- drivers/gpu/host1x/dev.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index 3f475f0e6545..27ca523a6ada 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -23,10 +23,6 @@ #include #undef CREATE_TRACE_POINTS =20 -#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) -#include -#endif - #include "bus.h" #include "channel.h" #include "context.h" @@ -379,17 +375,6 @@ static struct iommu_domain *host1x_iommu_attach(struct= host1x *host) struct iommu_domain *domain =3D iommu_get_domain_for_dev(host->dev); int err; =20 -#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) - if (host->dev->archdata.mapping) { - struct dma_iommu_mapping *mapping =3D - to_dma_iommu_mapping(host->dev); - arm_iommu_detach_device(host->dev); - arm_iommu_release_mapping(mapping); - - domain =3D iommu_get_domain_for_dev(host->dev); - } -#endif - /* * We may not always want to enable IOMMU support (for example if the * host1x firewall is already enabled and we don't support addressing --=20 2.55.0 From nobody Fri Sep 25 08:47:51 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012063.outbound.protection.outlook.com [52.101.48.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAA733CFF72; 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We are about to enable default domain based DMA domains for Host1x and TegraDRM devices. These will take the same path as on 64-bit ARM, but we need to avoid trying to detach the now perfectly functional mapping on the device, so get rid of that code. Strictly speaking, the code removed here would not be harmful but would cause WARNs to happen. Signed-off-by: Mikko Perttunen --- drivers/gpu/drm/tegra/drm.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index dd6c564ff408..39a271241cf0 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -25,10 +25,6 @@ #include #include =20 -#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) -#include -#endif - #include "dc.h" #include "drm.h" #include "gem.h" @@ -947,17 +943,6 @@ int host1x_client_iommu_attach(struct host1x_client *c= lient) struct iommu_group *group =3D NULL; int err; =20 -#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) - if (client->dev->archdata.mapping) { - struct dma_iommu_mapping *mapping =3D - to_dma_iommu_mapping(client->dev); - arm_iommu_detach_device(client->dev); - arm_iommu_release_mapping(mapping); - - domain =3D iommu_get_domain_for_dev(client->dev); - } -#endif - /* * If the host1x client is already attached to an IOMMU domain that is * not the shared IOMMU domain, don't try to attach it to a different --=20 2.55.0 From nobody Fri Sep 25 08:47:51 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011008.outbound.protection.outlook.com [40.107.208.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8EC83D34AC; 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Some device drivers still rely on explicit domains (and being able to detach a legacy ARM DMA domain if any), so DMA default domains are enabled on a per-swgroup basis via a use_dma_api flag. As drivers are converted to DMA API usage we can eventually get rid of this. Initially the flag is enabled for TegraDRM and Host1x devices. On multi_v7_defconfig (where CONFIG_ARM_DMA_USE_IOMMU was always enabled), this will fix TegraDRM probing with certain probe orderings where the legacy implementation's lack of support for multiple devices in one IOMMU group would cause breakage. On tegra_defconfig, as this now enables CONFIG_ARM_DMA_USE_IOMMU, all devices move to either the legacy ARM DMA path or the new one. This should in principle not cause issues as the drivers would already have been verified on multi_v7_defconfig. Signed-off-by: Mikko Perttunen --- drivers/iommu/Kconfig | 1 + drivers/iommu/tegra-smmu.c | 58 +++++++++++++++++++++++++++++++++++++= +--- drivers/memory/tegra/tegra114.c | 13 +++++---- drivers/memory/tegra/tegra124.c | 10 ++++--- drivers/memory/tegra/tegra30.c | 16 +++++++----- include/soc/tegra/mc.h | 7 +++++ 6 files changed, 86 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 6e07bd69467a..817e84e0e6ab 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -252,6 +252,7 @@ config TEGRA_IOMMU_SMMU depends on TEGRA_AHB depends on TEGRA_MC select IOMMU_API + select ARM_DMA_USE_IOMMU if ARM help This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra SoCs (Tegra30 up to Tegra210). diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 6636a044905f..8a5c3f80fcff 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -1037,12 +1037,26 @@ static int tegra_smmu_of_xlate(struct device *dev, =20 static int tegra_smmu_def_domain_type(struct device *dev) { + struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); + struct tegra_smmu *smmu =3D dev_iommu_priv_get(dev); + unsigned int i; + + if (!fwspec || !smmu) + return IOMMU_DOMAIN_IDENTITY; + /* - * FIXME: For now we want to run all translation in IDENTITY mode, due - * to some device quirks. Better would be to just quirk the troubled - * devices. + * Only clients known to work with the DMA API get a DMA default domain. + * The rest keep running in identity mode. */ - return IOMMU_DOMAIN_IDENTITY; + for (i =3D 0; i < fwspec->num_ids; i++) { + const struct tegra_smmu_swgroup *group; + + group =3D tegra_smmu_find_swgroup(smmu, fwspec->ids[i]); + if (!group || !group->use_dma_api) + return IOMMU_DOMAIN_IDENTITY; + } + + return IOMMU_DOMAIN_DMA; } =20 static const struct iommu_ops tegra_smmu_ops =3D { @@ -1151,6 +1165,40 @@ static void tegra_smmu_debugfs_exit(struct tegra_smm= u *smmu) debugfs_remove_recursive(smmu->debugfs); } =20 +/* + * The default domain type is a property of the IOMMU group, so all swgrou= ps in + * one group must agree on use_dma_api. Otherwise the core sees conflicting + * def_domain_type and falls back to identity for the whole group. + */ +static void tegra_smmu_check_groups(struct tegra_smmu *smmu) +{ + const struct tegra_smmu_soc *soc =3D smmu->soc; + unsigned int i, j; + + for (i =3D 0; i < soc->num_groups; i++) { + const struct tegra_smmu_group_soc *group =3D &soc->groups[i]; + int dma_api =3D -1; + + for (j =3D 0; j < group->num_swgroups; j++) { + const struct tegra_smmu_swgroup *swgrp; + + swgrp =3D tegra_smmu_find_swgroup(smmu, + group->swgroups[j]); + if (!swgrp) + continue; + + if (dma_api < 0) + dma_api =3D swgrp->use_dma_api; + else if (swgrp->use_dma_api !=3D !!dma_api) + break; + } + + WARN(j < group->num_swgroups, + "SMMU group %s mixes DMA API and identity swgroups\n", + group->name); + } +} + struct tegra_smmu *tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc, struct tegra_mc *mc) @@ -1185,6 +1233,8 @@ struct tegra_smmu *tegra_smmu_probe(struct device *de= v, smmu->dev =3D dev; smmu->mc =3D mc; =20 + tegra_smmu_check_groups(smmu); + smmu->pfn_mask =3D BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1; dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra11= 4.c index 2883c4f91144..024c63bdd480 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -1029,15 +1029,18 @@ static const struct tegra_mc_client tegra114_mc_cli= ents[] =3D { =20 static const struct tegra_smmu_swgroup tegra114_swgroups[] =3D { { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0= x240, - .defer_enable =3D true }, + .defer_enable =3D true, .use_dma_api =3D true }, { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0= x244, - .defer_enable =3D true }, + .defer_enable =3D true, .use_dma_api =3D true }, { .name =3D "epp", .swgroup =3D TEGRA_SWGROUP_EPP, .reg =3D 0= x248 }, - { .name =3D "g2", .swgroup =3D TEGRA_SWGROUP_G2, .reg =3D 0= x24c }, + { .name =3D "g2", .swgroup =3D TEGRA_SWGROUP_G2, .reg =3D 0= x24c, + .use_dma_api =3D true }, { .name =3D "avpc", .swgroup =3D TEGRA_SWGROUP_AVPC, .reg =3D 0= x23c }, - { .name =3D "nv", .swgroup =3D TEGRA_SWGROUP_NV, .reg =3D 0= x268 }, + { .name =3D "nv", .swgroup =3D TEGRA_SWGROUP_NV, .reg =3D 0= x268, + .use_dma_api =3D true }, { .name =3D "hda", .swgroup =3D TEGRA_SWGROUP_HDA, .reg =3D 0= x254 }, - { .name =3D "hc", .swgroup =3D TEGRA_SWGROUP_HC, .reg =3D 0= x250 }, + { .name =3D "hc", .swgroup =3D TEGRA_SWGROUP_HC, .reg =3D 0= x250, + .use_dma_api =3D true }, { .name =3D "msenc", .swgroup =3D TEGRA_SWGROUP_MSENC, .reg =3D 0= x264 }, { .name =3D "ppcs", .swgroup =3D TEGRA_SWGROUP_PPCS, .reg =3D 0= x270 }, { .name =3D "vde", .swgroup =3D TEGRA_SWGROUP_VDE, .reg =3D 0= x27c }, diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra12= 4.c index a38fbf2baf6c..17068aaf163f 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -1071,13 +1071,14 @@ static const struct tegra_mc_client tegra124_mc_cli= ents[] =3D { =20 static const struct tegra_smmu_swgroup tegra124_swgroups[] =3D { { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0= x240, - .defer_enable =3D true }, + .defer_enable =3D true, .use_dma_api =3D true }, { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0= x244, - .defer_enable =3D true }, + .defer_enable =3D true, .use_dma_api =3D true }, { .name =3D "afi", .swgroup =3D TEGRA_SWGROUP_AFI, .reg =3D 0= x238 }, { .name =3D "avpc", .swgroup =3D TEGRA_SWGROUP_AVPC, .reg =3D 0= x23c }, { .name =3D "hda", .swgroup =3D TEGRA_SWGROUP_HDA, .reg =3D 0= x254 }, - { .name =3D "hc", .swgroup =3D TEGRA_SWGROUP_HC, .reg =3D 0= x250 }, + { .name =3D "hc", .swgroup =3D TEGRA_SWGROUP_HC, .reg =3D 0= x250, + .use_dma_api =3D true }, { .name =3D "msenc", .swgroup =3D TEGRA_SWGROUP_MSENC, .reg =3D 0= x264 }, { .name =3D "ppcs", .swgroup =3D TEGRA_SWGROUP_PPCS, .reg =3D 0= x270 }, { .name =3D "sata", .swgroup =3D TEGRA_SWGROUP_SATA, .reg =3D 0= x274 }, @@ -1093,7 +1094,8 @@ static const struct tegra_smmu_swgroup tegra124_swgro= ups[] =3D { { .name =3D "sdmmc2a", .swgroup =3D TEGRA_SWGROUP_SDMMC2A, .reg =3D 0= xa98 }, { .name =3D "sdmmc3a", .swgroup =3D TEGRA_SWGROUP_SDMMC3A, .reg =3D 0= xa9c }, { .name =3D "sdmmc4a", .swgroup =3D TEGRA_SWGROUP_SDMMC4A, .reg =3D 0= xaa0 }, - { .name =3D "vic", .swgroup =3D TEGRA_SWGROUP_VIC, .reg =3D 0= x284 }, + { .name =3D "vic", .swgroup =3D TEGRA_SWGROUP_VIC, .reg =3D 0= x284, + .use_dma_api =3D true }, { .name =3D "vi", .swgroup =3D TEGRA_SWGROUP_VI, .reg =3D 0= x280 }, }; =20 diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 0ee4715413ba..df6b5a499ccc 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -1140,19 +1140,23 @@ static const struct tegra_mc_client tegra30_mc_clie= nts[] =3D { =20 static const struct tegra_smmu_swgroup tegra30_swgroups[] =3D { { .name =3D "dc", .swgroup =3D TEGRA_SWGROUP_DC, .reg =3D 0x240, - .defer_enable =3D true }, + .defer_enable =3D true, .use_dma_api =3D true }, { .name =3D "dcb", .swgroup =3D TEGRA_SWGROUP_DCB, .reg =3D 0x244, - .defer_enable =3D true }, + .defer_enable =3D true, .use_dma_api =3D true }, { .name =3D "epp", .swgroup =3D TEGRA_SWGROUP_EPP, .reg =3D 0x248 }, - { .name =3D "g2", .swgroup =3D TEGRA_SWGROUP_G2, .reg =3D 0x24c }, + { .name =3D "g2", .swgroup =3D TEGRA_SWGROUP_G2, .reg =3D 0x24c, + .use_dma_api =3D true }, { .name =3D "mpe", .swgroup =3D TEGRA_SWGROUP_MPE, .reg =3D 0x264 }, { .name =3D "vi", .swgroup =3D TEGRA_SWGROUP_VI, .reg =3D 0x280 }, { .name =3D "afi", .swgroup =3D TEGRA_SWGROUP_AFI, .reg =3D 0x238 }, { .name =3D "avpc", .swgroup =3D TEGRA_SWGROUP_AVPC, .reg =3D 0x23c }, - { .name =3D "nv", .swgroup =3D TEGRA_SWGROUP_NV, .reg =3D 0x268 }, - { .name =3D "nv2", .swgroup =3D TEGRA_SWGROUP_NV2, .reg =3D 0x26c }, + { .name =3D "nv", .swgroup =3D TEGRA_SWGROUP_NV, .reg =3D 0x268, + .use_dma_api =3D true }, + { .name =3D "nv2", .swgroup =3D TEGRA_SWGROUP_NV2, .reg =3D 0x26c, + .use_dma_api =3D true }, { .name =3D "hda", .swgroup =3D TEGRA_SWGROUP_HDA, .reg =3D 0x254 }, - { .name =3D "hc", .swgroup =3D TEGRA_SWGROUP_HC, .reg =3D 0x250 }, + { .name =3D "hc", .swgroup =3D TEGRA_SWGROUP_HC, .reg =3D 0x250, + .use_dma_api =3D true }, { .name =3D "ppcs", .swgroup =3D TEGRA_SWGROUP_PPCS, .reg =3D 0x270 }, { .name =3D "sata", .swgroup =3D TEGRA_SWGROUP_SATA, .reg =3D 0x278 }, { .name =3D "vde", .swgroup =3D TEGRA_SWGROUP_VDE, .reg =3D 0x27c }, diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index ea67972fd585..1cbd990fc0f4 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -78,6 +78,13 @@ struct tegra_smmu_swgroup { * tegra_smmu_enable_translation(). */ bool defer_enable; + + /* + * Set once the clients behind this swgroup are known to work with an + * IOMMU_DOMAIN_DMA default domain. All swgroups of a + * tegra_smmu_group_soc must agree. + */ + bool use_dma_api; }; =20 struct tegra_smmu_group_soc { --=20 2.55.0