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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bfb19f8cesm4740083eec.2.2026.09.15.23.04.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 23:04:26 -0700 (PDT) From: Qiang Yu Date: Tue, 15 Sep 2026 23:04:21 -0700 Subject: [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align with HPG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-align_pcie_init_sequence_0916-v1-1-0b2195836f30@oss.qualcomm.com> References: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Vinod Koul , Neil Armstrong , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789538665; l=11264; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=wBvSB5WoOED4qErJlwYmr87tVRah/FuLj4HM3VOi0Vw=; b=wcM+CQ29Wxa0qsL2ZxHWjjmycqeaUP7KCCcteTeY659CQX0oEdm77HKH+Ls0itXWUSF8luEdI pIh/eSwUu0BD5uPtDZJgKpxiRmzQU0856rYaAzbqvhDVUyoYmIuXIQ1 X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfX1WVfhgcS89HH 1tjfwuIvnLn9pFP2W+Hoi+toS6BoyoSLun+nFdO/VvHWNs7gLoSYAuOPv4gcofbmOpig6L8YIbM Qfi6P2vJTSg86KoeHZO8uLmSybqzeAg= X-Authority-Analysis: v=2.4 cv=HrTjiETS c=1 sm=1 tr=0 ts=6aaa316c cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=ltsZTcXAoX5SLtwclHIA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: Xy_H1bp6MErK18tMYOKUvSOM447Y60u7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfX9cmQS1f9JCc6 AqcDHhogKEdfI10qysjffHNxr06OXtC0QKgIJ+z0xu0UmziU0Q//p4G+U3BgbhYNyFt9lsoctfm XajEmZaR2d9jy1sYBxqVFGnHAgrfu1+nW3n4qzL8ZrUKC5AeeUTUXvKpFcZ8HlOVWhbhCrZpKoL +2zYNX+YIJoUZnkHjhF/X5mTUXaImQy3bZ0ZQ7VphXNvK1ierj8Qfwf0iQoXhp1gP6HhOFMRhKZ ijhS4n+NtHNZp+N/3lkvhD+p/niqftuoZ9taDkLhObhytJzByG/P3m46mOfWLAMMM1TTLLzWpZ6 EKcrsUlxkQ7/hm0wkV9KYUZ0snJ+Qb1uRjviz4GzB1Z512RgbBHP3JYcspBOs0+BCnYbHn4YnZy sTt0WlbpIVt9cgakIY/fALWeQNz3moZ1JHELL3J9+Gkw0Mmn6YJ/qwnalyoN/u1SIhb1ddGQjlC ndfHstW0T2hGJGwbBYg== X-Proofpoint-GUID: Xy_H1bp6MErK18tMYOKUvSOM447Y60u7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 phishscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609160076 HPG requires the controller/PHY GDSCs powered up and all controller/PHY clocks enabled first, then the controller's reset and the PHY's reset toggled together as a group, PARF_DEVICE_TYPE set right after, and the rest of the PARF/DBI config left until the PHY is ready. Make use of phy_init() and phy_reset(), and change the call flow to: qcom_pcie_host_init(): phy_init() (PHY GDSCs/regulators/clocks up) qcom_pcie_ops::init: enable controller clocks assert controller reset phy_reset() (toggle the PHY's own reset) deassert controller reset write PARF_DEVICE_TYPE phy_power_on() qcom_pcie_ops::post_init (rest of the PHY/PARF/DBI setup) phy_init() moves into qcom_pcie_host_init() and phy_exit() into qcom_pcie_host_deinit(), right before and right after they call qcom_pcie_ops::init/qcom_pcie_ops::deinit. Apply this to qcom_pcie_init_2_7_0()/_2_9_0()/_2_3_2()/_2_3_3(). qcom_pcie_init_2_3_3() was enabling clocks after the reset deassert; move that ahead of the reset assert to match the same ordering. Also add or move the PARF_DEVICE_TYPE write to right after the reset group in each of those four functions. For most platforms phy_init()/phy_exit()/phy_reset() are no-ops against their phy_ops, so moving the calls around has no effect yet; the PHY's clocks/reset actually start being driven this way once a later PHY driver change implements phy_ops::init/phy_ops::exit/phy_ops::reset. phy-qcom-pcie2.c does implement phy_init()/phy_exit(), but moving the call site into qcom_pcie_host_init()/qcom_pcie_host_deinit() keeps them at the same point relative to that platform's own clock/reset programming, so its init sequence doesn't change either. Signed-off-by: Qiang Yu Tested-by: Kathiravan Thirumoorthy=20 --- drivers/pci/controller/dwc/pcie-qcom.c | 165 +++++++++++++++++++++++++----= ---- 1 file changed, 126 insertions(+), 39 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index ee63a6ec99de..c1792f35f9eb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -508,6 +508,58 @@ static enum dw_pcie_ltssm qcom_pcie_2_1_0_get_ltssm(st= ruct qcom_pcie *pcie) return (enum dw_pcie_ltssm)FIELD_GET(ELBI_SYS_STTS_LTSSM_STATE_MASK, val); } =20 +static void qcom_pcie_phy_exit(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port; + + list_for_each_entry(port, &pcie->ports, list) + phy_exit(port->phy); +} + +static int qcom_pcie_phy_init(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port, *failed_port =3D NULL; + struct device *dev =3D pcie->pci->dev; + int ret; + + list_for_each_entry(port, &pcie->ports, list) { + ret =3D phy_init(port->phy); + if (ret) { + dev_err(dev, "phy init failed (%d)\n", ret); + failed_port =3D port; + goto err_exit_phy; + } + } + + return 0; + +err_exit_phy: + list_for_each_entry(port, &pcie->ports, list) { + if (port =3D=3D failed_port) + break; + phy_exit(port->phy); + } + + return ret; +} + +static int qcom_pcie_phy_reset(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port; + struct device *dev =3D pcie->pci->dev; + int ret; + + list_for_each_entry(port, &pcie->ports, list) { + ret =3D phy_reset(port->phy); + if (ret) { + dev_err(dev, "phy reset failed (%d)\n", ret); + return ret; + } + } + + return 0; +} + static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res =3D &pcie->res.v2_1_0; @@ -791,11 +843,23 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pci= e) ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret) { dev_err(dev, "cannot prepare/enable clocks\n"); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - return ret; + goto err_disable_regulators; } =20 + ret =3D qcom_pcie_phy_reset(pcie); + if (ret) + goto err_disable_clocks; + + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); + return 0; + +err_disable_clocks: + clk_bulk_disable_unprepare(res->num_clks, res->clks); +err_disable_regulators: + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + + return ret; } =20 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) @@ -957,18 +1021,28 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pc= ie) struct device *dev =3D pci->dev; int ret; =20 + ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) { + dev_err(dev, "cannot prepare/enable clocks\n"); + return ret; + } + ret =3D reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); if (ret < 0) { dev_err(dev, "cannot assert resets\n"); - return ret; + goto err_disable_clocks; } =20 usleep_range(2000, 2500); =20 + ret =3D qcom_pcie_phy_reset(pcie); + if (ret) + goto err_assert_resets; + ret =3D reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); if (ret < 0) { dev_err(dev, "cannot deassert resets\n"); - return ret; + goto err_assert_resets; } =20 /* @@ -977,11 +1051,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pci= e) */ usleep_range(2000, 2500); =20 - ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); - if (ret) { - dev_err(dev, "cannot prepare/enable clocks\n"); - goto err_assert_resets; - } + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); =20 return 0; =20 @@ -991,6 +1061,8 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) * the original failure in 'ret'. */ reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); +err_disable_clocks: + clk_bulk_disable_unprepare(res->num_clks, res->clks); =20 return ret; } @@ -1066,7 +1138,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pci= e) struct qcom_pcie_resources_2_7_0 *res =3D &pcie->res.v2_7_0; struct dw_pcie *pci =3D pcie->pci; struct device *dev =3D pci->dev; - u32 val; int ret; =20 ret =3D regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); @@ -1085,6 +1156,10 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pc= ie) goto err_disable_clocks; } =20 + ret =3D qcom_pcie_phy_reset(pcie); + if (ret) + goto err_disable_clocks; + usleep_range(1000, 1500); =20 ret =3D reset_control_deassert(res->rst); @@ -1099,6 +1174,21 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pc= ie) /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); =20 + return 0; +err_disable_clocks: + clk_bulk_disable_unprepare(res->num_clks, res->clks); +err_disable_regulators: + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + + return ret; +} + +static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) +{ + const struct qcom_pcie_cfg *pcie_cfg =3D pcie->cfg; + struct dw_pcie *pci =3D pcie->pci; + u32 val; + /* Force PHY out of lowest power state */ val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_TEST_PWR_DOWN; @@ -1126,19 +1216,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pc= ie) val |=3D EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); =20 - return 0; -err_disable_clocks: - clk_bulk_disable_unprepare(res->num_clks, res->clks); -err_disable_regulators: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - - return ret; -} - -static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) -{ - const struct qcom_pcie_cfg *pcie_cfg =3D pcie->cfg; - if (pcie_cfg->override_no_snoop) writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN, pcie->parf + PARF_NO_SNOOP_OVERRIDE); @@ -1298,10 +1375,14 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *p= cie) struct device *dev =3D pcie->pci->dev; int ret; =20 + ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) + return ret; + ret =3D reset_control_assert(res->rst); if (ret) { dev_err(dev, "reset assert failed (%d)\n", ret); - return ret; + goto err_disable_clocks; } =20 /* @@ -1310,15 +1391,26 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *p= cie) */ usleep_range(2000, 2500); =20 + ret =3D qcom_pcie_phy_reset(pcie); + if (ret) + goto err_disable_clocks; + ret =3D reset_control_deassert(res->rst); if (ret) { dev_err(dev, "reset deassert failed (%d)\n", ret); - return ret; + goto err_disable_clocks; } =20 usleep_range(2000, 2500); =20 - return clk_bulk_prepare_enable(res->num_clks, res->clks); + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); + + return 0; + +err_disable_clocks: + clk_bulk_disable_unprepare(res->num_clks, res->clks); + + return ret; } =20 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) @@ -1335,7 +1427,6 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie= *pcie) =20 qcom_pcie_configure_dbi_atu_base(pcie); =20 - writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS | @@ -1447,10 +1538,14 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *p= p) =20 qcom_pcie_perst_assert(pcie); =20 - ret =3D pcie->cfg->ops->init(pcie); + ret =3D qcom_pcie_phy_init(pcie); if (ret) return ret; =20 + ret =3D pcie->cfg->ops->init(pcie); + if (ret) + goto err_exit_phy; + ret =3D qcom_pcie_phy_power_on(pcie); if (ret) goto err_deinit; @@ -1503,6 +1598,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) qcom_pcie_phy_power_off(pcie); err_deinit: pcie->cfg->ops->deinit(pcie); +err_exit_phy: + qcom_pcie_phy_exit(pcie); =20 return ret; } @@ -1524,6 +1621,7 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp *= pp) =20 qcom_pcie_phy_power_off(pcie); pcie->cfg->ops->deinit(pcie); + qcom_pcie_phy_exit(pcie); } =20 static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp) @@ -2109,10 +2207,6 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pc= ie, struct device_node *node if (!port) return -ENOMEM; =20 - ret =3D phy_init(phy); - if (ret) - return ret; - INIT_LIST_HEAD(&port->perst); =20 ret =3D qcom_pcie_parse_perst(pcie, port, node); @@ -2157,7 +2251,6 @@ static int qcom_pcie_parse_ports(struct qcom_pcie *pc= ie) list_for_each_entry_safe(port, tmp_port, &pcie->ports, list) { list_for_each_entry_safe(perst, tmp_perst, &port->perst, list) list_del(&perst->list); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bfb19f8cesm4740083eec.2.2026.09.15.23.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 23:04:27 -0700 (PDT) From: Qiang Yu Date: Tue, 15 Sep 2026 23:04:22 -0700 Subject: [PATCH 2/4] PCI: qcom-ep: Move PHY init and drive PHY reset to align with HPG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-align_pcie_init_sequence_0916-v1-2-0b2195836f30@oss.qualcomm.com> References: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Vinod Koul , Neil Armstrong , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789538665; l=3449; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=h3fngNlkhZEZKpBHI/IT3xTrpcNvbLpoMF3Il2nEqag=; b=eTZfXLMDSIpr2rD0kW+QmRWdp9HNs5rYFTSCCvbAdhqFxpkC15bmD+pT/64Xq3BBABZm7nE6r kif1GcsJYCKBDLi+hJrEpTvhL5VVFDqdA8qCq0ZLA5sRh1Fa7EGYA62 X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-GUID: Px_a6gCIHuHsTR3dbLxGBreubWBg-kOa X-Authority-Analysis: v=2.4 cv=aJ1lOr9m c=1 sm=1 tr=0 ts=6aaa316d cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=PV8ZVrNDrE42_2bsUUYA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfX+7xAESnFx2nP TAQldDS4XSck+MS7FKnT9+ZBq20pr+voZKjdjlie4QD4DarhqQQjVN8zzC2o8ZcXrh05OcmCv4F 3f35+QbGHV7iYRNbjZs0GuubUflfYUXyC40ojua6AbXlLGb/PuKbko9LtKvvBfDg4ZrKqxbErnc 0t+5H/WVUeXho21CFm2qSNTnotjPCZJaSrwTBKYGgf5N2fzIg3OXayM3dMQtjhIiRX2p4R99B3U LGoTxaoTZPR3Hgp2AqWZsj8ajBZk7A8hHBDf9XvYQibk1cwYqqDtywJIozQj+lN6ncSG/BkFJny 2hzffC2IGpFRdr65Mw/tJA9om1g97Lnx3CdJ9CR6gtrxz7I+/TFohKgJwIf0B97pbmCWq2jYiu9 tvv9n+wy1b72Xi5tRG8g4fr7lKKCd2yT6oBXYKNFs7SO778HLZdUtfEOzVusb2IOxzz0Ws+HUax kCp2O2C4RlqSBQ9bYcg== X-Proofpoint-ORIG-GUID: Px_a6gCIHuHsTR3dbLxGBreubWBg-kOa X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfX9zi7UsZKl4fe SThm4Z/rDHCeRQtZwrdPcrEQqkBpeNmHGrBMDPO8Rq8HwcA/zh7Ruef+TvmRiGdBE9u9nvH+wUm 4IdnGzZxq6vh/Y5Zz7iUWMQNRp32CcQ= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609160076 HPG requires the GDSC to be powered up and all PHY/controller clocks enabled before the controller's core reset and the PHY's reset are toggled together as one atomic group, with PARF_DEVICE_TYPE set right after that reset group, same as the RC-mode change. Move phy_init() ahead of the controller's own clock enable, and fold phy_reset() into the core reset assert/deassert. phy_power_on() keeps running afterwards. Also move the PARF_DEVICE_TYPE write out of qcom_pcie_perst_deassert() to right after the reset group, in qcom_pcie_enable_resources(). phy_reset() and phy_init are currently a no-op against the PHY this driver uses, so the init sequence doesn't change yet; it actually changes once the PHY driver later implements .reset. Signed-off-by: Qiang Yu --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 8364696a1b98..cd7725d277c5 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -228,7 +228,7 @@ struct qcom_pcie_ep { int perst_irq; }; =20 -static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) +static int qcom_pcie_ep_phy_core_reset(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci =3D &pcie_ep->pci; struct device *dev =3D pci->dev; @@ -242,6 +242,12 @@ static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep= *pcie_ep) =20 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); =20 + ret =3D phy_reset(pcie_ep->phy); + if (ret) { + dev_err(dev, "Cannot reset phy\n"); + return ret; + } + ret =3D reset_control_deassert(pcie_ep->core_reset); if (ret) { dev_err(dev, "Cannot de-assert core reset\n"); @@ -332,25 +338,25 @@ static int qcom_pcie_enable_resources(struct qcom_pci= e_ep *pcie_ep) struct dw_pcie *pci =3D &pcie_ep->pci; int ret; =20 - ret =3D clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); + ret =3D phy_init(pcie_ep->phy); if (ret) return ret; =20 - ret =3D qcom_pcie_ep_core_reset(pcie_ep); + ret =3D clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); if (ret) - goto err_disable_clk; + goto err_phy_exit; =20 - ret =3D phy_init(pcie_ep->phy); + ret =3D qcom_pcie_ep_phy_core_reset(pcie_ep); if (ret) goto err_disable_clk; =20 ret =3D phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP); if (ret) - goto err_phy_exit; + goto err_disable_clk; =20 ret =3D phy_power_on(pcie_ep->phy); if (ret) - goto err_phy_exit; + goto err_disable_clk; =20 /* * Some Qualcomm platforms require interconnect bandwidth constraints @@ -370,10 +376,10 @@ static int qcom_pcie_enable_resources(struct qcom_pci= e_ep *pcie_ep) =20 err_phy_off: phy_power_off(pcie_ep->phy); -err_phy_exit: - phy_exit(pcie_ep->phy); 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Making that actually happen here needs phy_ops::init and phy_ops::reset implemented, and phy_ops::power_on adjusted to match. Split the combined phy_ops::power_on/power_off into phy_ops::init/exit/reset/power_on to do that. phy_ops::init enables power domains, regulators, and all PHY clocks (pipe clock first). phy_ops::reset does the no-CSR reset assert/ delay/deassert/delay. phy_ops::power_on is left with just the PCS status poll. phy_ops::exit mirrors phy_ops::init in reverse; phy_ops::power_off is dropped since nothing remains for it to do. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c | 94 +++++++++----------= ---- 1 file changed, 35 insertions(+), 59 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c b/drivers/ph= y/qualcomm/phy-qcom-qmp-pcie-multiphy.c index e93cba4369fb..aa7130efca45 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c @@ -280,20 +280,18 @@ static int qmp_pcie_init(struct phy *phy) goto err_pd_power_off; } =20 - ret =3D reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_= resets); - if (ret) { - dev_err(qmp->dev, "no-csr reset assert failed: %d\n", ret); + ret =3D clk_bulk_prepare_enable(qmp->cfg->num_pipe_clks, qmp->pipe_clks); + if (ret) goto err_disable_regulators; - } - - usleep_range(200, 300); =20 ret =3D clk_bulk_prepare_enable(qmp->cfg->num_clks, qmp->clks); if (ret) - goto err_disable_regulators; + goto err_disable_pipe_clks; =20 return 0; =20 +err_disable_pipe_clks: + clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); err_pd_power_off: @@ -310,31 +308,47 @@ static int qmp_pcie_exit(struct phy *phy) reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets); =20 clk_bulk_disable_unprepare(qmp->cfg->num_clks, qmp->clks); + clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks); regulator_bulk_disable(cfg->num_vregs, qmp->vregs); qmp_pcie_pd_power_off(qmp); =20 return 0; } =20 -static int qmp_pcie_power_on(struct phy *phy) +static int qmp_pcie_reset(struct phy *phy) { struct qmp_pcie *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; - const struct qmp_pcie_offsets *offs =3D cfg->offsets; - void __iomem *status; - unsigned int val; - int i, ret; + int ret; =20 - ret =3D clk_bulk_prepare_enable(qmp->cfg->num_pipe_clks, qmp->pipe_clks); - if (ret) + ret =3D reset_control_bulk_assert(cfg->num_nocsr_resets, qmp->nocsr_reset= s); + if (ret) { + dev_err(qmp->dev, "no-csr reset assert failed: %d\n", ret); return ret; + } =20 - ret =3D reset_control_bulk_deassert(qmp->cfg->num_nocsr_resets, qmp->nocs= r_resets); + udelay(5); + + ret =3D reset_control_bulk_deassert(cfg->num_nocsr_resets, qmp->nocsr_res= ets); if (ret) { dev_err(qmp->dev, "no-csr reset deassert failed: %d\n", ret); - goto err_disable_pipe_clk; + return ret; } =20 + udelay(5); + + return 0; +} + +static int qmp_pcie_power_on(struct phy *phy) +{ + struct qmp_pcie *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + const struct qmp_pcie_offsets *offs =3D cfg->offsets; + void __iomem *status; + unsigned int val; + int i, ret; + for (i =3D 0; i < cfg->num_regs; i++) { status =3D qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_STATUS]; ret =3D readl_poll_timeout(status, val, !(val & cfg->phy_status), 200, @@ -342,56 +356,18 @@ static int qmp_pcie_power_on(struct phy *phy) if (ret) { dev_err(qmp->dev, "PHY power on timed-out (%s): %d\n", cfg->reg_names[i], ret); - goto err_disable_pipe_clk; + return ret; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bfb19f8cesm4740083eec.2.2026.09.15.23.04.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 23:04:29 -0700 (PDT) From: Qiang Yu Date: Tue, 15 Sep 2026 23:04:24 -0700 Subject: [PATCH 4/4] phy: qcom-qmp-pcie: Split phy_ops into init/exit/reset/power_on Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-align_pcie_init_sequence_0916-v1-4-0b2195836f30@oss.qualcomm.com> References: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Vinod Koul , Neil Armstrong , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789538665; l=9312; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=/wSopYesC3qMtlVXkRsTFtC77+NTlle5qs5EdeUCzCM=; b=rRhym0yddZi4OGKtctf1tWZ7gm/qQ5GFKplmWgjzH0qIek07/cqoS0jaO0sJbmupOR1gXubU3 NgYdhKo63+MBSE0R6Q1MrMdOWUsRmdxPkJXMqrEon/TQNyymO9e2S/D X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfX6irmzqob3/vt BdnAYf90Cd/LjYL6rQ1h5AuPstb2C64s8lx7vhhn3VuAefVKXcSN24IZhCJJruoI9Qv1jko3Gf3 9wFEaZuIJJh+TdDpAl+na8pst1tXyAE= X-Authority-Analysis: v=2.4 cv=PsIG/AM3 c=1 sm=1 tr=0 ts=6aaa316f cx=c_pps a=lVi5GcDxkcJcfCmEjVJoaw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=6OVxYtpLaVGWezP7JUUA:9 a=QEXdDO2ut3YA:10 a=rBiNkAWo9uy_4UTK5NWh:22 X-Proofpoint-ORIG-GUID: 7EOzvucbwedGjKGs9WbytEWBYVHIYjdu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfX09zysnv1oh2g 4RzOO8CEbzUTJKhBN5pxkSs+IgXn2yURxLB/375mhZ56cnT3l/40tQrTYCJ+92uk35BcMHB1p6A XedKIW3lWe0yFrsJuofjXIq8D/J/33R6MMWah66mLJb86sYhcbH2hEv2TyEzlyrCxkpqrR7nk+6 f6X2GTVYGB4nJKckyUVAcPOxJJ3hKXf6SpA3ZS4iwlJ0Hv1KlH9rNQwqAMCtN6hLNgUEIbPXuXz 2jttWRpwS2L6zrFeZq0KxPSCOBpg4yzPD2XeRs9kdgUP+B0Y1K1XU7gJsutoqXCYLkiXU7xvajI A9V9SKaUMPFRPTsX4XtYbGWB0/JuoZckXrqqTOshqBU/86uDiaSRD2FmapE2hnR5/U+qrhmg1VD JBczSZ1HKnJz1d8oZgFAOrOftVJgxlIwEN2+8vWhVG6O2NUmgcwWTPBgUNZ+BphQbJzTUC+fU3a dhc4r+9/3CYJ7ZmkIlQ== X-Proofpoint-GUID: 7EOzvucbwedGjKGs9WbytEWBYVHIYjdu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609160076 The controller now calls phy_init() from qcom_pcie_host_init()/qcom_pcie_enable_resources() and phy_reset() from inside its own core reset assert/deassert, so the PHY's reset toggles alongside the controller's core reset as HPG requires. Making that actually happen here needs phy_ops::init and phy_ops::reset implemented, and phy_ops::power_on adjusted to match. Split the combined phy_ops::power_on/power_off into phy_ops::init/exit/reset/power_on to do that. phy_ops::init enables regulators and all clocks (pipe clock first) and determines skip_init/skip_reset. phy_ops::reset toggles the reset that skip_init picked. Register-table programming used to run while the no-CSR reset was still asserted; now it runs afterwards, in phy_ops::power_on. Adds skip_reset to struct qmp_pcie so phy_ops::reset and phy_ops::power_on share the value phy_ops::init determined instead of re-reading PCS registers. Signed-off-by: Qiang Yu Tested-by: Kathiravan Thirumoorthy=20 --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 184 ++++++++++++++-------------= ---- 1 file changed, 80 insertions(+), 104 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index d30194c6ed17..2b6741a4120c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4058,6 +4058,7 @@ struct qmp_pcie { const struct qmp_phy_cfg *cfg; bool tcsr_4ln_config; bool skip_init; + bool skip_reset; =20 void __iomem *serdes; void __iomem *pcs; @@ -5747,9 +5748,22 @@ static int qmp_pcie_init(struct phy *phy) struct qmp_pcie *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; void __iomem *pcs =3D qmp->pcs; - bool skip_reset; int ret; =20 + ret =3D regulator_bulk_enable(cfg->num_vregs, qmp->vregs); + if (ret) { + dev_err(qmp->dev, "failed to enable regulators, err=3D%d\n", ret); + return ret; + } + + ret =3D clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); + if (ret) + goto err_disable_regulators; + + ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); + if (ret) + goto err_disable_pipe_clks; + /* * We can skip PHY initialization if all of the following conditions * are met: @@ -5763,59 +5777,21 @@ static int qmp_pcie_init(struct phy *phy) qphy_checkbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START= ) && qphy_checkbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_c= trl); =20 - skip_reset =3D qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY_PCS_= STATUS], + qmp->skip_reset =3D qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY= _PCS_STATUS], cfg->phy_status); =20 if (!qmp->skip_init && !cfg->tbls.serdes_num) { dev_err(qmp->dev, "Init sequence not available\n"); - return -ENODATA; - } - - ret =3D regulator_bulk_enable(cfg->num_vregs, qmp->vregs); - if (ret) { - dev_err(qmp->dev, "failed to enable regulators, err=3D%d\n", ret); - return ret; - } - - /* - * Toggle BCR reset for PHY that doesn't support no_csr reset or has not - * been initialized. - */ - if (!qmp->skip_init) { - ret =3D reset_control_bulk_assert(cfg->num_resets, qmp->resets); - if (ret) { - dev_err(qmp->dev, "reset assert failed\n"); - goto err_disable_regulators; - } - } - - if (!skip_reset) { - ret =3D reset_control_assert(qmp->nocsr_reset); - if (ret) { - dev_err(qmp->dev, "no-csr reset assert failed\n"); - goto err_assert_reset; - } - - usleep_range(200, 300); - } - - if (!qmp->skip_init) { - ret =3D reset_control_bulk_deassert(cfg->num_resets, qmp->resets); - if (ret) { - dev_err(qmp->dev, "reset deassert failed\n"); - goto err_assert_reset; - } + ret =3D -ENODATA; + goto err_disable_clks; } =20 - ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); - if (ret) - goto err_assert_reset; - return 0; =20 -err_assert_reset: - if (!qmp->skip_init) - reset_control_bulk_assert(cfg->num_resets, qmp->resets); +err_disable_clks: + clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); +err_disable_pipe_clks: + clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); =20 @@ -5833,12 +5809,62 @@ static int qmp_pcie_exit(struct phy *phy) reset_control_bulk_assert(cfg->num_resets, qmp->resets); =20 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); + clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); =20 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); =20 return 0; } =20 +static int qmp_pcie_reset(struct phy *phy) +{ + struct qmp_pcie *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + int ret; + + if (qmp->skip_reset) + return 0; + + if (qmp->skip_init) { + ret =3D reset_control_assert(qmp->nocsr_reset); + if (ret) { + dev_err(qmp->dev, "no-csr reset assert failed\n"); + return ret; + } + + usleep_range(200, 300); + + ret =3D reset_control_deassert(qmp->nocsr_reset); + if (ret) { + dev_err(qmp->dev, "no-csr reset deassert failed\n"); + return ret; + } + + return 0; + } + + /* + * Toggle BCR reset for PHY that doesn't support no_csr reset or has not + * been initialized. + */ + ret =3D reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + return ret; + } + + usleep_range(200, 300); + + ret =3D reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + reset_control_bulk_assert(cfg->num_resets, qmp->resets); + return ret; + } + + return 0; +} + static int qmp_pcie_power_on(struct phy *phy) { struct qmp_pcie *qmp =3D phy_get_drvdata(phy); @@ -5847,17 +5873,14 @@ static int qmp_pcie_power_on(struct phy *phy) void __iomem *pcs =3D qmp->pcs; void __iomem *status; unsigned int mask, val; - bool skip_reset; int ret; =20 - skip_reset =3D qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY_PCS_= STATUS], - cfg->phy_status); /* * Write CSR register for PHY that doesn't support no_csr reset or has not * been initialized. */ if (qmp->skip_init) - goto skip_tbls_init; + goto skip_serdes_start; =20 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); @@ -5870,22 +5893,6 @@ static int qmp_pcie_power_on(struct phy *phy) qmp_pcie_init_registers(qmp, &cfg->tbls); qmp_pcie_init_registers(qmp, mode_tbls); =20 -skip_tbls_init: - ret =3D clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); - if (ret) - return ret; - - if (!skip_reset) { - ret =3D reset_control_deassert(qmp->nocsr_reset); - if (ret) { - dev_err(qmp->dev, "no-csr reset deassert failed\n"); - goto err_disable_pipe_clk; - } - } - - if (qmp->skip_init) - goto skip_serdes_start; - /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); =20 @@ -5902,15 +5909,10 @@ static int qmp_pcie_power_on(struct phy *phy) PHY_INIT_COMPLETE_TIMEOUT); if (ret) { dev_err(qmp->dev, "phy initialization timed-out\n"); - goto err_disable_pipe_clk; + return ret; } =20 return 0; - -err_disable_pipe_clk: - clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); - - return ret; } =20 static int qmp_pcie_power_off(struct phy *phy) @@ -5918,8 +5920,6 @@ static int qmp_pcie_power_off(struct phy *phy) struct qmp_pcie *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; =20 - clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); - /* * While powering off the PHY, only qmp->nocsr_reset needs to be checked.= In * this way, no matter whether the PHY settings were initially programmed= by @@ -5927,7 +5927,7 @@ static int qmp_pcie_power_off(struct phy *phy) * next time. */ if (qmp->nocsr_reset) - goto skip_phy_deinit; + return 0; =20 /* PHY reset */ qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); @@ -5940,36 +5940,9 @@ static int qmp_pcie_power_off(struct phy *phy) qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); =20 -skip_phy_deinit: return 0; } =20 -static int qmp_pcie_enable(struct phy *phy) -{ - int ret; - - ret =3D qmp_pcie_init(phy); - if (ret) - return ret; - - ret =3D qmp_pcie_power_on(phy); - if (ret) - qmp_pcie_exit(phy); - - return ret; -} - -static int qmp_pcie_disable(struct phy *phy) -{ - int ret; - - ret =3D qmp_pcie_power_off(phy); - if (ret) - return ret; - - return qmp_pcie_exit(phy); -} - static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int subm= ode) { struct qmp_pcie *qmp =3D phy_get_drvdata(phy); @@ -5988,8 +5961,11 @@ static int qmp_pcie_set_mode(struct phy *phy, enum p= hy_mode mode, int submode) } =20 static const struct phy_ops qmp_pcie_phy_ops =3D { - .power_on =3D qmp_pcie_enable, - .power_off =3D qmp_pcie_disable, + .init =3D qmp_pcie_init, + .exit =3D qmp_pcie_exit, + .power_on =3D qmp_pcie_power_on, + .power_off =3D qmp_pcie_power_off, + .reset =3D qmp_pcie_reset, .set_mode =3D qmp_pcie_set_mode, .owner =3D THIS_MODULE, }; --=20 2.34.1